57 CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags Features * Depth Expansion Capability * 52-pin PLCC and 52-pin PQFP * High-speed, low-power, first-in first-out (FIFO) memories * 512 x 18 (CY7C455) * 1,024 x 18 (CY7C456) * 2,048 x 18 (CY7C457) * 0.65 micron CMOS for optimum speed/power * High-speed 83-MHz operation (12 ns read/write cycle time) * Low power -- ICC=90 mA * Fully asynchronous and simultaneous read and write operation * Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags * TTL compatible * Retransmit function * Parity generation/checking * Output Enable (OE) pins * Independent read and write enable pins * Center power and ground pins for reduced noise * Supports free-running 50% duty cycle clock inputs * Width Expansion Capability The CY7C455, CY7C456, and CY7C457 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide. The CY7C455 has a 512-word memory array, the CY7C456 has a 1,024-word memory array, and the CY7C457 has a 2,048-word memory array. The CY7C455, CY7C456, and CY7C457 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Empty flags and generation/checking of parity. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (CKW) and a write enable pin (ENW). Pin Configurations D0 - 17 INPUT REGISTER FL/RT XI READ POINTER RESET LOGIC EXPANSION LOGIC XI HF ENW E/F CKW PAFE/XO HF E/F XO/PAFE Q0 Q1 Q2 Q3 8 9 10 11 12 13 14 15 16 17 18 19 20 7C455 7C456 7C457 21 22 23 24 25 26 27 28 THREE-STATE OUTPUT REGISTER RETRANSMIT LOGIC READ CONTROL D11 D12 D9 D10 46 45 44 43 42 41 40 39 38 37 36 35 34 29 30 31 32 33 D13 D14 D15 D16 D17 FL/RT MR CKR ENR OE Q17/PG2/PE2 Q16 Q15 Q14 MR RAM ARRAY 512 x 18 1024 x 18 2048 x 18 D2 D1 D0 Q11 Q12 Q13 FLAG LOGIC WRITE POINTER 7 6 5 4 3 2 1 52 51 50 49 48 47 FLAG/PARITY PROGRAM REGISTER PARITY WRITE CONTROL VCC VCC(N) D3 D4 D5 D6 D7 D8 VSS ENW Q4 Q5 Q6 Q7 Q8/PG1/PE1 VSS CKW PLCC Top View VSS(N) Q9 Q10 Logic Block Diagram Functional Description OE Q0 - 7, Q8/PG1/PE1 Q9- 16, Q17/PG2/PE2 Cypress Semiconductor Corporation Document #: 38-06003 Rev. *A * CKR ENR 3901 North First Street c455-1 * c455-2 San Jose * CA 95134 * 408-943-2600 Revised December 26, 2002 CY7C455 CY7C456 CY7C457 Pin Configurations (continued) Functional Description (continued) D9 D10 D11 D12 VCC VCC(N) D3 D4 D5 D6 D7 D8 VSS PQFP Top View 52 51 50 49 48 47 46 45 44 43 42 41 40 D2 D1 D0 XI ENW CKW HF E/F XO/PAFE Q0 Q1 Q2 Q3 1 2 3 4 5 6 7 8 9 10 11 12 13 7C455 7C456 7C457 14 15 16 17 18 19 20 21 39 38 37 36 35 34 33 32 31 30 29 28 27 22 23 24 25 26 D13 D14 D15 D16 D17 FL/RT MR CKR ENR OE Q17/PG2/PE2 Q16 Q15 Q14 Q11 Q12 Q13 VSS(N) Q9 Q10 Q4 Q5 Q6 Q7 Q8/PG1/PE1 VSS c455-3 In the standalone and width expansion configurations, a LOW on the retransmit (RT) input causes the FIFOs to retransmit the data. Read enable (ENR) and the write enable (ENW) must both be HIGH during the retransmit, and then ENR is used to access the data.When ENW is asserted, data is written into the FIFO on the rising edge of the CKW signal. While ENW is held active, data is continually written into the FIFO on each CKW cycle. The output port is controlled in a similar manner by a free-running read clock (CKR) and a read enable pin (ENR). In addition, the CY7C455, CY7C456, and CY7C457 have an output enable pin (OE). The read (CKR) and write (CKW) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 83.3 MHz are achievable in the standalone configuration, and up to 83.3 MHz is achievable when FIFOs are cascaded for depth expansion. Depth expansion is possible using the cascade input (XI), cascade output (XO), and First Load (FL) pins. The XO pin is connected to the XI pin of the next device, and the XO pin of the last device should be connected to the XI pin of the first device. The FL pin of the first device is tied to VSS. The CY7C455, CY7C456, and CY7C457 provide three status pins. These pins are decoded to determine one of six states: Empty, Almost Empty, Less than or Equal to Half Full, Greater than Half Full, Almost Full, and Full (see Table 1). The Almost Empty/Full flag (PAFE) shares the XO pin on the CY7C455, CY7C456, and CY7C457. This flag is valid in the standalone and width-expansion configurations. In the depth expansion, this pin provides the expansion out (XO) information that is used to signal the next FIFO when it will be activated. The flags are synchronous, i.e., they change state relative to either the read clock (CKR) or the write clock (CKW). When entering or exiting the Empty and Almost Empty states, the flags are updated exclusively by the CKR. The flags denoting Half Full, Almost Full, and Full states are updated exclusively by CKW. The synchronous flag architecture guarantees that the flags maintain their status for some minimum time. This time is typically equal to approximately one cycle time. The CY7C455/6/7 uses center power and ground for reduced noise. All configurations are fabricated using an advanced 0.65u CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Document #: 38-06003 Rev. *A Page 2 of 23 CY7C455 CY7C456 CY7C457 Selection Guide 7C455/6/7-12 7C455/6/7-14 7C455/6/7-20 7C455/6/7-30 Maximum Frequency (MHz) 83.3 71.4 50 33.3 Maximum Cascadable Frequency 83.3 71.4 50 33.3 Maximum Access Time (ns) 9 10 15 20 Minimum Cycle Time (ns) 12 14 20 30 Minimum Clock HIGH Time (ns) 5 6.5 9 12 Minimum Clock LOW Time (ns) 5 6.5 9 12 Minimum Data or Enable Set-Up (ns) 4 5 6 7 Minimum Data or Enable Hold (ns) 0 0 0 0 Maximum Flag Delay (ns) Maximum Current (mA) 9 10 15 20 Commercial 160 160 140 120 Industrial 180 180 160 140 Selection Guide (continued) Density OE, Depth Cascadable Package CY7C455 CY7C456 CY7C457 512 x 18 1,024 x 18 2,048 x 18 Yes Yes Yes 52-Pin PLCC/PQFP 52-Pin PLCC/PQFP 52-Pin PLCC/PQFP Maximum Ratings[1] Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current..................................................... >200 mA Storage Temperature ................................-65C to +150 C Operating Range Ambient Temperature with Power Applied............................................-55C to +125 C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V DC Input Voltage............................................ -3.0V to +7.0V Output Current into Outputs (LOW) .............................20 mA Document #: 38-06003 Rev. *A Range Ambient Temperature VCC Commercial 0 C to +70 C 5V 10% -40C to +85C 5V 10% Industrial [2] Notes: 1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. TA is the "instant on" case temperature. Page 3 of 23 CY7C455 CY7C456 CY7C457 Pin Definitions I/O Description D0 - 17 Signal Name I Data Inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (D0 - 17) into the FIFO's memory. If MR is asserted at the rising edge of CKW, data is written into the FIFO's programming register. D8, 17 are ignored if the device is configured for parity generation. Q0 - 7 Q9 - 16 O Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (Q0 - 7, Q9 - 16) out of the FIFO's memory. If MR is active at the rising edge of CKR, data is read from the programming register. Q8/PG1/PE1 Q17/PG2/PE2 O Function varies according to mode: Parity disabled - same function as Q0 - 7 and Q9 - 16 Parity enabled, generation - parity generation bit (PG x) Parity enabled, check - Parity Error Flag (PEx) ENW I Enable Write: Enables the CKW input (for both non-program and program modes). ENR I Enable Read: Enables the CKR input (for both non-program and program modes). CKW I Write Clock: The rising edge clocks data into the FIFO when ENW is LOW; updates Half Full, Almost Full, and Full flag states. When MR is asserted, CKW writes data into the program register. CKR I Read Clock: The rising edge clocks data out of the FIFO when ENR is LOW; updates the Empty and Almost Empty flag states. When MR is asserted, CKR reads data out of the program register. HF O Half Full Flag: Synchronized to CKW. E/F O Empty or Full Flag: E is synchronized to CKR; F is synchronized to CKW. PAFE/XO O Dual-Mode Pin: Not Cascaded - programmable Almost Full is synchronized to CKW; Programmable Almost Empty is synchronized to CKR. Cascaded - expansion out signal, connected to XI of next device. XI I Expansion-In Pin: Not Cascaded - XI is tied to VSS. Cascaded - expansion Input, connected to XO of previous device. FL/RT I First Load/Retransmit Pin: Cascaded - the first device in the daisy chain will have FL tied to VSS; all other devices will have FL tied to VCC (Figure 1). Not Cascaded - tied to VCC. Retransmit function is also available in standalone mode by strobing RT. MR I Master Reset: Resets device to empty condition. Non-Programming Mode: Program register is reset to default condition of no parity and PAFE active at 16 or less locations from Full/Empty. Programming Mode: Data present on D0 - 9,10, or 11 and D15-17 is written into the programmable register on the rising edge of CKW. Program register contents appear on Q0 - 9,10, or 11 and Q15-17 after the rising edge of CKR. OE I Output Enable for Q0 - 7, Q 9 - 16, Q8/PG1/PE1 and Q 17/PG2/PE2 pins. Document #: 38-06003 Rev. *A Page 4 of 23 CY7C455 CY7C456 CY7C457 Electrical Characteristics Over the Operating Range Parameter 7C455/6/7- 7C455/6/7- 7C455/6/7- 14 20 30 Min. Test Conditions Min. VOH Output HIGH Voltage VCC = Min., IOH = -2.0 mA 2.4 VOL Output LOW Voltage VCC = Min., I OL = 8.0 mA VIH[3] Input HIGH Voltage [3] Input LOW Voltage VIL Description 7C455/6/7- 12 Max 0.4 2.2 Max 2.4 Min. 2.2 Min. 2.2 VCC 2.2 Unit V 0.4 VCC Max 2.4 0.4 VCC Max 2.4 0.4 V VCC V -0.5 0.8 -0.5 0.8 -0.5 0.8 -0.5 0.8 V IIX Input Leakage Current VCC = Max. -10 +10 -10 +10 -10 +10 -10 +10 A IOS[4] Output Short Circuit Current VCC = Max., VOUT = GND -90 IOZL IOZH Output OFF, High Z Current OE > VIH, VSS < VO < VCC -10 ICC1[5] Operating Current VCC = Max., IOUT = 0 mA Com'l 160 160 Ind 180 ICC2[6] Operating Current VCC = Max., IOUT = 0 mA Com'l 90 Ind VCC = Max., IOUT = 0 mA ISB [7] Standby Current -90 -90 -90 mA +10 A 140 120 mA 180 160 140 mA 90 90 90 mA 100 100 100 100 mA Com'l 40 40 40 40 mA Ind 40 40 40 40 mA +10 -10 +10 -10 +10 -10 Capacitance[8] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 5.0V Max. Unit 10 pF 12 pF AC Test Loads and Waveforms[9, 10, 11, 12, 13] R1 500 ALL INPUT PULSES 5V OUTPUT 3.0V CL R2 333 INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT 200 OUTPUT c455-4 GND 3 ns 90% 10% 90% 10% 3 ns c455-5 2V Notes: 3. The VIH and VIL specifications apply for all inputs except XI. The XI pin is not a TTL input. It is connected to either XO of the previous device or V SS. 4. Test no more than one output at a time for not more than one second. 5. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency (fMAX), while data inputs switch at fMAX/2. Outputs are unloaded. 6. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz. Outputs are unloaded. 7. All input signals are connected to VCC . All outputs are unloaded. Read and write clocks switch at maximum frequency (fMAX). 8. Tested initially and after any design or process changes that may affect these parameters. 9. CL = 30 pF for all AC parameters except for t OHZ. 10. CL = 5 pF for t OHZ . 11. All AC measurements are referenced to 1.5V except tOE, t OLZ, and tOHZ . 12. tOE and t OLZ are measured at 100 mV from the steady state. 13. tOHZ is measured at +500 mV from VOL and - 500 mV from VOH . Document #: 38-06003 Rev. *A Page 5 of 23 CY7C455 CY7C456 CY7C457 Switching Characteristics Over the Operating Range[14] 7C455/6/7- 7C455/6/7- 7C455/6/7- 12 14 20 Parameter Description 7C455/6/7- 30 Min. Max. Min. Max. Min. Max. Min. Max. Unit tCKW Write Clock Cycle 12 14 20 30 ns tCKR Read Clock Cycle 12 14 20 30 ns tCKH Clock HIGH 5 6.5 9 12 ns tCKL Clock LOW 5 6.5 9 12 ns tA Data Access Time tOH Previous Output Data Hold After Read HIGH 0 0 0 0 ns tFH Previous Flag Hold After Read/Write HIGH 0 0 0 0 ns tSD Data Set-Up 4 5 6 7 ns tHD Data Hold 0 0 0 0 ns tSEN Enable Set-Up 4 5 6 7 ns tHEN Enable Hold 0 tOE OE LOW to Output Data Valid 9 10 0 9 15 0 10 20 0 15 ns ns 20 ns [8, 15] OE LOW to Output Data in Low Z [8, 15] OE HIGH to Output Data in High Z 9 10 15 20 ns tPG Read HIGH to Parity Generation 9 10 15 20 ns tPE Read HIGH to Parity Error Flag 9 10 15 20 ns Flag Delay 9 10 15 20 ns tOLZ tOHZ tFD 0 0 0 0 ns tSKEW1 [16] Opposite Clock After Clock 0 0 0 0 ns tSKEW2 [17] Opposite Clock Before Clock 12 14 20 30 ns tPMR Master Reset Pulse Width (MR LOW) 14 14 20 30 ns tSCMR Last Valid Clock LOW Set-Up to MR LOW 0 0 0 0 ns tOHMR Data Hold From MR LOW 0 0 0 0 ns tMRR Master Reset Recovery (MR HIGH Set-Up to First Enabled Write/Read) 12 14 20 30 ns tMRF MR HIGH to Flags Valid tAMR MR HIGH to Data Outputs LOW tSMRP Program Mode--MR LOW Set-Up 12 14 20 30 ns tHMRP Program Mode--MR LOW Hold 9 10 15 20 ns tFTP Program Mode--Write HIGH to Read HIGH 12 14 20 30 ns tAP Program Mode--Data Access Time tOHP Program Mode--Data Hold Time from MR HIGH 0 0 0 0 ns tPRT Retransmit Pulse Width 12 14 20 30 ns tRTR Retransmit Recovery Time 12 14 20 30 ns 12 14 12 20 14 12 20 14 20 30 ns 30 ns 30 ns 14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and output loading as shown in AC Test Loads and Waveforms and capacitance as in notes 9 and 10, unless otherwise specified. 15. At any given temperature and voltage condition, tOLZ is greater than t OHZ for any given device. 16. tSKEW1 is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle (for purposes of flag update). If the opposite clock occurs less than tSKEW1 after the clock, the decision of whether or not to include the opposite clock in the current clock cycle is arbitrary. Note: The opposite clock is the signal to which a flag is not synchronized; i.e., CKW is the opposite clock for Empty and Almost Empty flags, CKR is the opposite clock for the Almost Full, Half Full, and Full flags. The clock is the signal to which a flag is synchronized; i.e., CKW is the clock for the Half Full, Almost Full, and Full flags, CKR is the clock for Empty and Almost Empty flags. 17. tSKEW2 is the minimum time an opposite clock can occur before a clock and still be guaranteed to be included in the current clock cycle (for purposes of flag update). If the opposite clock occurs less than t SKEW2 before the clock, the decision of whether or not to include the opposite clock in the current clock cycle is arbitrary. See Note 16 for definition of clock and opposite clock. Document #: 38-06003 Rev. *A Page 6 of 23 CY7C455 CY7C456 CY7C457 Switching Waveforms tCKW Write Clock Timing Diagram tCKH CKW tCKL ENABLED WRITE tSD D0 - 17 DISABLED WRITE tHD VALID DATA IN tSEN tHEN ENW tSEN tFH tHEN E/F,PAFE,HF tFH tFD Read Clock Timing Diagram tCKR tCKH CKR c455-6 tCKL ENABLED READ DISABLED READ tA tOH Q0 - 17 tFD PREVIOUS WORD NEW WORD tSEN tHEN ENR tSEN tFH tHEN E/F,PAFE tFH tFD tFD c455-7 [18, 19, 20, 21] MasterReset (Defaultwith Free-RunningClocks) Timing Diagram tPMR MR tSCMR CKW tMRR FIRST WRITE ENW tSCMR tMRR CKR ENR tOHMR Q0 - 17 tAMR ALL DATA OUTPUTS LOW VALID DATA tMRF E/F,PAFE tMRF HF c455-8 Notes: 18. To only perform reset (no programming), the following criteria must be met: ENW or CKW must be inactive while MR is LOW. 19. To only perform reset (no programming), the following criteria must be met: ENR or CKR must be inactive while MR is LOW. 20. All data outputs (Q0 - 17) go LOW as a result of the rising edge of MR after t AMR . 21. In this example, Q0 - 17 will remain valid until tOHMR if either the first read shown did not occur or if the read occurred soon enough such that the valid data was caused by it. Document #: 38-06003 Rev. *A Page 7 of 23 CY7C455 CY7C456 CY7C457 Switching Waveforms (continued) [20, 21] Master Reset (Programming Mode) Timing Diagram tSMRP tHMRP MR tSCMR CKW ENW tCKH tMRR LAST VALID WRITE PGM WRITE tHD LAST WORD PGM WORD tSCMR CKR ENR WORD 1 tSMRP WORD 2 tHMRP LAST VALID READ PGM READ tCKH LOW tOHMR Q0 - 17 SECOND WRITE tFTP LOW tSD D0 - 17 FIRST WRITE tAP VALID DATA tOHP tAMR ALL DATA OUTPUTS LOW PGM WORD c455-9 [20, 21] Master Reset (Programming Mode with Free-Running Clocks) Timing Diagram tSMRP tHMRP tCKW MR tSCMR CKW tCKH LAST VALID WRITE tCKL tMRR PGM WRITE tSEN FIRST WRITE SECOND WRITE tHEN ENW tFTP D0 - 17 LAST WORD PGM WORD WORD 1 WORD 2 tCKR tSCMR CKR tSMRP tMRR tHMRP PGM READ LAST VALID READ tCKH tSEN tCKL tHEN ENR tOHMR Q0 - 17 VALID DATA tAP tOHP PGM WORD tAMR ALL DATA OUTPUTS LOW c455-10 Document #: 38-06003 Rev. *A Page 8 of 23 CY7C455 CY7C456 CY7C457 Switching Waveforms (continued) [22, 25, 26] Read to Empty Timing Diagram COUNT 3 1 2 1 0 1 (NO CHANGE) 0 LATENT CYCLE R1 ENABLED READ CKR R2 ENABLED READ R3 ENABLED READ R4 FLAG UPDATE READ R5 ENABLED READ tFD tFD ENR tSKEW1 CKW ENW tSKEW2 W1 ENABLED WRITE LOW tFD E/F c455-12 [22, 23, 24, 25] Read to Empty Timing Diagram with Free-RunningClocks COUNT 1 CKR 0 LATENT CYCLE 1 R1 ENABLED READ R2 IGNORED READ R3 IGNORED READ tSKEW2 R4 FLAG UPDATE READ 0 R5 ENABLED READ R6 IGNORED READ ENR tSKEW1 CKW W1 W2 tSKEW2 W3 ENABLED WRITE W4 W5 W6 ENW HF HIGH tFD tFD tFD E/F PAFE LOW c455-11 Notes: 22. "Count" is the number of words in the FIFO. 23. The FIFO is assumed to be programmed with P>0 (i.e., PAFE does not transition at Empty or Full). 24. R2 is ignored because the FIFO is empty (count = 0). It is important to note that R3 is also ignored because W3, the first enabled write after empty, occurs less than tSKEW2 before R3. Therefore, the FIFO still appears empty when R3 occurs. Because W3 occurs greater than t SKEW2 before R4, R4 includes W3 in the flag update. 25. CKR is clock and CKW is opposite clock. 26. R3 updates the flag to the Empty state by asserting E/F. Because W1 occurs greater than t SKEW1 after R3, R3 does not recognize W1 when updating flag status. But because W1 occurs tSKEW2 before R4, R4 includes W1 in the flag update and, therefore, updates FIFO to Almost Empty state. It is important to note that R4 is a latent cycle; i.e., it only updates the flag status regardless of the state of ENR. It does not change the count or the FIFO's data outputs. Document #: 38-06003 Rev. *A Page 9 of 23 CY7C455 CY7C456 CY7C457 Switching Waveforms (continued) [22, 25, 27] Read to Almost Empty Timing Diagram with Free-Running Clocks COUNT 17 16 R1 ENABLED READ CKR 18 17 R2 17 R3 16 R4 ENABLED READ 15 R5 ENABLED READ R6 ENABLED READ ENR tSKEW1 CKW tSKEW2 W2 ENABLED WRITE W1 W3 ENABLED WRITE W4 W5 W1 W6 ENW HF HIGH E/F HIGH tFD tFD tFD PAFE c455-14 Read to Almost Empty Timing Diagram with Read Flag Update Cycle with Free-Running Clocks [22, 25, 27, 28, 29] 18 (no change) COUNT 17 CKR 17 16 R1 ENABLED READ FLAG UPDATE CYCLE 18 R2 R3 R4 FLAG UPDATE READ 17 16 15 R5 ENABLED READ R6 ENABLED READ R7 ENABLED READ W5 W6 W7 ENR tSKEW1 CKW tSKEW2 W2 ENABLED WRITE W1 W3 ENABLED WRITE W4 ENW HF HIGH E/F HIGH tFD tFD tFD PAFE c455-13 Notes: 27. The FIFO in this example is assumed to be programmed to its default flag values. Almost Empty is 16 words from Empty; Almost Full is 16 locations from Full. 28. R4 only updates the flag status. It does not affect the count because ENR is HIGH. 29. When making the transition from Almost Empty to Intermediate, the count must increase by two (16 A18; two enabled writes: W2, W3) before a read (R4) can update flags to the Less Than Half Full state. Document #: 38-06003 Rev. *A Page 10 of 23 CY7C455 CY7C456 CY7C457 Switching Waveforms (continued) [22, 30, 31, 32] Write to Half Full Timing Diagram with Free-Running Clocks 1024 [512] [256] COUNT 1025 [513] [257] CKW W1 ENABLED WRITE 1024 [512] [256] 1023 [511] [255] W2 W3 1024 [512] [256] 1025 [513] [257] W4 ENABLED WRITE 1026 [514] [258] W6 ENABLED WRITE W5 ENABLED WRITE ENW tSKEW1 CKR tSKEW2 R2 ENABLED READ R1 R3 ENABLED READ R4 R5 R6 ENR tFD tFD tFD HF E/F HIGH PAFE HIGH c455-15 Write to Half Full Timing Diagram with Write Flag Update Cycle with Free-Running Clocks 1024 COUNT [512] [256] CKW 1025 [513] [257] 1024 [512] [256] 1023 [511] [255] W2 W3 W1 ENABLED WRITE 1023 [511] [255] (no change) FLAG UPDATE CYCLE 1024 [512] [256] W4 FLAG UPDATE WRITE W5 ENABLED WRITE R4 R5 [22, 30, 31, 32, 33, 34] 1025 [513] [257] 1026 [514] [258] W6 ENABLED WRITE W7 ENABLED WRITE ENW tSKEW1 CKR tSKEW2 R2 ENABLED READ R1 R3 ENABLED READ R6 R7 ENR tFD tFD tFD HF E/F HIGH PAFE HIGH c455-16 Notes: 30. CKW is clock and CKR is opposite clock. 31. Count = 1,025 indicates Half Full for the CY7C446 and CY7C456. Count = 513 indicates Half Full for the CY7C447 and CY7C457. Count = 257 indicates Half Full for the CY7C448 and CY7C458. 32. When the FIFO contains 1,024 [512] [256] words, the rising edge of the next enabled write causes the HF to be true (LOW). 33. The HF write flag update cycle does not affect the count because ENW is HIGH. It only updates HF to HIGH. 34. When making the transition from Half Full to Less Than Half Full, the count must decrease by two (i.e., 1,025 A1,023; two enabled reads: R2 and R3) before a write (W4) can update flags to less than Half Full. Document #: 38-06003 Rev. *A Page 11 of 23 CY7C455 CY7C456 CY7C457 Switching Waveforms (continued) Write to Almost Full Timing Diagram COUNT 2030 [1016] [494] CKW 2031 [1017] [495] [22, 27, 30, 35, 36] 2032 [1018] [496] W1 ENABLED WRITE 2031 [1017] [495] 2030 [1016] [494] W2 ENABLED WRITE 2031 [1017] [495] 2032 [496] 2033 [497] 2030 [1016] [494] 2031 [1017] [495] 2032 [1018] [496] W4 ENABLED WRITE W5 ENABLED WRITE W3 ENABLED WRITE FLAG UPDATE ENW LOW tSKEW1 tSKEW2 R1 ENABLED READ CKR ENR R2 ENABLED READ LOW tFD tFD tFD tFD PAFE HF LOW E/F HIGH c455-18 [22, 27, 30] Write to Almost Full Timing Diagram with Free-RunningClocks COUNT 2031 [1017] [495] CKW 2032 [1018] [496] W1 ENABLED WRITE 2031 [1017] [495] W2 2030 [1016] [494] W3 2031 [1017] [495] W4 ENABLED WRITE 2032 [1018] [496] 2033 [1019] [497] W5 ENABLED WRITE W6 ENABLED WRITE ENW tSKEW1 CKR tSKEW2 R2 ENABLED READ R1 R3 ENABLED READ R4 R6 R5 ENR HF LOW E/F HIGH tFD tFD tFD PAFE c455-17 Notes: 35. W2 updates the flag to the Almost Full state by asserting PAFE. Because R1 occurs greater than t SKEW1 after W2, W2 does not recognize R1 when updating flag status. W3 includes R2 in the flag update because R2 occurs greater than tSKEW2 before W3. Note that W3 does not have to be enabled to update flags. 36. The dashed lines show W3 as a flag update write rather than an enabled write because ENW is HIGH. Document #: 38-06003 Rev. *A Page 12 of 23 CY7C455 CY7C456 CY7C457 Switching Waveforms (continued) Write to Almost Full Timing Diagram with Write Flag Update Cycle and Free-Running Clocks [22, 27, 30] 2030 [1016] [494] (no change) 2031 COUNT [1017] [495] CKW 2031 [1017] [495] 2032 [1018] [496] W1 ENABLED WRITE 2030 [1016] [494] W2 FLAG UPDATE CYCLE W3 W4 FLAG UPDATE WRITE 2031 [1017] [495] 2033 [1019] [497] 2032 [1018] [496] W5 ENABLED WRITE W6 ENABLED WRITE W7 ENABLED WRITE R5 R6 R7 ENW tSKEW1 CKR tSKEW2 R1 R2 ENABLED READ R4 R3 ENABLED READ ENR HF LOW E/F HIGH tFD tFD tFD PAFE c455-19 Write to Full Flag Timing Diagram with Free-Running Clocks COUNT 2047 [1023] [511] 2048 [1024] [512] 2048 [1024] [512] W1 ENABLED WRITE CKW W2 IGNORED WRITE [22, 30, 37] LATENT CYCLE 2047 [1023] [511] W3 IGNORED WRITE tSKEW2 W4 FLAG UPDATE WRITE 2048 [1024] [512] W5 ENABLED WRITE 2048 [1024] [512] W6 IGNORED WRITE ENW tSKEW1 CKR tSKEW2 R2 R1 R3 ENABLED READ R4 R6 R5 ENR HF LOW tFD tFD tFD E/F PAFE LOW c455-20 Note: 37. W2 is ignored because the FIFO is full (count = 2,048 [1,024] [512]). It is important to note that W3 is also ignored because R3, the first enabled read after full, occurs less than tSKEW2 before W3. Therefore, the FIFO still appears full when W3 occurs. Because R3 occurs greater than tSKEW2 before W4, W4 includes R3 in the flag update. Document #: 38-06003 Rev. *A Page 13 of 23 CY7C455 CY7C456 CY7C457 Switching Waveforms (continued) Even Parity Generation Timing Diagram CKR [38, 39] ENABLED READ DISABLED READ tPG PE1, (PE2) Q0- 7 (Q9 - 16) PREVIOUS WORD: EVEN NUMBER OF 1s NEW WORD: ODD NUMBER OF 1s ENR c455-21 Even Parity GenerationTiming Diagram CKR ENABLED READ DISABLED READ tPG PE1, (PE2) Q0- 7 (Q9 - 16) [38, 40] PREVIOUS WORD: ODD NUMBER OF 1s NEW WORD: EVEN NUMBER OF 1s ENR c455-22 Notes: 38. In this example, the FIFO is assumed to be programmed to generate even parity. The Q0-7 word is shown. The example is similar for the Q 9-16 word. 39. If Q0-7 "new word" also has an even number of 1s, then PG1 stays LOW. 40. If Q0-7 "new word" also has odd number of 1s, then PG1 stays HIGH. Document #: 38-06003 Rev. *A Page 14 of 23 CY7C455 CY7C456 CY7C457 Switching Waveforms (continued) Even Par ity Checking [41] CKW WRITE M WRITE M+1 WRITE M+2 ENW WORD M: WORD M+ 1: ODD NUMBER OF 1" s D0- 7 EVEN NUMBER OF 1" s WORD M+ 2: EVEN NUMBER OF 1"s CKR READ M READ M+1 READ M+2 ENR tPE tPE F1 PE1 (PE2) 8 LSBs OF WORD M-1 Q0- 7 (Q9- 16) 8 LSBs OF WORD M 8 LSBs OF WORD M+1 8 LSBs OF WORD M+2 c455-23 [42, 43] Output Enable Timing CKR ENR READ M+1 LOW OE tOHZ Q0- 17 tOE VALID DATA WORD M VALID DATA WORD M+1 tOLZ c455-24 [44, 45] Retransmit Timing FL/RT tPRT tRTR REN/WEN E/F, HF, PAFE 42X5-21 Notes: 41. In this example, the FIFO is assumed to be programmed to check for even parity. The Q0-7 word is shown. 42. This example assumes that the time from the CKR rising edge to valid word M+1 > tA. The Q 0-7 word is shown. 43. If ENR was HIGH around the rising edge of CKR (i.e., read disabled), the valid data at the far right would once again be word M instead of word M+1. 44. Clocks are free running in this case. 45. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR. Document #: 38-06003 Rev. *A Page 15 of 23 CY7C455 CY7C456 CY7C457 Architecture The CY7C455/6/7 consists of an array of 512, 1024, or 2048 words of 18 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (CKR, CKW, ENR, ENW, and MR), and flags (HF, E/F, PAFE). The CY7C455/6/7 also includes the control signals OE, FL, XI, and XO for depth expansion. Resetting the FIFO Upon power-up, the FIFO must be reset with a Master Reset (MR) cycle. This causes the FIFO to enter the Empty condition signified by E/F and PAFE being LOW and HF being HIGH. All data outputs (Q0-17) go low at the rising edge of MR. In order for the FIFO to reset to its default state, a falling edge must occur on MR and the user must not read or write while MR is LOW (unless ENR and ENW are HIGH or unless the device is being programmed). Upon completion of the master reset cycle, all data outputs will go LOW tAMR after MR is deasserted. All flags are guaranteed to be valid tMRF after MR is taken HIGH. FIFO Operation When the ENW signal is active (LOW), data present on the D0-17 pins is written into the FIFO on each rising edge of the CKW signal. Similarly, when the ENR signal is active, data in the FIFO memory will be presented on the Q0-17 outputs. New data will be presented on each rising edge of CKR while ENR is active. ENR must set up tSEN before CKR for it to be a valid read. ENW must occur tSEN before CKW for it to be a valid write. An output enable (OE) pin is provided to three-state the Q0-17 outputs when OE is asserted. When OE is enabled (low), data in the output register will be available to the Q0-17 outputs after tOE. If devices are cascaded, the OE function will only output data on the FIFO that is read enabled. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q0-17 outputs even after additional reads occur. Programming The CY7C455/6/7 is programmed during a master reset cycle. If MR and ENW are LOW, a rising edge on CKW will write the D0-7,8,or9 and D15-17 inputs into the programming register[46]. MR must be set up a minimum of tSMRP before the program write rising edge and held tHMRP after the program write falling edge. The user has the ability to also perform a program read during the master reset cycle. This will occur at the rising edge of CKR when MR and ENR are asserted. The program read must be performed a minimum of tFTP after a program write, and the program word will be available tAP after the read occurs. If a program write does not occur, a program read may occur a minimum of tSMRP after MR is asserted. This will read the default program value. When free-running clocks are tied to CKW and CKR, programming can still occur during a master reset cycle with the adherence to a few additional timing parameters. The enable pins must be set-up tSEN before the rising edge of CKW or CKR. Hold times of tHEN must also be met for ENW and ENR. Data present on D0-9 during a program write will determine the distance from Empty (Full) that the Almost Empty (Almost Full) flags will become active. See Table 1 for a description of the six possible FIFO states. P in Table 1 refers to the decimal equivalent of the binary number represented by D0-7, 8 or 9. Programming options for the CY7C455/6/7 are listed in Table 4. The programmable PAFE function on the CY7C455/6/7 is only valid when not cascaded. If the user elects not to program the FIFO's flags, the default is as follows: the Almost Empty condition (Almost Full condition) is activated when the FIFO contains 16 or less words (empty locations). Parity is programmed with the D15-17 bits. See Table 4 for a summary of the various parity programming options. Data present on D15-17 during a program write will determine whether the FIFO will generate or check even/odd parity for the data present on D0-7 and D9-16 thereafter. If the user elects not to program the FIFO, the parity function is disabled. Flag operation and parity are described in greater detail in subsequent sections. Flag Operation The CY7C455/6/7 provides three status pins when not cascaded. The three pins, E/F, PAFE, and HF, allow decoding of six FIFO states (Table 1). PAFE is not available when the CY7C455/6/7 is cascaded for depth expansion. All flags are synchronous, meaning that the change of states is relative to one of the clocks (CKR or CKW, as appropriate).[47] The Empty and Almost Empty flag states are exclusively updated by each rising edge of the read clock (CKR). For example, when the FIFO contains 1 word, the next read (rising edge of CKR while ENR=LOW) causes the flag pins to output a state that represents Empty. The Half Full, Almost Full, and Full flag states are updated exclusively by the write clock (CKW). For example, if the CY7C457 contains 2,047 words (2,048 words indicate Full for the CY7C457), the next write (rising edge of CKW while ENW=LOW) causes the flag pins to output a state that is decoded as Full. Since the flags denoting emptiness (Empty, Almost Empty) are only updated by CKR and the flags signifying fullness (Half Full, Almost Full, Full) are exclusively updated by CKW, careful attention must be given to the flag operation. The user must be aware that if a boundary (Empty, Almost Empty, Half Full, Almost Full, or Full) is crossed due to an operation from a clock that the flag is not synchronized to (i.e., CKW does not affect Empty or Almost Empty), a flag update cycle is necessary to represent the FIFO's new state. The signal to which a flag is not synchronized will be referred to as the opposite clock (CKW is opposite clock for Empty and Almost Empty flags; CKR is the opposite clock for Half Full, Almost Full, and Full flags). Until a proper flag update cycle is executed, the synchronous flags will not show the new state of the FIFO. Notes: 46. CKW will write D0-9 into the programming register. CKR will read D0-9 during a programming register read. 47. The synchronous architecture guarantees the flags valid for approximately one cycle of the clock they are synchronized to. Document #: 38-06003 Rev. *A Page 16 of 23 CY7C455 CY7C456 CY7C457 When updating flags, the FIFO must make a decision as to whether or not the opposite clock was recognized when a clock updates the flag. For example (when updating the Empty flag), if a write occurs at least tSKEW1 after a read, the write is guaranteed not to be included when CKR updates the flag. If a write occurs at least tSKEW2 before a read, the write is guaranteed to be included when CKR updates flag. If a write occurs within tSKEW1 after or tSKEW2 before CKR, then the decision of whether or not to include the write when the flag is updated by CKR is arbitrary. The update cycle for non-boundary flags (Almost Empty, Half Full, Almost Full) is different from that used to update the boundary flags (Empty, Full). Both operations are described below. Boundary and Non-Boundary Flags Boundary Flags (Empty) The Empty flag is synchronized to the CKR signal (i.e., the Empty flag can only be updated by a clock pulse on the CKR pin). An empty FIFO that is written to will be described with an Empty flag state until a rising edge is presented to the CKR pin. When making the transition from Empty to Almost Empty (or Empty to Less than or Equal to Half Full), a clock cycle on CKR is necessary to update the flags to the current state. In such a state (flags showing Empty even though data has been written to the FIFO), two read clock cycles are required to read data out of the FIFO. The first read serves only to update the flags to the Almost Empty or Less than or Equal to Half Full state, while the second read outputs the data. This first read cycle is known as the latent or flag update cycle because it does not affect the data in the FIFO or the count (number of words in FIFO). It simply deasserts the Empty flag. The flag is updated regardless of the ENR state. Therefore, the update occurs even when ENR is deasserted (HIGH), so that a valid read is not necessary to update the flags to correctly describe the FIFO. In this example, the write must occur at least tSKEW2 before the flag update cycle in order for the FIFO to guarantee that the write will be included in the count when CKR updates the flags. When a free-running clock is connected to CKR, the flag is updated each cycle. Table 2 shows an example of a sequence of operations that update the Empty flag. Boundary Flags (Full) The Full flag is synchronized to the CKW signal (i.e., the Full flag can only be updated by a clock pulse on the CKW pin). A full FIFO that is read will be described with a Full flag until a rising edge is presented to the CKW pin. When making the transition from Full to Almost Full (or Full to Greater Than Half Full), a clock cycle on CKW is necessary to update the flags to the current state. In such a state (flags showing Full even through data has been read from the FIFO), two write cycles are required to write data into the FIFO. The first write serves only to update the flags to the Almost Full or Greater Than Half Full state, while the second write inputs the data. This first write cycle is known as the latent or flag update cycle because it does not affect the data in the FIFO or the count (number of words in the FIFO). It simply deasserts the Full flag. The flag is updated regardless of the ENW state. Therefore, the update occurs even when ENW is deasserted (HIGH), so that a valid write is not necessary to update the flags to correctly describe the FIFO. In this example, the read must occur at least tSKEW2 before the flag update cycle in order for the FIFO to guarantee that the read will be included in the count when CKW updates the flags. When a free-running clock is connected to CKW, the flag updates each cycle. Full flag operation is similar to the Empty flag operation described in Table 2. Non-Boundary Flags (Almost Empty, Half Full, Almost Full) The CY7C455/6/7 features programmable Almost Empty and Almost Full flags. Each flag can be programmed a specific distance from the corresponding boundary flags (Empty or Full). The flags can be programmed to be activated at the Empty or Full boundary, or at any distance from the Empty/Full boundary. When the FIFO contains the number of words or fewer for which the flags have been programmed, the PAFE flag will be asserted signifying that the FIFO is Almost Empty. When the FIFO is within that same number of empty locations from being Full, the PAFE will also be asserted signifying that the FIFO is Almost Full. The HF flag is decoded to distinguish the states. The default distance from where PAFE becomes active to the boundary (Empty, Full) is 16 words/locations. The Almost Full and Almost Empty flags can be programmed so that they are only active at Full and Empty boundaries. However, the operation will remain consistent with the non-boundary flag operation that is discussed below. . Table 1. Flag Truth Table[48] E/F 0 1 1 1 1 0 PAFE 0 0 1 1 0 0 HF 1 1 1 0 0 0 State Empty Almost Empty Less than or Equal to Half Full Greater than Half Full Almost Full Full 7C455 Words in FIFO 0 1 => P P + 1 => 256 257 => 511 - P 512 - P => 511 512 7C456 Words in FIFO 7C457 Words in FIFO 0 1 => P P + 1 => 512 513 => 1023 - P 1024 - P => 1023 1024 0 1 => P P + 1 => 1024 1025 => 2047 - P 2048 - P => 2047 2048 Notes: 48. P is the decimal value of the binary number represented by D0-7 for the CY7C455, D 0-8 for the CY7C456, and D0-9 for the CY7C457. P = 0 signifies that the Almost Empty state = Empty state. Document #: 38-06003 Rev. *A Page 17 of 23 CY7C455 CY7C456 CY7C457 Table 2. Empty Flag (Boundary Flag) Operation Example Status Before Operation Status After Operation E/F AFE HF Number of Words in FIFO E/F AFE HF Number of Words in FIFO Empty 0 0 1 0 Write (ENW = 0) Empty 0 0 1 1 Write Empty 0 0 1 1 Write (ENW = 0) Empty 0 0 1 2 Write Empty 0 0 1 2 Read (ENR = X) AE 1 0 1 2 Flag Update AE 1 0 1 2 Read (ENR = 0) AE 1 0 1 1 Read AE 1 0 1 1 Read (ENR = 0) Empty 0 0 1 0 Read (transition from Almost Empty to Empty) Empty 0 0 1 0 Write (ENR = 0) Empty 0 0 1 1 Write Empty 1 0 1 1 Read (ENR = X) AE 1 0 1 1 Flag Update AE 1 0 1 1 Read (ENR = 0) Empty 0 0 1 0 Read (transition from Almost Empty to Empty) Current State of FIFO Next State of FIFO Operation Comments Almost Empty is only updated by CKR while Half Full and Almost Full are updated by CKW. Non-boundary flags employ flag update cycles similar to the boundary flag latent cycles in order to update the FIFO status. For example, if the FIFO just reaches the Greater than Half Full state, and then two words are read from the FIFO, a write clock (CKW) will be required to update the flags to the Less than Half Full state. However, unlike the boundary flag latent cycle, the state of the enable pin (ENW in this case) affects the operation. Therefore, set-up and hold times for the enable pins must be met (tSEN and tHEN). If the enable pin is active during the flag update cycle, the count and data are updated in addition to PAFE and HF. If the enable pin is not asserted during the flag update cycle, only the flags are updated. Table 3 shows an example of a sequence of operations that update the Almost Empty and Almost Full flags ignored. The parity bits are stored internally as D8 and D17, and during a subsequent read will be available on the PG1 and PG2 pins along with the data words from which the parity was generated (Q0-7 and Q9-16). For example, if parity generate is set to ODD and the D 0-7 inputs have an EVEN number of 1s, PG1 will be HIGH. The CY7C455/6/7 also features even or odd parity checking and generation. D15-17 are used during a program write to describe the parity option desired. Table 4 summarizes programmable parity options. If the user elects not to program the device, then parity is disabled. Parity information is provided on two multi-mode output pins (Q 8/PG1/PE1 and Q17/PG2/PE2). The three possible modes are described in the following paragraphs. Retransmit Programmable Parity Parity Disabled (Q8/Q 17 mode) When parity is disabled (or the user does not program parity option) the FIFO stores all 18 bits present on D0-17 inputs internally and will output all 18 bits on Q0-17. Parity Generate (PG mode) This mode is used to generate either even or odd parity (as programmed) from D0-7 and D9-16. D8 and D17 inputs are Document #: 38-06003 Rev. *A Parity Check (PE mode) If the FIFO is programmed for parity checking, it will compare the parity of D0-8 and D9-17 with the program register. For example, D8 and D17 will be set according to the result of the parity check on each word. When these words are later read, PE1 and PE2 will reflect the result of the parity check. If a parity error occurs in D0-8, D8 will be set LOW internally. When this word is later read, PE1 will be LOW. The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The Retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred since the last MR cycle. A LOW pulse on RT resets the internal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and tRTR after the retransmit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted. Page 18 of 23 CY7C455 CY7C456 CY7C457 Width Expansion Modes next device, with XO of the last device connected to XI of the first device. The first device has its first load pin (FL) tied to VSS while all other devices must have this pin tied to VCC. The first device will be the first to be write and read enabled after a master reset. During width expansion all flags (programmable and nonprogrammable) are available. These FIFOs can be expanded in width to provide word width greater than 18 in increments of 18. During width expansion mode all control line inputs are common. When the FIFO is being read near the Empty (Full) boundary, it is important to note that both sets of flags should be checked to see if they have been updated to the Not Empty (Not Full) condition to insure that the next read (write) will perform the same operation on all devices. Proper operation also requires that all cascaded devices have common CKW, CKR, ENW, ENR, D0-17, Q0-17, and MR pins. When cascaded, one device at a time will be read enabled so as to avoid bus contention. By asserting XO when appropriate, the currently enabled FIFO alerts the next FIFO that it should be enabled. The next rising edge on CKR puts Q0-17 outputs of the first device into a high-impedance state. This occurs regardless of the state of ENR or the next FIFO's Empty flag. Therefore, if the next FIFO is empty or undergoing a latent cycle, the Q 0-17 bus will be in a high-impedance state until the next device receives its first read, which brings its data to the Q0-17 bus. Checking all sets of flags is critical so that data is not read from the FIFOs "staggered" by one clock cycle. This situation could occur when the first write to an empty FIFO and a read are very close together. If the read occurs less than tSKEW2 after the first write to two width-expanded devices, A and B, device A may go Almost Empty (read recognized as flag update) while device B stays Empty (read ignored). This occurs because a read can be either recognized or ignored if it occurs within tSKEW2 of a write. The next read cycle outputs the first half of the first word on device A while device B updates its flags to Almost Empty. Subsequent reads will continue to output "staggered" data assuming more data has been written to FIFOs. Program Write/Read of Cascaded Devices Programming of cascaded FIFOs is the same as for a single device. Because the controls of the FIFOs are in parallel when cascaded, they all get programmed the same. During program mode, only parity is programmed since Almost Full and Almost Empty flags are not available when CY7C455/6/7 is cascaded. Only the "first device" (FIFO with FL=LOW) will output its program register contents on Q 0-7 during a program read. Q0-17 of all other devices will remain in a high-impedance state to avoid bus contention. Depth Expansion Mode The CY7C455/6/7 can operate up to 83.3 MHz when cascaded. Depth expansion is accomplished by connecting expansion out (XO) of the first device to expansion in (XI) of the CKW ENW CKR ENR XI D0 - 17 Q0 - 17 CKW CKR CY7C455,6,7 ENW ENR MR HF OE E/F FL/RT PAFE/XO DATA OUT DATA IN D0- 17 MR Q0- 17 VSS XI D0 - 17 Q0 - 17 CKR CKW CY7C455,6,7 ENW ENR MR HF FULL E/F OE FL/RT PAFE/XO VCC EMPTY c455-25 Figure 1. Depth Expansion with CY7C455/6/7 Document #: 38-06003 Rev. *A Page 19 of 23 CY7C455 CY7C456 CY7C457 Table 3. Almost Empty Flag (Non-Boundary Flag) Operation Example[49] Status Before Operation Current State of FIFO E/F Status After Operation AFE HF Number of Words in FIFO Operation Next State of FIFO E/F PAF E HF Number of words in FIFO Comments AE 1 0 1 32 Write (ENW = 0) AE 1 0 1 33 Write AE 1 0 1 33 Write (ENW = 0) AE 1 0 1 34 Write AE 1 0 1 34 Read (ENR = 0) <HF 1 1 1 33 Flag Update and Read <HF 1 1 1 33 Read (ENR = 1) <HF 1 1 1 33 Ignored Read (ENR = 1) <HF 1 1 1 33 Read (ENR = 0) AE 1 0 1 32 Read (transition from <HF to AE) Table 4. Programmable Parity Options D17 D16 D15 0 X X Parity disabled. Condition 1 0 0 Generate even parity on PG output pin. 1 0 1 Generate odd parity on PG output pin. 1 1 0 Check for even parity. Indicate error on PE output pin. 1 1 1 Check for odd parity. Indicate error on PE output pin. Note: 49. Applies to CY7C455/6/7 operations when devices are programmed so that Almost Empty becomes active when the FIFO contains 32 or fewer words. Document #: 38-06003 Rev. *A Page 20 of 23 CY7C455 CY7C456 CY7C457 Ordering Information 512x18 Clocked FIFO Speed (ns) 12 14 20 30 Package Name Package Type Operating Range CY7C455-12JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C455-12NC N52 52-Pin Plastic Quad Flatpack CY7C455-12JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C455-14JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C455-14NC N52 52-Pin Plastic Quad Flatpack CY7C455-14JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C455-20JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C455-20NC N52 52-Pin Plastic Quad Flatpack CY7C455-20JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C455-30JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C455-30NC N52 52-Pin Plastic Quad Flatpack CY7C455-30JI J69 52-Lead Plastic Leaded Chip Carrier Package Name Package Type Operating Range CY7C456-12JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C456-12NC N52 52-Pin Plastic Quad Flatpack CY7C456-12JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C456-14JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C456-14NC N52 52-Pin Plastic Quad Flatpack CY7C456-14JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C456-20JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C456-20NC N52 52-Pin Plastic Quad Flatpack CY7C456-20JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C456-30JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C456-30NC N52 52-Pin Plastic Quad Flatpack CY7C456-30JI J69 52-Lead Plastic Leaded Chip Carrier Package Name Package Type Operating Range CY7C457-12JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C457-12NC N52 52-Pin Plastic Quad Flatpack CY7C457-12JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C457-14JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C457-14NC N52 52-Pin Plastic Quad Flatpack CY7C457-14JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C457-20JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C457-20NC N52 52-Pin Plastic Quad Flatpack CY7C457-20JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C457-30JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C457-30NC N52 52-Pin Plastic Quad Flatpack CY7C457-30JI J69 52-Lead Plastic Leaded Chip Carrier Ordering Code Industrial 1Kx18 Clocked FIFO Speed (ns) 12 14 20 30 Ordering Code Industrial 2Kx18 Clocked FIFO Speed (ns) 12 14 20 30 Ordering Code Document #: 38-06003 Rev. *A Industrial Page 21 of 23 CY7C455 CY7C456 CY7C457 Package Diagrams 52-Lead Plastic Leaded Chip Carrier J69 52-Lead Plastic Quad Flatpack N52 Document #: 38-06003 Rev. *A Page 22 of 23 (c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C455 CY7C456 CY7C457 Document Title: CY7C455, CY7C456, CY7C457 512 X 18, 1K X 18 and 2K X 18 Cascadable Clocked Fifo's with Programmable Flags Document Number: 38-06003 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106464 07/11/01 SZV Change from Spec Number: 38-00211 to 38-06003 *A 122256 12/26/02 RBI Power up requirements added to Maximum Ratings Information Document #: 38-06003 Rev. *A Page 23 of 23