CY7C456-30JIT - Cypress Semiconductor Corp.

512 x 18, 1K x 18, and 2K x 18 Ca scadable

Clocked FIFOs with Programmable Flags

CY7C455

CY7C456

CY7C457

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-06003 Rev. *A Revised December 26, 2002

Features

• High-speed, low-power, first-in first-out (FIFO)

memories

• 512 x 18 (CY7C455)

• 1,024 x 18 (CY7C456)

• 2,048 x 18 (CY7C457)

• 0.65 micron CMOS for optimum speed/power

• High-spe ed 83-M Hz operation (12 ns read/write cyc le

time)

• Low power — ICC=90 mA

• Fully asynchronous and simultaneous read and write

operation

• Empty , Full, Half Full, and programmable Almost Empty

and Almost Full status flags

• TTL compatible

• Retransmit function

• Parity generation/checking

• Output Enable (OE) pins

• Independent read and write enable pins

• Center power and ground pins for reduced noise

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

• Depth Expansion Capability

• 52-pin PLCC and 52-pin PQFP

Functional Description

The CY7C455, CY7C456, and CY7C457 are high-speed,

low-power, first-in first-out (FI FO) memories with c locked read

and w rite in terfa ce s. All are 18 bit s wi de. Th e C Y7 C 455 ha s a

512-word memory array, the CY7C456 has a 1,024-word

memory array, and the CY7C457 has a 2,048-word memory

array. The CY7C455, CY7C456, and CY7C457 can be cas-

caded to increase FIFO depth. Programmable features in-

clude Almost Full /Empty flags a nd generatio n/checking o f par-

ity. These FIFOs provide solutions for a wide variety of data

buffering needs, including high-speed data acquisition, multi-

processor interfaces, and communications buffering.

These FIFOs have 18-bit input and output ports that are con-

trolled by separate clock an d ena bl e si gna ls . The input port i s

controlled by a free-running clock (CKW) and a write enable

pin (ENW).

LogicBlockDiagram Pin Configurations

c455-1 c455-2

PARITY

THREE–STATE

OUTPUT REGISTER READ

CONTROL

FLAG

LOGIC

WRITE

CONTROL

WRITE

POINTER READ

POINTER

RESET

LOGIC

EXPANSION

LOGIC

INPUT

FLAG/PARITY

PROGRAM

D0–17

ENR

CKR

E/F

PAFE/XO

Q0–7,Q

8/PG1/PE1

Q9–16, Q17/PG2/PE2

ENWCKW

FL/RT

RAM

ARRAY

512 x 18

1024 x 18

2048 x 18

Top Vi e w

PLCC

21 2223 24 25 26 27 28 29 30 31 32 33

7 6 5 4 3 2 525150494847

E/F

ENW

XO/PAFE

CKW

D13

D14

D15

D16

D17

FL/RT

CKR

ENR

Q17

Q16

Q15

D12

D11

D10

VCC(N)

VCC

VSS

Q8/PG1/PE1

VSS

VSS(N)

Q10

Q11

Q12

Q13

Q14

RETRANSMIT

LOGIC

/PG2/PE2

7C455

7C456

7C457

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 2 of 23

Functional Description (continued)

In the st and alone and wid th ex pan sion conf igu rations , a LOW

on the retransmit (RT) input causes the FIFOs to retransmit

the data. Read enable (ENR) and the write enable (ENW) must

both be HIGH during the retransmit, and then ENR is used to

access the data.When ENW is asserted, data is written into

the FIFO on the ris in g edg e of the CKW sig nal . Whi le ENW is

held active, data is continually written into the FIFO on each

CKW cycle. The output port is controlled in a similar manner

by a free-running read clock (CKR) and a read enable pin

(ENR). In addition, the CY7C455, CY7C456, and CY7C457

have an output enable pin (OE). The read (CKR) and write

(CKW) clocks may be tied together for single-clock operation

or the two c loc ks m ay be run i nde pen de ntly f or a sy nc hron ou s

read/wri te appl icati ons. Clo ck freq uenci es up t o 83.3 M Hz ar e

achievable in the standalone configuration, and up to 83.3

MHz is achieva ble when FIFOs are cascaded for depth expan-

sion.

Depth expansion is possible using the cascade inp ut (XI), cas-

cade output (XO), and First Load (FL) pins. The XO pin is

connected to the XI pin of the next device, and the XO pin of

the last device should be connected to the XI pin of the first

device. The FL pin of the first device is tied to VSS.

The CY7C 4 55, CY7 C456 , and CY7C4 57 p rov ide three st atu s

pins. These pins are decoded to determine one of six states:

Empty, Almost Empty, Less than o r Equal to Half Fu ll, G reater

than H alf Fu ll, Alm os t F ull , a nd Full (see Table 1). The Almost

Empty/Full flag (PAFE) shares the XO pin on the CY7C455,

CY7C456, and CY7C457. This flag is valid in the standalone

and width-expansion configurations. In the depth expansion,

this pin provides the expansion out (XO) information that is

used to signal the next FIFO when it will be activated.

The flags are synchronous, i.e., they change state relative to

either the read clock (CKR) or the write clock (CKW). When

entering or exiting the Empty and Almost Empty states, the

flags are updated exclusively by the CKR. The flags denoting

Half Full, Almost Full, and Full states are updated exclusively

by CKW. The synchronous flag architecture guarantees that

the flags maintain their status for some minimum time. This

time is typically equal to approximately one cycle time.

The CY7C455/6/7 u se s cen ter po w er a nd g roun d for reduce d

noise. All configurations are fabricated using an advanced

0.65u CMOS technology. Input ESD protection is greater

than 20 01V, and la tch- up is pre vent ed by th e use of guard

rings.

Pin Configurations (continued)

14 1516 17 18 19 20 21 22 23 24 25 26

52 51 50 49 48 47 4544 43 42 41 40

E/F

ENW

XO/PAFE

CKW

D12

D11

D10

VCC(N)

VCC

VSS

D13

D14

D15

D16

D17

FL/RT

CKR

ENR

Q17/PG2/PE2

Q16

Q15

c455-3

Top View

PQFP

Q8/PG1/PE1

VSS

VSS(N)

Q10

Q11

Q12

Q13

Q14

7C455

7C456

7C457

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 3 of 23

Maximum Ratings[1]

(Above which the useful life may be impaired. For user guide-

lines, not tes ted .)

Storage Temperature ................................–65°C to +150°C

Ambient Temperature with

Power Applied............................................–55°C to +125°C

Supply Voltage to Ground Potential...............–0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State ...............................................–0.5V to +7.0V

DC Input Voltage............................................–3.0V to +7.0V

Output Current into Outputs (LOW).............................20 mA

Static Discha rge Voltag e..... ...... ................. ..... ...... .....>2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.....................................................>200 mA

Selection Guide

7C455/6/7–12 7C455/6/7–14 7C455/6/7–20 7C455/6/7–30

Maximu m Frequency (MHz) 83.3 71.4 50 33.3

Maximum Cascad able Frequenc y 83.3 71.4 50 33.3

Maximum Access Time (ns) 910 15 20

Minimum Cycle Time (ns) 12 14 20 30

Minimum Clock HIGH Time (ns) 56.5 912

Minimum Clock LOW Time (ns) 56.5 912

Minimum Data or Enable Set-Up (ns) 4 5 6 7

Minimum Data or Enable Hold (ns) 0 0 0 0

Maximum Flag Delay (ns) 910 15 20

Maxi mum Cur re n t

(mA) Commercial 160 160 140 120

Industrial 180 180 160 140

Selection Guide (continued)

CY7C455 CY7C456 CY7C457

Density 512 x 18 1,024 x 18 2,048 x 18

OE, Depth Cascadable Yes Yes Yes

Package 52-Pin PLCC/PQFP 52-Pin PLCC/PQFP 52-Pin PLCC/PQFP

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +70°C 5V ± 10%

Industrial[2] –40°C to +85°C 5V ± 10%

Notes:

1. The Voltage on any input or I/O pin cannot exceed the power pin during

power-up.

2. TA is the “instant on” case temperature.

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 4 of 23

Pin Definitions

Signal Name I/O Description

D0 − 17 IData Input s: When the FIFO is not f ull and ENW is acti ve, C KW (ri sing edge ) wri tes d ata (D0 − 17) into

the FIFO ’s memory. If MR is asserted at the rising edge of CKW, data is written into the FIFO’s

progr amming regi ster. D8, 17 are ignored if the device is configured for parity generation.

Q0 − 7

Q9 − 16 OData Ou tputs: When the FIFO is not em pt y an d ENR is active, CKR (rising edge) reads data (Q0 − 7,

Q9 − 16) out of the FI FO’s mem ory. If MR is active at the rising edge of CKR, data is read from the

progr amming regi ster.

Q8/PG1/PE1

Q17/PG2/PE2 OFunction varies according to mode:

Parity disab led – same function as Q0 − 7 and Q9 − 16

Parity enabled, generation – parity generation bit (PGx)

Parity enabled, check – Parity Error Flag (PEx)

ENW IEnable Write: Enables the CKW input (for both non-program and program modes).

ENR IEnable Read: Enables the CKR input (for both non-program and program modes).

CKW IWr ite Clock : The rising edg e cl ock s data into t he FIF O whe n ENW is LOW; updates Half Full, Almost

Full, and F ull fl ag stat es. W hen MR is ass erted , CKW w rite s data int o th e progr am regi ster.

CKR IRead Clock: The rising edge clocks data out of the FIFO when ENR i s LOW; upda tes the Em pty and

Almost Empty flag states. When MR is asserted, CKR reads data out of the program register.

HF OHalf Full Flag: Synchronized to CKW.

E/F OEmpty or Full Flag: E is synchronized to CKR; F is synchron ized to CKW.

PAFE/XO ODual-Mode Pin:

Not Cascad ed – programmable Almost Full is synchronized to CKW; Programmable Almost Empty is

synchronized to CKR.

Cascaded – expansion out signal, connected to XI of next de vice.

XI IExpansion-In Pin:

Not Cascad ed – XI is tied to VSS.

Cascaded – expansion Input, connected to XO of previous device.

FL/RT IFirst Load/Retransmit Pin:

Cascaded – the first devic e in the daisy ch ain will have FL tied to VSS; all other devi ces w ill have FL tied

to VCC (Figure 1).

Not Cascad ed – tied to VCC.

Retransmit function is also available in standalone mode by strobing RT.

MR IMaster Reset: Resets device to empty condition.

Non-Programming Mode: Program register is reset to default condition of no parity and PAFE active at

16 or less locations from Full/Empty.

Programmi ng Mod e: D at a pres en t on D 0 - 9,10, or 11 and D 15-17 is written into the programmable register

on the ris ing edge of CKW . Pro gram register c ontent s appear o n Q0 - 9, 10, or 11 and Q15-17 after t he rising

edge of CKR.

OE IOutput Enable for Q0 − 7, Q9 − 16, Q8/PG1/PE1 and Q17/PG2/PE2 pins.

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 5 of 23

Electrical Characteristi cs Over the Operating Range

7C455/6/7–

12 7C455/6/7–

14 7C455/6/7–

20 7C455/6/7–

Parameter Description Test Conditions Min. Max Min. Max Min. Max Min. Max Unit

VOH Output HIGH

Voltage VCC = Min., IOH = –2.0 mA 2.4 2.4 2.4 2.4 V

VOL Output LOW

Voltage VCC = Min., I OL = 8. 0 mA 0.4 0.4 0.4 0.4 V

VIH[3] Input HIGH Voltage 2.2 VCC 2.2 VCC 2.2 VCC 2.2 VCC V

VIL[3] Input LOW Volta ge –0.5 0.8 –0.5 0.8 –0.5 0.8 –0.5 0.8 V

IIX Input Leakage

Current VCC = Max. –10 +10 –10 +10 –10 +10 –10 +10 µA

IOS[4] Output Short

Circuit Current VCC = Max., VOUT = GND –90 –90 –90 –90 mA

IOZL

IOZH Output OFF, High Z

Current OE > VIH, VSS < VO < VCC –10 +10 –10 +10 –10 +10 –10 +10 µA

ICC1[5] Operating Current VCC = Max.,

IOUT = 0 mA Com’l160 160 140 120 mA

Ind 180 180 160 140 mA

ICC2[6] Operating Current VCC = Max.,

IOUT = 0 mA Com’l90 90 90 90 mA

Ind 100 100 100 100 mA

ISB[7] Standby Current VCC = Max.,

IOUT = 0 mA Com’l40 40 40 40 mA

Ind 40 40 40 40 mA

Capacitance[8]

Parameter Description Te st Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VCC = 5. 0V 10 pF

COUT Output Capacitance 12 pF

AC Test Loads and Waveforms[9, 10, 11, 12, 13]

Notes:

3. Th e V IH and VIL spe cifi cat ions appl y for all inpu ts ex cept XI. The XI pin is not a TTL input. It i s connect ed to ei the r XO of the prev ious dev ice or VSS.

4. Test no more than one output at a time for not more than one second.

5. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency (fMAX), while data inputs

switch at fMAX/2. Outputs are unloaded.

6. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz.

Outputs are unloaded.

7. All input signals are connected to VCC. All outputs are unloaded. Read and write clocks switch at maximum frequency (fMAX).

8. Tested initially and after any design or process changes that may affect these parameters.

9. CL = 30 pF for all AC parameters except for tOHZ.

10. CL = 5 pF for tOHZ.

11. All AC measurements are referenced to 1.5V except tOE, tOLZ, and tOHZ.

12. tOE and tOLZ are measured at ± 100 mV from the steady state.

13. tOHZ is measured at +500 mV from VOL and – 500 mV from VOH.

3.0V

OUTPUT

R1 500Ω

333Ω

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

≤3ns ≤3ns

OUTPUT 2V

Equivalent to: THÉ VENIN EQUIVALENT

c455-4

200Ω

ALL INPUT PULSES

c455-5

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 6 of 23

Switching Characteristics Over the Operating Range[14]

7C455/6/7–

12 7C455/6/7–

14 7C455/6/7–

20 7C455/6/7–

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit

tCKW Write Clock Cycle 12 14 20 30 ns

tCKR Read Clock Cycle 12 14 20 30 ns

tCKH Clock HIGH 56.5 912 ns

tCKL Clock LOW 56.5 912 ns

tAData Access Time 910 15 20 ns

tOH Previous Output Data Hold After Read HIGH 0 0 0 0 ns

tFH Previous Flag Hold After Read/Write HIGH 0 0 0 0 ns

tSD Data Set-Up 4 5 6 7 ns

tHD Data Hold 0 0 0 0 ns

tSEN Enable Set-Up 4 5 6 7 ns

tHEN Enable Hold 0 0 0 0 ns

tOE OE LOW to Output Data Valid 910 15 20 ns

tOLZ[8, 15] OE LOW to Output Data in Low Z 0 0 0 0 ns

tOHZ[8, 15] OE HIGH to Output Data in High Z 910 15 20 ns

tPG Read HIGH to Parity Generation 910 15 20 ns

tPE Read HIGH to Parity Error Flag 910 15 20 ns

tFD Flag Delay 910 15 20 ns

tSKEW1[16] Opposite Cloc k After Cloc k 0 0 0 0 ns

tSKEW2[17] Opposite Cloc k Befo re Clock 12 14 20 30 ns

tPMR Master R eset Pulse Width (MR LOW) 14 14 20 30 ns

tSCMR Last Valid Clock LOW Set-Up to MR LOW 0 0 0 0 ns

tOHMR Data Hold From MR LOW 0 0 0 0 ns

tMRR Master Reset Recovery

(MR HIGH Set-Up to First Ena bled Wri te/Read) 12 14 20 30 ns

tMRF MR HIGH to Flags Valid 12 14 20 30 ns

tAMR MR HIGH to Data Outpu t s LO W 12 14 20 30 ns

tSMRP Program Mode—MR LOW Set-Up 12 14 20 30 ns

tHMRP Program Mode—MR LOW Hol d 910 15 20 ns

tFTP Program Mode—Write HIGH to Read HIGH 12 14 20 30 ns

tAP Program Mode—Data Access Time 12 14 20 30 ns

tOHP Program Mode—Data Hold Time from MR HIGH 0 0 0 0 ns

tPRT Retransmit Pulse Width 12 14 20 30 ns

tRTR Retransmit Recovery Time 12 14 20 30 ns

14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and output loading as shown in AC Test Loads and

Waveforms and capacitance as in notes 9 and 10, unless otherwise specified.

15. At any given temperature and voltage condition, tOLZ is greater than tOHZ for any given device.

16. tSKEW1 is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle

(for purposes of flag update). If the opposite clock occurs less than tSKEW1 after the clock, the decision of whether or not to include the

opposite clock in the current clock cycle is arbitrary. Note: The opposite clock is the signal to which a flag is not synchronized; i.e., CKW is

the opposite clock for Empty and Almost Empty flags, CKR is the opposite clock for the Almost Full, Half Full, and Full flags. The clock is the signal

to which a flag is synchronized; i.e., CKW is the clock for the Half Full, Almost Full, and Full flags, CKR is the clock for Empty and Almost Empty flags.

17. tSKEW2 is the minimum time an opposite clock can occur before a clock and still be guaranteed to be included in the current clock cycle (for

purpose s of flag update). I f the opposi te cl ock occurs less th an tSKEW2 before t he clock, the decis ion of whet her or not to incl ude the opposi te

clock in the current clock cycle is arbitrary. See Note 16 for definition of clock and opposite clock.

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 7 of 23

Switching Waveforms

Notes:

18. To only perform reset (no programming), the following criteria must be met: ENW or CKW must be inactive while MR is LOW.

19. To only perform reset (no programming), the following criteria must be met: ENR or CKR must be inactive while MR is LOW.

20. All data outputs (Q0 - 17) go LOW as a result of the rising edge of MR after tAMR.

21. In this example, Q0 - 17 will r ema in va li d un ti l tOHMR if eit her the fir st rea d shown di d not oc cur or if th e read occ urre d soon en ough su ch tha t the vali d

data was caused by it.

Write Clock Timing Diagram

Read Clock Timing Diagram

tCKW

c455-6

c455-7

tCKH tCKL

tHD

tSD

ENABLED WRITE DISABLED WRITE

VALID DATA IN

tSEN tHEN

ENABLED READ DISABLED READ

PREVIOUS WORD

tCKR

tCKH tCKL

tOH

tSEN tHEN

NEW WORD

MasterReset(Defaultwith Free-RunningClocks)TimingDiagram

tPMR

tMRR

tSCMR

tMRR

tOHMR

VALID DATA

tAMR

tMRF

ALL DATA

OUTPUTS LOW

tSCMR

tMRF

HF c455-8

FIRST

WRITE

tFH

tFH tFD

tFD

tFH

tFH tFD

tFD

tFH

D0−17

ENW

E/F,PAFE,HF

Q0−17

ENR

E/F,PAFE

CKR

CKW

ENW

ENR

Q0−17

E/F,PAFE

CKR

CKW

[18, 19, 20, 21]

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 8 of 23

Switching Waveforms (continued)

tSMRP

tMRR

tSCMR

tHMRP

tCKH

tSCMR

tFTP

tSD tHD

tSMRP tHMRP

tCKH

tAP

tOHMR tOHP tAMR

VALID DATA ALL DATA

OUTPUTS LOW

LAST

VALID

READ

PGM

READ

LAST

WORD PGM

WORD WORD 1 WORD 2

LAST

VALID

WRITE

PGM

WRITE FIRST

WRITE SECOND

WRITE

c455-9

Master Reset (ProgrammingMode with Free-RunningClocks) Timing Diagram

tSMRP

c455-10

tMRR

tSCMR

tHMRP

tCKH

tSCMR

tHEN

tFTP

tSMRP

tAP

tOHMR tOHP tAMR

VALID DATA PGM WORD ALL DATA

OUTPUTS LOW

LAST

WORD PGM

WORD WORD 1 WORD 2

tCKL

tCKW

tSEN

tCKR

tCKL

tCKH tHEN

tSEN

PGM

READ

LAST

VALID

WRITE PGM

WRITE FIRST

WRITE SECOND

WRITE

LAST

VALID

READ

tHMRP

LOW

tMRR

MasterReset (ProgrammingMode) TimingDiagram

ENW

CKW

ENR

Q0−17

CKR

ENW

CKW

D0−17

Q0−17

CKR

D0 −17

ENR

PGM WORD

[20, 21]

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 9 of 23

Notes:

22. “Count” is the number of words in the FIFO.

23. The FIFO is assumed to be programmed with P>0 (i.e., P AFE does not transition at Empty or Full).

24. R2 is ignored because the FIFO is empty (count = 0). It is important to note that R3 is also ignored because W3, the first enabled write af ter empty, occurs

less than tSKEW2 before R3. The refore, the FI FO still appears empty when R3 oc curs. Becaus e W3 occurs grea ter than tSKEW2 before R4 , R4 includes

W3 in the flag update.

25. CKR is clock and CKW is opposite clock.

26. R3 upd at e s th e f l ag to t he Em pt y s tate by ass e rti n g E/F. Because W1 occurs greater than tSKEW1 after R3, R3 does not recognize W1 when updating

flag status. But because W1 occurs tSKEW2 before R4, R4 includes W1 in the flag update and, therefore, updates FIFO to Almost Empty state. It is

important to note that R4 is a latent cycle; i.e., it only updates the flag status regardless of the state of ENR. It does not change the count or the

FIFO’s da ta ou tp u ts.

Switching Waveforms (continued)

Readto EmptyTiming DiagramwithFree-RunningClocks

LATENTCYCLE

tSKEW1 tSKEW2

tFD tFD

tFD

10 1 0

ENABLED

READ FLAG

UPDATE ENABLED

READ IGNORED

READ

ENABLED

WRITE

IGNORED

READ IGNORED

READ READ

ENR

ENW

PAFE

E/F

c455-11

HIGH

LOW

Readto Empty Timing Diagram

32 0 1 (NO CHANGE)

tFD tFD

ENABLED FLAG

UPDATE

LATENT CYCLE

READ

ENABLED

WRITE

tSKEW2

tSKEW1

E/F

LOW

tFD

c455-12

READ

ENABLED

READ

ENABLED

READ

ENABLED

READ

R1 R2 R3 R4 R5 R6

W1 W2 W4 W5 W6

tSKEW2

ENR

CKR

ENW

CKW

COUNT

CKR

CKW

[22, 25, 26]

[22, 23 , 24, 25]

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 10 of 23

Notes:

27. The FIFO in this example is assumed to be programmed to its default flag values. Almost Empty is 16 words from Empty; Almost Full is 16 locations from Full.

28. R4 only updates the flag status. It does not affect the count because ENR is HIGH.

29. When making the transition from Almost Empty to Intermediate, the count must increase by two (16 Á18; two enabled writes : W2, W3) before a read (R4)

can update flags to the Less Than Half Full state.

Switching Waveforms (continued)

Read to Almost Empty TimingDiagram withFree-RunningClocks

Read to Almost Empty Timing Diagram with Read Flag Update Cycle with Free-Running Clocks

tSKEW1 tSKEW2

tFD tFD

tFD

17 16 18 16

ENABLED

READ

17 17 15

ENABLED

WRITE

18 16

tSKEW2

tFD tFD

FLAG

UPDATE ENABLED

READ ENABLED

READ

17 17 15

ENABLED

READ

FLAG UPDATE CYCLE

c455-13

c455-14

HIGH

R1 R2 R3 ENABLED

READ

R4 ENABLED

READ

R5 ENABLED

READ

W2 ENABLED

WRITE

W3 W4 W1W5 W6

R2 R3 R4 R5 R6 R7

ENABLED

WRITE

W2 ENABLED

WRITE

W3 W4 W5 W6 W7

18 (no change)

COUNT

ENR

ENW

E/F

PAFE

CKW

17 16

tSKEW1

tFD

ENR

ENW

PAFE

ENABLED

READ

E/F

HIGH

COUNT

CKR

CKW

[22, 25, 27]

[22 , 25, 27, 28 , 29]

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 11 of 23

Notes:

30. CKW is clock and CKR is opposite clock.

31. Count = 1,025 indicates Half Full for the CY7C446 and CY7C456. Count = 513 indicates Half Full for the CY7C447 and CY7C457. Count = 257 indicates

Half Full for the CY7C448 and CY7C458.

32. When the FIFO contains 1,024 [512] [256] words , the rising edge of the next enab led write causes the HF to be true (LOW).

33. The HF write flag update cycle does not affect the count because ENW is HIGH. It only updates HF to HIGH.

34. When making the transition from Half Full to Less Than Half Full, the count must decrease by two (i.e., 1,025 Á1,023; two enabled reads: R2 and R3)

before a write (W4) can update flags to less than Half Full.

Switching Waveforms (continued)

Write toHalf Full TimingDiagram withFree-RunningClocks

1025 1023 1025

tSKEW1 tSKEW2

tFD tFD

tFD

ENABLED

WRITE ENABLED

WRITE

ENABLED

READ ENABLED

READ

1024 1024 1026

c455-15

[513] [512] [511] [512] [513] [514]

Write to Half Full Timing Diagram with Write Flag Update Cycle with Free-Running Clocks

1024 1025 1023 1025

tSKEW1 tSKEW2

tFD tFD

tFD

ENABLED

WRITE FLAG

UPDATE ENABLED

WRITE ENABLED

WRITE

1024 1024 1026

ENABLED

WRITE

ENABLED

READ ENABLED

READ

WRITE

FLAG UPDATE CYCLE

[512] [513] [512] [511] [512] [513] [514]

PAFE

c455–16

ENW

ENR

PAFE

E/F

HIGH

W1 W2 W3 W4 W5 W6

R1 R4 R5 R6

R3R2

W1 W2 W3 W4 W5 W6 W7

R1 R4 R5 R6

R2 R3 R7

[257] [256] [255] [256] [257] [258]

1023 [511]

[255] (no change)

[256] [257] [256] [255] [256] [257] [258]

1024

[512]

ENR

E/F HIGH

[256]

COUNT

ENW

CKW

CKR

COUNT

CKW

CKR

[22 , 30, 31, 32]

[22, 30, 31, 32, 33, 34]

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 12 of 23

Notes:

35. W2 updates the flag to the Almost Full state by asserting PAFE. Because R1 occurs greater than tSKEW1 after W2, W2 does not recognize R1 when

updating fla g status. W3 i ncludes R2 in the f lag update beca use R2 occurs great er than tSKEW2 before W3. N ote that W3 does not have to be enabled

to update flags.

36. The d ashed lines show W3 as a flag update write rather than an enabled write b ecause ENW is HIGH.

Switching Waveforms (continued)

Write to Almost Full TimingDiagram

2030 2031 2031 2032

tFD tFD

tFD

ENABLED

WRITE ENABLED

WRITE

2032 2031 [1017] 2033

[1017] [1018] [1017] [495] [496] [497]

ENABLED

WRITE

2030

[1016]

W1 W2 W3 W4

2030 [1016]

[494] 2031 [1017]

[495] 2032 [1018]

[496]

ENABLED

READ ENABLED

READ

R1 R2

tSKEW1 tSKEW2

tFD

LOW

HIGH

ENW

PAFE

ENR

E/F

Write to Almost Full TimingDiagram with Free-RunningClocks

tSKEW1 tSKEW2

tFD tFD

tFD

ENABLED

WRITE ENABLED

WRITE

ENABLED

READ ENABLED

READ

c455-17

ENW

ENR

PAFE

E/F

c455-18

HIGH

LOW

W1 W2 W3 W4 W5 W6

R2 R3 R6

R5R4R1

[1016]

FLAG UPDATE

[494] [495] [496] [495] [494]

2031

[1017]

[495]

2032

[1018]

[496]

2031

[1017]

[495]

2030

[1016]

[494]

2031

[1017]

[495]

2032

[1018]

[496]

2033

[1019]

[497]

COUNT

CKW

CKR

LOW

COUNT

CKW

CKR

[22, 27, 30]

[22, 27, 30, 35, 36]

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 13 of 23

Note:

37. W2 is ignored because the FIFO is full (count = 2,048 [1,024] [512]). It is important to note that W3 is also ignored because R3, the first enabled read after

full, occurs less than tSKEW2 before W3. Therefore, the FIFO still appears full when W3 occurs. Because R3 occurs greater than tSKEW2 before W4,

W4 includes R3 in the flag update.

Switching Waveforms (continued)

Write to Almost Full Timing Diagram with Write Flag Update Cycle and Free-Running Clocks

2031 2032 2030 2032

tSKEW1 tSKEW2

tFD tFD

tFD

ENABLED

WRITE FLAG

UPDATE ENABLED

WRITE ENABLED

WRITE

2031 2031 2033

c455-19

ENABLED

WRITE

ENABLED

READ ENABLED

READ

WRITE

FLAG UPDATE CYCLE

[1017] [1018] [1017] [1016] [1017] [1018] [1019]

ENW

ENR

PAFE

E/F

Write to Full Flag Timing Diagram with Free-Running Clocks

tSKEW1 tSKEW2

tFD tFD

tFD

2047 2048 2047 2048

ENABLED

WRITE ENABLED

WRITE

ENABLED

READ

ENW

ENR

PAFE

E/F

FLAG

UPDATE IGNORED

WRITE

c455-20

IGNORED

WRITE IGNORED

WRITE WRITE

[1023] [1024] [1023] [1024]

LATENT CYCLE

HIGH

LOW

W1 W2 W3 W4 W5 W6 W7

R2 R3 R6

R5R4R1

R4 R5 R6 R7

R2 R3

W1 W2 W3 W4 W5 W6

2030 [1016]

tSKEW2

[495] [496] [495] [494]

[494] (no change)

[495] [496] [497]

[511] [512] [511] [512]

2048

[1024]

[512]

COUNT

CKW

CKR

COUNT

CKW

CKR

2048

[1024]

[512]

[22 , 27, 30]

[22, 30, 37]

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 14 of 23

Notes:

38. In this example, the FIFO is assumed to be programmed to generate even parity . The Q0−7 word is shown. The example is similar for the Q9-16 word.

39. If Q0−7 “new word” also has an even number of 1s, then PG1 stays LOW.

40. If Q0−7 “new word” also has odd number of 1s, then PG1 stays HIGH.

Switching Waveforms (continued)

EvenParity GenerationTimingDiagram

tPG

PREVIOUS WORD:

EVEN NUMBER OF 1s NE W WO RD:

ODD NUMBER OF 1s

CKR

Q0−7

(Q9−16)

PE1,(PE

ENR

ENABLED READ DISABLED READ

c455-21

PREVIOUS WORD:

ODD NUMBER OF 1s NE W WO RD:

EVEN NUMBER OF 1s

ENABLED READ DISABLED READ

EvenParity GenerationTimingDiagram

tPG

CKR

ENR

c455-22

Q0−7

(Q9−16)

PE1,(PE

[38, 39]

[38, 40]

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 15 of 23

Notes:

41. In this example, the FIFO is assumed to be programmed to check for even parity. The Q0-7 word is show n.

42. This example assumes that the time from the CKR rising edge to valid word M+1 > tA. The Q0-7 word is sh own.

43. If ENR was HIG H around t he ris ing edge of C KR (i .e ., read di sabled), t he val id dat a at the f ar r igh t woul d o nce again be w ord M ins tea d of word M+1.

44. Clocks are free running in this case.

45. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.

Switching Waveforms (continued)

Even ParityChecking

Outp ut Enable Timing

WRITE M

c455-23

READ M

WRITE M+1 WRITE M+2

WORD M+ 1:

ODD NUMBER

OF 1“s

WORD M+ 2:

EVEN NUMBER

OF 1“s

READ M+1 READ M+2

tPE tPE

8 LSBs OF

WORD M+2

8 LSBs OF

WORD M+1

8 LSBs OF

WORD M

8 LSBs OF

WORD M-1

PE1

(PE2)

ENW

ENR

D0−7

Q0−7

(Q9−16)

VALID DATA

WORD M

READ M+1

CKR

Q0−17

ENR

tOHZtOE

tOLZ

VALID DATA

WORD M+1

c455–24

LOW

WORD M:

EVEN NUMBER

OF 1“s

CKW

CKR

[41]

[42, 43]

Retransmit Timing

REN/WEN

FL/RT tPRT

tRTR

42X5–21

E/F, HF, PAFE

[44, 45]

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 16 of 23

Architecture

The CY7C455/6/7 consists of an array of 512, 1024, or 2048

words of 18 bits each (implemented by a dual-port array of

SRAM cells), a read pointer, a write pointer, control signals

(CKR, CKW , ENR, ENW, and MR), and flags (HF, E/F, P AFE).

The CY7C455/6/7 also includes the control signals OE, FL, XI,

and XO for depth expansion.

Resetting the FIFO

Upon power-up, the FIFO must be reset with a Master Reset

(MR) cy cle. This ca uses the F IFO to ente r the Empty condition

signified by E/F and PAFE being LO W and HF being HIG H. All

data outputs (Q0−17) go low at the rising edge of MR. In order

for the FIFO to reset to its default state, a falling edge must

occur on MR and the user must not read or write while MR is

LOW (unless ENR and ENW are H IGH or unle ss the devi ce is

being programmed). Upon completion of the master reset cy-

cle, all data outputs w il l g o LO W tAMR after MR is deasserted.

All flags are guaranteed to be valid tMRF after MR is taken

HIGH.

FIFO Operation

When the ENW signal is active (LOW), data present on the

D0−17 pins is written into the FIFO on each rising edge of the

CKW signal. Similarly, when the ENR signal is active, data in

the FIFO memory will be presented on the Q0−17 outpu ts. New

dat a will be p r es ent ed o n ea ch rising edge of CK R w hil e ENR

is active. ENR must s et up tSEN before CKR for it t o be a valid

read. ENW must occur tSEN before CKW for it to be a valid

write.

An outpu t enab le (OE) pi n is provid ed to three-st ate the Q 0−17

outputs when OE is asserted . When OE is enabled (low), data

in the output register will be available to the Q0−17 outputs after

tOE. If devices are cascaded, the OE functi on wi ll on ly ou tpu t

data on the FIFO that is read enabled.

The FIFO contains overflow circuitry to disallow additional

writes when the FIF O is f ull, and unde rflow circuitry to disallow

additional reads when the FIFO is empty. An empty FIFO

maintai ns the data of th e last val id read on its Q0–17 outputs

even after additional reads occur.

Programming

The CY7C455/6/7 is programmed during a maste r reset cycle.

If MR and ENW ar e LOW, a rising ed ge on CK W wi ll w ri te th e

D0−7,8,or9 and D15–17 inputs into the pr og ram mi ng regi ste r[46].

MR must be set up a minimum of tSMRP before the program

write ris ing edge and h eld tHMRP after the pro gram write fallin g

edge. Th e us er has the ab ili ty to a ls o pe rform a pro gram rea d

during th e master res et cycle. This will occur at the rising edge

of CKR when MR and ENR are asserted. The program read

must be perform ed a minim um of tFTP after a program write,

and the program word will be available tAP after the read oc-

curs. If a program write does not occur, a program read may

occur a minimum of tSMRP after MR is ass ert ed. This will rea d

the default program value.

When free- running clocks are tied to CKW and CKR, program-

ming can still occur during a master reset cycle with the adh er-

ence to a few additional timing parameters. The enable pins

must be set-up tSEN before the rising edge of CKW or CKR.

Hold times of tHEN must also be met for ENW and ENR.

Data present on D0−9 during a prog ram write will determine th e

dist ance from Empty (Full) that the Almost Empty (Almost Full)

flags will become active. See Table 1 f or a descr iption of the

six possible FIFO states. P in Table 1 refers to the decimal

equivalent of the binary number represented by D0−7, 8 or 9.

Programming options for the CY7C455/6/7 are listed in

Table 4.

The programmable P AFE function on the CY7C455/6/7 is only

valid whe n not cas caded. If th e user el ect s not to p rogram th e

FIFO’s flags, the default is as follows: the Almost Empty con-

dition (Almost Full condition) is activated when the FIFO con-

tains 16 or less words (empty locations).

Parity is programmed with the D15−17 bits. See Table 4 for a

summary of the various parity programming options. Data

present on D15−17 during a program write will determine

whether the FIFO will generate or check even/odd parity for

the data present on D0−7 and D9−16 thereafter. If the user

elect s no t to pro gram th e FIFO , the p ari ty fun ction is disab led.

Flag operation and parity are described in greater detail in sub-

sequent sections.

Flag Operation

The CY7C455/6/7 provides three status pins when not cas-

caded. The three pins, E/F, PAFE, and HF, allow decoding of

six FIFO states (Table 1). PAFE is not available when the

CY7C455/6/7 is cascaded for depth expansion. All flags are

synchronous, meaning that the change of states is relative to

one of the cl ocks (CKR or CKW, as appro priate).[47] T he Emp-

ty and Almost Empty flag states are exclusively updated by

each rising edge of the read clock (CKR). For example, when

the FIFO contains 1 word, the next read (rising edge of CKR

while ENR=LOW) causes the flag pins to output a state that

represents Empty. The Half Full, Almost Full, and Full flag

states are updated exclusively by the write clock (CKW). For

example, if the CY7C457 contains 2,047 words (2,048 words

indicate Full for the CY7C457), the next write (rising edge of

CKW while ENW=LOW) causes the flag pi ns to out put a st ate

that is decoded as Full.

Since the flags denoting emptiness (Empty , Almost Empty) are

only updated by CKR and the flags signifying fullness (Half

Full, Almost Full, Full) are exclusively updated by CKW, careful

attention must be given to the flag operation. The user must

be aware that if a boundary (Empty, Almost Empty, Half Full,

Almost Full, or Full) is crossed due to an operation from a clock

that the flag is not synchronized to (i.e., CKW does not affect

Empty or Almost Empty), a flag update cycle is necessary to

represent the FIFO’s new state. The signal to which a flag is

not synchronized will be referred to as the opposite clock

(CKW is opposite clock for Empty and Almost Empty flags;

CKR is the opposite clock for Half Full, Almost Full, and Full

flags). Until a proper flag update cycle is executed, the syn-

chronous flags will not show the new state of the FIFO.

Notes:

46. CKW will write D0–9 into the programming register. CKR will read D0–9 during a programming regist er read.

47. The synchronous architecture guarantees the flags valid for approximately one cycle of the clock they are synchronized to.

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 17 of 23

When updating flags, the FIFO must make a decision as to

whether or not the opposite clock was recognized when a

clock updates the flag. For example (when updating the Empty

flag), if a write occurs at least tSKEW1 after a read, the write is

guaranteed not to be included when CKR updates the flag. If

a write occurs at least tSKEW2 before a read, the write is gu ar-

anteed to be included when CKR updates flag. If a write occurs

within tSKEW1 after or tSKEW2 befo re CKR, then the deci sion of

whethe r or not to incl ude the writ e when the flag is updated b y

CKR is arbitrary.

The update cycle for non-boundary flags (Almost Empty, Half

Full, Almost Full) is different from that used to update the

boundary flags (Empty, Full). Both operations are described

below.

Boundary and Non-Boundary Flags

Boundary Flags (Empty)

The Empty flag is synchronized to the CKR signal (i.e., the

Empty flag can only be updated by a clock pulse on the CKR

pin). An empty FIFO that is writ ten to will be d escribed wit h an

Empty flag state until a rising edge is presented to the CKR

pin. When making the transition from Empty to Almost Empty

(or Empty to Less than or Equal to Half Full), a clock cycle on

CKR is necessary to update the flags to the current state. In

such a s tate (flags showing Empty even though d ata has been

written to the FIFO), two read clock cycles are required to read

data out of the FIFO. The first read serves only to update the

flags to the Almost Empty or Less than or Equal to Half Full

state, while the second read outputs the data. This first read

cycle is known as the latent or flag update cycle because it

does not affect the data in the FIFO or the count (number of

words i n FIFO). It simply de assert s th e Empty fl ag. The fl ag is

updated regardless of the ENR state. Therefore, the update

occu rs even whe n ENR is deasserted (HIGH), so that a valid

read is not ne cess ary to upd ate the fla gs to corr ect ly describ e

the FIFO. In this examp le, the write m ust occur at le ast tSKEW2

befor e the fla g update cycle in order fo r the FIFO t o guar antee

that the w rite wi ll b e inc lu ded in th e co unt w h en CK R upd ates

the flags. When a free-runnin g clock is conne cted to CKR , the

flag is updated each cycle. Table 2 shows an example of a

sequence of operations that update the Empty flag.

Boundary Flags (Full)

The Full flag is synchronized to the CKW signal (i.e., the Full

flag can on ly be upd ate d by a clo ck pul se on the C KW pi n). A

full FIFO that is read will be described with a Full flag until a

rising edge is presented to the CKW pin. When making the

transiti on from Fu ll to Al most Full (o r Full to Grea ter Tha n Half

Full ), a clock cycl e on CKW is nece ssary to upd ate the fla gs

to th e curr ent state . In such a state (flags showin g Full even

through data has been read from the FIFO), two write cycles

are required to write data into the FIFO. The first write serves

only to update the fla gs to the Almost Full or Greater Than Half

Full state, while the second write inputs the data. This first write

cycle is known as the latent or flag update cycle because it

does not affect the data in the FIFO or the count (number of

words in the FIFO). It simply deasserts the Full flag. The flag

is upd ated regardle ss of the ENW st ate. Therefore, the update

occurs even when ENW is deasserted (HIGH), so that a valid

write is no t necessary to upd ate the flags to cor rectly desc ribe

the FIFO . In this e xample, the read must occur at least tSKEW2

before th e flag u pdate cy cle in order for th e FIFO t o guarantee

that the read w ill be inc luded in the coun t when CKW upd ates

the flags . When a free-runnin g clock is connec ted to CKW , the

flag updates each cycle. Full flag operation is similar to the

Empty flag operation described in Table 2.

Non-Boundary Flags (Almost Empty, Half Full, Almost Full)

The CY7C455/6/7 features programmable Almost Empty and

Almost Full flags. Each flag can be programmed a specific

distance from the corresponding boundary flags (Empty or

Full). The flags can be programmed to be activated at the

Empty or Full boundary, or at any distance from the Empty/Full

boundary. When the FIFO contains the number of words or

fewer for which the flags have been programmed, the PAFE

flag will be asserted signifying that the FIFO is Almost Empty.

When th e F IFO is within that same numbe r of em pty locati ons

from being Ful l, the PAFE will also be asserted signifying that

the FIFO is Alm ost Fu ll. The HF flag is d ec ode d to distingu is h

the states.

The default distance from whe re PAFE become s ac tiv e to the

boundary (Emp ty, Full) is 16 wo rds/ locations. Th e Almos t Ful l

and Almost Empty flags can be programmed so that they are

only active at Full and Empty boundaries. However, the oper-

ation w i ll rem ai n c on si ste nt with th e non-bou nda ry fla g opera-

tion that is discussed below.

Table 1. Flag Truth Ta ble[48]

E/F PAFE HF State 7C455

Words in FIFO 7C456

Words in FIFO 7C457

Words in FIFO

0 0 1 Empty 000

1 0 1 Almost Empty 1 => P 1 => P 1 => P

1 1 1 Less than or Equal to Half Full P + 1 => 256 P + 1 => 512 P + 1 => 1024

1 1 0 Greater than Half Full 257 => 511 – P 513 => 1023 – P 1025 => 2047 – P

1 0 0 Almost Full 512 – P => 511 1024 – P => 1023 2048 – P => 2047

0 0 0 Full 512 1024 2048

Notes:

48. P is the decimal value of the binary number represented by D0–7 for the CY7C455, D0–8 for the CY7C456, and D0–9 for the CY7C457. P = 0 signifies

that the Almost Empty state = Empty state.

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 18 of 23

Almost Empty is only updated by CKR while Half Full and Al-

most Full are updated by CKW. Non-boundary flags employ

flag update cycles si mi lar to the boun da ry flag laten t cy cl es in

order t o up dat e th e FIFO sta tus . For example , if t he F IFO jus t

reaches the Greater than Half Full state, and then two words

are r ead f rom the FIFO , a wri te clo ck (C KW) wil l be r equi red

to update the flags to the Less than Half Full state. However,

unlike the boundary flag latent cycle, the state of the enable

pin (ENW in this case) affects the operation. Therefore, set-up

and hold times for the enable pins must be met (tSEN and

tHEN). If the enable pin is active during the flag update cycle,

the cou nt a nd data are updated in add iti on to PAFE and HF. If

the enable pin is not asserted during the flag update cycle, only

the flags are updated. Table 3 shows an example of a se-

quence of operations that update the Almost Empty and Al-

most Full flags

The CY7C455/6/7 also features even or odd parity checking

and generation. D15–17 are used during a program write to

desc ribe the pa rity opti on desired . Table 4 summariz es pro-

grammable parity options. If the user elects not to program

the device, t hen parity is disabl ed. Parity i nformatio n is pro-

vided on two multi-mode output pins (Q8/PG1/PE1 and

Q17/PG2/PE2). The three possible modes are descri bed in

the f ol lo w ing par ag rap hs .

Programmable Parity

Par ity Disabled (Q8/Q17 mode)

When parity is disabled (or the user does not program parity

option) the FIFO stores all 18 bits present on D0–17 inputs

internally and will output all 18 bits on Q0–17.

Parity Generate (PG mode)

This mode is used to generate either even or odd parity (as

programmed) from D0–7 and D9–16. D8 and D17 inputs are

ignore d. The p arity bit s ar e sto red in terna lly as D8 and D17,

and during a subsequent read will be av ailable on the PG1

and PG2 pins along with the data words from which the

pari ty was gen erated (Q0–7 and Q9–16). For exam ple, if par-

ity generate is set to ODD and the D0–7 inputs have an

EVEN n umber of 1s, P G1 will be HIGH .

Parity Check (PE mode )

If the FIFO is programmed for parity checking, it will compare

the parity of D0–8 and D9–17 with the program register. For

examp le, D8 and D17 will be set according to the result of

the parity check on each word. When these words are later

read, PE1 and PE2 will re flec t the re sult of the p ari ty chec k.

If a p arity erro r occurs in D 0–8, D8 will be set LOW internally .

When this word is lat er re ad, P E1 will be LOW.

Retransmit

The retransm it feat ure is ben eficial when tran sfe rrin g pa ckets

of data. It enables the receipt of data to be acknowledged by

the receiver and retransmitted if necessary.

The Retransmit (RT) input is active in the standalone and width

expansion modes. The retransmit feature is intended for use

when a numb er of wr ites equal to or less tha n the d ept h of th e

FIFO h ave occurre d since the last M R cycle. A LOW pulse on RT

resets the internal read pointer to the first physical location of the

FIFO. WCLK and RCLK may be free running but must be disabled

during and tRTR after the retransmit pulse. With every valid read cycle

after retransmit, previously accessed data is read and the read point-

er is incremented until it is equal to the write pointer. Flags are gov-

erned by the relative locations of the read and write pointers and are

updated during a retransmit cycle. Data written to the FIFO after ac-

tivation of RT are transmitted also.

The full depth of the FIFO can be repeatedly retransmitted.

Table 2. Empty Flag (Boundary Flag) Operation Example

Status Before Operation Status After Operation

Current

State of

FIFO E/F AFE HF

Number

Words

in FIFO Operation

State

of FIFO E/F AFE HF

Number

Words

in FIFO Comments

Empty 0 0 1 0 Write

(ENW = 0) Empty 0 0 1 1 Write

Empty 0 0 1 1 Write

(ENW = 0) Empty 0 0 1 2 Write

Empty 0 0 1 2 Read

(ENR = X) AE 1 0 1 2 Flag Update

AE 1 0 1 2 Read

(ENR = 0) AE 1 0 1 1 Read

AE 1 0 1 1 Read

(ENR = 0) Empty 0 0 1 0 Read (tran sit ion from

Almost Empty to Empty)

Empty 0 0 1 0 Write

(ENR = 0) Empty 0 0 1 1 Write

Empty 1 0 1 1 Read

(ENR = X) AE 1 0 1 1 Flag Update

AE 1 0 1 1 Read

(ENR = 0) Empty 0 0 1 0 Read (tran sit ion from

Almost Empty to Empty)

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 19 of 23

Width Expansion Modes

During width expansion all flags (programmable and nonpro-

grammable) are available. These FIFOs can be expanded in

width to provide word width greater than 18 in increments of

18. During width expansion mode all control line inputs are

common. When the FIFO is being read near the Empty (Full)

boundary, it is important to note that both sets of flags should

be chec ked to see if the y have been upd ated to the Not Empt y

(Not Full) condi tion to in sure th at the next re ad (write ) will per-

form the same operation on all devic es .

Checking all sets of flags is critical so that dat a is not read from

the FIFOs “staggered” by one clock cycle. This situation could

occur when the first write to an empty FIFO and a read are very

close together. If the read occurs less than tSKEW2 after the

first wri te t o t wo widt h-ex panded dev ices, A an d B , d evice

A may go Almost Empty (read recognized as flag update)

whil e devi ce B s ta ys Emp ty (re ad ig nored ). T his oc curs be-

cause a read can be either recognized or ignored if it oc-

curs within tSKEW2 of a write. The next read cycle outputs

the first half of the first word on device A while device B

updates its flags to Almost Empty. Subsequent reads will

continue to output “staggered” data assuming more data

has been writ ten t o FIFOs.

Depth Expansion Mode

The CY7C 45 5/6/ 7 can opera te up to 83.3 MHz when cas ca d-

ed. Depth expansion is accomplished by connecting expan-

sion o ut (XO ) of the first device to expansion in (XI) of the

next d evice, with XO of the last device connected to XI of

the first device. The first device has its first load pin (FL)

tied to VSS while all other devices must have this pin tied

to VCC. T he fir st de vice wi ll be th e first t o b e write an d r ea d

enable d aft er a maste r reset .

Proper ope ration a lso requir es that all casc aded dev ices hav e

common CKW, CKR, ENW, ENR, D0–17, Q0–17, and MR

pins. When cascaded, one device at a time will be read

enabled so as to avoid bus contention. By asserting XO

when appropriate, the currently enabled FIFO alerts the

next F IFO tha t it shou ld be en abled. Th e next r ising ed ge

on CKR puts Q0–17 output s of the fi rst device into a hig h-im-

pedance state. This occurs regardless of the state of ENR

or the next FIFO’s Empty flag. Therefore, if the next FIFO

is emp ty or u nd erg oi ng a la te nt cy cl e, the Q0–17 bus will be

in a high-imp ed an ce state until the nex t de vice receives its

first read, which brings its data to the Q0–17 bus.

Program Write/Read of Cascaded Devices

Programming of cascaded FIFOs is the same as for a single

device. Because the controls of the FIFOs are in parallel when

cascaded , they all get programme d the same. During program

mode, only parity is programmed since Almost Full and Almost

Empty flags are not available when CY7C455/6/7 is cascaded.

Only the “first device” (FIFO with FL=LOW) will output its

progr am regist er conten ts on Q0–7 during a program read.

Q0–17 of all ot her devices will re main in a high- impedance

state to avoid bus contention.

Figure 1. Depth Expansion with CY7C455/6/7

DATA IN DATA OUT

D0–17

CKW

ENW

Q0–17

CKR

ENR

Q0–17

D0–17

MR PAFE/XO

VCC

VSS

E/F

FL/RT

CY7C455,6,7

CKW CKR

ENRENW

FULL EMPTY

D0–17

CKW

ENW

Q0–17

CKR

ENR

PAFE/XO

E/F

FL/RT

CY7C455,6,7

c455-25

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 20 of 23

Table 3. Almost Empty Flag (Non-Boundary Flag) Operation Example[49]

Status Before Operation Stat us Aft er Operation

Current

St ate of FIFO E/F AFE HF

Number

Words

in FIFO Operation Next State

of FIFO E/F PAF

EHF

Number

of words

in FIFO Comments

AE 101 32 Write

(ENW = 0) AE 101 33 Write

AE 101 33 Write

(ENW = 0) AE 101 34 Write

AE 101 34 Read

(ENR = 0) <HF 111 33 Flag Update and

Read

<HF 111 33 Read

(ENR = 1) <HF 111 33 Ignored Re ad

(ENR = 1)

<HF 111 33 Read

(ENR = 0) AE 101 32 Rea d (trans ition from

<HF to AE)

Table 4. Programmable Parity Options

D17 D16 D15 Condition

0 X X Parity disabled.

100Generate even parity on PG output pin.

101Genera te odd p ari ty on PG output pin .

110Check for even parity. Indicate error on PE outp ut pi n.

111Check for odd parity. Indicate error on PE output pin.

Note:

49. Applies to CY7C455/6/7 operations when devices are programmed so that Almost Empty becomes active when the FIFO contains 32 or fewer words.

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 21 of 23

Ordering Information

512x18 Clocked FIFO

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

12 CY7C455–12JC J69 52-Lead Plas tic Lead ed Ch ip Carrier Commercial

CY7C455–12NC N52 52-Pin Plastic Quad Flatpack

CY7C455–12JI J69 52-Lead Plas tic Lead ed Ch ip Carrier Industrial

14 CY7C455–14JC J69 52-Lead Plas tic Lead ed Ch ip Carrier Commercial

CY7C455–14NC N52 52-Pin Plastic Quad Flatpack

CY7C455–14JI J69 52-Lead Plas tic Lead ed Ch ip Carrier Industrial

20 CY7C455–20JC J69 52-Lead Plas tic Lead ed Ch ip Carrier Commercial

CY7C455–20NC N52 52-Pin Plastic Quad Flatpack

CY7C455–20JI J69 52-Lead Plas tic Lead ed Ch ip Carrier Industrial

30 CY7C455–30JC J69 52-Lead Plas tic Lead ed Ch ip Carrier Commercial

CY7C455–30NC N52 52-Pin Plastic Quad Flatpack

CY7C455–30JI J69 52-Lead Plas tic Lead ed Ch ip Carrier Industrial

1Kx18 Clocked FIFO

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

12 CY7C456–12JC J69 52-Lead Plas tic Lead ed Ch ip Carrier Commercial

CY7C456–12NC N52 52-Pin Plastic Quad Flatpack

CY7C456–12JI J69 52-Lead Plas tic Lead ed Ch ip Carrier Industrial

14 CY7C456–14JC J69 52-Lead Plas tic Lead ed Ch ip Carrier Commercial

CY7C456–14NC N52 52-Pin Plastic Quad Flatpack

CY7C456–14JI J69 52-Lead Plas tic Lead ed Ch ip Carrier Industrial

20 CY7C456–20JC J69 52-Lead Plas tic Lead ed Ch ip Carrier Commercial

CY7C456–20NC N52 52-Pin Plastic Quad Flatpack

CY7C456–20JI J69 52-Lead Plas tic Lead ed Ch ip Carrier Industrial

30 CY7C456–30JC J69 52-Lead Plas tic Lead ed Ch ip Carrier Commercial

CY7C456–30NC N52 52-Pin Plastic Quad Flatpack

CY7C456–30JI J69 52-Lead Plas tic Lead ed Ch ip Carrier Industrial

2Kx18 Clocked FIFO

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

12 CY7C457–12JC J69 52-Lead Plas tic Lead ed Ch ip Carrier Commercial

CY7C457–12NC N52 52-Pin Plastic Quad Flatpack

CY7C457–12JI J69 52-Lead Plas tic Lead ed Ch ip Carrier Industrial

14 CY7C457–14JC J69 52-Lead Plas tic Lead ed Ch ip Carrier Commercial

CY7C457–14NC N52 52-Pin Plastic Quad Flatpack

CY7C457–14JI J69 52-Lead Plas tic Lead ed Ch ip Carrier Industrial

20 CY7C457–20JC J69 52-Lead Plas tic Lead ed Ch ip Carrier Commercial

CY7C457–20NC N52 52-Pin Plastic Quad Flatpack

CY7C457–20JI J69 52-Lead Plas tic Lead ed Ch ip Carrier Industrial

30 CY7C457–30JC J69 52-Lead Plas tic Lead ed Ch ip Carrier Commercial

CY7C457–30NC N52 52-Pin Plastic Quad Flatpack

CY7C457–30JI J69 52-Lead Plas tic Lead ed Ch ip Carrier Industrial

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 22 of 23

of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi

ng so indemnifies Cypress Semiconductor against all charges.

Package Diagrams

52-LeadPlasticLeadedChipCarrier J69

52-LeadPlasticQuadFlatpackN52

CY7C455

CY7C456

CY7C457

Document #: 38-06003 Rev. *A Page 23 of 23

Document Title: CY7C455, CY7C456, CY7C457 512 X 18, 1K X 18 and 2K X 18 Cascadable Clocked Fifo’s with Pro-

grammable Flags

Document Number: 38-06003

REV. ECN NO. Issue

Date Orig. of

Change Description of Change

** 106464 07/11/01 SZV Change from Spec Number: 38-00211 to 38-06003

*A 122256 12/26/02 RBI Power up requirements added to Maximum Ratings Information