PGOOD is delayed from either power-up or VIN under-volt-
age lockout, and has three primary factors:
1) A synchronization delay, set to 2 ms after the slowest
controller in the system recognizes a valid level on EN, VCC
and VDD. This delay is timed out internally and allows for the
phase lock loops to synchronize.
2) TRACK up, in non-fault conditions.
3) Transition period from diode emulation mode to fully
synchronous operation, set to 2 ms.
CURRENT SENSE and CURRENT LIMIT
The LM3753 senses current to enforce equal current sharing
and to protect against over-current faults. There are two sys-
tem options for sensing current; a current-sense resistor, or
a DCR configuration which uses the DC resistance of the in-
ductor. The current-sense resistor is more accurate but less
efficient than the DCR configuration.
The input range of the differential current-sense signal (CS1
(2) – CSM) is from −15 mV to +40 mV. The common mode
range is the same as the controller’s output range which is 0V
to 3.6V. Two considerations determine the value of the cur-
rent-sense resistor. If the resistor is too large there is an
efficiency loss. If it is too small the current-sense signal to the
controller will be too low. Choose a resistor that gives a full
load current-sense signal of at least 25 mV. This is typically
a resistor in the 1 mΩ to 2 mΩ range. The current-sense re-
sistor is inserted between the inductor and the load. The load
side of the resistor which is VOUT, is connected to CSM, the
negative current-sense input. This is the negative current-
sense reference for both phases. The positive side of the
current-sense resistor goes to CS1(2).
For the DCR configuration a series resistor-capacitor combi-
nation is substituted for the current-sense resistor. The resis-
tor connects to the switch node (SW) and the capacitor
connects to VOUT. CSM is connected to VOUT as with the
sense resistor. CS1(2) is connected to the center point of the
resistor and capacitor, so that the current-sense signal is de-
veloped across the capacitor. The voltage across the capac-
itor is a low pass filtered version of the voltage across the
resistor-capacitor combination, in the same way the current
through the inductor is a low pass filtered version of the volt-
age applied across the inductor and its intrinsic series resis-
tance. Choose the DCR time constant (RDCR x CDCR) to be
1.0 to 1.5 times the inductor time constant (L / RL). RDCR is
selected so that the CS pin input bias current times RDCR does
not cause a significant change in the CS voltage. The inductor
time constant and the DCR time constant will skew over tem-
perature since the components have different temperature
coefficients. Critical applications may employ a correction cir-
cuit based on a positive temperature coefficient thermistor
(PTC).
The over-current limit is set by placing a resistor between ILIM
and CSM. The value of the resistor times the ILIM current of
94 µA sets the over-current limit.
CURRENT SHARING and CURRENT AVERAGING
The current sharing works by adjusting the duty cycle of each
phase up or down to make the phase current equal to the
average current. The maximum duty cycle shift is ±20%.
To determine the average current, each phase sources a cur-
rent onto the IAVE bus proportional to its load current as
measured by the current sense amplifier connected to the
CS1(2) and CSM pins. The IAVE pins of all controllers are
connected together and a resistance of 8 kΩ per phase (par-
allel) to SGND provides the proper voltage level for the IAVE
bus. Each phase compares its current sense output to the
IAVE bus and sums the resultant voltage into the common
COMP signal to adjust the duty cycle for optimum current
sharing.
IAVE forms the current sharing bus for the entire power con-
verter. The IAVE pins of all controllers must be connected
together. Filter capacitors with a time constant of RAV x CAV =
1 / fSW are connected between IAVE and SGND of each con-
troller. The parallel combination of the filter capacitors times
the summing resistors (one set per controller) forms the time
constant of the current sharing bus.
ERROR AMPLIFIER and LOOP COMPENSATION
The LM3753 uses a voltage mode PWM control method. This
requires a TYPE III or 3 pole, 2 zero compensation for opti-
mum bandwidth and stability. The error amplifier is a voltage
type operational amplifier with 70 dB open loop gain and unity
gain bandwidth of 15 MHz. This allows for sufficient phase
boost at high control loop frequencies without degrading the
error amplifier performance.
The error amplifier output COMP connections are different for
Master and Slave controllers. For the Master, a compensation
network is placed between the COMP pin and the FB pin. The
COMP pin of the Master is connected to the SNSP pin of each
Slave. The SNSM pin of each Slave is connected to the bot-
tom of the Master feedback divider at SGND. The COMP pin
of each Slave is connected to its corresponding VDIF pin. This
provides sufficient buffering of the master COMP signal for
the internal summing of the current averaging circuit.
OSCILLATOR and SYNCHRONIZATION
A resistor and decoupling capacitor are connected between
FREQ and SGND to program the switching frequency be-
tween 200 kHz to 1 MHz. These components must be sup-
plied on each controller, even if the system is synchronized
to an external clock.
The switching frequency and synchronization are controlled
by the Master. The Master can switch in a free-running mode
or be synchronized to an external clock. To synchronize the
Master apply the external clock to the SYNC pin of the Master,
otherwise ground this pin. The amplitude of the signal on the
SYNC pin must be limited to be between 0V and VCC.
The value of the frequency setting resistor is determined as:
A 1000 pF ceramic capacitor is used to provide sufficient de-
coupling. If the Master is synchronized set the resistor ac-
cording the nominal applied frequency. If the signal on the
SYNC pin is below 150 kHz the signal will be ignored and the
device will revert to free-running mode. The SYNCOUT signal
from the Master is applied to the first Slave’s SYNC pin. The
SYNCOUT pin of the first Slave is connected to the SYNC pin
of the second Slave, and so on, in a daisy chain configuration.
SYNCOUT of the last Slave (or the Master in a single con-
troller system) is left unconnected.
The configuration of the system, namely the number of con-
trollers and phases is programmed by the voltage on the PH
pin. For each controller connect the midpoint of a resistor di-
vider between VCC and SGND to the PH pin. The division
ratios are given in the Electrical Characteristics table and
nominal resistor values in Table 1. This sets the phase shift
between SYNC and the SYNCOUT pin. Where an even num-
ber of phases (N) are employed, the phase delay from SYNC
17 www.ti.com
LM3753