FA3687V
1
■ Block diagram
FA3687V
■ Dimensions, mm
TSSOP-16
■ Description
FA3687V is a PWM type DC-to-DC converter control IC with
2ch outputs that can directly drive po w er MOSFETs . CMOS
de vices with high breakdo wn voltage are used in this IC and
low po w er consumption is achieved. This IC is suitable f or very
small DC-to-DC converters because of their small and thin
package (1.1mm max.), and high frequency operation (up to
1.5MHz). You can select Pch or Nch of MOSFETs driv en, and
design any topology of DC-to-DC converter circuit lik e a b uc k, a
boost, inv erting, a fly-back, or a f orw ard.
■ Features
• Wide range of supply voltage: VCC=2.5 to 20V
• MOSFET direct driving
• Selectable output stage for Pch/Nch MOSFET on each
channel
• Low oper ating current b y CMOS process: 2.5mA (typ.)
• 2ch PWM control IC
• High frequency operation: 300kHz to 1.5MHz
• Simple setting of operation frequency by timing resistor
• Soft start function at each channel
• Adjustable maxim um duty cycle at each channel
• Built-in undervoltage lock out
• High accuracy reference voltage: VREF: 1.00V±1%
VREG: 2.20V±1%
• Adjustable built-in timer latch for short-circuit protection
• Thin and small pac kage: TSSOP-16
CMOS IC
For Switching Power Supply Control
Pin No. Pi n symbol Description
1 CP Timer latched shor t circuit protection
2 SEL2 Selection of type of driven MOSFET (OUT2)
3 FB2 Ch.2 output of error amplifier
4 IN2– Ch.2 inverting input to error amplifier
5 IN2+ Ch.2 non-inverting input to error amplifier
6 VCC Power supply
7 CS2 Soft star t for Ch.2
8 OUT2 Ch.2 output
9 OUT1 Ch.1 output
10 CS1 Soft star t for Ch.1
11 GND Ground
12 RT Oscillator timing resistor
13 VREG Regulated voltage output
14 IN1– Ch.1 inverting input to error amplifier
15 FB1 Ch.1 output of error amplifier
16 SEL1 Selection of type of driven MOSFET (OUT1)
18
9
16
0~8˚
0.65
6.4
±0.2
0.105 to
0.145
4.4
5
0.22
±0.02
0.5
±0.08
1.1max
0.10
±0.05
FA3687V
2
Maximum power dissipation curve
■ Recommended operating condition
Item Symbol Test condition Min. Typ. Max. Unit
Supply voltage VCC 2.5 18 V
CS1, CS2, CP pin voltage VCTR_IN 0.0 2.5 V
SEL1, SEL2 pin voltage VSEL_IN 0.0 2.5 V
IN1–, IN2–, IN2+ pin voltage VEA_IN 0.0 2.5 V
Oscillation frequency fOSC 300 500 1500 kHz
VREG pin capacitance CREG Vcc<10V 0.1 1.0 4.7 µF
10V⬉Vcc<18V 0.47 1.0 4.7 µF
VREG pin current IREG 1.0 mA
VCC pin capacitance CVCC 1.0 µF
CS1 pin capacitance CCS1 Between CS1 and GND 0.01 µF
CS2 pin capacitance CCS2 Between CS2 and VREG 0.01 µF
CP pin capacitance CCP Between CP and VREG * 0.01 µF
* If the timer latched mode is not needed, connect the CP pin to GND.
0
50
100
150
200
250
300
350
-30 0 30 60 90 120 150
Ambient temperature [˚C]
Maximun power dissipation [mW]
■ Absolute maximum ratings
Item Symbol Rating Unit
Power supply voltage VCC 20 V
SEL1, SEL2 pin voltage VSEL –0.3 to 5.0 V
FB1, IN1–, FB2, IN2–, IN2+ pin voltage VEA_IN –0.3 to 5.0 V
CS1, CS2, CP, R T, VREG pin voltage VCTR_IN –0.3 to 5.0 V
OUT1/2 OUT pin source current IOUT––400 (peak) mA
OUT pin sink current IOUT+ 150 (peak) mA
OUT1/2 OUT pin source current IOUT––50 (contin uous) mA
OUT pin sink current IOUT+ 50 (continuous) mA
Power dissipation * Pd300 (Ta⬉25˚C) mW
Operating junction temperature TJ+125 ˚C
Operating ambient temperature TOPR –30 to +85 ˚C
Storage temperature TSTG –40 to +125 ˚C
* Derating factor Ta⭌25˚C: 3mW/˚C
■ Electrical characteristics (VCC=3.3V, CREG=1.0µF, RT=12kΩ, Ta=+25˚C)
Regulated voltage for internal control blocks (VREG pin)
Item Symbol Test condition Min. Typ. Max. Unit
Regulated voltage VREG 2.178 2.200 2.222 V
Line regulation VREG_LINE VCC=2.5 to 18V ±5 ±15 mV
Load regulation VREG_LOAD IREG=0 to 1mA –5–1mV
Variation with temperature VREG_TC Ta= –30 to +85˚C ±0.5 %
Oscillator section (RT pin)
Item Symbol Test condition Min. Typ. Max. Unit
Oscillation frequency fOSC 435 500 565 kHz
Line regulation fOSC_LINE VCC=2.5 to 18V ±1 ±5 %
Variation with temperature fOSC_TC1 Ta= –30 to +85˚C±3%
FA3687V
3
Soft start section (CS1, CS2 pin)
Item Symbol Test condition Min. Typ. Max. Unit
Threshold voltage (CS1) VCS1D0N Duty cycle=0%, VFB1=1.4V 0.82 V
(Driving Nch-MOSFET) VCS1D20N Duty cycle=20%, VFB1=1.4V 0.89 0.925 0.96 V
VCS1D80N Duty cycle=80%, VFB1=1.4V 1.25 1.285 1.32 V
VCS1D100N Duty cycle=100%, VFB1=1.4V 1.38 V
Threshold voltage (CS1) VCS1D0P Duty cycle=0%, VFB1=1.4V 0.82 V
(Driving Pch-MOSFET) VCS1D20P Duty cycle=20%, VFB1=1.4V 0.90 0.935 0.97 V
VCS1D80P Duty cycle=80%, VFB1=1.4V 1.26 1.295 1.33 V
VCS1D100P Duty cycle=100%, VFB1=1.4V 1.38 V
Threshold voltage (CS2) VCS2D0N Duty cycle=0%, VFB2=0.7V 1.33 V
(Driving Nch-MOSFET) VCS2D20N Duty cycle=20%, VFB2=0.7V 1.21 1.245 1.28 V
VCS2D80N Duty cycle=80%, VFB2=0.7V 0.85 0.885 0.92 V
VCS2D100N Duty cycle=100%, VFB2=0.7V 0.80 V
Threshold voltage (CS2) VCS2D0P Duty cycle=0%, VFB2=0.7V 1.33 V
(Driving Pch-MOSFET) VCS2D20P Duty cycle=20%, VFB2=0.7V 1.20 1.23 1.27 V
VCS2D80P Duty cycle=80%, VFB2=0.7V 0.84 0.875 0.91 V
VCS2D100P Duty cycle=100%, VFB2=0.7V 0.80 V
Error amplifier section (IN1–, FB1, IN2–, IN2+, FB2 pin)
Item Symbol Test condition Min. Typ. Max. Unit
Reference voltage (ch.1) VREF1 * 0.99 1.00 1.01 V
VREF1 Line regulation (ch.1) VREF_LINE VCC=2.5 to 18V ±2 ±5 mV
VREF1 Variation with temperature (ch.1) VREF_TC1 Ta= –30 to +85˚C ±0.5 %
Input offset voltage (ch.2) VOFFSET VIN2+=1.0V, IN2+, IN2–±10 mV
VOFFSET Line regulation (ch.2) VOFF_LINE VCC=2.5 to 18V 0 mV
Input bias current IIN–VINx–=0.0 to 2.5V 0.0 mA
Common mode input voltage VCOM IN2+, IN2–0.7 1.5 V
Open loop gain AVO 70 dB
Unity gain bandwidth fT1.5 MHz
Output current (sink) ISIFB VFB1=0.5V, VIN1– =VREG 2.3 3.5 4.7 mA
VFB2=0.5V, VIN2– =VREG, VIN2+=1V
Output current (source) ISOFB VFB1=VREG–0.5V, VIN1–=0V –360 –270 –180 µA
VFB2=VREG–0.5V, VIN2–=0V, VIN2+=1V
* The FB1 v oltage is measured under the condition that IN1- pin and FB1 pin are shorted. The input offset voltage of the error amplifier is included.
Pulse width modulation (PWM) section (FB1, FB2 pin)
Item Symbol Test condition Min. Typ. Max. Unit
Threshold voltage (FB1) VFB1D0N Duty cycle=0%, VCS1=VREG 0.82 V
(Driving Nch-MOSFET) VFB1D20N Duty cycle=20%, VCS1=VREG 0.925 V
VFB1D80N Duty cycle=80%, VCS1=VREG 1.285 V
VFB1D100N Duty cycle=100%, VCS1=VREG 1.38 V
Threshold voltage (FB1) VFB1D0P Duty cycle=0%, VCS1=VREG 0.82 V
(Driving Pch-MOSFET) VFB1D20P Duty cycle=20%, VCS1=VREG 0.935 V
VFB1D80P Duty cycle=80%, VCS1=VREG 1.295 V
VFB1D100P Duty cycle=100%, VCS1=VREG 1.38 V
Threshold voltage (FB2) VFB2D0N Duty cycle=0%, VCS2=0V 1.33 V
(Driving Nch-MOSFET) VFB2D20N Duty cycle=20%, VCS2=0V 1.245 V
VFB2D80N Duty cycle=80%, VCS2=0V 0.885 V
VFB2D100N Duty cycle=100%, VCS2=0V 0.80 V
Threshold voltage (FB2) VFB2D0P Duty cycle=0%, VCS2=0V 1.33 V
(Driving Pch-MOSFET) VFB2D20P Duty cycle=20%, VCS2=0V 1.235 V
VFB2D80P Duty cycle=80%, VCS2=0V 0.875 V
VFB2D100P Duty cycle=100%, VCS2=0V 0.80 V
FA3687V
4
Overall section
Item Symbol Test condition Min. Typ. Max. Unit
Operating mode supply current ICCA Ch.1, Ch.2 operating mode 2.5 3.5 mA
ICCA1 Ch.1, Ch.2 off mode 2.0 mA
ICCA2 Ch.1, Ch.2 operating mode, Vcc=18V 3.0 mA
ICCA3 Latch mode 2.0 mA
Undervoltage lockout circuit section (VCC pin)
Item Symbol Test condition Min. Typ. Max. Unit
ON threshold voltage of VCC VUVLO 2.0 2.2 2.35 V
Hysteresis voltage 䉭VUVLO 0.1 V
*1 The current source of the CP pin operates when the v oltage of FB1 exceeds the threshold voltage as shown in the table.
*2 The current source of the CP pin operates when the voltage of FB2 falls below the threshold voltage as shown in the table.
*3 The timer latch of FB1 is disabled when the CS1 voltage is below the threshold v oltage as shown in the table.
*4 The timer latch of FB2 is disabled when the CS2 voltage is abov e the threshold voltage as shown in the table .
Timer latch protection section (CS pin)
Item Symbol Test condition Min. Typ. Max. Unit
Threshold voltage of FB1 VTHFB1TL *11.5 2.0 V
Threshold voltage of FB2 VTHFB2TL *20.2 0.6 V
Threshold voltage of CS1 VTHFB3TL *30.2 0.6 V
Threshold voltage of CS2 VVTHCS1TL *41.5 2.0 V
Charge current of CP ICP VCP=0.5V, VFB1=2.1V –2.4 –2.0 –1.5 µA
Threshold voltage of CP VTHCPTL 1.6 2.1 V
Output section (OUT1, OUT2, SEL1, SEL2 pin)
Item Symbol Test condition Min. Typ. Max. Unit
High side on resistance of OUT1/2 RONHI IOUT2= –50mA 10 20 Ω
IOUT1= –50mA, VCC=5V 9 Ω
IOUT1= –50mA, VCC=15V 8 Ω
Low side on resistance of OUT1/2 RONLO IOUT1=50mA 5 10 Ω
IOUT2=50mA, VCC=5V 5 Ω
IOUT2=50mA, VCC=15V 5 Ω
Rise time of OUT1/2 tRISE CL=1000pF 25 ns
Fall time of OUT1/2 tFALL CL=1000pF 40 ns
SEL pin voltage for driving Nch-MOSFET VSELN 0.0 0.2 V
SEL pin voltage for driving Pch-MOSFET VSELP VREG-0.2 VREG V
FA3687V
5
■ Characteristic curves
Oscillation frequency vs. timing resistor Oscillation frequency vs. supply v olta ge VCC
VCC=3.3V, Ta=25˚C Ta=25˚C, RT=12kΩ (fOSC=500kHz)
Oscillation frequency vs. ambient temperature Regulated voltage vs. supply voltage VCC
VCC=3.3V, RT=12kΩ (fOSC=500kHz) Ta=25˚C, RT=12kΩ (fOSC=500kHz)
Regulated voltage vs. ambient temperature Regulated voltage vs. load current
VCC=3.3V, RT=12kΩ (fOSC=500kHz) VCC=3.3V, RT=12kΩ (fOSC=500kHz)
0
200
400
600
800
1000
1200
1400
1600
1800
1 10 100
Timing resistor RT [kΩ]
Oscillation frequency [kHz]
490
492
494
496
498
500
502
504
506
508
510
0 5 10 15 20
Vcc [V]
Oscillation frequency [kHz]
430
450
470
490
510
530
550
570
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
Oscillation frequency [kHz]
2.17
2.18
2.19
2.20
2.21
2.22
2.23
0 5 10 15 20
Vcc [V]
Regulated voltage V
REG
[V]
Load current
I
REG
=0A
2.17
2.18
2.19
2.20
2.21
2.22
2.23
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
Regulated voltage VREG [V]
2.17
2.18
2.19
2.20
2.21
2.22
2.23
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Load current I
REG
[mA]
Regulated voltage V
REG
[V]
Ta=–30˚C
Ta=25˚C
Ta=85˚C
FA3687V
6
Reference voltage vs. suppl y voltage VCC Reference v olta ge vs. ambient temperature
Ta=25˚C, RT=12kΩ (fOSC=500kHz) VCC=3.3V, RT=12kΩ (fOSC=500kHz)
Error amp. output current (sink) vs. ambient temperature Error amp. output current (source) vs. ambient temperarure
VCC=3.3V, RT=12kΩ (fOSC=500kHz) VCC=3.3V, RT=12kΩ (fOSC=500kHz)
Charge current of CP vs. ambient temperature Threshold voltage of CP vs. ambient temperature
VCC=3.3V, RT=12kΩ (fOSC=500kHz) VCC=3.3V, RT=12kΩ (fOSC=500kHz)
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
0 5 10 15 20 25
Vcc [V]
Reference voltage V
REF
[V]
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
Reference voltage V
REF
[V]
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
Output current (sink) I
SIFB
[mA]
-350
-300
-250
-200
-150
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
Output current (source) ISOFB [uA]
-3.0
-2.5
-2.0
-1.5
-1.0
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
Charge current of CP [uA]
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
Threshold voltage of CP [V]
FA3687V
7
Output duty cyc le vs. Cs v oltage (c h. 1) Output duty cyc le vs. oscillation frequency (ch. 1)
Driving Nch MOSFET Driving Nch MOSFET
VCC=3.3V, Ta=25˚CVCC=3.3V, Ta=25˚C
Output duty cyc le vs. Cs v oltage (c h. 1) Output duty cyc le vs. oscillation frequency (ch. 1)
Driving Nch MOSFET Driving Nch MOSFET
VCC=3.3V, Ta=25˚CVCC=3.3V, Ta=25˚C
0
10
20
30
40
50
60
70
80
90
100
0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50
VCS1 [V]
Output duty cycle (ch.1) [%]
fosc=300kHz
fosc=500kHz
fosc=760kHz
fosc=1.5MHz
0
10
20
30
40
50
60
70
80
90
100
300 500 700 900 1100 1300 1500
Oscillation frequency [kHz]
Output duty cycle (ch.1) [%]
VCS1=0.85V
VCS1=1.35V
VCS1=0.90V
VCS1=0.95V
VCS1=1.00V
VCS1=1.05V
VCS1=1.10V
VCS1=1.15V
VCS1=1.20V
VCS1=1.25V
VCS1=1.30V
0
10
20
30
40
50
60
70
80
90
100
0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50
V
CS1
[V]
Output duty cycle (ch.1) [%]
fosc=300kHz
fosc=500kHz
fosc=760kHz
fosc=1.5MHz
0
10
20
30
40
50
60
70
80
90
100
300 500 700 900 1100 1300 1500
Oscillation frequency [kHz]
Output duty cycle (ch.1) [%]
VCS1=1.35V
VCS1=1.30V
VCS1=1.25V
VCS1=1.20V
VCS1=1.15V
VCS1=1.10V
VCS1=1.05V
VCS1=1.00V
VCS1=0.95V
VCS1=0.90V
VCS1=0.85V
FA3687V
8
Output duty cyc le vs. Cs v oltage (c h. 2) Output duty cyc le vs. oscillation frequency (ch. 2)
Driving Nch MOSFET Driving Nch MOSFET
VCC=3.3V, Ta=25˚CVCC=3.3V, Ta=25˚C
Output duty cyc le vs. Cs v oltage (c h. 2) Output duty cyc le vs. oscillation frequency (ch. 2)
Driving Nch MOSFET Driving Nch MOSFET
VCC=3.3V, Ta=25˚CVCC=3.3V, Ta=25˚C
0
10
20
30
40
50
60
70
80
90
100
0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40
VCS2 [V]
Output duty cycle (ch.2) [%]
fosc=300kHz
fosc=500kHz
fosc=760kHz
fosc=1.5MHz
0
10
20
30
40
50
60
70
80
90
100
300 500 700 900 1100 1300 1500
Oscillation frequency [kHz]
Output duty cycle (ch.2) [%]
VCS2=0.85V
VCS2=0.90V
VCS2=0.95V
VCS2=1.00V
VCS2=1.05V
VCS2=1.10V
VCS2=1.15V
VCS2=1.20V
VCS2=1.25V
VCS2=1.30V
VCS2=0.80V
0
10
20
30
40
50
60
70
80
90
100
0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40
V
CS2
[V]
Output duty cycle (ch.2) [%]
fosc=300kHz
fosc=500kHz
fosc=760kHz
fosc=1.5MHz
0
10
20
30
40
50
60
70
80
90
100
300 500 700 900 1100 1300 1500
Oscillation frequency [kHz]
Output duty cycle (ch.2) [%]
VCS2=0.85V
VCS2=0.90V
VCS2=0.95V
VCS2=1.00V
VCS2=1.05V
VCS2=1.10V
VCS2=1.15V
VCS2=1.20V
VCS2=1.25V
VCS2=1.30V
VCS2=0.80V
FA3687V
9
OUT1 terminal sour ce current vs. H level output v olta ge OUT2 terminal source current vs. H level output voltage
Ta=25˚C Ta=25˚C
OUT1 terminal sink current vs. H level output v oltage OUT2 terminal sink current vs. H level output v oltage
VCC=3.3V VCC=3.3V
OUT1 terminal sink current vs. H level output v oltage OUT2 terminal sink current vs. H level output v oltage
VCC=12V VCC=12V
-500
-450
-400
-350
-300
-250
-200
-150
-100
-50
0
0.0 1.0 2.0 3.0 4.0 5.0 6.0
Vcc–VOUT1 [V]
IOUT1 [mA]
Vcc=2.5V
Vcc= 3V
Vcc= 5V
Vcc=12V
-500
-450
-400
-350
-300
-250
-200
-150
-100
-50
0
0.0 1.0 2.0 3.0 4.0 5.0
Vcc–VOUT2 [V]
IOUT2 [mA]
Vcc=2.5V
Vcc= 3V
Vcc= 5V
Vcc=12V
-300
-250
-200
-150
-100
-50
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Vcc–VOUT1 [V]
IOUT1 [mA]
Ta=–30˚CTa=25˚C
Ta=85˚C
-300
-250
-200
-150
-100
-50
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Vcc–VOUT2 [V]
IOUT2 [mA]
Ta=–30˚C
Ta=85˚C
Ta=25˚C
-500
-400
-300
-200
-100
0
0.0 1.0 2.0 3.0 4.0 5.0
Vcc–VOUT1 [V]
IOUT1 [mA]
Ta=85˚C
Ta=–30˚C
Ta=25˚C
-500
-400
-300
-200
-100
0
0.0 1.0 2.0 3.0 4.0 5.0
Vcc–VOUT2 [V]
IOUT2 [mA]
Ta=–30˚C
Ta=25˚C
Ta=85˚C
FA3687V
10
OUT1 terminal sink current vs. L level v oltage OUT2 terminal sink current vs. L level v oltage
OUT1 terminal rise time vs. supply v olta ge VCC OUT2 terminal rise time vs. suppl y voltage VCC
CL=1000pF CL=1000pF
OUT1 terminal fall time vs. supply v olta ge VCC OUT2 terminal fall time vs. suppl y voltage VCC
CL=1000pF CL=1000pF
0
50
100
150
200
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VOUT1 [V]
IOUT1 [mA]
Ta=–30˚C
Ta=25˚C
Ta=85˚C
0
50
100
150
200
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VOUT2 [V]
IOUT2 [mA]
Ta=–30˚C
Ta=85˚C
Ta=25˚C
0
10
20
30
40
50
60
0 5 10 15 20
Vcc [V]
OUT1 terminal rise time t
RISE
[ns]
Ta=–30˚C
Ta=25˚C
Ta=85˚C
0
10
20
30
40
50
60
0 5 10 15 20
Vcc [V]
OUT2 terminal rise time t
RISE
[ns]
Ta=–30˚C
Ta=25˚C
Ta=85˚C
0
50
100
150
200
0 5 10 15 20
Vcc [V]
OUT1 terminal fall time t
FALL
[ns]
Ta=–30˚C
Ta=25˚C
Ta=85˚C
0
50
100
150
200
0 5 10 15 20
Vcc [V]
OUT2 terminal fall time tFALL [ns]
Ta=25˚C
Ta=–30˚C
Ta=85˚C
FA3687V
11
Operating mode supply current vs. oscillation frequency UVLO ON threshold vs. ambient temperature
Ta=25˚C
CS1 internal dischar ge switc h current vs. volta ge CS2 internal discharge s witc h current vs. volta ge
VCC=3.3V, RT=12kΩ (fOSC=500kHz) VCC=3.3V, RT=12kΩ (fOSC=500kHz)
Error amplifier gain and phase vs. frequency
2.0
3.0
4.0
5.0
6.0
300 500 700 900 1100 1300 1500
Oscillation frequency [kHz]
Operating mode supply current ICCA [mA]
Vcc=2.5V
Vcc=18V
Vcc=12V
Vcc=5V
Vcc=3.3V
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
UVLO ON threshold V
UVLO
[V]
0
50
100
150
200
250
300
350
400
0.00 0.50 1.00 1.50 2.00 2.50
VCS1 [V]
ICS1off [µA]
Ta=–30˚C
Ta=25˚C
Ta=85˚C
-200
-150
-100
-50
0
0.00 0.50 1.00 1.50 2.00
V
REG
–VCS2 [V]
ICS2 off [µA]
Ta=–30˚C
Ta=25˚C
Ta=85˚C
FA3687V
12
■ Description of each circuit
1. Reference voltage circuit (VREF)
This circuit generates the reference voltage of 1.00V±1%
compensated in temperature from VCC voltage, and is
connected to the non-in v erting input of the error amplifier. The
voltage cannot be observed directly because there is no
e xternal pin for this purpose.
2. Regulated voltage circuit (VREG)
This circuit generates 2.20V±1% based on the reference
voltage VREF, and is used as the power supply of the internal IC
circuits. The voltage is generated when the supply v oltage , VCC
is input. The VREG voltage is also used as a regulated power
supply f or soft start, maximum duty cycle limitation, and others.
The output current f or external circuit should be within 1mA. A
capacitor connected between VREG pin and GND pin is
necessary to stabilize the VREG voltage (To determine
capacitance, refer to recommended operating conditions). The
VREG v oltage is regulated in VCC v oltage of 2.4V or above.
3. Oscillator
The oscillator generates a triangular wavef orm by charging and
discharging the built-in capacitor. A desired oscillation
frequency can be set by the value of the resistor connected to
the R T pin (Fig. 1). The b uilt-in capacitor voltage oscillates
between approximately 0.82V and 1.38V at fosc=500kHz (that
of ch1 and ch2 are slightly diff erent) with almost the same
charging and discharging gr adients (Fig. 2).
You can set the desired oscillation frequency by changing the
gradients using the resistor connected to the RT pin (Large RT:
Low frequency, Small RT: High frequency). The oscillator
wa veform cannot be observ ed from the outside because a pin
f or this purpose is not provided. The RT pin voltage is
appro ximately 1V DC in normal operation. The oscillator output
is connected to the PWM comparator.
4. Error amplifier circuit
The error amplifier 1 has the inverting input of IN1(–) pin
(Pin14). The non-inv erting input is internally connected to the
ref erence voltage VREF (1.00V±1%; 25˚C). The error amplifier 2
has the inverting input IN2(–) pin (Pin4) and non-in verting input
IN2(+) pin (Pin5) e xternally. Since each input of error amplifier
2 is connected to the pins, CH2 is suitable for any circuit
topology. The FB pins (Pin3, Pin15) are the output of the error
amplifier. An external RC network is connected between FB pin
and IN–pin for gain and phase compensation setting. (Fig. 3)
F or connecting of each topology, see “Design advice”.
Fig. 1
Fig. 2
Fig. 3
12
OSC
RT
RT
RT value:Small
RT value:Large
0.82V
1.38V
+
14 15
5
43
13
IN1-
VREG
IN2+
IN2- FB2
FB1
Comp
Comp
Vout1
Vout2
R
NF
1
R
NF2
V
REF
(1.0V)
R1
R2
R3
R4
R5
R6
Er. Amp.1
Er. Amp.2
FA3687V
13
5. PWM comparator
The PWM output generates from the oscillator output, the error
amplifier output (FB1, FB2) and CS v oltage (CS1, CS2) (Fig. 4).
The oscillator output is compared with the pref erred lo wer
voltage betw een FB1 and CS1 for ch1. While the preferred
voltage is lower than oscillator output, the PWM output is low.
While the pref erred voltage is higher than oscillator output, the
PWM output is high. Since the phase of Ch2 is the opposite
phase of Ch1, higher v oltage betw een FB2 and CS2 is
pref erred and while the preferred voltage is lo w er than the
oscillator output, the PWM output 2 is high. (Cannot be
observ ed externally) The output polarity of OUT1, OUT2
changes according to the condition of SEL pin. (See Fig. 6)
6. Soft start function
This IC has a soft start function to protect DC-to-DC con verter
circuits from damage when starting operation. CS1 pin (Pin10),
and CS2 pin (Pin7) are used f or soft start function of ch1 and
ch2 respectiv ely (Fig. 5). When the supply voltage is applied to
the VCC pin and UVLO is cancelled, capacitor CCS1 and CCS2
is charged by VREG through the resistor R7 or R9. Therefore,
CS1 voltage g radually increases and CS2 voltage gradually
decreases. Since CS1 and CS2 pin are connected to the PWM
comparator internally, the pulses gradually widen and then the
soft start function operates (Fig. 6).
The maximum duty cycle can be set b y using the CS pins.
(See “Design advice” about the detail)
Fig. 4
Fig. 5
Fig. 6
N/P ch.
drive
N/P ch.
drive
UVLO
Oscillator
output
CS1
CS2
FB2
FB1 OUT1
OUT2
PWM
Comp.1
PWM
Comp.2
PWM output1
9
8
SEL1
16
SEL2
2
PWM output2
13
10
CS1
VREG
CCS1
R7
13
7
VREG
CS2
R9
C
CS2
Oscillator output CS1 pin voltage
Er. Amp.1 output
PWM
output 1
OUT1
Pch.drive
(SEL1:VREG)
OUT1
Nch.drive
(SEL1:GND)
Oscillator output
CS2 pin voltage Er. Amp.2 output
PWM
output2
OUT2
Pch.drive
(SEL2:VREG)
OUT2
Nch.drive
(SEL2:GND)
FA3687V
14
7. Timer latch short-circuit protection circuit
This IC has the timer latch short-circuit protection circuit. This
circuit cuts off the output of all channels when the output
voltage of DC-to-DC converter drops due to short circuit or
overload. To set delay time for timer latch operation, a capacitor
CCP should be connected to the CP pin (Fig. 7). When one of
the output voltage of the DC-to-DC converter drops due to short
circuit or overload, the FB1 pin v oltage increases up to around
the VREG voltage for ch1, or the FB2 pin voltage drops down to
around 0V f or ch2. When FB1 pin voltage exceeds 2.0V (max.)
or FB2 pin voltage falls below 0.2V (min.), constant-current
source (2µA typ .) starts charging the capacitor CCP connected
to the CP pin. If the v oltage of the CP pin exceeds 2.1 V (max.),
the circuit regards the case as abnormal. Then the IC is set to
off latch mode and the output of all channels is shut off (Fig. 8),
and the current consumption becomes 2mA (typ.). The period
(tp) between the occurrence of short-circuit in the conv erter
output and setting to off latched mode can be calculated b y the
f ollo wing equation:
You can reset off latched mode of the short-circuit protection by
either of the f ollo wing ways about 1) CP pin, or 2) VCC pin, or
3) CS1or CS2 pin:
1) CP v oltage = 0V
2) VCC voltage U VLO voltage (2.2V typ.) or belo w
3) Set the CS pin of the cause of off latched mode as follows
CS1 pin voltage = 0V, CS2 pin voltage = VREG
If the timer-latched mode is not necessary, connect the CP pin
to GND.
8. Output circuit
The IC contains a push-pull output stage and can directly drive
MOSFETs. The maximum peak current of the output stage is
sink current of +150mA, and source current of –400mA. The IC
can also drive NPN and PNP transistors. The maximum current
in such cases is ±50mA. You must design the output current
considering the rating of pow er dissipation. (See “Design
advice’)
You can switch the types of external discrete MOSFETs b y
wiring of the SEL pins (Pin 2, Pin 16). For driving Nch MOS ,
connect the SEL pins to GND. F or driving Pch MOS , connect
the SEL pins to VREG. You can design buc k converter or
inverting conv erter by driving Pch MOS, and boost converter by
driving Nch MOS.
Connect them either to GND or to VREG surely.
9. Underv olta ge loc k out circuit
The IC contains a undervoltage lockout circuit to protect the
circuit from the damage caused by malfunctions when the
supply voltage drops. When the supply voltage rises from 0V,
the IC starts to operate at VCC of 2.2V (typ.) and outputs
generate pulses . If a drop of the supply v oltage occurs, it stops
output at VCC of 2.1V (typ.). When it occurs , the CS1 pin is
turned to low le v el and the CS2 pin to high level, and then these
pins are reset.
Fig. 7
Fig. 8
VTHCPTL: CP pin latched mode threshold voltage [V]
ICP: CP charge source current [µA]
CCP: Capacitance of CP pin capacitor
1
CP
CCP
Icp
Vcp
CP pin voltage [V]
1.0
2.0
Time t
Start-up
Momentary short
circuit Short circuit
Short circuit
protection
tp
2.1V (max)
VREG pin voltag
tp [s] = CCP ⫻VTHCPTL
ICP
FA3687V
15
■ Design advice
1. Setting the oscillation frequency
As described in item 1 of “Description of each circuit,” a desired
oscillation frequency can be determined by the v alue of the
resistor connected to the R T pin. When designing an oscillation
frequency, you can set an y frequency betw een 300kHz and
1.5MHz. You can obtain the oscillation frequency from the
characteristic curv e “Oscillation frequency (f osc) vs . timing
resistor resistance (RT)” or the value can be appro ximately
calculated by the following e xpression.
This e xpression, ho w ever, can be used for rough calculation,
the obitained v alue is not guar anteed. The oper ation frequency
varies due to the conditions such as toler ance of the
characteristics of the ICs, influence of noises , or external
discrete components. When determining the values , examine
the eff ectiveness of the values in an actual circuit. The timing
resistor RT should be wired to the GND pin as shortly as
possible because the RT pin is a high impedance pin and is
easy aff ected b y noises .
2. Operation near the maximum or the minimum output
duty cyc le
As described in “Output duty cycle vs. v oltage”, the output duty
cycle of this IC changes sharply near the minimum and the
maximum output duty cycle . Note that these phenomena are
conspicuous f or high frequency oper ation (when the pulse width
is narrow).
3. Determining soft start period
The period from the start of charging the capacitor CCS to
widening n% of output duty cycle can be roughly calculated b y
the f ollo wing expression: (see Fig. 5 for symbols)
VCS1n and VCS2n are the v oltage of the CS1 and CS2 pins in
n% of output duty cycle, and vary in accordance with operating
frequency. The value can be obtained from the characteristic
curv e “Output duty cycle vs. CS voltage”
To reset the soft start function, the supply voltage VCC is
low ered belo w the UVLO voltage (2.1V typ.) and then the
internal switch discharges the CS capacitor. The characteristics
of the internal switch for discharge are shown in f ollo wing the
characteristics curv es of “Characteristics of CS1 internal
discharge s witch current vs . voltage” and “Characteristics of
CS2 internal discharge switch current vs . v oltage”. Theref ore,
when determining the period of soft start at restarting the power
supply, consider the characteristics carefully.
CCS1, CCS2: Capacitance connected to CS1or CS2 pin [µF]
R7, R9: Resistance connected to CS1 or CS2 pin [kΩ]
fOSC = 4050 ⫻ RT –0.86 fOSC: Oscillation frequency [kHz]
RT: Timing resistor [kΩ]
( )
RT = 4050
fOSC
1.16
F or CS1 pin
()
t [ms] = R7 ⫻ CCS1 ⫻ 1n 1 –VCS1n
VREG
For CS2 pin
()
t [ms] = R9 ⫻ CCS2 ⫻ 1n VCS2n
VREG
FA3687V
16
4. Setting maximum duty cyc le
As described in the Fig. 9, you can limit maximum duty cycle by
connecting a resistor divider “R7, R8 or R9, R10” between CS1,
CS2 and VREG pin. Set the maximum duty cycle considering
that relation between the maximum output duty cycle and the
CS pin v oltage changes with operation frequency as described
in the characteristic curves of “Output duty cycle vs. oscillation
frequency” and “Output duty cycle vs. CS voltage”. When the
maximum duty cycle is limited, CS pin voltage at start-up is
described in Fig. 10, and the approximate value of soft start
period can be obtained by the following expressions:
The divided CS1 v oltage is obtained b y:
The divided CS2 v oltage is obtained b y:
VCS1n and VCS2n are the v oltages of CS1 and CS2 under a
certain output duty cycle and v aries with operation frequencies .
The values of VCS1n and VCS2n can be obtained from the
characteristic curv es of “Output duty cycle vs. CS v oltage”.
The charging of CCS1 and CCS2 after UVLO is unloc k ed.
Theref ore, the period from power-on of Vcc to widening n% of
output duty cycle is the sum of t0 and t.
5. Determining the output voltage of DC-DC converter s
The ways to determine the output v oltage of the DC-DC
converter of each channel is shown in Fig. 10 and the f ollo wing
equations.
F or ch1:
The positive output voltage of DC-to-DC converter (a buck, a
boost) is determined by:
F or ch2:
The positive output voltage of DC-to-DC conv erter is
determined by:
Here,
When R5=R6,
CCS1, CCS2: Capacitance connected to the CS1 or CS2 pin [µF]
R7, R8, R9, R10: Resistance connected to CS1 or CS2 pin [kΩ]
VCS1 = R8 ⫻ VREG
R7 + R8
VCS2 = R9 ⫻ VREG
R9 + R10
For CS2
()
t [ms] = R0 ⫻CCS2 ⫻1n VCS2n – VCS2
VREG – VCS2
Vout1 = R1 + R2 ⫻ VREF
R2
Vout2 = V1 ⫻R3 + R4
R3
V1 = VREG ⫻R6
R5 + R6
For CS1
()
t [ms] = R0 ⫻CCS1 ⫻1n 1–VCS1n
VCS1
()
Vout2 = VREG ⫻R3 + R4
2R3
13
10
VREG
CS1
C
CS1
R7
R8
13
7
CS2
VREG
R9
R10
C
CS2
Fig. 9
Threshold voltage Vcc
tt0
tt0
⫻ V
REG
V
CS1N
R8
R7+R8
Threshold voltage
t0: Time from power-on of VCC to reaching unlock voltage of UVLO.
⫻ V
REG
V
REG
pin voltage
V
CS2n
V
CC
R9
R9+R10
Fig. 10
Ch1
Ch2
R0 =R7⫻R8
R7+R8
R0 =R9⫻R10
R9+R10
FA3687V
17
Fig. 11
The negativ e output voltage of DC-to-DC converter (inv erting) is
determined by:
The ratio of resistances is determined by:
(Use the absolute v alue of the Vout2 voltage.)
When R5 = R6,
Connect the SEL1 and SEL2 pin to GND or VREG surely.
6. Restriction of external discrete components and
recommended operating conditions
To achieve a stable oper ation of the IC, the value of external
discrete components connected to VCC, VREG, CS, CP pins
should be within the recommended operating conditions . And
the voltage and the current applied to each pin should be also
within the recommended operating conditions . If the pin voltage
of OUT1, OUT2, or VREG becomes higher than the VCC pin
voltage , the current flows from the pins to the VCC pin because
parasitic three diodes exist between the VCC pin and these
pins. Be careful not to allo w this current to flow .
7. Loss calculation
Since it is hard to measure IC loss directly, the calculation to
obtain the appro ximate loss of the IC connected directly to a
MOSFET is described below.
When the supply voltage is VCC, the current consumption of the
IC is ICCA, the total input gate charge of the driven MOSFET is
Qg and the s witching frequency is fsw, the total loss Pd of the
IC can be calculated by:
Pd ⱌ VCC ⫻ (ICCA + Qg ⫻ fs w).
The value in this expression is influenced by the effects of the
dependency of supply v oltage , the char acteristics of
temperature , or the tolerance of parameter . Theref ore , evaluate
the appropriateness of IC loss sufficiently considering the range
of values of above parameters under all conditions .
Example
ICCA=2.5mA for VCC=3.3V in the case of a typical IC from the
characteristic curves. Qg=6nC , fsw=500kHz, the IC loss “Pd” is
as f ollo ws .
Pd ⱌ 3.3 ⫻ (2.5mA + 6nC ⫻ 500kHz) ⱌ 18.2mW
If two MOSFETs are driven under the same condition for 2
channels, Pd is as follows:
Pd ⱌ 3.3 ⫻ {2.5mA+2 ⫻ (6nC ⫻ 500kHz)} = 28.1mW
IN1-
FB1
Vout1
R2
R1 SEL1VREG
OUT1
Vout1
9
16
15
14
+
V
REF
(1.0V)
IN1-
FB1
Vout1
R2
R1 SEL1
GND
OUT1
Vout1
9
16
15
14
+
V
REF
(1.0V)
Buck
Boost
5
43
13
VREG
IN2+
IN2- FB2
Vout2
R3
R4 R5
R6
2
SEL2VREG
OUT2
8
Vout2
V1
5
43
13
VREG
IN2+
IN2-
FB2
Vout2
R3
R4
R5
R6
2
SEL2VREG
OUT2
8
Vout2
V1
5
43
13
VREG
IN2+
IN2- FB2
Vout2
R3
R4 R5
R6
2
SEL2
GND
OUT2
8
Vout2
V1
Buck
Boost
Inverting
()
Vout2 = VREG ⫻R3 – R4
2R3
R3 =VREG – V1
R4 Vout2 + V1
Vout2 = R3 + R4 ⫻ V1 –R4 ⫻ VREG
R3 R3
FA3687V
18
■ Application circuit
40kΩ
10kΩ
22kΩ
11kΩ
100Ω
0.01µF
10µF
10µF
10µF
7to18V
GND
5V/500mA
3.3V/500mA
GND
0.01µF
0.068µF
0.47µF
0.1uF
1MΩ
1µF
0.1µF
10kΩ
6.2kΩ
100kΩ
100kΩ
10kΩ
FB1 IN1-
IN2-
GND
IN2+
FB2
RT CS1
CS2
SEL1
CP
VREG OUT1
VCC OUT2
SEL2
FA3687V
15 14 11 10
12
13 9
16
45
3
2
17
68
10kΩ
10kΩ
0.01µF
Parts tolerances characteristics are not defined in the circuit design
sample shown above. When designing an actual circuit for a product,
you must determine parts tolerances and characteristics for safe and
economical operation.
