1/41Novemb er 200 4
M50FW040
4 Mbit (512Kb x8, Uniform Block)
3V Supply Firmware Hub Flash Memory
FEATURES SUMMARY
■SUPPLY VOLTAGE
–V
CC = 3V to 3.6V for Program, Erase and
Read Operations
–V
PP = 12V for Fast Erase (optional)
■TWO INTERFACES
– Firmware Hub (FWH) Interface for
embedded operation with PC Chipsets.
– Address/Address Multiplexed (A/A Mux)
Interface for programming equipment
compatibility.
■FIRMWARE HUB (FWH) HARDWARE
INTERFACE MODE
– 5 Signal Communication Interface
supporting Read and Write Operations
– Hardware Write Protect Pins for Block
Protection
– Register Based Read and Write
Protection
– 5 Additional General Purpose Inputs for
platform design flexibility
– Synchronized with 33MHz PCI clock
■PROGRAMMING TIME: 10µs typical
■8 UNIFORM 64 Kbyte MEMORY BLOCKS
■PROGRAM/ERASE CONTROLLER
– Embedded Byte Program and Block
Erase alg orith ms
– Stat us Register Bits
■PROGRAM and ERASE SUSPEND
– Read other Blocks during Program/Erase
Suspend
– Program other Blocks during Erase
Suspend
■FOR USE in PC BIOS AP PLICATION S
■ELECTRONIC SIGNA TURE
– Manufa cture r Code: 20h
– Device Code : 2Ch
Figure 1. Packages
TSOP40 (N)
10 x 20mm
PLCC32 (K)
TSOP32 (NB)
8 x 14mm
M50FW040
2/41
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram (FWH Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 1. Signal Names (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Logic Diagram (A/A Mux Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Firmware Hub (FWH) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Input/Output Communications (FWH0-FWH3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Input Communication Frame (FWH4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Identification Inputs (ID0-ID3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
General Purpose Inputs (FGPI0-FGPI4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Interface Reset (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CPU Reset (INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Top Block Lock (TBL).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write En abl e (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Row/Column Address Select (RC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VPP Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Firmware Hub (FWH) Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3/41
M50FW040
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. FWH Bus Read Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. FWH Bus Read Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. FWH Bus Write Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. FWH Bus Write Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 7. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 19
Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Firmware Hub (FWH) General Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Device Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Firmware Hub (FWH) General Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
M50FW040
4/41
Device Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Firmware Hub Register Configuration Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. General Purpose Inputs Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 12. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. FWH Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. A/A Mux Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. FWH Interface AC Testing Input Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10.A/A Mux Interface AC Testing Input Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 18. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11.FWH Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 19. FWH Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12.FWH Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 20. FWH Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 21. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14.A/A Mux Interface Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 22. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 23. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline . . . . . . . . 31
Table 24. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data 32
Figure 17.TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline . . . . . . . . . . 33
Table 25. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data. . . 33
Figure 18.TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Outline . . . . . . . . . 34
Table 26. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Mechanical Data. . 34
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 20.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 37
Figure 21.Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5/41
M50FW040
Figure 22.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 39
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 28. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
M50FW040
6/41
SUMMARY D ESCRIPTION
The M50F W040 is a 4 Mbit ( 512Kb x8) no n-vola-
tile memory that can be read, erased and repro-
grammed. These operations can be performed
using a single low voltage (3.0 to 3.6V) supply. For
fast erasing in production lines an optional 12V
power supply can be used to reduce the erasing
time.
The memory is divided into blocks that can be
erased independen tly s o it is po ss i ble to p re se rve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental Pro-
gram or Erase commands from modifying the
memory. Prog ram and Er ase comma nds are writ-
ten to the C ommand Interface o f the memo ry. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any err or cond iti ons ide nti fie d. The co mmand
set required to control the memory is consistent
with JEDEC standards.
Two differen t bus inte rfaces are suppor ted by the
memory. The primary interface, the Firmware Hub
(or FWH) Interface, uses Intel’s proprietary FWH
protocol. This has been designed to remove the
need for the ISA bus in current PC Chipsets; the
M50FW040 acts as the PC BIOS on the Low Pin
Count bus for these PC Chipsets.
The secondary interface, the Address/Address
Multiplex ed (o r A/A M ux) Inter face, is de signe d to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is offered in TSOP32 (8 x 14mm),
TSOP40 (10 x 20mm) and PLCC32 packages and
it is supplied with all the bits erased (set to ’1’).
Figure 2. Logic Diagram (FWH Interface) Table 1. Signal Names (FWH Interface)
AI03623
4
FWH4
FWH0-
FWH3
VCC
M50FW040
CLK
VSS
4
IC
RP
TBL
5
INIT
WP
ID0-ID3
FGPI0-
FGPI4
VPP
FWH0-FWH3 Input/O utp ut Co mm u nic atio ns
FWH4 Input Communication Frame
ID0-ID3 Identification Inputs
FGPI0-FGPI4 General Purpose Inputs
IC Interface Configuration
RP Interface Reset
INIT CPU Re se t
CLK Clock
TBL Top Block Lock
WP Write Protect
RFU Reserved for Future Use. Leave
disconnected
VCC Supply Voltage
VPP Optional Supply Vo ltage for Fast
Erase Operations
VSS Ground
NC Not Connected Internally
7/41
M50FW040
Figure 3. Logic Diagram (A/A Mux Interface) Table 2. Signal Names (A/A Mux Interface)
Figure 4. PLCC Connections
Note: Pins 27 and 28 are not internally connected.
AI10719
11
RC
DQ0-DQ7
VCC
M50FW040
IC
VSS
8
G
W
RB
RP
A0-A10
VPP
IC Interface Configuration
A0-A10 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
GOutput En ab le
WWrite Enable
RC Row/Co lum n Ad dre ss Sele ct
RB Ready/B us y Ou tpu t
RP Interface Reset
VCC Supply Voltage
VPP Optional Supply Vo ltage for Fast
Program and Erase Operations
VSS Ground
NC Not Connected Internally
AI03616
FGPI4
NC
FWH4
RFU
17
ID1
ID0
FWH0
FWH1
FWH2
FWH3
RFU
FGPI1
TBL
ID3
ID2
FGPI0
WP
9
CLK
VSS
1
RP
VCC
NC
FGPI2
RFU
32
VPP
VCC
M50FW040
FGPI3
IC (VIL)
RFU
INIT
RFU
25
VSS
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A10
RC
RP
A8
VPP
VCC
A9
NC
W
VSS
VCC
NC
DQ7
IC (VIH)
G
RB
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
VSS
A/A Mux A/A Mux
A/A MuxA/A Mux
M50FW040
8/41
Figure 5. TSOP32 Connections
1. the RB pin is not available for the A/A Mux interface in the TSO P32 package.
Figure 6. TSOP40 Connections
AI10718
A1
A0
DQ0
A7
A4 A3
A2
A6
A5
A9
A8
W
DQ7
G
NC
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A/A Mux
A/A Mux
ID1
FWH1/LAD1
FWH2/LAD2
GPI3
TBL ID2
GPI0
WP
NC
NC
RFU
GPI4
NC FWH4/LFRAME
RFU
FWH3/LAD3
VSS
RFU
RFU
CLK
RP
VPP
VCC M50FW040
8
1
9
16 17
24
25
32
ID3/RFU
VSS
INIT
IC
NC
GPI2 FWH0/LAD0
GPI1 ID0
NC
NC
IC (VIH)
NC
NC
RC
RP
VPP
VCC
A10
VSS
AI03617
A1
A0
DQ0
A7
A4 A3
A2
A6
A5
A9
A8
W
VSS
VCC
DQ7
G
RB
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A/A Mux
A/A Mux
ID1
FWH1
FWH2
FGPI3
TBL ID2
FGPI0
WP
NC
VCC
NC
IC (VIL)
RFU
FGPI4
NC
VSS
FWH4
RFU
FWH3
VSS
VCC
RFU
RFU
NC
CLK
RP
NC
VPP
VCC
NC
M50FW040
10
1
11
20 21
30
31
40
ID3
NC INIT
NC RFU
FGPI2 FWH0
FGPI1 ID0
VSS
NC
NC
NC
IC (VIH)
NC
NC
NC
NC
RC
RP
VPP
VCC
NC
A10
VSS
VSS
VCC
9/41
M50FW040
SIGNAL DESCRIPTIONS
There are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Con-
figuration Pin, IC.
The signals for each interface are discussed in the
Firmware Hub (FWH ) Signal Descripti ons section
and the Address/Address Multiplexed (A/A Mux)
Signal Descriptions section below. The supply sig-
nals are discussed in the Supply Signal Descrip-
tions se cti on bel ow.
Firmware Hub (FWH) Signal Descriptions
For the Firmware Hub (FWH) Interface see Figure
2., Logic Diagram (FWH Interface), and Table
1., Signal Names (FWH Interface).
Input/Output Communications (FWH0-FWH3). All
Input and Output Communication with the memory
take pla ce on th es e pin s. Addr es ses an d Data fo r
Bus Read a nd Bus Wri te operation s are encod ed
on these pins.
Input Communication Frame (FWH4). The In-
put Communication Frame (FWH4) signals the
start of a bus operatio n. When In put Communica -
tion Frame is Low, VIL, on the rising edge of the
Clock a new bus operation is initiated. If Input
Communication Frame is Low, VIL, during a bus
operation then the op erati on is ab orted . When In-
put Communication Frame is High, VIH, the cur-
rent bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID3). The Identifica-
tion Inputs select the address that the memory re-
sponds to. Up to 16 memories can be addressed
on a bus. Fo r an address bit to be ‘0’ the pin can
be left float ing or driven L ow, VIL; a n in terna l pull -
down resistor is included with a value of RIL. For
an address bit to be ‘1’ the pin must be driven
High, VIH; there will be a leakage current of ILI2
through each pin when pulled to VIH; see Table 18.
By convention the boot memory must have ad-
dress ‘0 000’ and all add itional memor ies take se -
quential addresses starting from ‘0001’.
General Purpose Inputs (FGPI0-FGPI4). The Ge n-
eral Purpose Inputs can be used as digital inputs
for the CPU to read. The General Pur pose Inputs
Register holds the values o n these pins . The pins
must hav e st a ble da ta from befo re th e s tart of the
cycle that reads the General Purpose Input Regis-
ter until after the cycle is complete. These pins
must not be left to float, they should be driven Low,
VIL, or High, VIH.
Interface Configuration (IC). The Interface Con-
figuration input selects whether the Firmware Hub
(FWH) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be changed. The state of
the Interface Configuration, IC, should not be
changed during operation.
To select the Firmware Hub (FWH) Interface the
Interface Configuration pin should be left to float or
driven Low, VIL; to select the Address/Address
Multiplex ed (A /A Mux) In terface th e pin sh ould be
driven High, VIH. An internal pull-down resistor is
included with a value of RIL; there will be a leakage
cu rrent of ILI2 through each pin when pulled to VIH;
see Table 18.
Interface Reset (RP). The Interface Reset (RP)
input is used to reset the memory. When Interface
Reset (RP) is set Low, VIL, the memory is in Reset
mode: the ou tput s are put to h igh imped ance a nd
the current consumption is minimized. When RP is
set Hi gh, VIH, t he memory is in normal operation.
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT). The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the inter nal Reset line i s the logical OR (el ectric al
AND) of RP and INIT.
Clock (CLK). The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, FWH0-FWH3. The Clock
conforms to the PCI specification.
Top Block Lock (TBL). The Top Block Lock in-
put is used to prevent the Top Block (Block 7) from
being changed. When Top Block Lock, TBL, is set
Low, VIL, Program and Erase operations in the
Top Block have no e ffect, regardless of t he state
of the Lock R egist er. When To p Block Loc k, TB L,
is set Hig h, VIH, the protection of the Block is de-
termined by the Lock Register. The state of Top
Block L oc k, TBL , doe s not a ffect th e protect ion of
the Main Blocks (Blocks 0 to 6).
Top Block Lock, TBL, must be set prior to a Pro-
gram or E rase operati on is initi ated and must not
be changed until the operation completes or un-
pred ictable re sults may occur. Care sh ould be tak-
en to avoid unpredictable behavior by changing
TBL during Program or Erase Suspend.
Write Protect (WP). The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 6)
from being changed. When Write Protect, WP, is
set Low, VIL, Program and Erase operations in the
Main Blocks have no effect, regardless of the state
of the Lock Registe r. When Write Protect, WP, is
set High, VIH, the protection of the Block deter-
mined by the Lock Register. The state of Write
Protect, WP, does not affect the protection of the
Top Block (Block 7).
Write Protect, WP, must be set prior to a Program
or Erase operation is initiated and must not be
changed until the operation completes or unpre-
M50FW040
10/41
dictable results may occur. Care should be taken
to avoid unpredictable behavior by changing WP
during Program or Erase Suspend.
Reserved for Future Use (RFU). These pins do
not have as signed functi ons in th is rev ision of the
part. They must be left disconnected.
Address/Address Multiplexed (A/A Mux)
Signal Descriptions
For the Address/Address Multiplexed (A/A Mux)
Interface see Figure 2., Logic Diagram (FWH In-
terface), an d Table 1., Signal Nam es (FWH Int er-
face).
Address Inputs (A0-A10). The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A18). They are
latched du r ing any bu s operation by the Row / Col-
umn Address Select input, RC.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs hold the data that is written to or read
from the memory. They output the data stored at
the selected address during a Bus Read opera-
tion. During Bus Write operations they represent
the command s sent to the Comma nd Interface of
the internal state machine. The Data Inputs/Out-
puts, DQ0-DQ7, are latched during a Bus Write
operation.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Writ e En a bl e, W , controls
the Bus Write operation of the memory’s Com-
mand Interface.
Row/Column Address Select (RC). The Row/
Column Address Select input selects whether the
Addr ess Inputs shoul d be latched into the Row Ad-
dress bits (A0-A10) or the Column Address bits
(A11-A18). The Row Address bits are latched on
the falling edge of RC whereas the Column Ad-
dress bits are latched on the rising edge.
Ready/Busy Output (RB). The Ready/Busy pin
gives the status of the memory’s Program/Erase
Controller. When Ready/Busy is Low, VOL, the
memory is busy with a Program or Erase operation
and it will not accept any additional Program or
Erase command except the Program/Erase Sus-
pend comm and. When Ready/Bus y is High, VOH,
the memory is ready for any Read, Program or
Erase operation.
Supply Signal Descriptions
The Supply Signals are the same for both interfac-
es.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents be ing al ter ed wil l be i nv ali d. Afte r VCC
becomes valid the Command In terface is reset to
Read mode.
A 0.1µF capacitor should be connected between
the VCC Supply V oltage pin s and the VSS Ground
pin to decouple the current surges from the power
supply. Both VCC Supply Voltage pins must be
connected to the power supply. The PCB track
widths mu st be suffi cient to carr y the currents re-
quired during program and erase operations.
VPP Optional Supply Voltage. The VPP Optional
Supply Voltage pin is used to select the Fast Erase
option of the m emory and to pro tect the memory.
When VPP < VPPLK Program and Erase operations
cannot be performed and an error is reported in
the Status Register if an attempt to change the
memory co ntents is made. Wh en VPP = VCC Pro-
gram and Eras e oper ations tak e place as norma l.
When VPP = VPPH Fast Erase operations are
used. Any other voltage input to VPP wil l resu lt in
undefined behavior and should not be used.
VPP should not be set to VPPH for more than 80
hours during the life of the memory.
VSS Ground. VSS is the reference for all the volt -
age measure men ts.
Table 3. Block Addresses
Size
(Kbytes) Address Range Block
Number Block Type
64 70000h-7FFFFh 7 Top Block
64 60000h-6FFFFh 6 Main Block
64 50000h-5FFFFh 5 Main Block
64 40000h-4FFFFh 4 Main Block
64 30000h-3FFFFh 3 Main Block
64 20000h-2FFFFh 2 Main Block
64 10000h-1FFFFh 1 Main Block
64 00000h-0FFFFh 0 Main Block
11/41
M50FW040
BUS OPERATIONS
The two interfaces have similar bus operations but
the signals and timings are completely different.
The Firmware Hub (FWH) Interface is the usual in-
terface and all of the functionality of the part is
available through this interface. Only a subset of
functions are available through the Address/Ad-
dress Multiplexed (A/A Mux) Interface.
Follow th e section Firmware Hub (FWH) Bus Op-
erations below and the section Address/Address
Multi ple xed (A/A Mux) Bus Op erati ons bel ow f or a
description of the bus operations on each inter-
face.
Firmware Hub (FWH) Bus Operations
The Firmware Hub (FWH) Interface consists of
four data signals (FWH0-FW H3), one control line
(FWH4) and a clock (CLK). In addition protection
against accidental or malicious data corruption
can be achieved using two further signals (TBL
and WP). Finally two reset signals (R P and INIT)
are available to put the memory into a known
state.
The data si gnals, co ntrol signal and clock ar e de-
signed to be compatible with PCI electrical specifi-
cations. The i nterfa ce ope rates wit h cloc k sp eeds
up to 33MHz.
The following operations can be performed using
the appropr iate bus cycles : Bus Read, Bus Wri te,
Standby, Reset and Block Protection.
Bus Read. Bus Read operations read from the
memory cells, specific registers in the Command
Interface or Fi rmwar e Hub Registers. A va lid Bus
Read operati on star ts when Inp ut Communicati on
Frame, FWH4, is Low , VIL, as Clock rises and the
correct S tar t cyc le is on F WH0 -FWH 3. On the fol-
low in g cl oc k c ycl es t h e Host will s en d the Me mo ry
ID Select, Address and other control bits on
FWH0-FWH3. The memory responds by output-
ting Sync data until the wait-states have elapsed
followed by Data0-Data3 and Data4-Data7.
Refer to Table 4., FWH Bus Read Field Defini-
tions, and Figure 7., FWH Bus Read Waveforms,
for a description of the Field definitions for each
clock cycle of the transfer. See Table 20., FWH In-
terface AC Signal Timing Characteristics, and Fig-
ure 12., FWH Interface AC Signal Timing
Waveforms, for details on the timings of the sig-
nals.
Bus Write. Bus Write operations write to the
Command Interface or Firmware Hub Registers. A
valid Bu s Writ e operation s tarts when I nput Com -
munication Frame, FWH4, is Low, VIL, as Clock
rises and the correct Start cycle is on FWH0-
FWH3. On the following Clock cycles the Host will
send the Memory ID Select, Addres s, other control
bits, Data0-Data3 and Data4-Data7 on FWH0-
FWH3. The memory outputs Sync data until the
wait-states have elapsed.
Refer to Table 5., FWH Bus Write Field Defini-
tions, and Figure 8., FWH Bus Write Waveforms,
for a description of the Field definitions for each
clock cycle of the transfer. See Table 20., FWH In-
terface AC Signal Timing Characteristics, and Fig-
ure 12., FWH Interface AC Signal Timing
Waveforms, for details on the timings of the sig-
nals.
Bus Abort. The Bus Abort operation can be used
to immedi ately abort t he current b us operation. A
Bus Abo rt occurs when F WH4 is dr iven Low , VIL,
during th e bu s oper at ion ; the memory wi ll tri- st ate
the Input/Output Communication pins, FWH0-
FWH3.
Note that, during a Bus Write operation, the Com-
mand Interface starts executing the comma nd as
soon as the data is fully received; a Bus Abort dur-
ing the final TAR cycles is not guaranteed to abort
the command ; the bus, however, will be released
immediately.
Standby. When FWH4 is High, VIH, the memory
is put into Standby mode where FWH0-FWH3 are
put into a high-impedance state and the Supply
Current is reduced to the Standby level, ICC1.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when Interfac e Res et, RP, or CP U
Reset, INIT, i s Low, VIL. RP or INIT m ust be held
Low, VIL, for tPLPH. The memory resets to Read
mode upon return from Reset mode and the Lock
Registers return to their default state s regardless
of their sta te before Res et, see Table 10. If RP or
INIT goes Low, VIL, during a Program or Erase op-
eration, the operation is aborted an d the memor y
cells affected no longer contain valid data; the
memory can ta ke up to tPLRH to abort a Program
or Erase operation.
Block Protection. Block Protection can be
forc ed usin g the sig nals To p Block Lo ck, TBL, and
Write Protect, WP, regardless of the state of the
Lock Regis ter s.
Address/Address Multiplexed (A/A Mux) Bus
Operations
The Address/Address Multiplexed (A/A Mux) Inter-
face has a more traditional style interface. The sig-
nals con si st of a mu lti pl exed addres s si gna ls ( A0 -
A10), data signals, (DQ0-DQ7) and three control
signals (RC, G, W). An addit ional signal, RP, can
be used to reset the memory.
The Address/Address Multiplexed (A/A Mux) Inter-
face is included for use by Flash Programming
equipment fo r faster factory pro grammin g. Only a
M50FW040
12/41
subset of the features available to the Firmware
Hub (FWH) Interface are available; these include
all the Commands but exclude the Security fea-
tures and other registers.
The following operations can be performed using
the appropr iate bus cycles : Bus Read, Bus Wri te,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface is selected all the blocks are unprotect-
ed. It is not possible to protect any blocks through
this interface.
Bus Read. Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature and the Status Register. A valid
Bus Read operation begins by latching the Row
Address and Column Address signals into the
memory using the Address Inputs, A0-A10, and
the Row/Column Address Select RC. Then Write
Enable (W) and Interface Reset (RP) must be
High, VIH, and Output Enable, G, Low, VIL, in order
to perform a Bus Read operation. The Data Inputs/
Outputs wi ll output the value, s ee Figure 14., A /A
Mux Interface Read AC Waveforms, and Table
22., A/A Mux Interface Read AC Characteristics,
for details of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the Ad-
dress Inputs, A0-A10, and the Row/Column Ad-
dress Select RC. The data should be set up on the
Data Inputs/Outputs; Output Enable, G, and Inte r -
face Reset, RP, must be High, VIH and Write En -
able, W, must be Low, VIL. The Data Inputs/
Outputs are latched on the rising edge of Write En-
able, W. See Figure 15., A/A Mux Interface Write
AC Wavef orms , and Ta ble 23 ., A /A Mux In terfac e
Write AC Characteristics, for details of the timing
requirements.
Output Disable. The data outputs are high-im-
pedance when the Output Enable, G, is at VIH.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode wh en RP is Low, VIL. RP mus t be
held Low, VIL for tPLPH. If RP is goes Low, VIL, dur-
ing a Program or Erase operation, the operation is
aborted and the memory cells affected no longer
contain valid data; the memory can take up to tPL-
RH to abort a Program or Erase operation.
Table 4. FWH Bus Read Field Definitions
Clock
Cycle
Number
Clock
Cycle
Count Field FWH0-
FWH3 Memory
I/O Description
1 1 START 1101b I On the rising edge of CLK with FWH4 Low, the contents of FWH0-
FWH3 indicate the start of a FWH Read cycle.
2 1 IDSEL XXXX I Indicates which FWH Flash Memory is selected. The value on FWH0-
FWH3 is compared to the IDSEL strapping on the FWH Flash
Memory pins to select which FWH Flash Memory is being addressed.
3-9 7 ADDR XXXX I A 28-b it add ress ph ase is tra nsf err ed s t art ing wit h the mos t s ign ifi can t
nibble first.
10 1 MSIZE 0000b I Always 0000b (only single byte transfers are supported).
11 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.
12 1 TAR 1111b
(float) OThe FWH Flash Memory takes control of FWH0-FWH3 during this
cycle.
13-14 2 WSYNC 0101b O The FWH Flash Memory drives FWH0-FWH3 to 0101b (short wait-
sync) for two clock cycles, indicating that the data is not yet available.
Two wait-states are always included.
15 1 RSYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating
that data will be available dur ing the next clock cycle.
16-17 2 DATA XXXX O Data transfer is two CLK cycles, starting with the least significant
nibble.
18 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate a
turnar oun d cyc le .
19 1 TAR 1111b
(float) N/A The FWH Flash Memory floats its outputs, the host takes control of
FWH0-FWH3.
13/41
M50FW040
Figure 7. FWH Bus Read Waveforms
Table 5. FWH Bus Write Field Definitions
Figure 8. FWH Bus Write Waveforms
Clock
Cycle
Number
Clock
Cycle
Count Field FWH0-
FWH3 Memory
I/O Description
1 1 START 1110b I On the risin g ed ge of CL K with FWH4 Low, the conten ts of
FWH0-F WH 3 ind ica te the start of a FWH Writ e Cyc le.
2 1 IDSEL XXXX I
Indicates which FWH Flash Memory is selected. The value
on FWH0-FWH3 is compared to the IDSEL strapping on the
FWH Flash Memory pins to select which FWH Flash
Memory is bei ng addr ess ed .
3-9 7 ADDR XXXX I A 28-bit address phase is transferred starting with the most
significa nt nib ble first.
10 1 MSIZE 0000b I Always 0000b (single byte transfer).
11-12 2 DATA XXXX I Data transfer is two cycles, starting with the least significant
nibble.
13 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
14 1 TAR 1111b
(float) OThe FWH Flash Me mo ry takes contr ol of FW H0 -F WH 3
during this cycle.
15 1 SYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating it has received data or a command.
16 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b,
indicating a turnaround cycle.
17 1 TAR 1111b
(float) N/A The FWH Flash Memory floats its outputs and the host takes
control of FWH0-FWH3.
AI03437
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START IDSEL ADDR MSIZE TAR SYNC DATA TAR
11712322
AI03441
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START IDSEL ADDR MSIZE DATA TAR SYNC TAR
11712212
M50FW040
14/41
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations.
After power-up or a Reset operation the memory
enters Read mode.
The commands are summarized in Table
7., Commands. Refer to Table 7. in conjunction
with the text descriptions below.
Read Memory Array Command. The Read Mem-
ory Array command returns the memory to its
Read mode where it behaves like a ROM or
EPROM . One Bus Write cycle is required to issue
the Read Memory Array command and return the
memory to Re ad mode . Onc e the com mand i s is-
sued the memory re mains in Rea d mo de until an -
other command is issued. From Read mode Bus
Read operations will access the memory array.
While the Program/Erase Controller is executing a
Program or Erase operation the memory will not
accept the Read Memory Array command until the
operation completes.
Read Status Register Command. The Read Sta-
tus Register co mmand is us ed to read the S tatus
Register. One Bus Write cycle is required to issue
the Read Status Register command. Once the
comma nd is is sued s ubsequen t Bu s Read opera -
tions read the Status Register until another com-
mand is issued. See the section on the Status
Register for details on the definitions of the Status
Register bits.
Read Ele ctronic Sig natur e Comma nd. The Read
Electronic Signature command is used to read the
Manufacturer Code and the Device Code. One
Bus Write cycle is required to issue the Read Elec-
tronic Signa tur e co mma nd. Onc e the comm and is
issued s ub se que nt B us Re ad o perations re ad the
Manufacturer Code or the Device Code until an-
other command is issued.
After the Read Electronic Signature Command is
issued the Manufacturer Code and Device Code
can be rea d us in g B us Read ope ra tio ns usi ng the
addresses in Table 6.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. Two Bus Write opera-
tions are re qui red to is su e the co mmand; the sec-
ond Bus Wri te cy cl e la tch es the a ddres s an d da ta
in the internal state machine and starts the Pro-
gram/Erase Controller. Once the command is is-
sued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
If the address falls in a protected block then the
Program operation will abort, the data in the mem-
ory array wil l not be chan ged and the Stat us Reg -
ister will output the error.
During the Program operation the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other comm and s wil l be igno red. T yp ical P ro gram
times are given in Table 12.
Note that the Program command cannot change a
bit set at ‘0’ back to ‘1’ and attempting to do so will
not cause any modification on its value. The Erase
command must be used to set all of the bits in the
block to ‘1’.
See Figure 19., Program Flowchart and Pseudo
Code, for a suggested flowchart on using the Pro-
gram command.
Erase Command. The Erase command can be
used to erase a block. Two Bus Write operations
are required to issue the command; the second
Bus Write cycle latches the block address in the in-
ternal state machine and starts the Program/Erase
Controller. Once the command is issued subse-
quent Bus Read operatio ns read the S tatus Reg-
ister. See the section on the Status Register for
details on the definitions of the Status Register
bits.
If the block is protected then the Erase operation
will abort, the data in the block will not be changed
and the Status Register will output the er ro r.
During the Erase operation the memory will only
accept the Read Status Register command and
the Program/Erase Suspend command. All other
commands will be ignored. Typical Erase times
are given in Table 12.
The Erase command sets all of the bits in the block
to ‘1’. All previous data in the block is lost.
See Figure 21., Erase Flowchart and Pseudo
Code, for a suggested flowchart on using the
Erase command.
Clear Status Register Command. The Clear Sta-
tus Register command can be used to reset bits 1,
3, 4 and 5 in the Status Register to ‘0’. One Bus
Write is required to issue the Clear Status Register
command. Once the command is issued the mem-
ory ret urns to its previous mode, subseq uent Bus
Read operations continue to output the same data.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Program
or Erase command is issued. If an error occurs
then it is essential to clear any error bits in the Sta-
tus Register by issuing the Clear Status Register
command before attempting a new Program or
Erase command.
15/41
M50FW040
Program/ Erase Suspend Command. The Pro-
gram/Erase Suspend command can be used to
pause a Program or Erase operation. One Bus
Write cycle is required to issue the Program/Erase
Suspend command and pause the Program/Erase
Controller . Once th e comm and is issue d it is n ec-
essary to poll the Program/Erase Controller Status
bit to find out wh en the Program /Erase Controlle r
has paused; no other commands will be accepted
until the Program/Erase Controller has paused.
After the Program/Erase Controller has paused,
the memory will continue to output the Status Reg-
ister until another command is issued.
During the polling period between issuing the Pro-
gram/Erase Suspend command and the Program/
Erase Controller pa using it i s possible for the op -
eration to complete. Once Program/Erase Control-
ler Status bit indicates that the Program/Erase
Controller is no longer active, the Program Sus-
pend Status bit or the Erase Suspend Status bit
can be used to determine if the operation has com-
pleted or is suspended. For timing on the delay be-
tween issuing the Program/Erase Suspend
command and the Program/Erase Controller
pausing see Table 12.
During Pr ogr am /Eras e S usp end th e Read M emo-
ry Array, Read Status Register, Read Electronic
Signature and Program/Erase Resume com-
mands will be accepted by the Command Inter-
face. Additi on all y, if the su spe nded operation wa s
Erase then the Program command will also be ac-
cepted; only the blocks not being erased may be
read or programmed correctly.
See Figure 20., Program Suspend & Resume
Flowchart and Pseudo Code, and Figure
22., Erase Suspend & Resume Flowchart and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Suspend command.
Program/Erase Resume Command. The Pro-
gram/Erase Resume comma nd ca n be us ed to re -
start the Program/Erase Controller after a
Program /E rase S us pen d operation has pau se d it.
One Bus Write cycle is required to issue the Pro -
gram/Erase Resume command. Once the com-
mand is issued subsequent Bus Read operations
read the Status Register.
Table 6. Read Electronic Signature
Code Address Data
Manufacturer Code 00000h 20h
Device Co de 00001h 2C h
M50FW040
16/41
Table 7. Commands
Note: X Don’t Care, PA Program Address, PD Pr ogram Data, BA Any address in the Block.
Read Memor y Arra y . After a Read Memory Array command , read the memory as normal until another command is issued.
Read St atu s Register. After a Read Stat us Regis ter command, read the Stat us Registe r as normal unt il anoth er co mmand is issue d.
Read E l e c t r on ic Signatu re. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another com-
mand is issued .
Erase, Program. Af ter these commands read the Status Register until the comma nd completes and another command is issued.
Clear Status Register. Af ter the Clear Stat us Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’.
Program/Erase Suspend. After the Prog ram/Erase Suspend command has been accepted, issue Read Memory Array, Read Status
Register, Program (during Erase suspend) and Program/Erase resume commands.
Prog ram/Era se Resu me. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the
Status Regis ter until the Pro gram/Erase Controller completes and the memory returns to Read Mode.
Invalid/Reserved. Do not use Invalid or Reserved comman ds.
Command
Cycles
Bus Write Operations
1st 2nd
Address Data Address Data
Read Memory Array 1 X FFh
Read Status Register 1 X 70h
Read Electronic Signature 1 X 90h
1 X 98h
Program 2 X 40h PA PD
2 X 10h PA PD
Erase 2 X 20h BA D0h
Clear Status Register 1 X 50h
Program/Eras e Su spe nd 1 X B0h
Program /E r as e Re sum e 1 X D0h
Invalid/Reserved
1 X 00h
1 X 01h
1 X 60h
1X 2Fh
1X C0h
17/41
M50FW040
STATUS REGISTER
The Status Register provides information on the
current or previous Program or Erase operation.
Different b its in the S tatus Registe r convey diff er-
ent information and errors on the operation.
To re ad t h e Sta t us R e gi st e r t h e Rea d St a tus Re g-
ister command can be issued. The Status Register
is automatically read after Program, Erase and
Program/Erase Resume commands are issued.
The Status Register can be read from any ad-
dress.
The Status Register bits are summarized in Status
Register Bits. Refe r to Table 8. in conju nct ion wit h
the text descriptions below.
Program/Er ase Controller Stat us (Bit 7). The Pro-
gr a m/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
‘0’, the Program/Erase Controller is active; when
the bit is ‘1’, the Program/Erase Controller is inac-
tive.
The Pro gram/Eras e Controll er Status is ‘0’ imme -
diately afte r a Prog ram/Er ase Suspe nd comma nd
is issued until the Program/Erase Controller paus-
es. After the Program/Erase Controller pauses the
bit is ‘1’.
During Program and Erase operation the Pro-
gram/Erase Controller Status bit can be polled to
find the en d of the op erati on. T he othe r bits in the
Status Register should not be tested until the Pro-
gram/Erase Controller completes the operation
and the bit is ‘1’.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status, VPP
Status and B lock Pr otection Status b its sh ould be
tested for errors.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that an Erase operation
has been suspended and is waiting to be re-
sumed. The Erase Suspend Status should only be
considered valid when the Program/Erase Con-
troller Status bit is ‘1’ (Program/Erase Controller
inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Eras e Sus pe nd Sta tus bit is ‘0’ the Pro -
gram/Erase Controller is active o r has completed
its operation; when the bit is ‘1’ a Program/Erase
Suspend command has been issued and the
memory is waiting for a Program/Erase Resume
command.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns to ‘0’.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has applied the
maximum number of erase pulses to the block and
still failed to verify that the block has erased cor-
rectly. The Erase Status bit should be read once
the Program/Erase Controller Status bit is ‘1’ (Pro-
gram/Erase Controller inactive).
When the Erase Status bit is ‘0’ the memory has
successfully verified that the block has erased cor-
rectly; when the Erase Status bit is ‘1’ the Pro-
gram/Erase Controller has applied the maximum
number of pulses to the block and still failed to ver-
ify that the block has erased correctly.
Once the Erase Status bit is set to ‘1’ the it can
only be reset to ‘0’ by a Clear Status Register com-
mand or a hardware reset. If it is set to ‘1’ it should
be reset before a new Program or Erase command
is issued, otherwise the new command will appear
to fail.
Program Status (Bit 4). The Program Status bit
can b e used to iden tify if the memor y ha s app lied
the maximum number of program pulses to the
byte an d still failed to verify that th e byte has p ro-
grammed correctly. The Program Status bit should
be read once the Program/Erase Controller Status
bit is ‘1’ (Program/Erase Controller inactive).
When the Program Status bit is ‘0’ the memory has
successfully verified that the byte has pro-
grammed correctly; when the Program Status bit is
‘1’ the Program/Erase Controller has applied the
maximum number of pulses to the byte and still
failed to v erify that the byte h as pr ogram med cor -
rectly.
Once the Program Status bit is set to ‘1’ it can only
be reset to ‘0’ by a Clear Status Register com-
mand or a hardware reset. If it is set to ‘1’ it should
be reset before a new Program or Erase command
is issued, otherwise the new command will appear
to fail.
VPP Status (Bit 3). The VPP Status bit can be
used to identify an invalid voltage o n the VPP pin
during Program and Erase operations. The VPP
pin is only sampled at the beginning of a Program
or Erase operation. Inde terminate res ults can oc-
cur if VPP becomes invalid during a Program or
Erase operation.
When the VPP Status bit is ‘0’ the voltage on the
VPP pin was samp le d at a va li d vol tage; when the
VPP Status bit is ‘1’ the VPP pin has a voltage that
is below the VPP Lockout Voltage, VPPLK, the
memory is protected; Program and Erase opera-
tion cannot be performed.
Once the VPP Status bit set to ‘1’ it can only be re-
set to ‘0’ by a Clear Status Register command or a
hardware reset. If it is set to ‘1’ it s hould be reset
before a new Program or Erase command is is-
sued, othe rwise the new command will appea r to
fail.
M50FW040
18/41
Program Suspend Status (Bit 2). The Program
Susp en d S t at us bi t i ndicate s t h at a Progra m o pe r-
ation has been suspended and is waiting to be re-
sumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Control-
ler inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Program Suspend Status bit is ‘0’ the
Program/Erase Controller is active or has complet-
ed its operation; when the bit is ‘1’ a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
su me command.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns to
‘0’.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if the Pro-
gram or Erase operation has tried to modify the
contents of a protected block. When the Block Pro-
tection Status bit is to ‘0’ no Program or Erase op-
erations ha ve been attem pte d to protected bloc ks
since the last Clear Status Register command or
hardware r eset; when the Bloc k P ro tectio n S tatu s
bit is ‘1’ a Program or Erase operation has been at-
tempted on a protected block.
Once it is set to ‘1 ’ the Block Pr otect ion Status bit
can only be reset to ‘0’ by a Clear Status Register
command or a hardware reset. If it is set to ‘1’ it
should be reset before a new Program or Erase
comma nd is is sued, o the rwise the new co mma nd
will appear to fail.
Using the A/A Mux Interface the B lock Protecti on
Status bit is always ‘0’.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value should be masked.
Table 8. Status Register Bits
Note: 1. For Program operations during Erase Sus pend Bit 6 is ‘1’, othe rwise Bit 6 is ‘0’.
Operation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Program active ‘0’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Program suspended ‘1 X(1) ‘0’ ‘0’ ‘0’ ‘1’ ‘0’
Program completed successfully ‘1’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Program failure due to VPP Error ‘1’ X(1) ‘0’ ‘0’ ‘1’ ‘0’ ‘0’
Progr a m f a i lu r e du e t o B lo c k P r ot ec t i on ( FW H I n te r fa ce o n ly ) ‘1’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘1’
Program failure due to cell failure ‘1’ X(1) ‘0’ ‘1’ ‘0’ ‘0’ ‘0’
Erase active ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Erase suspended ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘ 0’
Erase completed successfully ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Erase failure due to VPP Error ‘1’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’
Erase failure due to Block Protection (FWH Interface only) ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’
Erase failure due to failed cell(s) in block ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’
19/41
M50FW040
FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS
When the Firmware Hub Interface is selected sev-
eral additional registers can be accessed. These
registers control the protection status of the
Blocks, read the General Purpose Input pins and
identify the memory using the Electronic Signature
codes. See Table 9. for the memory map of the
Configuration Registers.
Lock Registers
The Lock Registers control the protection status of
the Blocks. Each Block has its own Lock Register.
Three bits within each Lock Register control the
protection of each block, the Write Lock Bit, the
Read Lock Bit and the Lock Down Bit.
The Lock Registers can be read and written,
though care should be taken when writing as, once
the Lock Down Bi t is set, ‘1’, f urther m odific ation s
to the Lock Register cannot be made until cleared,
to ‘0’, by a reset or power-up.
See Table 10. for details on the bit definitions of
the Lock Registers.
Write Lock. The Write Lock Bit determines
whether the contents of the Block can be modified
(using the Program or Erase Command). When
the Write Lock Bit is set, ‘1’, the block is write pro-
tected; any operations that attemp t to change the
data in the block will fail and the Status Register
will r epo rt t h e er r or . W h en t he Wr it e Lo ck Bi t is r e-
set, ‘0’, the block is not write protected through the
Lock Register and may be modified unless write
protected through some other means.
When VPP is less than VPPLK all blocks are pro-
tected and cannot be modified, regardless of the
state of the Write Lock Bit. If Top Block Lock, TBL,
is Low, VIL, then the Top Block (Block 7) is write
protected and cannot be modified. Similarly, if
Write Protect, WP, is Low, VIL, then the Main
Blocks (Blocks 0 to 6) are write protected and can-
not be modified.
After power-up or reset the Write Lock Bit is al-
ways set to ‘1’ (write protected).
Read Lock. The Read Lock bit determines
whether the contents of the Block can be read
(f rom Rea d mode ). Wh en the R ead Lo ck Bit is set ,
‘1’, the bloc k is read pr otecte d; any opera tion that
attempts to read the contents of the block will read
00h instead. W hen the Re ad Loc k B it is r es et, ‘0 ’,
read operations in the Block return the data pro-
grammed into the block as expected.
After power-up or reset the Read Lock Bit is al-
ways reset to ‘0’ (not read protected).
Lock Down. The Lock Down Bit provides a
mechanis m for pr otecti ng s oftwa re data fr om sim-
ple ha cking and ma licious a ttack. When the Lock
Down Bit is set, ‘1’, further modification to the
Write Lock, Read Lock and Lock Down Bits cannot
be perform ed. A rese t or pow er -up is requir ed be-
fore changes to these bits can be made. When the
Lock Down Bit is reset, ‘0’, the Write Lock, Read
Lock and Lock Down Bits can be changed.
Firmware Hub (FWH) General Purpose Input
Register
The Firm ware Hub ( FWH) Ge neral Purpos e Input
Register holds the state of the Firmware Hub Inter-
face General Purpose Input pins, FGPI0-FGPI4.
When this register is read, the state of these pins
is returned. This register is read-only and writing to
it has no effect.
The signals on the Firmware Hub Interface Gener-
al Purpose Input pins should remain constant
throughout the whole Bus Read cycle in order to
guarantee that the correct data is read.
Manufacturer Code Register
Reading the Manufacturer Code Register returns
the manuf acturer co de for the memor y. The man -
ufacturer code for STMicroelectronics is 20h. This
register is read-only and writing to it has no effect.
Device Code Register
Reading the Device Code Register returns the de-
vice code for the memory, 2Ch. This register is
read-only and writing to it has no effect.
Firmware Hub (FWH) General Purpose Input
Register
The Firm ware Hub ( FWH) Ge neral Purpos e Input
Register holds the state of the Firmware Hub Inter-
face General Purpose Input pins, FGPI0-FGPI4.
When this register is read, the state of these pins
is returned. This register is read-only and writing to
it has no effect.
The signals on the Firmware Hub Interface Gener-
al Purpose Input pins should remain constant
throughout the whole Bus Read cycle in order to
guarantee that the correct data is read.
Manufacturer Code Register
Reading the Manufacturer Code Register returns
the manuf acturer co de for the memor y. The man -
ufacturer code for STMicroelectronics is 20h. This
register is read-only and writing to it has no effect.
Device Code Register
Reading the Device Code Register returns the de-
vice code for the memory, 2Ch. This register is
read-only and writing to it has no effect.
M50FW040
20/41
Table 9. Firmware Hub Register Configuration Map
Table 10. Lock Register Bit Definitions
Note: 1 . Applies to Top Block Lo ck Register (T_ BLOCK_LK) and Top Bl ock [-1] Loc k Register (T_MINUS 01_LK) to Top Bloc k [-7] Lock Reg-
ister (T_MINUS07_LK).
Table 11. General Purpose Inputs Register Definition
Note: 1. Applies to the Ge neral Purpose Inputs Register (FGPI-REG).
Mnemonic Register Name Memory
Address Default
Value Access
T_BLOCK_LK Top Block Lock Register (Block 7) FBF0002h 01h R/W
T_MINUS01_LK Top Block [-1] Lock Register (Block 6) FBE0002h 01h R/W
T_MINUS02_LK Top Block [-2] Lock Register (Block 5) FBD0002h 01h R/W
T_MINUS03_LK Top Block [-3] Lock Register (Block 4) FBC0002h 01h R/W
T_MINUS04_LK Top Block [-4] Lock Register (Block 3) FBB0002h 01h R/W
T_MINUS05_LK Top Block [-5] Lock Register (Block 2) FBA0002h 01h R/W
T_MINUS06_LK Top Block [-6] Lock Register (Block 1) FB90002h 01h R/W
T_MINUS07_LK Top Block [-7] Lock Register (Block 0) FB80002h 01h R/W
FGPI_REG Firmware Hub (FWH) General Purpose Input Register FBC0100h N/A R
MANUF_REG Manufacturer Code Register FBC0000h 20h R
DEV_REG Device Code Register FBC0001h 2Ch R
Bit Bit Name Value Function
7-3 Reserved
2 Read-Lock ‘1’ Bus Read operations in this Block always return 00h.
‘0’ Bus read operations in this Block return the Memory Array contents. (Default value).
1 Lock-Down ‘1’ Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a ‘1’ is
written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset to ‘0’ following
a Reset (using RP or INIT) or after power -up .
‘0’ Read-Lock and Write-Lock can be changed by writing new values to them. (Default value).
0 Write-Lock ‘1’ Program and Erase operations in this Block will set an error in the Status Register. The
memory contents will not be changed. (Default value).
‘0’ Pr og ra m a nd Er as e op er at ion s in t hi s Bl oc k ar e e xe cu t ed an d w i ll m od if y t he Bl oc k co nt en ts.
Bit Bit Name Value Function
7-5 Reserved
4 FGPI4 ‘1’ Input Pin FGPI4 is at VIH
‘0’ Input Pin FGPI4 is at VIL
3 FGPI3 ‘1’ Input Pin FGPI3 is at VIH
‘0’ Input Pin FGPI3 is at VIL
2 FGPI2 ‘1’ Input Pin FGPI2 is at VIH
‘0’ Input Pin FGPI2 is at VIL
1 FGPI1 ‘1’ Input Pin FGPI1 is at VIH
‘0’ Input Pin FGPI1 is at VIL
0 FGPI0 ‘1’ Input Pin FGPI0 is at VIH
‘0’ Input Pin FGPI0 is at VIL
21/41
M50FW040
PROGRAM AND ERASE TIMES
The Program and Erase times are shown in Table
12.
Table 12. Program and Erase Times
Note: 1. TA = 25°C, VCC = 3.3V
2. Sampled only, not 100% test ed.
Parameter Test Condition Min Typ (1) Max Unit
Byte Progr am 10 200 µs
Block Program 0.4 5 sec
Block Erase VPP = 12V ± 5% 0.75 8 sec
VPP = VCC 110sec
Program/Erase Suspend to Program pause(2) 5 µs
Program/Erase Suspend to Block Erase pause(2) 30 µs
M50FW040
22/41
MAXIMUM RATING
Stressing the dev ice above the ratin g lis ted in the
Absolute Maximum Ratin gs table ma y cause pe r-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other cond itions above thos e indicated in the
Operating sections of this specification is not im-
plie d. Exposu re to Abso lute Max imum Rat ing con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 13. Ab solute Maximum Ratings
Note: 1. Compliant with JEDEC Std J-ST D-020B (for smal l body , Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, and
the European directive on Re st rictions on Hazardous Substanc es (RoHS) 2002/95/EU.
2. Minimum Voltage may undershoot to –2V and for less than 20ns during transitions . Maximum Voltage may overshoot to VCC +2V
and for less than 20ns during transitions.
Symbol Parameter Min Max Unit
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering See note 1 °C
VIO (2) Input or Output Voltage –0.6 VCC + 0.6 V
VCC Supply Voltage –0.6 4 V
VPP Progra m Voltage –0.6 13 V
23/41
M50FW040
DC AND AC PARA METERS
This section summarizes the operating measure-
ment condi tions, an d the DC and AC characteri s-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 14., Table 15.
and Table 16. Designers should check that the op-
erating conditions in their circuit match the operat-
ing conditions when relying on the quoted
parameters.
Table 14. Operating Conditions
Table 15. FWH Interface AC Measurement Conditions
Table 16. A/A Mux Interface AC Measurement Conditions
Figure 9. FWH Interface AC Testing Input Output Waveforms
Symbol Parameter Min Max Unit
TAAmbient Operating Temperature (Device Grade 1) 0 70 °C
Ambient Operating Temperature (Device Grade 5) –20 85 °C
VCC Supply Voltage 3 3.6 V
Parameter Value Unit
Load Capacitance (CL)10 pF
Input Rise and Fall Times ≤ 1.4 ns
Input Pulse Voltages 0.2 VCC and 0.6 VCC V
Input and Output Timing Ref. Voltages 0.4 VCC V
Parameter Value Unit
Load Capacitance (CL)30 pF
Input Rise and Fall Times ≤ 10 ns
Input Pulse Voltages 0 to 3 V
Input and Output Timing Ref. Voltages 1.5 V
AI03404
0.6 VCC
0.2 VCC
0.4 VCC
IO > ILO
IO < ILO IO < ILO
Input and Output AC Testing Waveform
Output AC Tri-state Testing Waveform
M50FW040
24/41
Figure 10. A/A Mux Interface AC Testing Input Output Waveform
Table 17. Impedance
Note: 1. Sampled only, not 100% tested.
2. See PCI Specific a ti o n.
3. TA = 25 °C, f = 1 MHz).
Symb ol Parame te r Test Co ndition Min Max Unit
CIN(1) Input Capacitance VIN = 0V 13 pF
CCLK(1) Clock Capacitanc e VIN = 0V 312pF
LPIN(2) Recommended Pin
Inductance 20 nH
AI01417
3V
0V
1.5V
25/41
M50FW040
Table 18. DC Characteristics
Note: 1. Sampled only, not 100% tested.
2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs.
Symbol Parameter Interface Test Condition Min Max Unit
VIH Input High Voltage FWH 0.5 VCC VCC + 0.5 V
A/A Mux 0.7 VCC VCC + 0.3 V
VIL Input Low Voltage FWH –0.5 0.3 VCC V
A/A Mux -0.5 0.8 V
VIH(INIT)INIT Input High Voltage FWH 1.35 VCC + 0.5 V
VIL(INIT)INIT Input Low Voltage FWH –0.5 0.2 VCC V
ILI(2) Input Leakag e Current 0V ≤ VIN ≤ VCC ±10 µA
ILI2 IC, IDx Input Leakage
Current IC, ID0, ID1, ID2, ID3 = VCC 200 µA
RIL IC, IDx Input Pull Low
Resistor 20 100 kΩ
VOH Output High Voltage FWH IOH = –500µA0.9 VCC V
A/A Mux IOH = –100µAVCC – 0.4 V
VOL Output Low Voltage FWH IOL = 1.5mA 0.1 VCC V
A/A Mux IOL = 1.8mA 0.45 V
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA
VPP1 VPP Voltage 33.6V
VPPH VPP Voltage
(Fast Erase) 11.4 12.6 V
VPPLK(1) VPP Lockout Voltage 1.5 V
VLKO(1) VCC Lockout Voltage 1.8 2.3 V
ICC1 Supply Current (Standby) FWH FWH4 = 0.9 VCC, VPP = VCC
All other inputs 0.9 VCC to 0.1 VCC
VCC = 3.6V, f(CLK) = 33MHz 100 µA
ICC2 Supply Current (Standby) FWH FWH4 = 0.1 VCC, VPP = VCC
All other inputs 0.9 VCC to 0.1 VCC
VCC = 3.6V, f(CLK) = 33MHz 10 mA
ICC3 Supply Current
(Any internal operation
active) FWH VCC = VCC max, VPP = VCC
f(CLK) = 33MHz
IOUT = 0mA 60 mA
ICC4 Supply Current (Read) A/A Mux G = VIH, f = 6MHz 20 mA
ICC5(1) Supply Current
(Program/Erase) A/A Mu x Program /E ra se Co ntr olle r Act ive 20 mA
IPP VPP Supply Curren t
(Read/Standby) VPP > VCC 400 µA
IPP1(1) VPP Supp ly Cur ren t
(Program/Erase active) VPP = VCC 40 mA
VPP = 12V ± 5% 15 mA
M50FW040
26/41
Figure 11. FWH Interface Clock Waveform
Table 19. FWH Interface Clock Characteristics
Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed
by design rather than test ed. Refer to PCI Spec ification.
Symbol Param et er Te st Co nd itio n Value Unit
tCYC CLK Cycle Time(1) Min 30 ns
tHIGH CLK Hig h Time Min 11 ns
tLOW CLK Low Time Min 11 ns
CLK Slew Ra te peak to peak Min 1 V/ns
Max 4 V/ns
AI03403
tHIGH tLOW
0.6 VCC
tCYC
0.5 VCC
0.4 VCC
0.3 VCC
0.2 VCC
0.4 VCC, p-to-p
(minimum)
27/41
M50FW040
Figure 12. FWH Interface AC Signal Timing Waveforms
Table 20. FWH Interface AC Signal Timing Characteristics
Note: 1 . The timing measurement s for Active/ Float transit ions are defin ed when t he curr ent t hrough the pi n equa ls the leakage current spec-
ification.
2. Applies to all inputs except CLK.
Symbol PCI
Symbol Parameter Test Condition Value Unit
tCHQV tval CLK to Data Out Min 2 ns
Max 11 ns
tCHQX(1) ton CLK to Active
(Float to Active Delay) Min 2 ns
tCHQZ toff CLK to Inactive
(Active to Float Delay) Max 28 ns
tAVCH
tDVCH tsu Input Set-up Time(2) Min 7 ns
tCHAX
tCHDX thInput Hold Time(2) Min 0 ns
AI03405
tCHQV
tCHQX
tCHQZ
tCHDX
VALID
FWH0-FWH3
tDVCH
CLK
VALID OUTPUT DATA FLOAT OUTPUT DATA VALID INPUT DATA
M50FW040
28/41
Figure 13. Reset AC Waveforms
Table 21. Reset AC Characteristics
Note: 1. See Chapter 4 of the PCI Specification.
Symbol Parameter Test Condition Value Unit
tPLPH RP or INIT Reset Pulse Width Min 100 ns
tPLRH RP or INIT Low to Reset Program/Erase Inactive Max 100 ns
Program/Erase Active Max 30 µs
RP or INIT Slew Rate(1) Rising edge only Min 50 mV/ns
tPHFL RP or INIT High to FWH4 Low FWH Interface only Min 30 µs
tPHWL
tPHGL RP High to Wr it e Enab le or Outp ut
Enable Lo w A/A Mux Interface only Min 50 µs
AI03420
RP, INIT
W, G, FWH4
tPLPH
RB
tPLRH
tPHWL, tPHGL, tPHFL
29/41
M50FW040
Figure 14. A/A Mux Interface Read AC Waveforms
Table 22. A/A Mux Interface Read AC Characteristics
Note: 1. G may be delayed up to tCHQV – tGLQV after the rising edge of RC without impact on tCHQV.
Symbol Parameter Test Condition Value Unit
tAVAV Read Cycle Time Min 250 ns
tAVCL Row Address Val id to RC Low Min 50 ns
tCLAX RC Low to Row Address Transition Min 50 ns
tAVCH Column Address Valid to RC high Min 50 ns
tCHAX RC High to Column Address Transition Min 50 ns
tCHQV(1) RC High to Output Valid Max 150 ns
tGLQV(1) Output Enable Low to Output Valid Max 50 ns
tPHAV RP High to Row Address Valid Min 1 µs
tGLQX Output Enable Low to Output Transition Min 0 ns
tGHQZ Output Enable High to Output Hi-Z Max 50 ns
tGHQX Output Hold from Output Enable High Min 0 ns
AI03406
tAVAV
tCLAX tCHAX
tGLQX
tGLQV
tGHQX
VALID
A0-A10
G
DQ0-DQ7
RC
tCHQV
tGHQZ
COLUMN ADDR VALID
W
RP
tPHAV
ROW ADDR VALID NEXT ADDR VALID
tAVCL tAVCH
M50FW040
30/41
Figure 15. A/A Mux Interface Write AC Waveforms
Table 23. A/A Mux Interface Write AC Characteristics
Note: 1. Sampled only, not 100% tested.
2. Appl i c a b l e i f VPP is seen as a logic input (VPP < 3.6V).
Symbol Parameter Test Condition Value Unit
tWLWH Write Enable Low to Write Enable High Min 100 ns
tDVWH Data Valid to Write Enable High Min 50 ns
tWHDX Write Enable High to Data Transition Min 5 ns
tAVCL Row Address Val id to RC Low Min 50 ns
tCLAX RC Low to Row Address Transition Min 50 ns
tAVCH Column Address Valid to RC High Min 50 ns
tCHAX RC High to Column Address Transition Min 50 ns
tWHWL Write Enable High to Write Enable Low Min 100 ns
tCHWH RC High to Write Enable High Min 50 ns
tVPHWH(1) VPP High to Write Enable High Min 100 ns
tWHGL Write Enable High to Output Enable Low Min 30 ns
tWHRL Write Enable High to RB Lo w Min 0 ns
tQVVPL(1,2) Output Valid, RB High to VPP Low Min 0 ns
AI04185
tCLAX
tCHAX
tWHDXtDVWH
VALID SRD
A0-A10
G
DQ0-DQ7
RC
tCHWH
tWHRL
C1
W
R1
tAVCL
tAVCH
R2 C2
tWLWH
tWHWL
RB
VPP
tVPHWH tWHGL
tQVVPL
DIN1 DIN2
Write erase or
program setup
Write erase confirm or
valid address and data
Automated erase
or program delay Read Status
Register Data Ready to write
another command
31/41
M50FW040
PACKAGE MECHANICAL
Figure 16. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline
Note: Drawing is not to scale.
PLCC-A
D
E3 E1 E
1 N
D1
D3
CP
B
E2
e
B1
A1
A
R
0.51 (.020)
1.14 (.045)
F
A2
E2
D2 D2
M50FW040
32/41
Table 24. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 3.18 3.56 0.125 0.140
A1 1.53 2.41 0.060 0.095
A2 0.38 – 0.015 –
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
CP 0.10 0.004
D 12.32 12.57 0.485 0.495
D1 11.35 11.51 0.447 0.453
D2 4.78 5.66 0.188 0.223
D3 7.62 – – 0.300 – –
E 14.86 15.11 0.585 0.595
E1 13.89 14.05 0.547 0.553
E2 6.05 6.93 0.238 0.273
E310.16– –0.400– –
e 1.27 – – 0.050 – –
F 0.00 0.13 0.000 0.005
R 0.89 – – 0.035 – –
N32 32
33/41
M50FW040
Figure 17. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline
Note: Drawing is not to scale.
Table 25. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 0.950 1.050 0.0374 0.0413
α0° 5° 0° 5°
B 0.170 0.270 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.100 0.0039
D 13.800 14.200 0.5433 0.5591
D1 12.300 12.500 0.4843 0.4921
e 0.500 – – 0.0197 – –
E 7.900 8.100 0.3110 0.3189
L 0.500 0.700 0.0197 0.0276
N32 32
TSOP-a
D1
E
1N
CP
B
e
A2
A
N/2
D
DIE
C
LA1
α
M50FW040
34/41
Figure 18. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Outline
Note: Drawing is not to scale.
Table 26. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 0.950 1.050 0.0374 0.0413
B 0.170 0.270 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.100 0.0039
D 19.800 20.200 0.7795 0.7953
D1 18.300 18.500 0.7205 0.7283
e 0.500 – – 0.0197 – –
E 9.900 10.100 0.3898 0.3976
L 0.500 0.700 0.0197 0.0276
α0° 5° 0° 5°
N40 40
TSOP-a
D1
E
1N
CP
B
e
A2
A
N/2
D
DIE
C
LA1
α
35/41
M50FW040
PART NUMBERING
Table 27. Ordering Information Scheme
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Example: M50FW040 K1TG
Device Type
M50
Architecture
F = Firmware Hub Interface
Operatin g Voltage
W = 3V to 3.6V
Device Function
040 = 4 Mbit (x8), Uniform Block
Package
K = PLCC32
NB = TSOP32 (8 x 14mm)
N = TSOP40: 10 x 20 mm
Device Grade
5 = Temperature range –20 to 85 °C.
Device tested with standard test flow
1 = Temperature range 0 to 70 °C.
Device tested with standard test flow
Option
blank = Standard Pa ck ing
T = Tape & Reel Packing
Plating Technology
blank = Standard Sn Pb plati ng
G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free
M50FW040
36/41
FLOWCHARTS AND PSEUDO CODES
Figure 19. Program Flowchart and Pseudo Code
Note: 1. A Status check of b1 (Protected Block), b3 (VPP invalid) and b4 (Program Error) can be made after each Program operation by
following the correct command sequence.
2. If an error is found, the Stat us Register must be cleared before furt her Program/Erase Control l er operations.
Write 40h or 10h
AI03407
Start
Write Address
& Data
Read Status
Register
YES
NO
b7 = 1
YES
NO
b3 = 0
NO
b4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
Program command:
– write 40h or 10h
– write Address & Data
(memory enters read status state after
the Program command)
do:
–read Status Register if Program/Erase
Suspend command given execute
suspend program loop
while b7 = 1
If b3 = 1, VPP invalid error:
– error handler
If b4 = 1, Program error:
– error handler
YES
End
YES
NO
b1 = 0 Program to Protected
Block Error (1, 2) If b1 = 1, Program to protected block error:
– error handler
Suspend
Suspend
Loop
NO
YES
FWH
Interface
Only
37/41
M50FW040
Figure 20. Program Susp end & Resume Flowchart and Pseudo Code
Write 70h
AI03408
Read Status
Register
YES
NO
b7 = 1
YES
NO
b2 = 1
Program Continues
Write a read
Command
Program/Erase Suspend command:
– write B0h
– write 70h
do:
– read Status Register
while b7 = 1
If b2 = 0 Program completed
Write D0h Program/Erase Resume command:
– write D0h to resume the program
– if the Program operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
Read data from
another address
Start
Write B0h
Program Complete
Write FFh
Read Data
M50FW040
38/41
Figure 21. Era se Flowchart and Pseudo Code
Note: 1. If an error is foun d, the Status Register must be cleared before further Program/E rase Controller operations.
Write 20h
AI03409
Start
Write Block Address
& D0h
Read Status
Register
YES
NO
b7 = 1
YES
NO
b3 = 0
NO
b4, b5 = 0
VPP Invalid
Error (1)
Command
Sequence Error (1)
Erase command:
– write 20h
– write Block Address & D0h
(memory enters read Status Register after
the Erase command)
do:
– read Status Register
– if Program/Erase Suspend command
given execute suspend erase loop
while b7 = 1
If b3 = 1, VPP invalid error:
– error handler
If b4, b5 = 1, Command sequence error:
– error handler
YES
NO
b5 = 0 Erase Error (1)
YES
NO
Suspend
Suspend
Loop
If b5 = 1, Erase error:
– error handler
End
YES
NO
b1 = 0 Erase to Protected
Block Error (1) If b1 = 1, Erase to protected block error:
– error handler
YES
FWH
Interface
Only
39/41
M50FW040
Figure 22. Erase Suspend & Resume Flowchart and Pseudo Code
Write 70h
AI03410
Read Status
Register
YES
NO
b7 = 1
YES
NO
b6 = 1
Erase Continues
Program/Erase Suspend command:
– write B0h
– write 70h
do:
– read Status Register
while b7 = 1
If b6 = 0, Erase completed
Write D0h
Read data from
another block
or
Program
Start
Write B0h
Erase Complete
Write FFh
Read Data
Program/Erase Resume command:
– write D0h to resume erase
– if the Erase operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
M50FW040
40/41
REVISION HISTORY
Table 28. Document Revision History
Date Version Revision Details
Septem b er 20 00 -01 First Issue
04-Oct-2000 -02 DC Characteristics: ICC4 changed
11-Apr-01 -03 Document type: from Preliminary Data to Data Sheet
Program and Erase functions clarification
Read Electronic Signature table change
FWH Register Configuration Map table change
Input Register Definition table, note clarification
DC Characteristics parameters clarification and new VIH and VIL parameters added
FWH Interface AC Signal Timing Characteristics change
A/A Mux Interface Read AC Characteristics change
A/A Mux Interface Write AC Characteristics change
A/A Mux Interface Write AC Waveforms change
06-Jul-2001 -04 Note 2 changed (Table 13., Absolute Maxim u m Ra ting s)
12-Mar-2002 -05 RFU pins must be left disconnected
Specification of PLCC32 package mechanical data revised
09-Jul-2004 6.0
Revision numbering modified.
Document imported in new template (and so reformatted).
Temperature Range ordering information replaced by Device Grad e, Standard
packing option added and Plating Technology added to Table 27., Ordering
Information Scheme. TLEAD parameter added to Table 13., Absolute Maximum
Ratings and TBIAS parameter removed.
12-Jul-2004 7.0 Inches values corrected in Table 27., Ordering Information Scheme.
10-Nov-2004 8.0 TSOP32 package added. Figure 3., Logic Diagram (A/A Mux Interface) and Table
2., Signal Names (A/A Mux Interface) added.
41/41
M50FW040
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