AM29F032B-150EC - AMD - Product.Network

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data

Sheet may be rev is ed by subsequent versi ons or modificat ions due to changes in technical specif ic ations. Publicati on# 21610 Rev: DAmendment/+1

Issue Date: Dec em b er 5, 2000

Am29F032B

32 Megabit (4 M x 8-Bit)

CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■5.0 V ± 10%, single power suppl y operation

— Minimizes system level power requirements

■Manufactured on 0.32 µm process technology

■High performan c e

— Access times as fast as 70 ns

■Low power consumptio n

— 30 mA typical active read current

— 30 mA typical program/erase current

— <1 µA typical standby current (standard access

time to active mode)

■Flexible sector ar chitectur e

— 64 uniform sectors of 64 Kbytes each

— Any combination of sectors can be erased.

— Supports full chip erase

— Group sector protection:

— A hardware method of locking sector gr oups to

prevent any program or erase operations within

that sector group

— Temporary Sector Group Unprotect all ows code

changes in prev iously locked sectors

■Embe dde d Algorithms

— Embedded Erase algorithm automatically

preprogr ams and erases the entire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies bytes at specified addresses

■Minimum 1,000,000 write /erase cycles

guaranteed

■20-year data retention at 125°C

— Reliable operation for the life of the system

■Package option s

— 40-pin TSOP

— 44-pin SO

■Compatible wi th JEDEC standards

— Pinout and software compatible with

single-power-supply Flash standard

— Superior inadvertent write protection

■Data# Polling and toggle bits

— Provides a software method of detecting program

or erase cycle completi on

■Ready/Busy output (RY/BY#)

— Provides a hardware method for detecting

program or erase cycle completion

■Erase Suspend/Resume

— Suspends a sector erase operation to read data

from, or progr am data to, a non-er asing sector,

then resumes the erase operation

■Hardware reset pin (RESET#)

— Resets inter nal state machine to the read mode

2 Am29F032B

GENERAL DESCRIPTION

The Am29F032B is a 32 Mbit, 5.0 volt-only Flash

memor y or ganized as 4,19 4,304 bytes of 8 bits each.

The 4 Mbytes of data are divided into 64 sectors of 64

Kbytes ea ch for flex ible erase capa bility. The 8 bits of

data appear on DQ0–DQ7. The Am29F032B is off ered

in 40-pin TSOP and 44-pin SO packages. The

Am29F032B is manufactured using AMD’s 0.32 µm

process technology. This device is designed to be pro-

grammed in-system with the standar d system 5.0 volt

VCC supply. A 12.0 volt VPP is not required for program

or erase operations. The device can also be pro-

gr ammed in standard EPROM programmers.

The standard device offers access times of 70, 90,

120, and 150 ns, allo wing high-speed micr oprocessors

to operate wi thout wait states. To eliminate bus con-

tention, the device has separate chip enable (CE#),

write enable (WE#), and output enable (OE#) controls.

The device is entirely command set compatible with

the JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using stan-

dard microprocessor write timings. Register contents

ser ve as input to an internal state machine that con-

trols the er ase and progr amming circ uitry. Write cycles

also internally latch addresses and data needed for

the programming and erase operations. Reading data

out of the device is similar to reading from 12.0 volt

Flash or EPROM devices.

The device is programmed by executing the program

command sequence. This invokes the Embedded Pro-

gram algorithm—an inter nal algorithm that automati-

cally times the program pulse widths and verifies

proper ce ll margin. T he device is e rased by executing

the erase command sequence. This invokes the Em-

bedded Erase algorithm—an internal algorithm that

automatically preprograms the array (if it is not already

programmed) before executing the erase operation.

During erase, the device aut omatically times the er ase

pulse widths and verifies proper cell margin.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. A sector is typically

erased and verified within one second. The device is

erased when shipped from the factory.

The hardware sector group protection feature disables

both progr am and erase operat ions in any combi nation

of the eight sector groups of memory. A sector group

consists of four adjacent sectors.

The Erase Suspend feature enables the system to put

erase on hold for any period of time to read data from,

or program data to, a sector that is not being erased.

True bac kground erase can thus be achie ved.

The device re quires only a s ingle 5. 0 v olt p o wer supply

for both read and write functions. Inter nally generated

and regula ted voltages are provided for the program

and erase operations. A low VCC detector automati-

cally inhibits write operations during power transitions.

The host system can detect whether a program or

erase cycle is complete by using the RY/BY# p in, the

DQ7 (Dat a# Pollin g) or DQ6 (tog gle) status bits. After

a program or erase cycle has been completed, the de-

vice automatically returns to the read mode.

A hardware RESET# pin ter minates any operation in

progress. The internal state machine is reset to the

read mode. The RESET# pin may be tied to the sys-

tem reset circuitry. Therefore, if a system reset occurs

during either an Embedded Program or Embedded

Erase algorithm, the de vice i s a ut oma ti ca ll y r es et to t he

read mode. This enables the system’s microprocessor

to read the boot-up firmw are from the Flash memory.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability, and cost

effectiveness. The device electrically erases all bits

within a sector simultaneously via Fowler-Nordheim

tunneling. The bytes are programmed one byte at

a time using the programming mechanism of hot

electron injection.

Am29F032B 3
TABLE OF CONTENTS
Product Selecto r Guide. . . . . . . . . . . . . . . . . . . . .  4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4
Connection Diagram s . . . . . . . . . . . . . . . . . . . . . .  5
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . .  6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6
Ordering Information. . . . . . . . . . . . . . . . . . . . . . .  7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .  8
Table 1. Am29F032B Device Bus Operations .................................. 8
Requirements for  Reading Array Data .......... ..... ....... ..... ....... ... 8
Writing Commands/Command Sequence s ...... .. .. .................... 8
Program and Erase Operation Status ...................................... 9
Standby Mode ..... ..... ...................................... ................... ....... 9
RESET#: Hardware Reset Pin ................................................. 9
Output Disable Mode................................................................ 9
Table 2. Am29F032B Sector Address Table............. ....... .. ....... .. ....  10
Autoselect Mode..................................................................... 11
Table 3. Am29F032B Autoselect Codes......................................... 11
Sector Group Protection/Unprotection......... ............ ............ ... 12
Table 4. Sector Group Addresses................................................... 12
Temporary Sector Group Unprotect ....................................... 12
Figure 1. Tem porary Sector Group Unprotect Operation................ 12
Hardware Data Protection...................................................... 13
Low VCC Write Inhibit..................................................................... 13
Write Pulse “Glitch” Protection........................................................ 13
Logical Inhibit........... ....... ....... .... ..... ....... ....... ......... .... ... ......... ....... .. 13
Power-Up Write Inhibit.................................................................... 13
Command Definitions . . . . . . . . . . . . . . . . . . . . .  13
Reading Array Data........ ...... .. ......... ............................. ......... . 13
Reset Command..................................................................... 13
Autoselect Command Sequence................. ............ ............ ... 14
Byte Program Command Sequence... ....... ............ ....... .......... 14
Chip Erase Command Sequence........................................... 14
Figure 2. Program Operation .......................................................... 15
Sector Erase Command Sequence........................................ 15
Erase Suspend/Erase Resume Commands..... .. .................... 15
Figure 3. Erase Operation............................................................... 16
Command Definitions............................................................. 17
Table 5. Am29F032B Command Definitions................................... 17
Write Operation Status . . . . . . . . . . . . . . . . . . . .  18
DQ7: Data# Polling................................................................. 18
Figure 4. Data# Polling Algorithm ................................................... 18
RY/BY#: Ready/Busy# ........................................................... 19
DQ6: Toggle Bit I................................. ................................... 19
DQ2: Toggle Bit II................................ ................................... 19
Reading Toggle Bits DQ6/DQ2 .............................................. 19
DQ5: Exceeded Timing Lim its......................... ....................... 20
DQ3: Sector Erase Timer ....................................................... 20
Figure 5. Toggle Bit Algorithm........................................................  20
Table 6. Write Operation Status.....................................................  21
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 22
Figure 6. Maximum Negative Overshoot Waveform................. .. ...  22
Figure  7. Maximum Positive Overshoot Waveform........................  22
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 22
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
TTL/NMOS Compatible .......................................................... 23
CMOS Compatible.................................................................. 23
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure  8.  Test Setup......................................................................  24
Table 7. Test Specifications...........................................................  24
Key To Switching Waveforms . . . . . . . . . . . . . . . 24
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Read-only Operations............................................................. 25
Figure  9. Read Operation Timings.................................................  25
Hardware Reset (RESET#) ............................................. .... ... 26
Figure  10. RESET# Timings ..........................................................  26
Write (Erase/Program) Operations......................................... 27
Figure  11. Program Operation Timings..........................................  28
Figure  12. Chip/Sector Erase Operation Timings ..........................  29
Figure 13. Data# Polling Timings (During Embedded Algorithms).  30
Figure 14. Toggle Bit Timings (During Embedded Algorithms)......  30
Figure  15. DQ2 vs. DQ6.................................................................  31
Temporary Sector Unprotect .................................................. 31
Figure 16. Temporary Sector Group Unprotect Timings................  31
Write (Erase/ P r ogr am) Operations—Alternate CE# 
Controlled Writes.................................................................... 32
Figure 17. Alternate CE# Controlled Write Operation Tim ing s ......  33
Erase And Programming Performance . . . . . . . 34
Latchup Characteristic  . . . . . . . . . . . . . . . . . . . . 34
TSOP And SO Pin Capacitance   . . . . . . . . . . . . . 34
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 35
SO 044–44-Pin Small Outline Package....... ........................... 35
TS 040–40-Pin Standard Thin Small Outline Package........... 36
TSR040–40- Pin Reversed Thin Small Outline Package ........ 37
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 38
Revision A (June 1998) .......................................................... 38
Revision B (July 1998)............................................................ 38
Revision C (January 1999).............. ....... ........................... ..... 38
Revision C+1  (April 14, 1999).................................. ............ ... 38
Revision D (November 17, 1999) ........................................... 38
Revision D+1 (December 5, 2000) ........... .............................. 38

4 Am29F032B

PRODUCT SELECTOR GUIDE

Note: S ee “AC Characterist ics ” for full specifications.

BLOCK DIAGRAM

Family Part Number Am29F032B

Speed Options VCC = 5.0 V ± 5% -75

VCC = 5.0 V ± 10% -90 -120 -150

Max access time, ns (tACC) 70 90 120 150

Max CE# access time, ns (tCE) 70 90 120 150

Max OE# access time, ns (tOE) 40405075

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

VCC

VSS

WE#

CE#

OE#

STB

DQ0

–

DQ7

Sector Switches

RY/BY#

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A21

Am29F032B 5

CONNECTION DIAGRAMS

A19

A18

A17

A16

A15

A14

A13

A12

CE#

VCC

RESET#

A11

A10

A20

A21

WE#

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

VCC

VSS

DQ3

DQ2

DQ1

DQ0

40-Pin Standard TSOP

A19

A18

A17

A16

A15

A14

A13

A12

CE#

VCC

RESET#

A11

A10

A20

A21

WE#

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

VCC

VSS

DQ3

DQ2

DQ1

DQ0

40-Pin Reverse TSOP

RESET#

A11

A10

DQ0

DQ1

DQ2

DQ3

VSS

VCC

CE#

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

WE#

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

VCC

6 Am29F032B

PIN CONFIGURATION

A0–A21 = 22 Addresses

DQ0–DQ7 = 8 Data Inputs /Outputs

CE# = Chip Enable

WE# = Write Enable

OE# = Output Enable

RESET# = Hardware Reset Pin, Active Low

RY/BY# = Ready/Busy Output

VCC = +5.0 V single power supply

(see Product Selector Guide for

device speed ratings and voltage

supply tolerances)

VSS = Device Ground

NC = Pin Not Connected Internally

LOGIC SYMBOL

DQ0–DQ7

A0–A21

CE#

OE#

WE#

RESET# RY/BY#

Am29F032B 7

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Valid Combinations

Valid Combinations list configurations planned to be support-

ed in volum e for thi s dev ice. Cons ult the loc al AM D sale s of-

fice to con firm availability o f specific valid com binations and

to check on newly released combinations.

Am29F032B -75 E I

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 40-Pin Thin S mall Outline Package (TSOP) Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR040)

S = 44-Pin Small Outline Package (SO 044)

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am29F032B

32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory

5.0 V Read, Program, and E rase

Valid Combinations

AM29F032 B- 75 EC, EI, FC, FI, SC, SI

AM29F032B-90 EC, EI, EE, FC, FI, FE,

SC, SI, SE

AM29F032B-120

AM29F032B-150

8 Am29F032B

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memory loca-

tion. The regi st er is composed of latches that store the

commands, along with the address and data infor ma-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function of

the device. The appropriate device bus operations

table lists the inputs and control le vels required, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29F032B Device Bus Operations

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0

0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In

Note: See the sections Sector Group Protection and Temporary Sector Unprotect for more information.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at VIH.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. T his

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that asser t valid

addresses on the device address inputs produce valid

data on the device data outputs. The device remains

enabled for read access until the command register

contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specific a-

tions and to the Read Operations Timings diagram for

the timing waveform s. ICC1 in the DC Characteristics

table represents the active current specification for

reading array data.

Writing Commands/Command Sequences

To wr ite a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memor y), the system must drive WE# and

CE# to VIL, and OE# to VIH.

An erase oper at ion can er ase one sect or, multiple s ec-

tors, or the entire device. The Sector Address Tables

indicate the address space that each sector occupies.

A “sector address” consists of the address bits re-

quired to uniquely select a sector. See the “Wr iting

specific addres s and data commands or sequences

into the command register initiates device operations.

The C ommand D efinitions table de fines the va lid reg-

ister command sequences. Writing incorrect address

and data values or writing them in the improper se-

quence resets the device to reading array data.” sec-

tion for details on erasin g a sector or the entire chip, or

suspending/resuming the erase operation.

After the system wri tes the autosele ct command s e-

quence, the device enter s the autoselect m ode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the “Autoselect Mode” and “Au-

toselect Command Sequence” s ections for more infor-

mation.

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Operation CE# OE# WE# RESET# A0–A21 DQ0–DQ7

Read L L H H AIN DOUT

Write L H L H AIN DIN

CMOS Sta ndby VCC ± 0.5 V X X VCC ± 0.5 V X High-Z

TTL Standby H X X H X High-Z

Output Disable L H H H X High-Z

Hardware Reset X X X L X High-Z

Temporary Sector Unprotect

(See Note) XXX V

ID AIN DIN

Am29F032B 9

Characteristics” se ction contains timing specification

tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or prog ram oper ation, th e system ma y

check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle ti mings and ICC

read specificat ions apply. Refe r to “The Er as e Resume

command is valid only during the Erase Suspend

mode.” for more information, and to each AC Charac-

teristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to t he device ,

it can place the device in the standby mode. In this

mode, current co nsumption is g reat ly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The de vice enters the CMOS standby mode when CE#

and RESET# pins are both held at VCC ± 0.5 V. (Note

that this is a more restricted voltage range than VIH.)

The device enters the TTL standby mode when CE#

and RESET# pins are both held at VIH. The device re-

quires standard access time (tCE) f or read access when

the de vice is in either of these standb y modes, bef ore it

is ready to read data.

The device also enters the standby mode when the RE-

SET# pin is dr iven low. Refer to the next section, “RE-

SET#: Hardware Reset Pin”.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

In the DC Characteristics tables, ICC3 represents the

standby current specification.

RESET#: Hardware Reset Pin

The RESET# pin pro vides a har dware method of reset-

ting the device to reading arr ay data. When the sy stem

drives the RESET# pin low for at least a period of tRP

the device immediately terminates any operation in

progress, tristates all data output pins, and ignores all

read/write attempts for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the de vice is ready

to accept another command sequence, to ensure data

integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VIL, the device enters

the TTL standby mode; if RESET# is held at VSS ±

0.5 V, the dev i ce ent ers the CMOS standby mode.

The RESET# pin may be tied to the system reset cir-

cuitry. A sy stem reset would thus also reset the Flash

memory, enabling the system to read the boot-up f i rm-

ware from the Flash memory.

If RESET# is ass erted during a progr am or er ase oper-

ation, the RY/BY# pin remains a “0” (busy) until the in-

ternal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The sys-

tem can thus monitor R Y/BY# to determine whether the

reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of tREADY (not during Embedded Algo-

rithms). The system can read data tRH after the RE-

SET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# pa-

rameters and timing diagram.

Output Disable Mode

When the OE# input is at VIH, output fr om the device is

disabled. The output pins are plac ed in the h igh imped-

ance state.

10 Am29F032B

Table 2. Am29F032B Sector Address Table

Sector A21 A20 A19 A18 A17 A16 Sector Size Address Range

SA0 0 0 0 0 0 0 64K 000000h–00FFFFh

SA1 0 0 0 0 0 1 64K 010000h–01FFFFh

SA2 0 0 0 0 1 0 64K 020000h–02FFFFh

SA3 0 0 0 0 1 1 64K 030000h–03FFFFh

SA4 0 0 0 1 0 0 64K 040000h–04FFFFh

SA5 0 0 0 1 0 1 64K 050000h–05FFFFh

SA6 0 0 0 1 1 0 64K 060000h–06FFFFh

SA7 0 0 0 1 1 1 64K 070000h–07FFFFh

SA8 0 0 1 0 0 0 64K 080000h–08FFFFh

SA9 0 0 1 0 0 1 64K 090000h–09FFFFh

SA10 0 0 1 0 1 0 64K 0A0000h–0AFFFFh

SA11 0 0 1 0 1 1 64K 0B0000h–0BFFFFh

SA12 0 0 1 1 0 0 64K 0C0000h–0CFFFFh

SA13 0 0 1 1 0 1 64K 0D0000h–0DFFFFh

SA14 0 0 1 1 1 0 64K 0E0000h–0EFFFFh

SA15 0 0 1 1 1 1 64K 0F0000h–0FFFFFh

SA16 0 1 0 0 0 0 64K 100000h–10FFFFh

SA17 0 1 0 0 0 1 64K 110000h–11FFFFh

SA18 0 1 0 0 1 0 64K 120000h–12FFFFh

SA19 0 1 0 0 1 1 64K 130000h–13FFFFh

SA20 0 1 0 1 0 0 64K 140000h–14FFFFh

SA21 0 1 0 1 0 1 64K 150000h–15FFFFh

SA22 0 1 0 1 1 0 64K 160000h–16FFFFh

SA23 0 1 0 1 1 1 64K 170000h–17FFFFh

SA24 0 1 1 0 0 0 64K 180000h–18FFFFh

SA25 0 1 1 0 0 1 64K 190000h–19FFFFh

SA26 0 1 1 0 1 0 64K 1A0000h–1AFFFFh

SA27 0 1 1 0 1 1 64K 1B0000h–1BFFFFh

SA28 0 1 1 1 0 0 64K 1C0000h–1CFFFFh

SA29 0 1 1 1 0 1 64K 1D0000h–1DFFFFh

SA30 0 1 1 1 1 0 64K 1E0000h–1EFFFFh

SA31 0 1 1 1 1 1 64K 1F0000h–1FFFFFh

SA32 1 0 0 0 0 0 64K 200000h–20FFFFh

SA33 1 0 0 0 0 1 64K 210000h–21FFFFh

SA34 1 0 0 0 1 0 64K 220000h–22FFFFh

SA35 1 0 0 0 1 1 64K 230000h–23FFFFh

SA36 1 0 0 1 0 0 64K 240000h–24FFFFh

SA37 1 0 0 1 0 1 64K 250000h–25FFFFh

SA38 1 0 0 1 1 0 64K 260000h–26FFFFh

SA39 1 0 0 1 1 1 64K 270000h–27FFFFh

SA40 1 0 1 0 0 0 64K 280000h–28FFFFh

SA41 1 0 1 0 0 1 64K 290000h–29FFFFh

SA42 1 0 1 0 1 0 64K 2A0000h–2AFFFFh

SA43 1 0 1 0 1 1 64K 2B0000h–2BFFFFh

Am29F032B 11

Note: All sectors are 64 Kbytes in size.

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector g roup prot ection v erifica-

tion, through identifier codes output on DQ7–DQ0.

This mode is primarily intended for programming

equipment to automatically match a device to be pro-

grammed with its corresponding programming algo-

rithm. However, the autoselect codes can also be

accessed in-system through the command register.

When using programming equipmen t, the autoselect

mode requires VID (11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Table 3. In addition, when verifying sector group pro-

tectio n, the se ctor group a ddress must app ear on th e

appropriate highest order address bits (see Table 4).

Table 3 also shows the remaining address bits that are

don’t care. When all necessary bits have been set as

required, the programming equipment may then read

the corresponding identif ier code on DQ7-DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

com mand re gister, as shown in Table 5. This method

does not require VID on an address line. Refer to the

Autoselect Command Sequence s ection for more in-

formation.

Table 3. Am29F032B Autoselect Codes

Note: Identifier codes for manufacturer and device IDs exhibit odd parity with DQ7 defined as the parity bit.

SA44 1 0 1 1 0 0 64K 2C0000h–2CFFFFh

SA45 1 0 1 1 0 1 64K 2D0000h–2DFFFFh

SA46 1 0 1 1 1 0 64K 2E0000h–2EFFFFh

SA47 1 0 1 1 1 1 64K 2F0000h–2FFFFFh

SA48 1 1 0 0 0 0 64K 300000h–30FFFFh

SA49 1 1 0 0 0 1 64K 310000h–31FFFFh

SA50 1 1 0 0 1 0 64K 320000h–32FFFFh

SA51 1 1 0 0 1 1 64K 330000h–33FFFFh

SA52 1 1 0 1 0 0 64K 340000h–34FFFFh

SA53 1 1 0 1 0 1 64K 350000h–35FFFFh

SA54 1 1 0 1 1 0 64K 360000h–36FFFFh

SA55 1 1 0 1 1 1 64K 370000h–37FFFFh

SA56 1 1 1 0 0 0 64K 380000h–38FFFFh

SA57 1 1 1 0 0 1 64K 390000h–39FFFFh

SA58 1 1 1 0 1 0 64K 3A0000h–3AFFFFh

SA59 1 1 1 0 1 1 64K 3B0000h–3BFFFFh

SA60 1 1 1 1 0 0 64K 3C0000h–3CFFFFh

SA61 1 1 1 1 0 1 64K 3D0000h–3DFFFFh

SA62 1 1 1 1 1 0 64K 3E0000h–3EFFFFh

SA63 1 1 1 1 1 1 64K 3F0000h–3FFFFFh

Table 2. Am29F032B Sector Address Table (Continued)

Sector A21 A20 A19 A18 A17 A16 Sector Size Address Range

Description A21-A18 A17-A10 A9 A8-A7 A6 A5-A2 A1 A0 Ide ntif ier Co de on

DQ7-DQ0

Manufacturer ID: AMD X X VID XV

IL XV

IL VIL 01h

Device ID: Am29F032B X X VID XV

IL XV

IL VIH 41h

Sector Group Protec tion

Verification

Sector

Group

Address XV

ID XV

IL XV

IH VIL

01h (protec ted )

00h (unprotected)

12 Am29F032B

Sector Group Protection/Unprotection

The hardware sector group protection feature disables

both program and erase operations in any sector

group. Each sector group consists of four adjacent

sectors. Table 4 shows how the sectors are grouped,

and the address range that each sector group con-

tain s. The hardware sector group unprotection feature

re-enables both program and erase operations in pre-

viously protected sector groups.

Sector gr oup pr otection/unprotec tion must be imple-

mented using programming equipment. Th e proce-

dure requires a high voltage (VID) on address p in A9

and the control pi ns. D etails on this method are pr o-

vided in a supplement, publication number 22184.

Contact an AMD representat ive to obtain a copy of the

appropriate document.

The device is shipped with all sector grou ps unpro-

tected. AMD offers the optio n of prog r amming and pro-

tectin g sector groups at its factory prior to shipp ing the

dev ice through AMD’s ExpressFlash™ Service. Con-

tact an AMD representative for details.

It is possible to determ ine whether a sector gr oup is

protected or unpr otected. See “Autoselect Mode” for

details.

Table 4. Sector Group Addresses

Temporary Sector Group Unprotect

This feature allows temporary unprotection of previ-

ously protected sector groups to change data in-sys-

tem. The Sector Group Unprot ect mode is act iv at ed b y

setting the RE SET# pin to VID (11.5 V – 12.5 V). Dur-

ing this mode , formerly protected se ctor g roups can be

programmed or erased by selecting the sector group

addresses. Once VID is removed from the RESET#

pin, all the previously protected sector groups are

protected again. Figure 1 shows the algorithm, and

Figure 16 shows the timing diagrams, for this feature.

Figure 1. Tempo rar y Se ctor Group Unprotect

Operation

Sector

Group A21 A20 A19 A18 Sectors

SGA00000SA0

–

SA3

SGA10001SA4

–

SA7

SGA2 0 0 1 0 SA8

–

SA11

SGA3 0 0 1 1 SA12

–

SA15

SGA4 0 1 0 0 SA16

–

SA19

SGA5 0 1 0 1 SA20

–

SA23

SGA6 0 1 1 0 SA24

–

SA27

SGA7 0 1 1 1 SA28

–

SA31

SGA81000SA32–SA35

SGA9 1 0 0 1 SA36–SA39

SGA10 1 0 1 0 SA40–SA43

SGA11 1 0 1 1 SA44–SA47

SGA12 1 1 0 0 SA48–SA51

SGA13 1 1 0 1 SA52–SA55

SGA14 1 1 1 0 SA56–SA59

SGA15 1 1 1 1 SA60–SA63

START

Perform Erase or

Program Operations

RESET# = VIH

Tempor ary Se ctor Group

Unprotect Completed

(Note 2)

RESET# = VID

(Note 1)

Notes:

1. All protected sector groups unprotected.

2. All previously protected sector groups are protected

once again.

Am29F032B 13

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection.

In addition, the following hardware data protection

measures prevent accidental erasure or programming,

which m ight otherwi se be caused by spur ious sys tem

level signals during VCC power-up and power-down

transitions, or from system noise.

Low V CC Write Inhibit

When VCC is less than VLKO (see D C Characteristics

for voltage levels), the device does not accept any

write cycles. This protects data dur ing VCC power-up

and power-down. The command register and all inter-

nal pro gram /erase circuits are disabled. Unde r this

condition the device resets to the read mode. Subse-

quent writes are ignored until the VCC level is greater

than VLKO. The system must ensure that the control

pins are logically correct to prevent unintentional

writes when VCC is above VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical In hibit

Write cycles are inhibited by holding any one of OE# =

VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be at VIL while OE# is at VIH.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH duri ng power up,

the device does not accept commands on the rising

edge of WE #. The inter nal state mac hine is automati-

cally reset to the read mode on power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates de vice op-

erations. The Command Definitions table defines the

valid register com mand sequences. Wr iting incorrect

address an d data values or wr iting them in the im-

proper sequ ence resets the device to reading array

data.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Charac teristics” section.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

After the device accepts an Erase Suspend command,

the device enters the Eras e Suspend m ode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within erase-

suspended sectors, the device outputs status data.

After completing a programming operation in the

Erase Suspend mode, the system may once again

read array data with the same exception. See “Erase

Suspend/Erase Resume Commands” for more infor-

mation on this mode.

The system

must

issue the reset command to re-en-

able the device for reading array data if DQ5 goes

high, or while in the autoselec t mode. See the “Reset

Command” section, next.

See also “Requirements for Reading Array Data” in

the “Dev ice Bus Operations” section for more infor m a-

tion. The Read Operations table provides the read pa-

rameters, and Read Operation Timings diagram

shows the timing diagram.

Reset Command

Writing the reset command to the device resets the

device to reading array data. Address bits are don’t

care for this command.

The reset comma nd may be w ritten between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

The reset comma nd may be w ritten between the se-

quence cycles in a program command sequence be-

fore programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the dev ice ignores reset commands until the

operation is complete.

The reset comma nd may be w ritten between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must

be wr itten to retur n to read ing array data (also

applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command retur ns the device to read-

ing array data (also applies during Erase Suspend).

14 Am29F032B

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the man uf acture r and devices codes ,

and determine whether or not a sector is protected.

The Command Definitions table shows the address

and data requirements . This method is an alternativ e to

that shown in the Autoselect Codes (High Voltage

Method) table, which is intended for PROM program-

mers and requires VID on address bit A9.

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence.

A read cycle at address XX00h retrie v es the manuf ac-

turer code. A read cycle at address XX01h returns the

device code. A read cycle containing a sector address

(SA) and the address 02h in returns 01h if that sector

is protected, or 00h if it is unprotected. Refer to the

Sector Ad dre ss tables for valid sector address es.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two un-

lock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is

not

required to provide further

controls or timings. The device automatically provides

internally generated progr am pulses and v erify the pro-

grammed cell margin. The Command Definitions take

shows the address and data requirements for the byte

program command sequence.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using DQ7,

DQ6, or RY/BY#. See “Write Operation Status” for in-

formation on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The program command sequence

should be reinit iated once t he de vice has reset to read-

ing array data, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1 ”. Attempting to do so may

halt the operation and set DQ5 to “1”, or cause the

Data# Polling algorithm to indicate the operation wa s

successful. However, a succeeding read will show that

the data is still “0”. Only erase operations can co nvert

a “0” to a “1”.

Chip Erase Command Sequence

Chip erase i s a six -bus-cycle operat ion. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does

not

require the system to

preprogr am prior to erase. The Embedded Erase algo-

rithm automatically preprogr ams and verifies the entire

memor y for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. The Command

Definitions table shows the address and data require-

ments for the chip erase command sequence.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored. Not e that a hardware

reset during the chip erase operation immediately ter-

minates the operation. The Chip Erase command se-

quence should be reinitiated once the device has

returned to reading array data, to ensure data int eg rity.

The system can determine the status of the erase

operation b y using DQ7, DQ6, DQ2, or R Y/BY#. See

“The Erase Resume command is valid only during

the Erase Suspend mode.” for information on these

status bits. When the Embedded Erase algorithm is

complete, the device returns to reading array data

and address es are no long er latched.

Figure 3 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in “AC

Characteristics” for parameters , and to the Chip/Sec tor

Erase Operation Timings for timing waveforms.

Am29F032B 15

Note: See Table 5 for program command sequence.

Figure 2. Program Operation

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two un-

lock cycles, followed by a set-up command. Two addi-

tional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. The Command Definitions table

shows the address and data requirements for the sec-

tor erase command sequence.

The device does

not

require the system to preprogram

the memory prior to e rase. The Embedded Erase algo-

rithm automatically progr ams and verifies the sector f or

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector er ase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

ma y be done in any sequence , and the nu mber of sec-

tors ma y be from one sector to a ll sectors. The time be-

tween these additional cy cles must be less than 50 µs,

otherwise the last address and command might not be

accepted, and erasure may begin. It is recommended

that processor interrupts be disab led during this time to

ensure all commands are accepted. The inte rrupts can

be re-enabled after the last Sector Erase command is

written. If the time between additional sector erase

commands can be assumed to be less than 50 µs, the

system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the

time-out period resets the device to reading array

data. The system must rewrite the command sequence

and any additional sector addresses and commands.

The system can monitor DQ3 t o determine if the sector

erase timer has timed out. (See the “DQ3: Sector Erase

Timer” section.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, only the

Erase Suspend command is v alid. All othe r commands

are ignored. Note that a hardware reset during the

sector erase operation immediately term inates the op-

eration. The Sector Erase command sequence should

be reinitiated once the device has returned to reading

array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the

dev ice returns to reading arr a y dat a and addr esses are

no longer latched. The system can determine the sta-

tus of the e rase operat ion b y using DQ7, DQ6, DQ2, or

RY/BY#. Refer to “The Erase Resume command is

valid only during the Erase Suspend mode.” for infor-

mation on these status bits.

Figure 3 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “A C Char acteristics ” section for parameters , and to

the Sector Er ase Opera tions Timing diagr am for timing

waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend co mmand allo ws the s yste m to in-

terrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspe nd command during the

Sector Erase time-out immediately terminates the

time-out period an d sus pends t he er ase oper at ion. Ad-

dresses are “don’t-cares” when writing the Erase Sus-

pend command.

When the Erase Suspend command is written during a

sector erase oper ation, the devi ce requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

START

Write Program

Command Sequence

Data Poll

from System

Verify Data? No

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

16 Am29F032B

minates the time-out period and suspends the erase

operation.

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected f or eras ure. (The de vice “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended sec-

tors produces status data on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

See “The Er ase Res ume command is valid only during

the Erase Suspend mode.” for information on these

status bits.

After an erase-suspended program operation is com-

plete, t he system can once again read arr ay data within

non-suspended sectors. The system can determine

the status of the program operation using the DQ7 or

DQ6 status bits, just as in the standard progra m oper-

ation. See “The Erase Resume command is valid only

during the Erase Susp end mode.” f or more inf ormation.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device rever ts to

the Erase Suspend mode, and is ready for another

valid operation. See “ Autoselect Command Seq uence”

for more information.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase oper ation. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the de-

vice has resumed erasing.

Notes:

1. See the appropriate Command Definitions table for erase

command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operation

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

Am29F032B 17

Command Definitions

Table 5. Am29F032B Command Definitions

Legend:

X = Don’t care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

PD = Data to be programmed at location PA. Data latches on

the rising edge of WE# or CE# pulse, whichev er hap pens fir st.

SA = Address of the sector to be verified (in autoselect mode)

or erased. Address bits A21–A16 select a unique sector.

SGA = Address of the sector group to be verified. Address

bits A21–A 18 select a uniq ue sec tor group.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus

cycles are write operations.

4. Address bits A21–A11 are don’t cares for unlock and

command cycles, unless SA or PA required.

5. No unlock or command cycles required when reading

array data.

6. The Reset command is required to return to reading array

data when device is in the autoselect mode, or if DQ5

goes high (while the device is providing status data).

7. The f ourth cycle of the autoselect command sequence is

a read cycle.

8. The data is 00h f or an unprotected sector group and 01h

for a protected sector group.See “Autoselect Command

Sequence” for more information.

9. The system may read and program in non-erasing

sectors, or enter the autoselect mode, when in the Erase

Suspend mode. The Erase Suspend command is valid

only during a sector erase operation.

10. The Erase Resume command is valid only during the

Erase Suspend mode.

Command

Sequence

(Note 1)

Cycles

Bus Cycles (Notes 2–4)

First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (Note 5) 1 RA RD

Reset (Note 6) 1 XXX F0

Autoselect

(Note 7)

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01

Device ID 4 555 AA 2AA 55 555 90 X01 41

Sector Grou p Protect

Verify (Note 8) 4 555 AA 2AA 55 555 90 SGA

X02 XX00

XX01

Program 4 555 AA 2AA 55 555 A0 PA PD

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30

Erase Suspen d (Note 9) 1 XXX B0

Erase Resume (N ote 10) 1 XXX 30

18 Am29F032B

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,

and R Y/BY# . Table 6 and t he f ollowing s ubsections de-

scribe the functions of these bits. DQ7, RY/BY#, and

DQ6 each offer a method for determining whether a

program or erase operation is complete or in progress.

These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in

progress or completed, or whether the device is in

Erase Suspend. Data# P olling is v alid after the rising

edge of the final WE# pulse in the program or erase

command sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. Th is DQ7 status also a pplies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# P olling on DQ7 is activ e for ap-

proximately 2

s, then the device returns to reading

array data.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When t he Embedded Erase al-

gorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous t o the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status in-

formation on DQ7.

After an er ase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling

on DQ7 is activ e for appro ximately 100

s, then the de-

vice returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at

DQ7–DQ0 on the

following

read cycles. This is be-

cause DQ7 may change asynchronously with

DQ0–DQ6 while Output Enable (OE#) is asserted low.

The Data# Polling Timings (During Embedded Algo-

rithms) figure in the “AC Characteristics” section illus-

trates this.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 4 shows the Data# Polling algorithm.

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within

any sector selected for erasure. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 4. Data# P olli ng Algorithm

Am29F032B 19
RY/BY#: Ready/Busy# 
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the outpu t is low (Busy ), the de vice is activ ely er asing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 shows the outputs for RY/BY#. The timing dia-
grams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Er ase algorithm is in prog ress or complete ,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address,   and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles f or app roximately 100 
µ
s, then ret urns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected. 
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the de vice is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 
µ
s after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
The Write Operation Status tab le shows the outp uts for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is , the  Embedded Er ase algo rithm is in progr ess),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence. 
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode info rmation. Ref er t o Tabl e 6 to compare output s
for DQ2 and DQ6. 
Figure 5 shows the toggle bit algorithm in flowchart
form , and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsect i on.
Refer  to the Toggle Bit Timings figure for the toggle bit
timing diagr am. The DQ2 vs. DQ6 figure sho ws the dif-
ferences between DQ2 and DQ6 in graphical form. 
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row  to
determine whether a toggle  bi t is togg ling. Typica lly, a
system w ould note and  store the v alue  of the toggle  bit
after the first read. After the second read, the system
would co mpare the ne w v alue of the  toggle bit  with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The sys-
tem can r ead arra y data on  DQ7–DQ0 on  the f ollowing
read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as  DQ5 went high. If  the toggle bit is  no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
dev ice did not complete the operat ion successfully, and

20 Am29F032B

the system must write the reset command to return to

reading array data.

The remaining scenario is that the system initially de-

termines that the toggle bit is togglin g and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successiv e read cycles , de-

termining the stat us as described in the previous par a-

graph. Alternatively, it may choose to perform other

system tasks. In this case , the system must start at the

beginning of the algorithm when it re turns to determine

the status of the operation (top of Figure 5).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the prog ram or er ase cycle w as

not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is pre viously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the operation has ex-

ceeded the timing limits, DQ5 produces a “1.”

Under both these conditions, the system must issue the

reset command to return the device to reading array

data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system ma y read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tiona l sector s are selected f or erasure, th e entire time-

out also applies after each additional sector erase

command. When the time-out is complete, DQ3

switches from “0” to “1.” The system may ignore DQ3

if the s ystem can gua rant ee that t he ti me betw een ad-

ditional sector erase commands will always be less

than 50 µs . S ee als o the “Se ctor Er ase Command Se-

quence” section.

After the sector erase command sequence is written,

the system should re ad the s tatus on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has ac-

cepted the command sequence , and then read DQ3. If

DQ3 is “1”, the internally controlled erase cycle has be-

gun; all further commands (other th an Er ase Su spend)

are ignored until the erase operation is complete. If

DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the s ystem softw are should chec k the status

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been ac-

cepted. Table 6 shows the outputs for DQ3.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it ma y stop toggling as DQ5

changes to “1”. See text.

Figure 5. Toggle Bit Algorithm

(Notes

1, 2)

(Note 1)

Am29F032B 21

Table 6. Write Operation Status

Notes:

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

Operation DQ7

(Note 1) DQ6 DQ5

(Note 2) DQ3 DQ2

(Note 1) RY/BY#

Standard

Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase

Suspend

Mode

Reading within Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Reading within Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

22 Am29F032B

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

VCC (Note 1). . . . . . . . . . . . . . . . . .–2.0 V to 7.0 V

A9, OE#, RESET# (Note 2). . . . .–2.0 V to 13.0 V

All other pins (Note 1) . . . . . . . . . .–2.0 V to 7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, inputs may overshoot VSS to

–2.0 V for periods of up to 20 ns. See Figure 6. Maximum

DC voltage on output and I/O pins is VCC + 0.5 V. During

voltage transitions, outputs ma y ov ershoot to VCC + 2.0 V

for periods up to 20 ns. See Figure 7.

2. Minimum DC input voltage on A9, OE#, RESET# pins is

–0.5V. During voltage transitions , A9, OE#, RESET# pi ns

may ov ershoot VSS to –2.0 V f or periods of up to 20 ns. See

Figure 6. Maximum DC input voltage on A9, OE#, and

RESET# is 13.0 V whi ch may overshoot to 13.5 V for

periods up to 20 ns.

3. No more than one output shorted at a time. Duration of

the short circuit should not be greater than one second.

Stresses greater than those listed in this section may cause

per manent damag e to the device. This is a stress ratin g o nly;

functional o peration of t he device at these or any oth er condi-

tions a bove those indica ted in the operational sec tions of this

specification is not implied. Exposure of the device to absolute

maximum rating conditions for e xtended periods may aff ect de-

vice reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (TA) . . . . . . . . –55°C to +125°C

VCC Supply Voltages

VCC for ± 5% devices . . . . . . . . . . .+4.75 V to +5.25 V

VCC for ± 10% devices . . . . . . . . . .+4.50 V to +5.50 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

Figure 6. Maximum Negative

Overshoot Waveform

Figure 7. Maximum Positive

Overshoot Waveform

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

Am29F032B 23

DC CHARACTERISTICS

TTL/NMOS Compatible

CMOS Compatible

Notes for DC Characteristics (both tables):

1. The ICC current is typically less than 1 mA/MHz, with OE# at VIH.

2. ICC active while Embedded Program or Embedded Erase algorithm is in progress.

3. Not 100% tested.

Parameter

Symbol Parameter Description Test Description Min Typ Max Unit

ILI Input Load Current VIN = VSS to V CC, VCC = VCC Max ±1.0 µA

ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.0 V 50 µA

ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA

ICC1 VCC Read Current (Note 1) CE# = VIL, OE# = VIH 30 40 mA

ICC2 VCC Write Current (Notes 2, 3) CE# = VIL, OE# = VIH 40 60 mA

ICC3 VCC S tan dby Current

(CE# Controlled) CE# = VIH, RESET# = VIH 0.4 1.0 mA

ICC4 VCC S tan dby Current

(RESET# Controlled) VCC = VCC Max, RESET# = VIL 0.4 1.0 mA

VIL Input Low Level –0.5 0.8 V

VIH Input High Level 2.0 VCC + 0.5 V

VID Voltage for Autoselect and Sector

Protect VCC = 5.0 V 11.5 12.5 V

VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V

VOH Output High Level IOH = –2.5 mA VCC = VCC Min 2.4 V

VLKO L ow VCC Lock-out Vo ltag e 3.2 4.2 V

Parameter

Symbol Parameter Description Test Description Min Typ Max Unit

ILI Input Load Current VIN = VSS to V CC, VCC = VCC Max ±1.0 µA

ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.0 V 50 µA

ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA

ICC1 VCC Read Current (Note 1) CE# = VIL, OE# = VIH 30 40 mA

ICC2 VCC Write Current (Notes 2, 3) CE# = VIL, OE# = VIH 30 40 mA

ICC3 VCC S tan dby Current

(CE# Controlled) CE# = VCC ± 0.5 V,

RESET# = VCC ± 0.5 V 15µA

ICC4 VCC S tan dby Current

(RESET# Controlled) RESET# = VSS ± 0.5 V 1 5 µA

VIL Input Low Level –0.5 0.8 V

VIH Input High Level 0.7x VCC VCC + 0.3 V

VID Voltage for Autoselect

and Sector Protect VCC = 5.0 V 11.5 12.5 V

VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V

VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V

VOH2 IOH = –100 µA, VCC = VCC Min VCC – 0.4 V

VLKO L ow VCC Lock-out Voltage 3.2 4.2 V

24 Am29F032B

TEST CONDITIONS

Table 7. Test Specifications

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

CL6.2 kΩ

5.0 V

Device

Under

Test

Figure 8. Test Setup

Note: Diodes are IN3064 or equivalent

Test Co ndit ion -75 All oth ers Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig cap aci tan ce) 30 100 pF

Input Rise and Fall Times 5 20 ns

Input Pulse Levels 0.0–3.0 0.45–2.4 V

Input timing measurement

reference levels 1.5 0.8 V

Output timing measurement

reference levels 1.5 2.0 V

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changi ng from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

Am29F032B 25

AC CHARACTERISTICS

Read-only Operations

Notes:

1. Not 100% tested.

2. Refer to Figure 8 and Table 7 for test specifications.

Parameter Symbol

Parameter Description Test

Setup

Speed Options

UnitJEDEC Std -75 -90 -120 -150

tAVAV tRC Read Cycle Time (Note 1) Min 70 90 120 150 ns

tAVQV tACC Address to Output Delay CE# = VIL

OE# = VIL Max 70 90 120 150 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 90 120 150 ns

tGLQV tOE Output Enable to Output Delay Max 40 40 50 55 ns

tOEH Output Enable Hold

Time (Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 10 ns

tEHQZ tDF Chip Enable to Output High Z

(Note 1) Max20203035ns

tGHQZ tDF Output Enable to Output High Z

(Note 1) Max20203035ns

tAXQX tOH Output Hold Time From Addresses CE#

or OE# Whichever Occurs First Min 0 ns

tReady RESET# Pin Low to Read Mode

(Note 1) Max 20 µs

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tOE

0 V

RY/BY#

RESET#

tDF

tOH

Figure 9. Read O perati on Timi ng s

26 Am29F032B

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100 % test ed.

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

tREADY RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note) Max 20 µs

tREADY RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH RESET# High Time Before Read (See Note) Min 50 ns

tRB RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

Figure 10. RESET# Timings

Am29F032B 27

AC CHARACTERISTICS

Write (Erase/Program) Operations

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter

Parameter Description

Speed Options

UnitJEDEC Std -75 -90 -120 -150

tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 150 ns

tAVWL tAS Address Set up Tim e Min 0 ns

tWLAX tAH Address Hold Time Min 40 45 50 50 ns

tDVWH tDS Da ta Set up Tim e Min 40 45 50 50 ns

tWHDX tDH Data Hold Time Min 0 ns

tGHWL tGHWL Read Recover Time Before Write

(OE# high to WE# low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 40 45 50 50 ns

tWHWL tWPH Write Pulse Wid th High Min 20 ns

tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 7 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec

Max 8 sec

tVCS VCC Set Up Time (Note 1) Min 50 µs

tBUSY WE# to RY/BY# Valid Min 40 40 50 60 ns

28 Am29F032B

AC CHARACTERISTICS

OE#

WE#

CE#

VCC

Data

Addresses

tDS

tAH

tDH

tWP

tWHWH1

tWC tAS

tWPH

tVCS

555h PA PA

Read Status Data (last two cycles)

A0h

tCS

Status DOUT

Program Command Sequence (last two cycles)

RY/BY#

tRB

tBUSY

tCH

Note: PA = program address, PD = program data, DOUT is the true data at the program address.

Figure 11. Pr ogram Operation Timings

Am29F032B 29

AC CHARACTERISTICS

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

RY/BY#

tRB

tBUSY

Note: SA = Sector Address. VA = Valid Address for reading status data.

Figure 12. Chip/Sector Erase Operation Timings

30 Am29F032B

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

Note:

V A = V alid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 13. Data# Polling Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

tOE

DQ6/DQ2

RY/BY#

tBUSY

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

tACC

tRC

Valid DataValid StatusValid Status

(first read) (second read) (stops toggling)

Valid Status

Note:

V A = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle ,

and array data read cycle.

Figure 14. Toggle Bit Timings (During Embedded Algorithms)

Am29F032B 31

AC CHARACTERISTICS

Temporary Sector Unprotect

Note: Not 100% tested.

Parameter

All Speed OptionsJEDEC Std Description Unit

tVIDR VID Rise and Fall Time (See Note) Min 500 ns

tRSP RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the

erase-suspe nd ed sec tor.

Figure 15. DQ2 vs. DQ6

RESET#

tVIDR

12 V

0 or 5 V

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

0 or 5 V

Figure 16. Temporary Sector Group Unprotect Timings

32 Am29F032B

AC CHARACTERISTICS

Write (Erase/Program) Operations—Alternate CE# Controlled Writes

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter Symbol

Parameter Description

Speed Options

UnitJEDEC Std -75 -90 -120 -150

tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 150 ns

tAVEL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 40 45 50 50 ns

tDVEH tDS Data Setup Time Min 40 45 50 50 ns

tEHDX tDH Address Hold Time Min 0 ns

tGHEL tGHEL Read Recover Time Before Write Min 0 ns

tWLEL tWS CE# Setup Time Min 0 ns

tEHWH tWH CE# Hold Time Min 0 ns

tELEH tCP Wr ite Puls e Wid th Min 40 45 50 50 ns

tEHEL tCPH Write Pulse Width High Min 20 ns

tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 7 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec

Max 8 sec

Am29F032B 33

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.

2. Figure indicates the last two bus cycles of the command sequence.

Figure 17. Alternate CE# Controlled Write Operation Timings

34 Am29F032B

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

C, 5.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case co nditi ons of 90°C, VCC = 4.5 V, 1,000,000 cycles (4.75 V f or -75).

3. The typical chi p prog rammi ng time is c onsider ably less than the maximum chi p prog r amming time list ed, si nce most b yt es

progra m f aster than the maximum b yte prog ram time list ed. If the maximum b yte progr am time giv en is e xceeded, onl y then does

the de vi ce set DQ5 = 1. See t he sect ion on DQ5 for further information.

4. In the pre-pro grammi ng step of t he Embedded Er as e algorithm, all b yt es are prog r ammed to 00h before erasure .

5. System-level overhead is the time r equired to execute the four-bus-cy cle se quence for programmi ng. See Table 5 for further

inf ormation on command d efini tions .

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTIC

Note: Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25

C, f = 1.0 MHz.

DATA RETENTION

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 1 8 se c Excludes 00h programming prior to

erasure (Note 4)

Chip Erase Time 64 sec

Byte Programming Time 7 300 µs Excludes system-level overhead

(Note 5)

Chip Programming Time (Note 3) 28.8 86.4 sec

Description Min Max

Input Voltage with respect to VSS on I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C 10 Years

125°C 20 Years

Am29F032B 35

PH YS ICAL DIMENSIONS

SO 044–44-Pin Small Outline Package

Dwg rev AC; 10/99

36 Am29F032B

PH YS ICAL DIMENSIONS

TS 040–40-Pin Standard Thin Small Outline Package

Dwg rev AA; 10/99

Am29F032B 37

PH YS ICAL DIMENSIONS

TSR040–40-Pin Reversed Thin Small Outline Package

Dwg rev AA; 10/99

38 Am29F032B

REVISION SUMMARY

Revision A (June 1998)

Initial release.

Revision B (July 1998)

Distinctive Characteristics

Changed typical active read current t o 30 mA to match

DC Characteristics tab l e.

Operating Ranges

Corrected temperature range descriptions to “ambi-

ent.”

Revision C (January 1999)

Distinctive Characteristics

Added 20-year dat a retent ion subbullet.

Revision C+1 (April 14, 1999)

Deleted duplicate sections in the full data sheet.

Data Retention

Added table.

Revision D (November 17, 1999)

AC Characteristics—Figure 11. Program

Operations Timing and Figure 12. Chip/Sector

Erase Operations

Deleted tGHWL and changed OE# waveform to start at

high.

Physi cal Dimensions

Replaced figures with more detailed illustrations.

Revision D+1 (December 5, 2000)

Added tabl e of contents .

Ordering Info rmation

Deleted burn-in option.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification pur poses only and may be trademarks of their respective companies.