DESCRIPTION
The APS13290 and APS13291 are three-wire, planar Hall-effect
sensor integrated circuits (ICs) especially suited for operation
over extended temperature ranges (up to 125°C).
This family of precision Hall-effect latch ICs are ideal for
industrial and consumer applications and feature performance
enhancements permitting high-temperature operation up to
175°C junction temperatures. In addition, the APS13290/1
include a number of features designed specifically to maximize
system robustness, such as reverse-polarity protection, output
current limiter, overvoltage, and EMC protection.
The single silicon chip includes: a voltage regulator, a Hall
plate, small signal amplifier, chopper stabilization, Schmitt
trigger, and a short-circuit-protected open-drain output. A
south pole of sufficient strength turns the output on; a north
pole of sufficient strength is necessary to turn the output off.
The devices include on-board transient protection for all pins,
permitting operation directly from a vehicle battery or regulator
with supply voltages from 2.8 to 24 V.
Two package styles provide a choice of through-hole or surface
mounting. Package type LH is a modified 3-pin SOT23W
surface-mount package, while UA is a three-pin ultramini SIP
for through-hole mounting. Both packages are lead (Pb) free
and RoHS compliant, with 100% matte-tin-plated leadframes.
APS13290-1-DS, Rev. 1
MCO-0000385
FEATURES AND BENEFITS
• Symmetrical latch switchpoints
• Superior ruggedness and fault tolerance
• Reverse-polarity and transient protection
• Operation from –40°C to 175°C junction temperature
• Output short-circuit and overvoltage protection
• Superior temperature stability
• Resistant to physical stress
• High EMC immunity, ±12 kV HBM ESD
• Operation from unregulated supplies, 2.8 to 24 V
• Chopper stabilization
• Solid-state reliability
• Industry-standard packages and pinouts
Precision Hall-Effect Latches
for Consumer and Industrial Applications
PACKAGES:
Functional Block Diagram
Not to scale
APS13290
and APS13291
3-pin SOT23W
(suffix LH)
3-pin SIP
(suffix UA)
February 11, 2019
C
ONTROL
VCC
GND
VOUT
S
AMPLE
, H
OLD
&
A
VERAGING
H
ALL
A
MP
.
Hall
Element
D
YNAMIC
O
FFSET
C
ANCELLATION
L
OW
-P
ASS
F
ILTER
C
URRENT
L
IMIT
T
O
A
LL
S
UBCIRCUITS
R
EGULATOR
S
CHMITT
T
RIGGER
Precision Hall-Effect Latches
for Consumer and Industrial Applications
APS13290 and
APS13291
2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
RoHS
COMPLIANT
SELECTION GUIDE
Part Number Packing
[1] Mounting
Magnetic Switchpoints [2]
Ambient Temperature,
TA
Operate
BOP (G)
Release
BRP (G)
APS13290KLHALX 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
5 to 40 –5 to –40
–40°C to 125°C
APS13290KLHALT [3] 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
APS13290KUAA Bulk, 500 pieces/bag 3-pin SIP through hole
APS13291KLHALX 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
25 to 80 –25 to –80APS13291KLHALT [3] 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
APS13291KUAA Bulk, 500 pieces/bag 3-pin SIP through hole
[1] Contact Allegro for additional packing options.
[2] Algebraic convention used: (+) south polarity, (‒) north polarity.
[3] Available through authorized Allegro distributors only.
Figure 1: Typical Application Circuit
VSUPPLY
VOUT
2
CBYP =
0.1 µF
1
RLOAD =
1 kΩ
3
APS1329x
VCC VOUT
GND
Precision Hall-Effect Latches
for Consumer and Industrial Applications
APS13290 and
APS13291
3
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
PINOUT DIAGRAMS AND TERMINAL LIST TABLE
Terminal List
Name Description Number
Package LH Package UA
VCC Connects power supply to chip 1 1
VOUT Output from circuit 2 3
GND Ground 3 2
1
3
2
GND
VOUT
VCC
Package UA
Package LH
1
2
3
GND
VOUT
VCC
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Notes Rating Units
Forward Supply Voltage [1] VCC 30 V
Reverse Supply Voltage [1] VRCC –18 V
Output Off Voltage [1] VOUT 30 V
Output Current [2] IOUT 60 mA
Reverse Output Current IROUT –50 mA
Magnetic Flux Density [3] B Unlimited –
Operating Temperature Range TARange K –40 to 125 °C
Maximum Junction Temperature TJ(max) 165 °C
For 500 hours 175 °C
Storage Temperature Tstg –65 to 170 °C
ESD Voltage VESD(HBM) Human Body Model according to AEC-Q100-002 ±12 kV
VESD(CDM) Charged Device Model according to AEC-Q100-011 ±1 kV
[1] This rating does not apply to extremely short voltage transients such as load dump and/or ESD. Those events have individual ratings,
specific to the respective transient voltage event.
[2] Through short-circuit current limiting device.
[3] Guaranteed by design.
Precision Hall-Effect Latches
for Consumer and Industrial Applications
APS13290 and
APS13291
4
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ELECTRICAL CHARACTERISTICS: Valid over full operating voltage, ambient temperature range TA = –40°C to 125°C, and with
CBYP = 0.1 µF (unless otherwise specified)
Characteristics Symbol Test Conditions Min. Typ. [1] Max. Unit [2]
ELECTRICAL CHARACTERISTICS
Forward Supply Voltage VCC Operating, TJ < 175°C 2.8 – 24 V
Supply Current ICC 1 2 3 mA
Output Leakage Current IOUTOFF VOUTOFF = 24 V, B < BRP – – 10 µA
Output Saturation Voltage VOUT(SAT) IOUT = 20 mA, B > BOP – 200 500 mV
Output Off Voltage VOUTOFF B < BRP – – 24 V
Power-On Time
[3] tON
VCC ≥ VCC(min), B < BRP(min) – 10 G,
B > BOP(max) + 10 G – – 25 µs
Power-On State, Output
[3] POS VCC ≥ VCC(min), t < tON Low –
Chopping Frequency fC– 800 – kHz
Output Rise Time
[4] trRLOAD = 1 kΩ, CL = 20 pF – 0.2 2 µs
Output Fall Time
[4] tfRLOAD = 1 kΩ, CL = 20 pF – 0.1 2 µs
TRANSIENT PROTECTION CHARACTERISTICS
Output Short-Circuit Current Limit IOM 30 – 60 mA
Output Zener Clamp Voltage VZoutput IOUT = 3 mA, TA = 25°C, Output Off 30 – – V
Reverse Battery Current IRCC VRCC = –18 V, TA = 25°C – – –5 mA
Supply Zener Clamp Voltage VZICC = ICC(max) + 3 mA, TA = 25°C 30 – – V
MAGNETIC CHARACTERISTICS
Operate Point BOP
APS13290 5 20 40 G
APS13291 25 50 80 G
Release Point BRP
APS13290 –40 –20 –5 G
APS13291 –80 –50 –25 G
Hysteresis BHYS
APS13290 10 40 80 G
APS13291 50 100 160 G
Symmetry BSYM BOP + BRP –27.5 – 27.5 G
Magnetic Offset BOFF (BOP + BRP) / 2 –13.75 – 13.75 G
[1] Typical data are at TA = 25°C and VCC = 12 V.
[2] 1 G (gauss) = 0.1 mT (millitesla).
[3] Guaranteed by device design and characterization.
[4] CL = oscilloscope probe capacitance.
Precision Hall-Effect Latches
for Consumer and Industrial Applications
APS13290 and
APS13291
5
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions Value Units
Package Thermal Resistance RθJA
Package LH, 1-layer PCB with copper limited to solder pads 228 °C/W
Package LH, 2-layer PCB with 0.463 in.
2 of copper area each side
connected by thermal vias 110 °C/W
Package UA, 1-layer PCB with copper limited to solder pads 165 °C/W
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
25 45 65 85 105 125 145 165 185
Maximum Allowable VCC (V)
Temperature (°C)
Power Derating Curve
TJ(max) = 175°C; ICC = ICC(max), IOUT = 0 mA (Output Off)
VCC(max)
VCC(min)
Package UA, 1-layer PCB
(RθJA = 165 °C/W)
Package LH, 1-layer PCB
(RθJA = 228 °C/W)
Package LH, 2-layer PCB
(RθJA = 110 °C/W)
TJ(max)
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
25 45 65 85 105 125 145 165 185
Power Dissipation, PD(mW)
Temperature (°C)
Power Dissipation versus Ambient Temperature
Package LH, 2-layer PCB
(RθJA = 110°C/W)
Package UA, 1-layer PCB
(R
θJA
= 165°C/W)
Package LH, 1-layer PCB
(RθJA = 228°C/W)
Precision Hall-Effect Latches
for Consumer and Industrial Applications
APS13290 and
APS13291
6
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
CHARACTERISTIC PERFORMANCE DATA
Electrical Characteristics
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-60 -40 -20 020 40 60 80 100 120 140
I
CC
(mA)
T
A
(°C)
Average Supply Current versus Ambient Temperature
2.8
12
24
VCC (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2 6 10 14 18 22 26
I
CC
(mA)
VCC (V)
Average Supply Current versus Supply Voltage
-40
25
125
TA(°C)
0
50
100
150
200
250
300
350
400
450
500
2 6 10 14 18 22 26
VOUT(SAT) (mV)
VCC (V)
Average Low Output Voltage versus Supply Voltage for IOUT = 20 mA
-40
25
125
TA(°C)
0
50
100
150
200
250
300
350
400
450
500
-60 -40 -20 020 40 60 80 100 120 140
V
OUT(SAT)
(mV)
T
A
(°C)
Average Low Output Voltage versus Ambient Temperature for IOUT = 20 mA
2.8
12
24
VCC (V)
0
50
100
150
200
250
300
350
400
450
500
2 6 10 14 18 22 26
V
OUT(SAT)
(mV)
VCC (V)
Average Low Output Voltage versus Supply Voltage for IOUT = 20 mA
-40
25
125
TA(°C)
Precision Hall-Effect Latches
for Consumer and Industrial Applications
APS13290 and
APS13291
7
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
CHARACTERISTIC PERFORMANCE DATA (continued)
APS13290 Magnetic Characteristics
5
10
15
20
25
30
35
40
-60 -40 -20 020 40 60 80 100 120 140
BOP (G)
TA(°C)
Average Operate Point versus Ambient Temperature
2.8
12
24
VCC (V)
5
10
15
20
25
30
35
40
2 6 10 14 18 22 26
BOP (G)
VCC (V)
Average Operate Point versus Supply Voltage
-40
25
125
TA(°C)
10
20
30
40
50
60
70
80
-60 -40 -20 020 40 60 80 100 120 140
B
HYS
(G)
T
A
(°C)
Average Switchpoint Hysteresis versus Ambient Temperature
2.8
12
24
VCC (V)
10
20
30
40
50
60
70
80
2 6 10 14 18 22 26
BHYS (G)
VCC (V)
Average Switchpoint Hysteresis versus Supply Voltage
-40
25
125
TA(°C)
-40
-35
-30
-25
-20
-15
-10
-5
-60 -40 -20 020 40 60 80 100 120 140
BRP (G)
TA(°C)
Average Release Point versus Ambient Temperature
2.8
12
24
VCC (V)
-40
-35
-30
-25
-20
-15
-10
-5
2 6 10 14 18 22 26
BRP (G)
VCC (V)
Average Release Point versus Supply Voltage
-40
25
125
TA(°C)
-25
-20
-15
-10
-5
0
5
10
15
20
25
-60 -40 -20 020 40 60 80 100 120 140
B
SYM
(G)
TA(°C)
Average BOP + BRP Symmetry versus Ambient Temperature
2.8
12
24
VCC (V)
-25
-20
-15
-10
-5
0
5
10
15
20
25
2 6 10 14 18 22 26
BSYM (G)
VCC (V)
Average BOP + BRP Symmetry versus Supply Voltage
-40
25
125
TA(°C)
Precision Hall-Effect Latches
for Consumer and Industrial Applications
APS13290 and
APS13291
8
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
CHARACTERISTIC PERFORMANCE DATA (continued)
APS13291 Magnetic Characteristics
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
-60 -40 -20 020 40 60 80 100 120 140
BOP (G)
TA(°C)
Average Operate Point versus Ambient Temperature
2.8
12
24
VCC (V)
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
2 6 10 14 18 22 26
BOP (G)
V
CC
(V)
Average Operate Point versus Supply Voltage
-40
25
125
TA(°C)
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
-60 -40 -20 020 40 60 80 100 120 140
BHYS (G)
TA(°C)
Average Switchpoint Hysteresis versus Ambient Temperature
2.8
12
24
VCC (V)
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
2 6 10 14 18 22 26
BHYS (G)
VCC (V)
Average Switchpoint Hysteresis versus Supply Voltage
-40
25
125
TA(°C)
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-60 -40 -20 020 40 60 80 100 120 140
BRP (G)
TA(°C)
Average Release Point versus Ambient Temperature
2.8
12
24
VCC (V)
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
2 6 10 14 18 22 26
BRP (G)
VCC (V)
Average Release Point versus Supply Voltage
-40
25
125
TA(°C)
-25
-20
-15
-10
-5
0
5
10
15
20
25
-60 -40 -20 020 40 60 80 100 120 140
B
SYM
(G)
TA(°C)
Average BOP + BRP Symmetry versus Ambient Temperature
2.8
12
24
VCC (V)
-25
-20
-15
-10
-5
0
5
10
15
20
25
2 6 10 14 18 22 26
BSYM (G)
VCC (V)
Average BOP + BRP Symmetry versus Supply Voltage
-40
25
125
TA(°C)
Precision Hall-Effect Latches
for Consumer and Industrial Applications
APS13290 and
APS13291
9
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
OPERATION
The output of these devices switches low (turns on) when a mag-
netic field perpendicular to the Hall element exceeds the operate
point threshold, BOP (see Figure 2). After turn-on, the output volt-
age is VOUT(SAT)
. The output transistor is capable of continuously
sinking up to 30 mA. When the magnetic field is reduced below
the release point, BRP , the device output goes high (turns off)
to VOUTOFF. The difference in the magnetic operate and release
points is the hysteresis, BHYS , of the device. This built-in hyster-
esis allows clean switching of the output even in the presence of
external mechanical vibration and electrical noise.
Removal of the magnetic field will leave the device output
latched on if the last crossed switchpoint is BOP, or latched off if
the last crossed switch point is BRP.
POWER-ON BEHAVIOR
Device power-on occurs once tON has elapsed. During the
time prior to tON, and after VCC ≥ VCC(min), the output state is
VOUT(SAT) (Low). After tON has elapsed, the output will corre-
spond with the applied magnetic field for B > BOP or B < BRP.
See Figure 3 for an example.
Powering-on the device in the hysteresis range (less than BOP and
higher than BRP) will give an output state of VOUT(SAT). The cor-
rect state is attained after the first excursion beyond BOP or BRP
.
Figure 2: Switching Behavior of Latches
On the horizontal axis, the B+ direction indicates increasing
south polarity magnetic field strength, and the B– direction
indicates increasing north polarity field strength.
FUNCTIONAL DESCRIPTION
BOP
BRP
BHYS
VOUTOFF
VOUT
VOUT(SAT)
Switch to Low
Switch to High
B+
B–
V+
0
0
t
t
V
VCC(min)
tON
0
Output State
Undefined for
VCC
< VCC
(min) POS
VOUT(SAT )
VOUTOFF
V
VOUT
VCC
POS
B > BOP, BRP < B < BOP
B < BRP
Figure 3: Power-On Timing Diagram
Precision Hall-Effect Latches
for Consumer and Industrial Applications
APS13290 and
APS13291
10
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APPLICATIONS
It is strongly recommended that an external bypass capacitor be
connected (in close proximity to the Hall element) between the
supply and ground of the device to guarantee correct performance
under harsh environmental conditions and to reduce noise from
internal circuitry. As is shown in Figure 1: Typical Application
Circuit, a 0.1 µF capacitor is typical. In applications where maxi-
mum robustness is required, such as long-life industrial motors,
additional measures may be taken. In Figure 4: Enhanced Protec-
tion Circuit, a resistor in series with the VCC pin and a capacitor
on the VOUT pin enhance the EMC immunity of the device. It is
up to the user to fully qualify the Allegro sensor IC in their end
system to ensure they achieve their system requirements.
These devices are sensitive in the direction perpendicular to the
branded face, as depicted in Figure 5. For further information,
extensive applications information on magnets and Hall-effect
sensors is available in:
• Hall-Effect IC Applications Guide, AN27701,
• Hall-Effect Devices: Guidelines for Designing Subassemblies
Using Hall-Effect Devices AN27703.1
• Soldering Methods for Allegro’s Products – SMD and
Through-Hole, AN26009
All are provided on the Allegro website:
www.allegromicro.com
V
SUPPLY
V
OUT
2
C
BYP
=
0.1 µF
1
R
LOAD
=
1 kΩ
C
OUT
=
4.7 nF
R
S
=
100 Ω
V
PULL-UP
3
APS1329x
VCC VOUT
GND
A
A
A
RS and COUT are recommended for maximum
robustness in an automotive environment.
Figure 4: Enhanced Protection Circuit
Figure 5: Sensing Congurations
Precision Hall-Effect Latches
for Consumer and Industrial Applications
APS13290 and
APS13291
11
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Amp
Regulator
Clock/Logic
Hall Element
Sample and
Hold
Low-Pass
Filter
CHOPPER STABILIZATION
A limiting factor for switchpoint accuracy when using Hall-effect
technology is the small signal voltage developed across the Hall
plate. This voltage is proportionally small relative to the offset
that can be produced at the output of the Hall sensor. This makes
it difficult to process the signal and maintain an accurate, reliable
output over the specified temperature and voltage range. Chopper
stabilization is a proven approach used to minimize Hall offset.
The Allegro technique, dynamic quadrature offset cancellation,
removes key sources of the output drift induced by temperature
and package stress. This offset reduction technique is based on a
signal modulation-demodulation process. Figure 6 illustrates how
it is implemented.
The undesired offset signal is separated from the magnetically
induced signal in the frequency domain through modulation.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetically induced signal to recover
its original spectrum at baseband while the DC offset becomes
a high-frequency signal. Then, using a low-pass filter, the signal
passes while the modulated DC offset is suppressed. Allegro’s
innovative chopper stabilization technique uses a high-frequency
clock. The high-frequency operation allows a greater sampling
rate that produces higher accuracy, reduced jitter, and faster sig-
nal processing. Additionally, filtering is more effective and results
in a lower noise analog signal at the sensor output. Devices such
as the APS13290 and APS13291 that use this approach have an
extremely stable quiescent Hall output voltage, are immune to
thermal stress, and have precise recoverability after temperature
cycling. This technique is made possible through the use of a
BiCMOS process which allows the use of low offset and low
noise amplifiers in combination with high-density logic and
sample-and-hold circuits.
Figure 6: Model of Chopper Stabilization
(Dynamic O󰀨set Cancellation)
Precision Hall-Effect Latches
for Consumer and Industrial Applications
APS13290 and
APS13291
12
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
POWER DERATING
The device must be operated below the maximum junction tem-
perature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the appli-
cation. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems website.)
The Package Thermal Resistance, RθJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity, K,
of the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, RθJC, is a relatively
small component of RθJA. Ambient air temperature, TA, and air
motion are significant external factors, damped by overmolding.
The resulting power dissipation capability directly reflects upon
the ability of the device to withstand extreme operating condi-
tions. The junction temperature mission profile specified in the
Absolute Maximum Ratings table designates a total operating life
capability based on qualification for the most extreme conditions,
where TJ may reach 175°C.
The silicon IC is heated internally when current is flowing into
the VCC terminal. When the output is on, current sinking into the
VOUT terminal generates additional heat. This may increase the
junction temperature, TJ, above the surrounding ambient tempe-
rature. The APS13290 and APS13291 are permitted to operate
up to TJ = 175°C. As mentioned above, an operating device will
increase TJ according to equations 1, 2, and 3 below. This allows
an estimation of the maximum ambient operating temperature.
PD = VIN × IIN (1)
ΔT = PD × RθJA (2)
TJ = TA + ΔT (3)
For example, given common conditions such as: TA= 25°C,
VCC = 12 V, ICC = 2 mA, VOUT = 200 mV, IOUT = 20 mA (output
on), and RθJA = 165°C/W, then:
PD = (VCC × ICC) + (VOUT × IOUT) =
(12 V × 2 mA) + (200 mV × 20 mA) =
24 mW + 4 mW = 28 mW
ΔT = PD × RθJA = 28 mW × 165°C/W = 4.6°C
TJ = TA + ΔT = 25°C + 4.6°C = 29.6°C
A worst-case estimate, PD(max), represents the maximum allow-
able power level (VCC(max), ICC(max)), without exceeding
TJ(max), at a selected RθJA.
For example, given the conditions RθJA = 228°C/W, TJ(max) =
175°C, VCC(max) = 24 V, ICC(max) = 3.25 mA, VOUT = 500 mV,
and IOUT = 30 mA (output on), the maximum allowable operating
ambient temperature can be determined.
The power dissipation required for the output is shown below:
PD(VOUT) = VOUT × IOUT = 500 mV × 30 mA = 15 mW
The power dissipation required for the IC supply is shown below:
PD(VCC) = VCC × ICC = 24 V × 3.25 mA = 78 mW
Next, by inverting using equation 2:
ΔT = PD × RθJA = [PD(VOUT) + PD(VCC)] × 228°C/W =
(15 mW + 78 mW) × 228°C/W =
93 mW × 228°C/W = 21.2°C
Finally, by inverting equation 3 with respect to voltage:
TA(est) = TJ(max) – ΔT = 175°C – 21.2°C = 153.8°C
In the above case, there is sufficient power dissipation capability
to operate up to TA(est). The example indicates that TA(max)
can be as high as 153.8°C without exceeding TJ(max). However,
the TA(max) rating of the devices is 125°C; the APS13290 and
APS13291 performance is not guaranteed above TA = 125°C.
Precision Hall-Effect Latches
for Consumer and Industrial Applications
APS13290 and
APS13291
13
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
0.55 REF
Gauge Plane
Seating Plane
0.25 BSC
0.95 BSC
0.95
1.00
0.70
2.40
2
1
AActive Area Depth, 0.28 mm REF
B
C
B
Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Branding scale and appearance at supplier discretion
A
PCB Layout Reference View
Branded Face
CStandard Branding Reference View
APS13290KLHA
1
A25
APS13291KLHA
1
A27
2.90 +0.10
–0.20
4°±4°
8X 10° REF
0.180+0.020
–0.053
0.05 +0.10
–0.05
0.25 MIN
1.91 +0.19
–0.06
2.98 +0.12
–0.08
1.00 ±0.13
0.40 ±0.10
For Reference Only; not for tooling use (reference dwg. 802840)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
DHall element, not to scale
D
D
D
1.49
0.96
3
Package LH, 3-Pin (SOT-23W)
Precision Hall-Effect Latches
for Consumer and Industrial Applications
APS13290 and
APS13291
14
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Package UA, 3-Pin SIP
2 31
1.27 NOM
1.02
MAX
45°
45°
C
1.52 ±0.05
B
Gate and tie bar burr area
A
B
C
Dambar removal protrusion (6×)
A
D
Active Area Depth, 0.50 mm ±0.08
Branding scale and appearance at supplier discretion
Mold Ejector
Pin Indent
0.41 +0.03
–0.06
0.43 +0.05
–0.07
14.99 ±0.25
4.09 +0.08
–0.05
3.02 +0.08
–0.05
0.79 REF
10°
Branded
Face
For Reference Only – Not for Tooling Use
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of moldflash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
(Reference DWG-0000406, Rev. 1)
0.51 REF
D
A28
Standard Branding Reference View
1
A26
1
E
E
2.04
1.44 E
EHall element, not to scale
APS13290KUAA
APS13291KUAA
Precision Hall-Effect Latches
for Consumer and Industrial Applications
APS13290 and
APS13291
15
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Copyright ©2019, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Number Date Description
– March 6, 2018 Initial release
1 February 11, 2019 Minor editorial updates