High Performance ba ea) ) CMOS SRAM y AOS s2KX8 CMOS SRAM (Cominon 1/0) Bers Gran Ts! AS7C256 Features * Organization: 32,768 words x 8 bits * Easy memory expansion with CE and OE inputs * High speed TTL-compatible, three-state I/O - 10/12/15/20/25/35 ns address access time * 28-pin JEDEC standard packages - 3/3/4/5/6/8 ns output enable access time - 300 mil PDIP and SOJ * Low power consumption Socket compatible with 7C512 and 7C1024 - Active: 660 mW max (10 ns cycle) - 330 mil SOIC - Standby: |] mW max, CMOS I/O - 8X13.4 TSOP 2.75 mW max, CMOS I/O, L version * ESD protection 2 2000 volts - Very low DC component in active power * Latch-up current 2 200 mA * 2.0V data retention (L version) * Equal access and cycle times Logic block diagram Pin arrangement ~T TSOP 8X13.4 DIP, SOJ, SOIC Veo > GND + Input buffer aa co vo A ! 28 a9 [24 19) 3 2 Ag 25 18] 4 25 AO AL 26 Al - vo? we id g 2 3 Az 256x1 28x68 2 Veo (28 5 1 z A3 em 5 Aw Cyl AS7C56 14 8 8 Ad ho Armay > g Alz2 ([]2 13 9 uw AS 1262,144) a a7 (3 12 10 = o 1OO 3 5 io i 5 Als a Ee 3 1 45 aa? 8 1 Column decoder Control _ ME circuit _ OF +- CE AAAAAAA 73.9 10111213 Selection guide 7256-10 7C256-12 9 7256-15 7C256-20 7C256-25 7C256-35 = Unit Maximum address access time 10 12 15 20 25 35 ns Maximum output enable access time 3 3 4 5 6 8 ns Maximum operating current 120 1s 110 100 90 80 mA 2.0 2.0 2.0 2.0 2.0 2.0 mA Maximum CMOS standby current L 0.5 0.5 0.5 0.5 0.5 0.5 mA ALLIANCE SEMICONDUCTORSey AS7C256 AS7C256L | Functional description The AS7C256 1s a hogh performance CMOS 262, 144-bit Stauc Random Access Memory (SRAM) organized as 32,768 words x 8 bits. It is designed tor memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle umes (tas. tae. tye) of L0/12-15/20/25/35 ns with output enable access times (tog) of 3/3/4/5/6/8 ns are ideal for high performance applications. A chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. When CE is HIGH the device enters standhy mode. The standard AS7C256 15 guaranteed not to exceed 11 mW power consumption in standby mode; the L version is guaranteed not to exceed 2.75 mW, and typically requires only 500 {AW. The L version also offers 2.0V data retention, with maximum power consumpuon in Uus mode of 300 uw A write cycle 15 accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins 1/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplshed by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) HIGH. The chip drives [/ Q pins with the data word referenced by the input address. When chip enable or output enable 1s HIGH, or write enable is LOW, output drivers stay in high-impedance mode All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C256 is packaged in all high volume industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on any pin relative to GND Vv, -0.5 +7.0 Vv Power dissipation Py - 1.0 Ww Storage temperature (plastic) Tog 55 +150 C Temperature under bias Thias -10 +85 C DC output current Iout - 20 mA Stresses greater than those listed under Absolute Maximum Rutings may cause permanent damage to the device This 1s a stress rating only and functional operation of the device at chese or any other conditions Outside those indicated in the operanonal sections uf this specification is not implied. Exposure to absolute max- imum rating conditions for extended periods may affect reliability Truth table CE WE OF Data Mode H xX xX High Z Standby (Isp, Ispy) L H H High Z Output disable L H L Dout Read I L x Din Write X = Don't Care, L = LOW, H = HIGH Recommended operating conditions (T, = 0C to +70C) Parameter Symbol Min Typ Max Unit Vee 4.5 5.0 5.5 Vv Supply voltage GND 0.0 0.0 0.0 v Vin 2.2 - Voctl Vv Input voltage Vie 05 = 08 v "Vi, min = 3 OF for pulse width tess chan ty, 72AS7C256 | AS7C256 zs DC operating characteristics! (Vcc = 5VE10%, GND = OV, T, = 0C ta +70C) -10 -12 -15 -20 -25 -35 Parameter Symbol Test Conditions Min Max] Min Max| Min Max} Min Max| Min Max! Min Max] Unit Input leakage Vec = max, current : Wut vez GND to Voc ~ | ~ ~ | - | ~ | ~ HA Output leakage Ilr! CE = Vay. Voc = max, a ee current Vout = GND to Ver Operating power I. CE = Vy, f = fnax, - 120) ~ LES} ~ 110} - 100} - 90] ~ 80] mA supply current ce four = O mA Ly] - 215) 110) - 105] - 95) 85} 75] mA lep = Vien f = hanae - 45] - 40); - 30) - 30] - 25] - 25] mA Standby L]- 40; - 35] - 257 - 25) - 20} - 20} mA power supply CE> Vec-0.2V, f= 0, -~ 2.0) - 2.0] - 2.0] - 20} - 2.0] - 2.0] mA sumer spi Vin S$ 0.2 or Lt - o5/- 05] - 0o5;- 05] - 95) - 05] mA Vin 2 Voc-0.2V Vo. lo, = 8 MA, Voc = min - os) - o4[ o4] - o4f - o4f - o4] v Output voltage = - - Vou lo = 4 mA, Vec = min 24 {24 -f24 -f2z4 - 24 -[z4 - | Vv Capacitance? (f = | MHz, T, = Room temperature, Vee = 5V) Parameter Symbol Signals Test conditions Max Unit Input capacitance Cin A, CE, WE, OE Vin = OV 5 pF [/O capacitance Crap [fO Vin = Vour = OV 7 pF Read cycle? (Voc = 5V10%, GND = OV, T, = 0C to +70C) -10 -12 -15 -20 -25 -35 Parameter Symbel | Min Max | Min Max} Min Max} Min Max! Min Max| Min Max] Unit Notes Read cycle time tre 10 ~ | 2 -~ 7S =~ 720 ~ 125 - 135 - ns Address access time tas - 10} - 12|{ - IS] - 20) 25) -~ 35] ns 3 Chip enable (CE) access time lace - 10] - 32} - 15] - 20} - 25] - 35] ns 3 Output enable (OE) access time log - 3]7y- 3] - 4f- S]|T- 6F/y- 8 ns Output hold from address change toy > -]7f 3 -~]3 =~] 3 =~] 3 =~] 3 = ns 5 CE LOW to output in Low Z tcLz 3 - 3 - 3 ~ | 3 - 30 3 - ns 4,5 CE HIGH to output in High Z teuz -~ 3/- 3/- 4]- st- oeof- 8] ns 4,5 OE LOW to output in Low Z towz 0 -|o -jo -]/o0 -J}fo -J]o -|J| as 4,5 OE HIGH to output in High Z tonz - 3/- 3)- 4/- s/t- 6/- 8] ns 45 Power up time tpy oO -|0 j~}; 0 ~]| 0 ~]O - |] QO = ns 4,5 Power down time tpp - 10); - 2} 15} - 20} - 25] - 35] ns 4,5 Key to switching waveforms _5 Rising input [""} Falling input Undefined output/don't care 27* AS7C256 AS7C256L H @ Read waveform 13:67.9 Address controlled tac | Address on Dout Data valid Read waveform 23689 CE controlled cuz lack Dour Data valid tcLz tee \ lec Supply H 50% 50% Isp current White cycle (Voc = 5V+10%, GND = OV, T, = 0C to +70C) -10 -12 -15 -20 -25 -35 Parameter Symbol | Min Max {Min Max} Min Max| Min Max|Min Max] Min Max| Unit Notes Write cycle ume twe 10 712 -]18 -]20 - |]20 - |]30 - ]) ns Chip enable to write end Sow 9 -]710 - ]12 -] 12 -]1S -]20 -] ns Address setup to write end taw 9 -};10 -]12 -1/ 12 -]1S - | 20 - |] ns Address setup time las oO -;oO -~|0 -+-|0 -~]O0 -|] 0 =) ns Write pulse width twp 7 --} 8 -] 9 -471B =] 15 =] 17 = ns Address hold from end of write aH oO -}/0 j-~-|0 -~/;}0 -]0 -}| 0 -] ns Data valid to write end pw 6 -16 -}] 8 -];10 -]10 -j] 15 - ns Data hold time lon o -j}o -{|0 -~]|0 -]0 -]| 60 -Jons 4,5 Write enable to output in High Z | tyz ~- Sft=- S}Pt> S]T- SPT> SPS ns 15 Output active from write end tow 3 -{3 -) 3 =), 3 -] 3 =f 3 = ns 4,5 28Ae. AS7C256 AS7C256 Write waveform | WE controlled twe law | t AW | AH Address __ twe VV WE K 7 +| t AS } tow pH De } Data valid | wz - _ oe D Write waveform 2 Address Data retention characteristics pw Data valid CE controlled L version only Parameter Symbol Test conditions Min Max Unit Vec tor data retention Vor Veo = 2.0V 2.0 - v Data retention current lee - 150 pA : - aaa CE 2 Ve0.2V Chip enable to data retention time tepR 0 - ns Operation recovery time IR Vin 2 Yec0.2V or trc ~ ns Vi, S0.2V Input leakage current lige in - 1 pA Data retention waveform L version only -_ Data retention mode _____ , Ts ee f4ysy..t Vec 45V Vor 22.09 a 4.5V tcpr tr YF Vv | CE a Vin DR Vin *AS7C256 AS7C256L j AC test conditions ~ Output toad: see Figure B. . Thevenin equivalent: except for toyz and tcyz see Figure C. 16gw Input pulse level: GND to 3.0V. See Figure A. Douey~\ +1728 Input rise and fall times: 5 ns. See Figure A. Input and output timing reference levels: 1.5V. +5 +5V 480W 480W Dau Down 255W. 30 pP* 255W. 5 pF* including scope and jig capacitance GND GND Figure A: Input waveform Figure B: Output load Figure C: Output load for tezz, texyz Notes During Voc power-up, a pull-up resistor to Ve on CE is required to meet Isq specification, This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, C. terz and toyz are specified with CL = SpF as in Figure C. Transition is measured +500m from steady-state valtage This parameter is guaranteed bur nat tested. WE is HIGH for read cycle. CE and OF are LOW for read cycle. Address valid prior to or coincident with CE wansition LOW, All read cycle timings are referenced from the last valid address to the first transitioning address. 0 CE or WE must be HIGH during address transitions. I All write cycle timings are referenced from the last valid address to the first transitioning address. ~~ COON AWM kw N 30AS7C256 | AS7C256 oe Typical DC and AC characteristics Normalized supply current [c-, [sp Normalized supply current Ic, [gg Normalized supply current Ica, vs. supply voltage Vec vs. ambient temperature T, vs ambient temperature T, [4 Lt 1.2 hd = 625 lee = Vee = 5.0 4 t.0 2 1.0 oe 25 = 08 = 08 aS x N 5 3 0.6 3 06 z l E E 3 3 0.4 S Ot 5 0.2 0.2 0.2 'sB * 0.04 0.0 0.0 4.0 +5 $.0 5.5 6.0 -5$ -10 35 80 125 -$5 -t0 3S 80 125 Supply voltage (V) Ambient temperature (C) Ambient temperature (C) Normalized access time tay Normalized access time tag, Normalized supply current I vs, supply voltage Vie vs. ambient temperature T, vs. cycle frequency I /tyc, b/twe 15 bit P Z Ver = 5.0 = 1.3 = C 2 2 a g 1.2 3 oO gf? E x 9 9 3 x od g 2 3 a : E 1.0 E 2 Z z 0.9 0.8 . 4.0 4.5 5.0 5.5 6.0 $5 -10 35 80 125 0 25 50 75 100 Supply voltage (V} Ambient temperature (C) Cycle frequency (MHz) Output source current Igy Output sink current Ig, Typical access time change Arty. vs, output voltage Vou vs. output voltage Voy vs. output capacitive loading 140 z 120 < of = Veo = 5.0 3 _ Vou = 4.5V z T, = 25C = 100 a $ = S 3 E 80 2 z o & 5 = 60 Bo 3 2 & 3 z 9 5 c 20 0 0.0 1.25 2.5 375 5.0 0.0 1.25 2.5 3.75 5.0 0 250 500 750 1000 Ourput voltage (V) Output voltage () Capacitance (pF) 31 NeaAS7C256 AS/C256L AS7C256 ordering information Package / Access ume 10 ns 12 ns 1S ns 20 ns 25 ns 35 ns AS7C256-12PC = AS7C256-15PC = AS7C256-20PC = AS7C256-25PC = AS7C256-35PC Plastic DIP, 300 mil AS7C2S6L-12PC AS7C256L-15PC AS7C256L-20PC AS7C256L-25PC AS7C256L-35PC Plastic SOJ, 300 mil AS7C256-10JC AS7C256L-10JC AS7C256-12JC AS7C2S6L-12JC AS7C256-15JC AS7C256L-15JC AS7C256-20JC AS7C256L-20fC AS7C256-25}C AS7C256L-25JC AS7C256-35JC AS7C2S56L-35JC Plastic SOIC, 330 mil AS7C256-10SC AS7C256L-10SC AS7C256-128C AS7C256L- | 2SC AS7C256-15SC AS7C256L-15SC AS7256-20SC AS7C256L-20SC AS7C256-25SC AS7C256L-25SC AS7C256-358C AS7C256L-35SC TSOP 8x1 3.4 AS7C256-LOTC AS7C256L-10TC AS7C256-12TC AS7C2S6L-12TC AS7C256-1 STC AS7C256L-1STC AS7C256-20TC AS7C256L-20TC AS7C256-25TC AS7C256L-2S5TC AS7C256-35TC AS7C256L-35TC AS7C256 part numbering systern AS7C 256 x ~XX xX Cc + Device SRAM prefix number Blank = Standard power Access Package: P = PDIP 300 milJ L = Low power S =SOIC 330 milT ame = SOJ 300 mil Commercial temperature range. = TSOP 8x14 0C to 70 C 32