June 2003 Preliminary Information AS7C1025B (R) 5V 128K X 8 CMOS SRAM (Center power and ground) Features * * * * Pin arrangement 32-pin TSOP 2 A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 Logic block diagram VCC GND 512 x 256 x 8 Array (1,048,576) I/O7 Sense amp A0 A1 A2 A3 A4 A5 A6 A7 A8 Row decoder Input buffer A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 WE OE CE A9 A10 A11 A12 A13 A14 A15 A16 Control circuit 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A12 A11 A10 A9 A8 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) I/O0 Column decoder 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AS7C1025B * * TTL/LVTTL-compatible, three-state I/O * JEDEC-standard packages - 32-pin, 300 mil SOJ - 32-pin, 400 mil SOJ - 32-pin, TSOP 2 * ESD protection 2000 volts * Latch-up current 200 mA Product AS7C1025B Industrial and commercial temperatures Organization: 131,072 x 8 bits High speed - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time Low power consumption: ACTIVE - 605mW / max @ 10 ns Low power consumption: STANDBY - 28 mW / max CMOS 6 T 0.18 u CMOS technology Easy memory expansion with CE, OE inputs Center power and ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AS7C1025B * * * * 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A12 A11 A10 A9 A8 Selection guide -10 -12 -15 -20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 5 6 7 8 ns 110 100 90 80 mA 5 5 5 5 mA Maximum operating current Maximum CMOS standby current 7/14/03, v.0.0.4 Alliance Semiconductor P. 1 of 8 Copyright (c) Alliance Semiconductor. All rights reserved. AS7C1025B (R) Functional description The AS7C1025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 x 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are ideal for highperformance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems. When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C1026B is guaranteed not to exceed 28 mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1025B is packaged in common industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on VCC relative to GND Vt1 -0.50 +7.0 V Voltage on any pin relative to GND Vt2 -0.50 VCC + 0.5 V Power dissipation PD - 1.0 Storage temperature (plastic) Tstg -65 W +150 o C Ambient temperature with VCC applied Tbias -55 +125 oC DC current into outputs (low) IOUT - 20 mA NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H X X High Z Standby (ISB, ISB1) L H H High Z Output disable (ICC) L H L DOUT Read (ICC) L L X DIN Write (ICC) Key: X = don't care, L = low, H = high. 7/14/03, v.0.0.4 Alliance Semiconductor P. 2 of 8 AS7C1025B (R) Recommended operating conditions Parameter Symbol Min Nominal Max Unit VCC 4.5 5.0 5.5 V VIH 2.2 - VCC + 0.5 V VIL -0.5 - 0.8 Supply voltage Input voltage commercial Ambient operating temperature TA industrial 0 TA - -40 - V 70 o C 85 o C VIL min. = -3.0 V for pulse width less than tRC/2. DC operating characteristics (over the operating range)1 -10 Test conditions -12 -15 -20 Parameter Symbol Input leakage current | ILI | VCC = Max, VIN = GND to VCC Min Max Min Max Min Max Min Max Unit - 1 - 1 - 1 - 1 A Output leakage current | ILO | VCC = Max, CE = VIH, Vout = GND to VCC - 1 - 1 - 1 - 1 A Operating power supply current ICC CE = VIL, f = fMax, IOUT = 0 mA - 110 - 100 - 90 - 80 mA Standby power supply current1 ISB CE = VIH, f = fMax, fOUT = 0 - 50 - 45 - 45 - 40 mA ISB1 CE VCC-0.2 V, VIN 0.2 V or VIN VCC -0.2 V, f = 0, fOUT = 0 - 5 5 mA VOL IOL = 8 mA, VCC = Min - 0.4 VOH IOH = -4 mA, VCC = Min 2.4 Output voltage 5 5 - 0.4 - 0.4 - 0.4 V 2.4 - 2.4 - 2.4 - V Capacitance (f = 1 MHz, Ta = 25o C, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE, WE, OE VIN = 0 V 5 pF I/O capacitance CI/O I/O VIN = VOUT = 0 V 7 pF 7/14/03, v.0.0.4 Alliance Semiconductor P. 3 of 8 AS7C1025B (R) Read cycle (over the operating range)3,9 -10 Parameter -12 -15 -20 Symbol Min Max Min Max Min Max Min Max Unit Notes Read cycle time tRC 10 - 12 - 15 - 20 - ns Address access time tAA - 10 - 12 - 15 - 20 ns 3 Chip enable (CE) access time tACE - 10 - 12 - 15 - 20 ns 3 Output enable (OE) access time tOE - 5 - 6 - 7 - 8 ns Output hold from address change tOH 3 - 3 - 3 - 3 - ns 5 CE low to output in low Z tCLZ 3 - 3 - 3 - 3 - ns 4, 5 CE low to output in high Z tCHZ - 4 - 5 - 6 - 7 ns 4, 5 OE low to output in low Z tOLZ 0 - 0 - 0 - 0 - ns 4, 5 OE high to output in high Z tOHZ - 4 - 5 - 6 - 7 ns 4, 5 Power up time tPU 0 - 0 - 0 - 0 - ns 4, 5 Power down time tPD - 10 - 12 - 15 - 20 ns 4, 5 Key to switching waveforms Rising input Falling input Undefined/don't care Read waveform 1 (address controlled)3,6,7,9 tRC Address tAA tOH DOUT Data valid Read waveform 2 (CE and OE controlled)3,6,8,9 tRC1 CE tOE OE DOUT Supply current 7/14/03, v.0.0.4 tOHZ tCHZ tOLZ tACE tCLZ tPU Data valid tPD 50% Alliance Semiconductor ICC ISB 50% P. 4 of 8 AS7C1025B (R) Write cycle (over the operating range)11 -10 Parameter -12 -15 Min Max Min -20 Symbol Min Max Max Min Max Unit Notes Write cycle time tWC 10 - 12 - 15 - 20 - ns Chip enable (CE) to write end tCW 8 - 9 - 10 - 12 - ns Address setup to write end tAW 8 - 9 - 10 - 10 - ns Address setup time tAS 0 - 0 - 0 - 0 - ns Write pulse width tWP 7 - 8 - 9 - 12 - ns Write recovery time tWR 0 - 0 - 0 - 0 - ns Address hold from end of write tAH 0 - 0 - 0 - 0 - ns Data valid to write end tDW 5 - 6 - 8 - 10 - ns Data hold time tDH 0 - 0 - 0 - 0 - ns 4, 5 Write enable to output in high Z tWZ - 5 - 6 - 7 - 8 ns 4, 5 Output active from write end tOW 1 - 1 - 1 - 2 - ns 4, 5 Write waveform 1 (WE controlled)10,11 tWC tAW tWR tAH Address tWP WE tAS tDW DIN tDH Data valid tWZ tOW DOUT 7/14/03, v.0.0.4 Alliance Semiconductor P. 5 of 8 AS7C1025B (R) Write waveform 2 (CE controlled)10,11 tAW tWC tAH tWR Address tAS tCW CE tWP WE tWZ tDW DIN tDH Data valid DOUT AC test conditions - - - - Output load: see Figure B. Input pulse level: GND to 3.5 V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5 V. +5 V Thevenin equivalent: 480 +3.5 V GND 90% 10% DOUT 255 90% 2 ns 10% Figure A: Input pulse C13 DOUT 168 +1.728 V (5 V and 3.3 V) GND Figure B: 5 V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. tCLZ and tCHZ are specified with CL = 5 pF, as in Figure C. Transition is measured 500 mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is high for read cycle. CE and OE are low for read cycle. Address is valid prior to or coincident with CE transition low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be high during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. N/A. C = 30 pF, except all high Z and low Z parameters where C = 5 pF. 7/14/03, v.0.0.4 Alliance Semiconductor P. 6 of 8 AS7C1025B (R) Package dimensions 32-pin TSOP 2 N N/2+1 E E1 1 32-pin TSOP 2 (mm) Symbol Min Max A - 1.2 A1 0.05 0.15 b 0.3 0.52 C 0.12 0.21 D 20.82 21.08 E1 10.03 10.29 E 11.56 11.96 N/2 D Seating plane A ZD c A1 b e 1.27 BSC L 0.40 ZD a D e E1 E2 B Pin 1 A A1 c b A2 0 5 c 32-pin SOJ 300 mil/400 mil Seating plane E 32-pin SOJ 300 mil 32-pin SOJ 400 mil Symbol Min Max Min Max A - 0.145 - 0.145 A1 0.025 - 0.025 - A2 0.086 0.105 0.086 0.115 B 0.026 0.032 0.026 0.032 b 0.014 0.020 0.015 0.020 c 0.006 0.013 0.007 0.013 D 0.820 0.830 0.820 0.830 E 0.250 0.275 0.360 0.380 E1 0.292 0.305 0.395 0.405 E2 0.330 0.340 0.435 0.445 e 7/14/03, v.0.0.4 0.95 REF. L 0.60 Alliance Semiconductor 0.050 BSC 0.050 BSC P. 7 of 8 AS7C1025B (R) Ordering Codes Package \ Access time Temperature TSOP 2 Commercial 10 ns 12 ns 15 ns 20 ns AS7C1025B-10HFC AS7C1025B-12HFC AS7C1025B-15HFC AS7C1025B-20HFC AS7C1025B-12HFI AS7C1025B-15HFI AS7C1025B-20HFI AS7C1025B-10TJC AS7C1025B-12TJC AS7C1025B-15TJC AS7C1025B-20TJC AS7C1025B-12TJI AS7C1025B-15TJI AS7C1025B-20TJI AS7C1025B-12JC AS7C1025B-15JC AS7C1025B-20JC AS7C1025B-12JI AS7C1025B-15JI AS7C1025B-20JI Industrial 300-mil SOJ Commercial Industrial 400-mil SOJ Commercial AS7C1025B-10JC Industrial Note: Add suffix `N' to the above part number for LEAD FREE parts. (Ex AS7C1025B-10TJCN) Part numbering system AS7C SRAM prefix 1025B -XX Device number Access time 7/14/03, v.0.0.4 X X X Package: HF = TSOP 2 / 32 pin TJ = SOJ 300 mil J = SOJ 400 mil Temperature range C = commercial, 0 C to 70 C I = industrial, -40 C to 85 C N = LEAD FREE PART Alliance Semiconductor P. 8 of 8 (c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. 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