TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 INTEGRATED IQ DEMODULATOR Check for Samples: TRF371135 FEATURES DESCRIPTION * * The TRF371135 is a highly linear and integrated direct-conversion quadrature demodulator. The TRF371135 integrates balanced I and Q mixers, LO buffers, and phase splitters to convert an RF signal directly to I and Q baseband. The on-chip programmable-gain amplifiers allow adjustment of the output signal level without the need for external variable-gain (attenuator) devices. The TRF371135 integrates programmable baseband low-pass filters that attenuate nearby interference, eliminating the need for an external baseband filter. 1 2 * * * * * * * Frequency Range: 1700 MHz to 6000 MHz Integrated Baseband Programmable-Gain Amplifier On-Chip Programmable Baseband Filter High Out-of-Band IP3: 22 dBm at 3550 MHz High Out-of-Band IP2: 52 dBm at 3550 MHz Hardware and Software Power Down Three-Wire Serial Interface Single Supply: 4.5-V to 5.5-V Operation Silicon Germanium Technology Housed in a 7-mm x 7-mm QFN package, the TRF371135 provides the smallest and most integrated receiver solution available for high-performance equipment. APPLICATIONS * * * * Multicarrier Wireless Infrastructure WiMAX High-Linearity Direct-Downconversion Receiver LTE (Long Term Evolution) To Microcontroller READBACK NC Gain_B1 Gain_B2 NC Gain_B0 MIXIoutn NC STROBE MIXIoutp CLOCK RFin DATA To Microcontroller 48 47 46 45 44 43 42 41 40 39 38 37 36 GNDDIG 1 VCCDIG 2 35 GND CHIP_EN 3 34 BBIoutn VCCMIX1 4 33 BBIoutp VCCBBI To ADC I GND 5 32 GND MIXinp 6 31 LOip MIXinn 7 30 LOin GND 8 29 VCCLO VCCMIX2 9 28 BBQoutp NC 10 27 BBQoutn NC 11 26 LOin TRF371135 NC GND VCCBBQ VCM VCCBIAS GNDBIAS NC REXT NC MIXQoutn GND MIXQoutp GND 25 12 13 14 15 16 17 18 19 20 21 22 23 24 GND GND To ADC Q 30 kW 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010, Texas Instruments Incorporated TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE DEVICE OPTIONS (1) PRODUCT PACKAGE LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKINGS TRF371135 QFN-48 RGZ -40C to 85C TRF371135 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TRF371135IRGZR Tape and reel, 2500 TRF371135IRGZT Tape and reel, 500 MIXIoutn 44 45 MIXIoutp FUNCTIONAL DIAGRAM ADC Driver VCCs PGA 33 BBIoutp 34 BBIoutn 24 VCM 30 LOin 31 LOip 27 BBQoutn 28 BBQoutp 48 CLOCK GND DC Offset Control I 0 MIXinp 6 MIXinn 7 90 DC Offset Control Q PGA ADC Driver CHIP_EN 3 Power Down DC Offset Control 47 LPFADJ Control 46 37 DATA STROBE READBACK Gain_B2 39 40 Gain_B1 41 Gain_B0 17 MIXQoutn MIXQoutp 16 PGA Control Q SPI B0385-01 (1) 2 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 DEVICE INFORMATION PIN ASSIGNMENTS space NC READBACK Gain_B2 Gain_B0 Gain_B1 NC NC MIXIoutn STROBE MIXIoutp DATA CLOCK RGZ PACKAGE QFN-48 (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 36 VCCBBI GNDDIG 1 VCCDIG 2 35 GND CHIP_EN 3 34 BBIoutn VCCMIX1 4 33 BBIoutp GND 5 32 GND MIXinp 6 31 LOip TRF371135 MIXinn 7 30 LOin GND 8 29 VCCLO VCCMIX2 9 28 BBQoutp NC 10 27 BBQoutn NC 11 26 GND VCCBBQ VCM NC GNDBIAS VCCBIAS REXT NC NC MIXQoutn GND MIXQoutp GND 25 12 13 14 15 16 17 18 19 20 21 22 23 24 GND GND PIN FUNCTIONS PIN NO. NAME I/O DESCRIPTION 1 GNDDIG Digital ground 2 VCCDIG 3 CHIP_EN 4 VCCMIX1 5 GND 6 MIXinp I Mixer input: positive terminal 7 MIXinn I Mixer input: negative terminal 8 GND Ground 9 VCCMIX2 Mixer power supply 10 NC No connect 11 NC No connect 12 GND Ground 13 GND Ground 14 GND Ground 15 GND Ground Digital power supply I Chip enable Mixer power supply Ground Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 3 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com PIN FUNCTIONS (continued) PIN NO. 4 NAME I/O DESCRIPTION 16 MIXQoutp O Mixer Q output: positive terminal 17 MIXQoutn O Mixer Q output: negative terminal 18 NC 19 NC 20 REXT 21 VCCBIAS Bias block power supply 22 GNDBIAS Bias block ground 23 NC 24 VCM 25 VCCBBQ 26 GND 27 BBQoutn O Baseband Q (in quadrature) output: negative terminal 28 BBQoutp O Baseband Q (in quadrature) output: positive terminal 29 VCCLO 30 LOin I Local oscillator input: negative terminal 31 LOip I Local oscillator input: positive terminal 32 GND 33 BBIoutp O Baseband I (in-phase) output: positive terminal 34 BBIoutn O Baseband I (in-phase) output: negative terminal 35 GND Ground 36 VCCBBI Baseband I (in phase) power supply 37 NC No connect 38 READBACK O SPI readback data 39 Gain_B2 I PGA fast gain control bit 2 40 Gain_B1 I PGA fast gain control bit 1 41 Gain_B0 I PGA fast gain control bit 0 42 NC 43 NC 44 MIXIoutn O Mixer I output: negative terminal 45 MIXIoutp O Mixer I output: positive terminal 46 STROBE I SPI enable 47 DATA I SPI data input 48 CLOCK I SPI clock input No connect No connect O Reference bias external resistor No connect I Baseband common-mode input voltage Baseband Q chain power supply Ground Local oscillator power supply Ground No connect No connect Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT Supply voltage range (2) -0.3 to 6 V Digital I/O voltage range -0.3 to 6 V Operating free-air temperature range, TA -40 to 85 C Operating virtual junction temperature range, TJ -40 to 150 C Storage temperature range, Tstg -65 to 150 C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VCC Power-supply voltage MIN NOM MAX 4.5 5 5.5 V 940 VPP Power-supply voltage ripple UNIT TA Operating free-air temperature range -40 85 C TJ Operating virtual junction temperature range -40 150 C MAX UNIT THERMAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER (1) TEST CONDITIONS Soldered slug, no airflow RqJA Thermal resistance, junction-to-ambient (1) (2) TYP 26 Soldered slug, 200-LFM airflow 20.1 Soldered slug, 400-LFM airflow 17.4 RqJA (2) RqJB MIN C/W 25 Thermal resistance, junction-to-board 12 C/W Determined using JEDEC standard JESD-51 with high-K board 16 layers, high-K board Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 5 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com ELECTRICAL CHARACTERISTICS VCC = 5 V, LO power = 0 dBm, TA = 25C (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT DC PARAMETERS ICC Total supply current 370 mA Power-down current 2 mA IQ DEMODULATOR AND BASEBAND SECTION fRF Frequency range 1700 Gain range 22 (1) 6000 24 MHz dB Gain step See 1 dB Pinmax Max. RF power input Before damage 25 dBm OIP3 Output third-order intercept point Gain setting = 24 (2) 30 dBVRMS 3 dBVRMS 1 tone (3) P1dBmin Min. output compression point fmin Min. baseband low-pass filter cutoff frequency 1-dB point fmax Max. baseband low-pass filter cutoff frequency 3-dB point (4) fbypass Baseband low-pass filter cutoff frequency in bypass mode 3-dB point (5) (4) 700 15 8 2 x fC 32 3 x fC 54 4 x fC 75 5 x fC Image suppression Vcm Output, common-mode Baseband harmonic level dB 90 fLO = 3550 MHz -35 Output BB attenuator Output load impedance MHz 1 1.5 x fC Baseband relative attenuation at LPF cutoff frequency (fC) (6) MHz 30 1 x fC Fsel kHz dB 3 dB 1 k Parallel capacitance 20 pF Measured at I- and Q-channel baseband outputs 1.5 V -95 dBc -103 dBc Parallel resistance Second harmonic (7) Third harmonic (7) LOCAL OSCILLATOR PARAMETERS Local oscillator frequency 1700 LO input level See (8) LO leakage At MIXinn/p at 0-dBm LO drive level -3 0 6000 MHz 6 dBm -58 dBm DIGITAL INTERFACE VIH High-level input voltage 0.6 x VCC VIL Low-level input voltage 0 VOH High-level output voltage VOL Low-level output voltage (1) (2) (3) (4) (5) (6) (7) (8) 6 5 VCC V 0.8 V 0.8 x VCC V 0.2 x VCC V Two consecutive gain settings Two CW tones at an offset from LO frequency smaller than the baseband-filter cutoff frequency. Performance is set by baseband circuitry regardless of LO frequency. Single CW tone at an offset from LO frequency smaller than the baseband-filter cutoff frequency. Performance is set by baseband circuitry regardless of LO frequency. Baseband low-pass filter cutoff frequency is programmable through SPI register LPFADJ. LPFADJ = 0 corresponds to maximum bandwidth; LPFADJ = 255 corresponds to minimum BW. Filter Ctrl setting equal to 0 Attenuation relative to passband gain LO frequency set to 3.55 GHz. I or Q output power level -6 dBVRMS differential. Gain setting at 24. DC offset calibration engaged. Input signal set at 1-MHz offset. LO power outside of this range is possible but may introduce degraded performance. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 ELECTRICAL CHARACTERISTICS VCC = 5 V, LO power = 0 dBm, TA = 25C (1) (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fLO = 1740 MHz Gmax Maximum gain (2) Gain setting = 24 45 dB NF Noise figure Gain setting = 24 10 dB (3) (4) 19 dBm 60 dBm IIP3 Third-order input intercept point Gain setting = 24 IIP2 Second-order input intercept point Gain setting = 24 (4) (5) Gmax Maximum gain (2) Gain setting = 24 44.3 NF Noise figure Gain setting = 24 10.5 IIP3 Third-order input intercept point Gain setting = 24 (3) (4) 20 dBm IIP2 Second-order input intercept point Gain setting = 24 (4) (5) 57 dBm Gmax Maximum gain (2) Gain setting = 24 44 dB NF Noise figure Gain setting = 24 11 dB (3) (4) fLO = 1950 MHz dB dB fLO = 2025 MHz IIP3 Third-order input intercept point Gain setting = 24 21 dBm IIP2 Second-order input intercept point Gain Setting = 24 (4) (5) 57 dBm Gmax Maximum gain (2) Gain setting = 24 43 dB N3F Noise figure Gain setting = 24 12 IIP3 Third-order input intercept point Gain setting = 24 (3) (4) 23.5 dBm IIP2 Second-order input intercept point Gain setting = 24 (4) (5) 58 dBm Maximum gain (2) Gain setting = 24 40 dB Gain setting = 24 13.8 dB fLO = 2400 MHz dB fLO = 3550 MHz Gmax NF Noise figure Gain setting = 16 15 dB IIP3 Third-order input intercept point Gain setting = 24 (3) (4) 22 dBm IIP2 Second-order input intercept point Gain setting = 24 (4) (5) 52 dBm Gmax Maximum gain (2) Gain setting = 24 37.5 dB NF Noise figure Gain setting = 24 17.5 dB fLO = 5400 MHz (3) (4) 22 dBm 60 dBm IIP3 Third-order input intercept point Gain setting = 24 IIP2 Second-order input intercept point Gain setting = 24 (4) (5) (1) (2) (3) (4) (5) For broadband frequency sweeps, the Picosecond balun (model #5310A) is used at the RF and LO inputs. For the frequency band between 3300 MHz and 3800 MHz, the Johanson 3600BL14M050E balun is used. For the frequency band between 4900 MHz and 5900 MHz the Johanson 5400BL15B050E balun is used. Performance parameters adjusted for balun insertion loss. Recommended baluns for respective frequency bands are shown as follows: 1740 MHz: Murata LDB211G8005C-001 (or equivalent) 1950 MHz: Murata LDB211G9005C-001 (or equivalent) 2025 MHz: Murata LDB211G9005C-001 (or equivalent) 2500 MHz: Murata LDB212G4005C-001 (or equivalent) 3550 MHz: Johanson 3600BL14M050E (or equivalent) 5400 MHz: Johanson 5400BL15B050E (or equivalent) Gain defined as voltage gain from Mixin (VRMS) to either baseband output: BBI/Qout (VRMS) Two CW tones of -30 dBm at fRF1 = fLO (2 x fC) and fRF2 = fLO [(4 x fC) + 100 kHz] (fC = baseband filter 1-dB cutoff frequency). Because the 2-tone interferers are outside of the baseband filter bandwidth, the results are inherently independent of the gain setting. Intermodulation parameters are recorded at maximum gain setting, where measurement accuracy is best. Two CW tones of -30 dBm at fRF1 = fLO (2 x fC) and fRF2 = fLO [(2 x fC) + 100 kHz]; IM2 product measured at 100-kHz output frequency (fC = baseband filter 1-dB cutoff frequency) Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 7 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com TIMING REQUIREMENTS VCC = 5 V, LO power = 0 dBm, TA = 25C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(CLK) Clock period 50 ns t(CH) Clock-signal high time 20 ns t(CL) Clock-signal low time 20 ns tsu1 Setup time, data 10 ns th Hold time, data 10 ns tw Pulse duration, STROBE 20 ns tsu2 Setup time, STROBE 10 ns td Delay time, clock to readback-data output 10 ns tsu1 t(CL) t(CLK) th t(CH) st Register Write CLOCK DATA nd 1 Write CLOCK Pulse 32 Write CLOCK Pulse DB0 (LSB) Address Bit 0 DB1 Address Bit 1 DB3 Address Bit 3 DB2 Address Bit 2 DB30 DB29 READBACK DATA READBACK DATA Bit 30 Bit 29 DB31 (MSB) READBACK DATA Bit 31 tsu2 "End of Write Cycle"Pulse Latch Enable nd CLOCK 32 Write CLOCK Pulse tsu2 READBACK tw st 1 Read CLOCK Pulse nd nd 2 Read CLOCK Pulse rd 32 Read CLOCK Pulse 33 Read CLOCK Pulse tw td STROBE "End of Write Cycle" Pulse READBACK DATA READBACK Data Bit 0 READ BACK Data Bit 1 READ BACK Data Bit 29 READBACK Data Bit 30 READBACK Data Bit 31 T0265-02 Figure 1. Timing Requirements Diagram 8 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 TYPICAL CHARACTERISTICS VCC = 5 V, LO power = 0 dBm, TA = 25C (unless otherwise noted) Table of Graphs Broadband Data (1700-6000 MHz) Gain vs LO frequency (1) Figure 2, Figure 3, Figure 4 Noise figure vs LO frequency (1) Figure 5, Figure 6, Figure 7 (2) (3) (4) IIP3 vs LO frequency IIP2 vs LO frequency (2) (3) (4) Figure 8, Figure 9, Figure 10 Figure 11, Figure 12, Figure 13 3.5G Band Data (3300-3800 MHz) Gain vs LO frequency (5) IIP3 vs LO frequency (3) (4) (5) Figure 17, Figure 18, Figure 19, Figure 20 IIP2 vs LO frequency (3) (4) (5) Figure 21, Figure 22, Figure 23, Figure 24 Noise figure vs LO frequency (5) Figure 25, Figure 26, Figure 27 Gain vs LO frequency (6) Figure 28, Figure 29, Figure 30 IIP3 vs LO frequency (3) (4) (6) Figure 31, Figure 32, Figure 33 IIP2 vs LO frequency (3) (4) (6) Figure 34, Figure 35, Figure 36 Noise figure vs LO frequency (6) Figure 14, Figure 15, Figure 16 5G Band Data (4900-5900 MHz) Figure 37, Figure 38, Figure 39 Baseband-Related Data OIP3 vs Frequency offset (7) Noise figure vs BB gain setting Gain vs BB gain setting Gain vs Frequency offset Figure 46, Figure 47 Gain vs Frequency offset (bypass mode) Figure 48, Figure 49 1-dB LPF corner frequency vs LPFADJ setting Figure 50 Relative LPF group delay Frequency offset (8) Figure 51 Image rejection vs BB frequency offset Figure 52 DC offset limit vs Temperature (9) Figure 53 Out-of-band P1dB vs Relative offset multiplier to corner frequency (10) Figure 54 Figure 40, Figure 41, Figure 42, Figure 43 Figure 44 Figure 45 (1) Measured with broadband Picosecond 5310A balun on the LO input and single-ended connection on the RF input. Performance gain adjusted for the 3-dB differential to single-ended insertion loss. (2) Measured with broadband Picosecond 5310A balun on the LO input and RF input. Balun insertion loss is compensated for in the measurement. (3) Out-of-band intercept point is defined with tones that are at least 2 times farther out than the programmed LPF corner frequency that generates an intermodulation tone that falls inside the LPF passband. (4) Out-of-band intercept point is dependent on the demodulator performance and not the baseband circuitry; the measurement is taken at maximum gain but is valid across all PGA settings. (5) Measured with Johanson 3600BL14M050E balun on the LO input and RF input. All dc-blocking and bypass capacitors are 4.7 pF as listed on the EVM schematic. (6) Measured with Johanson 5400 BL15B050E balun on the LO input and RF input. All dc-blocking and bypass capacitors are 1.8 pF as listed on the EVM schematic. (7) Measured with filter in bypass mode to characterize the pass-band circuitry across baseband frequencies. Tone spacing set to 100 kHz, and tone frequencies are varied from 5/5.1 MHz to 25/25.1 MHz (x-axis of graph). (8) Relative to the low-frequency offset group delay in bypass mode (9) Idet set to 50 A; RF signal is off; LO at 2.4 GHz at 0 dBm; Det filter set to 1 kHz; Div set to 1024. (10) In-band tone set to 1 MHz; out-of-band jammer tone set to specified relative offset ratio from the programmed corner frequency. Jammer tone is increased until in-band tone compresses 1 dB. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 9 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS, BROADBAND DATA (1700 MHz-6000 MHz) VCC = 5 V, LO power = 0 dBm, TA = 25C (unless otherwise noted) GAIN vs LO FREQUENCY GAIN vs LO FREQUENCY 48 48 T A = -40C T A = -10C T A = 25C T A = 85C 46 44 Gain (dB) Gain (dB) 44 42 40 VCC = 4.5V VCC = 5V VCC = 5.5V 46 38 42 40 38 36 36 See Note 1 See Note 1 34 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 LO Frequency (MHz) G002 34 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 LO Frequency (MHz) G001 Figure 2. Figure 3. GAIN vs LO FREQUENCY NOISE FIGURE vs LO FREQUENCY 20 48 LO Pwr = -3dBm LO Pwr = 0dBm LO Pwr = 3dBm LO Pwr = 6dBm 46 Noise Figure (dB) Gain (dB) 44 18 42 40 38 T A = -40C T A = -10C T A = 25C T A = 85C 16 14 12 10 36 See Note 1 34 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 LO Frequency (MHz) G003 See Note 1 8 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 LO Frequency (MHz) G004 Figure 4. Figure 5. NOISE FIGURE vs LO FREQUENCY NOISE FIGURE vs LO FREQUENCY 20 VCC = 4.5V VCC = 5 V VCC = 5.5V 18 Noise Figure (dB) Noise Figure (dB) 18 20 16 14 12 10 LO Pwr = -3dBm LO Pwr = 0dBm LO Pwr = 3dBm LO Pwr = 6dBm 16 14 12 10 See Note 1 8 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 LO Frequency (MHz) G005 See Note 1 8 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 LO Frequency (MHz) G006 Figure 6. 10 Figure 7. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 TYPICAL CHARACTERISTICS, BROADBAND DATA (1700 MHz-6000 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C (unless otherwise noted) IIP3 vs LO FREQUENCY W I 34 32 30 TA = -40C TA = -10C TA = 25C TA = 85C IIP3 (dBm) 28 26 24 22 20 18 16 14 1500 500 2000 2000 2500 2500 3000 3000 3500 3500 4000 4000 4500 4500 5000 5000 5500 5500 6000 6000 Q 34 32 30 IIP3 (dBm) 28 26 24 22 20 18 16 See Notes 2, 3 and 4 14 1500 2000 2500 3000 3500 4000 LO Frequency (MHz) 4500 5000 5500 6000 G007 Figure 8. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 11 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS, BROADBAND DATA (1700 MHz-6000 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C (unless otherwise noted) IIP3 vs LO FREQUENCY W I 32 30 VCC = 4.5V VCC = 5V VCC = 5.5V 28 IIP3 (dBm) 26 24 22 20 18 16 14 1500 500 2000 2000 2500 2500 3000 3000 3500 3500 4000 4000 4500 4500 5000 5000 5500 5500 6000 6000 Q 32 30 28 IIP3 (dBm) 26 24 22 20 18 16 See Notes 2, 3 and 4 14 1500 2000 2500 3000 3500 4000 LO Frequency (MHz) 4500 5000 5500 6000 G008 Figure 9. 12 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 TYPICAL CHARACTERISTICS, BROADBAND DATA (1700 MHz-6000 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C (unless otherwise noted) IIP3 vs LO FREQUENCY W I 34 32 30 LO Pwr = -3dB LO Pwr = 0dB LO Pwr = 3dB LO Pwr = 6dB 28 IIP3 (dBm) 26 24 22 20 18 16 14 12 1500 500 2000 2000 2500 2500 3000 3000 3500 3500 4000 4000 4500 4500 5000 5000 5500 5500 6000 6000 Q 34 32 30 28 IIP3 (dBm) 26 24 22 20 18 16 14 See Notes 2, 3 and 4 12 1500 2000 2500 3000 3500 4000 LO Frequency (MHz) 4500 5000 5500 6000 G009 Figure 10. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 13 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS, BROADBAND DATA (1700 MHz-6000 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C (unless otherwise noted) IIP2 vs LO FREQUENCY W I 100 90 TA = -40C TA = -10C TA = 25C TA = 85C IIP2 (dBm) 80 70 60 50 40 1500 500 2000 2000 2500 2500 3000 3000 3500 3500 4000 4000 4500 4500 5000 5000 5500 5500 6000 6000 Q 100 90 IIP2 (dBm) 80 70 60 50 See Notes 2, 3 and 4 40 1500 2000 2500 3000 3500 4000 LO Frequency (MHz) 4500 5000 5500 6000 G010 Figure 11. 14 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 TYPICAL CHARACTERISTICS, BROADBAND DATA (1700 MHz-6000 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C (unless otherwise noted) IIP2 vs LO FREQUENCY W I 100 90 VCC = 4.5V VCC = 5V VCC = 5.5V IIP2 (dBm) 80 70 60 50 40 1500 500 2000 2000 2500 2500 3000 3000 3500 3500 4000 4000 4500 4500 5000 5000 5500 5500 6000 6000 Q 100 90 IIP2 (dBm) 80 70 60 50 See Notes 2, 3 and 4 40 1500 2000 2500 3000 3500 4000 LO Frequency (MHz) 4500 5000 5500 6000 G011 Figure 12. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 15 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS, BROADBAND DATA (1700 MHz-6000 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C (unless otherwise noted) IIP2 vs LO FREQUENCY W I 100 LO Pwr = -3dB LO Pwr = 0dB LO Pwr = 3dB LO Pwr = 6dB 90 IIP2 (dBm) 80 70 60 50 40 30 1500 500 2000 2000 2500 2500 3000 3000 3500 3500 4000 4000 4500 4500 5000 5000 5500 5500 6000 6000 Q 100 90 IIP2 (dBm) 80 70 60 50 See Notes 2, 3 and 4 40 1500 2000 2500 3000 3500 4000 LO Frequency (MHz) 4500 5000 5500 6000 G012 Figure 13. 16 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 TYPICAL CHARACTERISTICS, 3.5G BAND DATA (3300 MHz-3800 MHz) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 3600BL14M050E (unless otherwise noted) GAIN vs LO FREQUENCY GAIN vs LO FREQUENCY 44 44 T A = -40C T A = -10C T A = 25C T A = 85C 43 42 41 Gain (dB) Gain (dB) 42 VCC = 4.5V VCC = 5V VCC = 5.5V 43 40 39 38 41 40 39 38 37 37 See Note 5 36 3300 3400 3500 3600 LO Frequency (MHz) 3700 3800 See Note 5 36 3300 3400 3500 3600 LO Frequency (MHz) G013 Figure 14. 3700 3800 G014 Figure 15. GAIN vs LO FREQUENCY 44 LO Pwr = -3dBm LO Pwr = 0dBm LO Pwr = 3dBm LO Pwr = 6dBm 43 Gain (dB) 42 41 40 39 38 37 See Note 5 36 3300 3400 3500 3600 LO Frequency (MHz) 3700 3800 G015 Figure 16. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 17 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS, 3.5G BAND DATA (3300 MHz-3800 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 3600BL14M050E (unless otherwise noted) IIP3 vs LO FREQUENCY W I 30 28 TA = -40C TA = -10C TA = 25C TA = 85C IIP3 (dBm) 26 24 22 20 18 16 3300 330 3400 3400 3500 3500 3600 3600 3700 3700 3800 3800 3500 3600 LO Frequency (MHz) 3700 3800 Q 30 28 IIP3 (dBm) 26 24 22 20 18 See Notes 3, 4 and 5 16 3300 3400 G016 Figure 17. 18 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 TYPICAL CHARACTERISTICS, 3.5G BAND DATA (3300 MHz-3800 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 3600BL14M050E (unless otherwise noted) IIP3 vs LO FREQUENCY W I 30 28 VCC = 4.5V VCC = 5V VCC = 5.5V IIP3 (dBm) 26 24 22 20 18 16 3300 330 3400 3400 3500 3500 3600 3600 3700 3700 3800 3800 3500 3600 LO Frequency (MHz) 3700 3800 Q 30 28 IIP3 (dBm) 26 24 22 20 18 See Notes 3, 4 and 5 16 3300 3400 G017 Figure 18. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 19 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS, 3.5G BAND DATA (3300 MHz-3800 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 3600BL14M050E (unless otherwise noted) IIP3 vs LO FREQUENCY W I 30 28 LO Pwr = -3dB LO Pwr = 0dB LO Pwr = 3dB LO Pwr = 6dB IIP3 (dBm) 26 24 22 20 18 16 3300 330 3400 3400 3500 3500 3600 3600 3700 3700 3800 3800 3500 3600 LO Frequency (MHz) 3700 3800 Q 30 28 IIP3 (dBm) 26 24 22 20 18 See Notes 3, 4 and 5 16 3300 3400 G018 Figure 19. 20 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 TYPICAL CHARACTERISTICS, 3.5G BAND DATA (3300 MHz-3800 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 3600BL14M050E (unless otherwise noted) IIP3 vs LO FREQUENCY W I 30 28 LPFADJ = 0 LPFADJ = 25 LPFADJ = 85 LPFADJ = 142 IIP3 (dBm) 26 24 22 20 18 16 3300 330 3400 3400 3500 3500 3600 3600 3700 3700 3800 3800 3500 3600 LO Frequency (MHz) 3700 3800 Q 30 28 IIP3 (dBm) 26 24 22 20 18 See Notes 3, 4 and 5 16 3300 3400 G019 Figure 20. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 21 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS, 3.5G BAND DATA (3300 MHz-3800 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 3600BL14M050E (unless otherwise noted) IIP2 vs LO FREQUENCY W I 100 90 TA = -40C TA = -10C TA = 25C TA = 85C IIP2 (dBm) 80 70 60 50 40 3300 330 3400 3400 3500 3500 3600 3600 3700 3700 3800 3800 3500 3600 LO Frequency (MHz) 3700 3800 Q 100 90 IIP2 (dBm) 80 70 60 50 See Notes 3, 4 and 5 40 3300 3400 G020 Figure 21. 22 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 TYPICAL CHARACTERISTICS, 3.5G BAND DATA (3300 MHz-3800 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 3600BL14M050E (unless otherwise noted) IIP2 vs LO FREQUENCY W I 100 90 VCC = 4.5V VCC = 5V VCC = 5.5V IIP2 (dBm) 80 70 60 50 40 3300 330 3400 3400 3500 3500 3600 3600 3700 3700 3800 3800 3500 3600 LO Frequency (MHz) 3700 3800 Q 100 90 IIP2 (dBm) 80 70 60 50 See Notes 3, 4 and 5 40 3300 3400 G021 Figure 22. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 23 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS, 3.5G BAND DATA (3300 MHz-3800 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 3600BL14M050E (unless otherwise noted) IIP2 vs LO FREQUENCY W I 100 90 LO Pwr = -3dB LO Pwr = 0dB LO Pwr = 3dB LO Pwr = 6dB IIP2 (dBm) 80 70 60 50 40 3300 330 3400 3400 3500 3500 3600 3600 3700 3700 3800 3800 3500 3600 LO Frequency (MHz) 3700 3800 Q 100 90 IIP2 (dBm) 80 70 60 50 See Notes 3, 4 and 5 40 3300 3400 G022 Figure 23. 24 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 TYPICAL CHARACTERISTICS, 3.5G BAND DATA (3300 MHz-3800 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 3600BL14M050E (unless otherwise noted) IIP2 vs LO FREQUENCY W I 100 90 LPFADJ = 0 LPFADJ = 25 LPFADJ = 85 LPFADJ = 142 IIP2 (dBm) 80 70 60 50 40 3300 330 3400 3400 3500 3500 3600 3600 3700 3700 3800 3800 3500 3600 LO Frequency (MHz) 3700 3800 Q 100 90 IIP2 (dBm) 80 70 60 50 See Notes 3, 4 and 5 40 3300 3400 G023 Figure 24. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 25 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS, 3.5G BAND DATA (3300 MHz-3800 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 3600BL14M050E (unless otherwise noted) NOISE FIGURE vs LO FREQUENCY NOISE FIGURE vs LO FREQUENCY 20 19 T A = -40C T A = -10C T A = 25C T A = 85C 19 18 17 Noise Figure (dB) Noise Figure (dB) 18 20 16 15 14 13 12 17 16 15 14 13 12 11 10 3300 VCC = 4.5V VCC = 5 V VCC = 5.5V 11 See Note 5 3400 3500 3600 LO Frequency (MHz) 3700 3800 See Note 5 10 3300 3400 3500 3600 LO Frequency (MHz) G026 Figure 25. 3700 3800 G027 Figure 26. NOISE FIGURE vs LO FREQUENCY 20 19 Noise Figure (dB) 18 LO Pwr = -3dBm LO Pwr = 0dBm LO Pwr = 3dBm LO Pwr = 6dBm 17 16 15 14 13 12 11 10 3300 See Note 5 3400 3500 3600 LO Frequency (MHz) 3700 3800 G028 Figure 27. 26 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 TYPICAL CHARACTERISTICS, 5G BAND DATA (4900 MHz-5900 MHz) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 5400BL15B050E (unless otherwise noted) GAIN vs LO FREQUENCY GAIN vs LO FREQUENCY 42 42 T A = -40C T A = -10C T A = 25C T A = 85C 41 40 39 Gain (dB) Gain (dB) 40 VCC = 4.5V VCC = 5V VCC = 5.5V 41 38 37 36 39 38 37 36 35 35 See Note 6 34 4900 5100 5300 5500 LO Frequency (MHz) 5700 5900 See Note 6 34 4900 5100 5300 5500 LO Frequency (MHz) G044 Figure 28. 5700 5900 G045 Figure 29. GAIN vs LO FREQUENCY 42 LO Pwr = -3dBm LO Pwr = 0dBm LO Pwr = 3dBm LO Pwr = 3dBm 41 Gain (dB) 40 39 38 37 36 35 See Note 6 34 4900 5100 5300 5500 LO Frequency (MHz) 5700 5900 G046 Figure 30. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 27 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS, 5G BAND DATA (4900 MHz-5900 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 5400BL15B050E (unless otherwise noted) IIP3 vs LO FREQUENCY W I 30 28 TA = -40C TA = -10C TA = 25C TA = 85C IIP3 (dBm) 26 24 22 20 18 4900 490 5000 5000 5100 5100 5200 5200 5300 5300 5400 5400 Q 5500 5500 5600 5600 5700 5700 5800 5800 5900 5900 See Notes 3, 4 and 6 18 4900 5000 5100 5200 5300 5400 5500 LO Frequency (MHz) 5600 5700 5800 5900 30 28 IIP3 (dBm) 26 24 22 20 G047 Figure 31. 28 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 TYPICAL CHARACTERISTICS, 5G BAND DATA (4900 MHz-5900 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 5400BL15B050E (unless otherwise noted) IIP3 vs LO FREQUENCY W I 30 28 VCC = 4.5V VCC = 5V VCC = 5.5V IIP3 (dBm) 26 24 22 20 18 4900 490 5000 5000 5100 5100 5200 5200 5300 5300 5400 5400 Q 5500 5500 5600 5600 5700 5700 5800 5800 5900 5900 See Notes 3, 4 and 6 18 4900 5000 5100 5200 5300 5400 5500 LO Frequency (MHz) 5600 5700 5800 5900 30 28 IIP3 (dBm) 26 24 22 20 G048 Figure 32. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 29 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS, 5G BAND DATA (4900 MHz-5900 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 5400BL15B050E (unless otherwise noted) IIP3 vs LO FREQUENCY W I 30 28 LO Pwr = -3dB LO Pwr = 0dB LO Pwr = 3dB LO Pwr = 6dB IIP3 (dBm) 26 24 22 20 18 4900 490 5000 5000 5100 5100 5200 5200 5300 5300 5400 5400 Q 5500 5500 5600 5600 5700 5700 5800 5800 5900 5900 See Notes 3, 4 and 6 18 4900 5000 5100 5200 5300 5400 5500 LO Frequency (MHz) 5600 5700 5800 5900 30 28 IIP3 (dBm) 26 24 22 20 G049 Figure 33. 30 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 TYPICAL CHARACTERISTICS, 5G BAND DATA (4900 MHz-5900 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 5400BL15B050E (unless otherwise noted) IIP2 vs LO FREQUENCY W I 90 IIP2 (dBm) 80 TA = -40C TA = -10C TA = 25C TA = 85C 70 60 50 40 4900 490 5000 5000 5100 5100 5200 5200 5300 5300 5400 5400 Q 5500 5500 5600 5600 5700 5700 5800 5800 5900 5900 See Notes 3, 4 and 6 40 4900 5000 5100 5200 5300 5400 5500 LO Frequency (MHz) 5600 5700 5800 5900 90 IIP2 (dBm) 80 70 60 50 G050 Figure 34. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 31 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS, 5G BAND DATA (4900 MHz-5900 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 5400BL15B050E (unless otherwise noted) IIP2 vs LO FREQUENCY W I 90 VCC = 4.5V VCC = 5V VCC = 5.5V IIP2 (dBm) 80 70 60 50 40 4900 490 5000 5000 5100 5100 5200 5200 5300 5300 5400 5400 Q 5500 5500 5600 5600 5700 5700 5800 5800 5900 5900 See Notes 3, 4 and 6 40 4900 5000 5100 5200 5300 5400 5500 LO Frequency (MHz) 5600 5700 5800 5900 90 IIP2 (dBm) 80 70 60 50 G051 Figure 35. 32 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 TYPICAL CHARACTERISTICS, 5G BAND DATA (4900 MHz-5900 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 5400BL15B050E (unless otherwise noted) IIP2 vs LO FREQUENCY W I 90 IIP2 (dBm) 80 LO Pwr = -3dB LO Pwr = 0dB LO Pwr = 3dB LO Pwr = 6dB 70 60 50 40 4900 490 5000 5000 5100 5100 5200 5200 5300 5300 5400 5400 Q 5500 5500 5600 5600 5700 5700 5800 5800 5900 5900 See Notes 3, 4 and 6 40 4900 5000 5100 5200 5300 5400 5500 LO Frequency (MHz) 5600 5700 5800 5900 90 IIP2 (dBm) 80 70 60 50 G052 Figure 36. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 33 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS, 5G BAND DATA (4900 MHz-5900 MHz) (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, balun = Johanson 5400BL15B050E (unless otherwise noted) NOISE FIGURE vs LO FREQUENCY NOISE FIGURE vs LO FREQUENCY 20 T A = -40C T A = -10C T A = 25C T A = 85C 19 Noise Figure (dB) Noise Figure (dB) 19 20 18 17 16 15 VCC = 4.5V VCC = 5 V VCC = 5.5V 18 17 16 15 See Note 6 14 4900 5100 5300 5500 LO Frequency (MHz) 5700 See Note 6 5900 14 4900 5100 5300 5500 LO Frequency (MHz) G053 Figure 37. 5700 5900 G054 Figure 38. NOISE FIGURE vs LO FREQUENCY 20 Noise Figure (dB) 19 LO Pwr = -3dBm LO Pwr = 0dBm LO Pwr = 3dBm LO Pwr = 6dBm 18 17 16 15 See Note 6 14 4900 5100 5300 5500 LO Frequency (MHz) 5700 5900 G055 Figure 39. 34 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 TYPICAL CHARACTERISTICS, BASEBAND-RELATED DATA VCC = 5 V, LO power = 0 dBm, TA = 25C, independent of balun used (unless otherwise noted) OIP3 vs FREQUENCY OFFSET OIP3 vs FREQUENCY OFFSET 52 52 T A = -40C T A = 25C T A = 85C 50 48 46 OIP3 (dBVrms) OIP3 (dBVrms) 48 44 42 40 46 44 42 40 38 38 36 36 34 VCC = 4.5V VCC = 5V VCC = 5.5V 50 34 See Note 7 32 See Note 7 32 0 5 10 15 Frequency Offset (MHz) 20 25 0 5 10 15 Frequency Offset (MHz) G029 Figure 40. OIP3 vs FREQUENCY OFFSET G030 OIP3 vs FREQUENCY OFFSET 50 BB Gain = 12dB BB Gain = 16dB BB Gain = 20dB BB Gain = 24dB 48 46 3dB Attn On 3dB Attn Off 48 46 44 OIP3 (dBVrms) OIP3 (dBVrms) 25 Figure 41. 50 42 40 38 36 44 42 40 38 36 34 34 See Note 7 See Note 7 32 32 0 5 10 15 Frequency Offset (MHz) 20 25 0 5 10 15 Frequency Offset (MHz) G031 Figure 42. 20 25 G032 Figure 43. NOISE FIGURE vs BB GAIN SETTING GAIN vs BB GAIN SETTING 28 43 3dB Attn On 3dB Attn Off 3dB Attn On 3dB Attn Off 40 25 37 34 22 Gain (dB) Noise Figure (dB) 20 19 31 28 25 22 16 19 16 13 13 0 2 4 6 8 10 12 14 16 BB Gain Setting 18 20 22 24 0 2 G033 Figure 44. 4 6 8 10 12 14 16 BB Gain Setting 18 20 22 24 G034 Figure 45. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 35 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS, BASEBAND-RELATED DATA (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, independent of balun used (unless otherwise noted) GAIN vs FREQUENCY OFFSET GAIN vs FREQUENCY OFFSET 20 5 LPFADJ = 0 LPFADJ = 25 LPFADJ = 85 LPFADJ = 142 4 0 3 2 Gain (dB) Gain (dB) -20 -40 -60 -80 1 0 -1 -2 LPFADJ = 0 LPFADJ = 25 LPFADJ = 85 LPFADJ = 142 -100 0.1 -3 -4 1 10 Frequency Offset (MHz) -5 0.1 100 1 10 Frequency Offset (MHz) G035 Figure 46. GAIN vs FREQUENCY OFFSET GAIN vs FREQUENCY OFFSET 5 Filter Ctrl 0 Filter Ctrl 1 Filter Ctrl 2 Filter Ctrl 3 4 0 3 2 Gain (dB) Gain (dB) -20 -40 -60 1 0 -1 -2 Filter Ctrl 0 Filter Ctrl 1 Filter Ctrl 2 Filter Ctrl 3 -100 0.1 1 -3 -4 10 100 Frequency Offset (MHz) -5 0.1 1000 1 10 Frequency Offset (MHz) G037 Figure 48. Bypass Mode 1-dB LPF CORNER FREQUENCY vs LPFADJ SETTING G038 RELATIVE LPF GROUP DELAY vs FREQUENCY OFFSET 500 See Note 8 14 Relative LPF Group Delay (ns) 1-dB LPF Corner Frequency (MHz) 100 Figure 49. Bypass Mode 16 12 10 8 6 4 2 0 0 50 100 150 LPFADJ Setting 200 250 Bypass LPFADJ = 0 LPFADJ = 25 LPFADJ = 85 LPFADJ = 142 400 300 200 100 0 -100 0.1 G039 Figure 50. 36 G036 Figure 47. 20 -80 100 1 10 Frequency Offset (MHz) 100 G040 Figure 51. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 TYPICAL CHARACTERISTICS, BASEBAND-RELATED DATA (continued) VCC = 5 V, LO power = 0 dBm, TA = 25C, independent of balun used (unless otherwise noted) IMAGE REJECTION vs BB FREQUENCY OFFSET DC OFFSET LIMIT vs TEMPERATURE 0 60 See Note 9 40 DC Offset Limit (mV) Image Rejection (dB) -10 -20 -30 -40 -50 -60 -25 20 0 -20 -40 -20 -15 -10 -5 0 5 10 BB Frequency Offset (MHz) 15 20 -60 -45 -35 -25 -15 -5 25 G041 5 15 25 35 45 55 65 75 85 Temperature (C) G042 Figure 52. Figure 53. OUT-OF-BAND P1dB vs REL OFFSET MULTIPLIER to CORNER FREQUENCY 15 LPFADJ = 0 LPFADJ = 25 LPFADJ = 85 LPFADJ = 142 Out-of-Band P1dB (dBm) 10 5 0 -5 -10 -15 -20 See Note 10 -25 0 0.5 1 1.5 2 2.5 3 3.5 4 Relative Offset Multiplier to Corner Frequency 4.5 G043 Figure 54. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 37 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com SERIAL INTERFACE PROGRAMMING REGISTERS DEFINITION The TRF371135 features a three-wire serial programming interface (SPI) that controls an internal 32-bit shift register. There are three signals that must be applied: CLOCK (pin 48), serial DATA (pin 47), and STROBE (pin 46). DATA (DB0-DB31) is loaded LSB-first and is read on the rising edge of CLOCK. STROBE is asynchronous to CLOCK, and at its rising edge the data in the shift register is loaded into the selected internal register. The first two bits (DB0-DB1) are the address to select the available internal registers. READBACK Mode The TRF371135 implements the capability to read back the content of the serial programming interface registers. In addition, it is possible to read back the status of the internal DAC registers that are automatically set after an auto dc-offset calibration. Each readback is consists of two phases: writing followed by the actual reading of the internal data (refer to timing diagram in Figure 55). During the writing phase, a command is sent to the TRF371135 to set it in readback mode and to specify which register is to be read. In the proper reading phase, at each rising clock edge, the internal data is transferred into the READBACK pin and can be read at the following falling edge (LSB first). The first clock after LE goes high (end of writing cycle) is idle, and the following 32 clock pulses transfer the internal register content to the READBACK pin. tsu1 t(CL) t(CLK) th t(CH) st Register Write CLOCK DATA nd 1 Write CLOCK Pulse 32 Write CLOCK Pulse DB0 (LSB) Address Bit 0 DB1 Address Bit 1 DB3 Address Bit 3 DB2 Address Bit 2 DB30 DB29 READBACK DATA READBACK DATA Bit 30 Bit 29 DB31 (MSB) READBACK DATA Bit 31 tsu2 "End of Write Cycle"Pulse Latch Enable nd CLOCK 32 Write CLOCK Pulse tsu2 READBACK tw st 1 Read CLOCK Pulse nd nd 2 Read CLOCK Pulse rd 32 Read CLOCK Pulse 33 Read CLOCK Pulse tw td STROBE "End of Write Cycle" Pulse READBACK Data Bit 0 READBACK DATA READ BACK Data Bit 1 READ BACK Data Bit 29 READBACK Data Bit 30 READBACK Data Bit 31 T0265-02 Figure 55. Serial Programming Timing Diagram 38 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 Table 1. Register Summary (1) Bit # Reg 1 Reg 2 ADDR<0,2> ADDR<0,2> Bit # Bit0 Bit1 Bit2 Bit3 ADDR<3,4> ADDR<3,4> Bit5 PWD_MIX EN_AUTOCAL Bit6 NU Bit6 Bit7 PWD_BUF Bit7 Bit8 PWD_FILT Bit8 Bit9 NU Bit9 Bit10 PWD_DC_OFF_DIG Bit11 NU Bit4 Bit4 ADDR<0,2> ADDR<0,2> IDAC_BIT<0,7> Bit13 Bit14 BBGAIN_<0,4> Bit14 Bit15 Bit15 Bit16 Bit16 Bit17 QDAC_BIT<0,7> Bit18 Bit19 Bit21 Bit22 IDET_B<0,1> Bit23 Bit24 CAL_SEL MIX_GM_TRIM<0,1> ILOAD_a<0,5> EN_FLT_B<0,1> Bit27 EN_FASTGAIN Bit28 GAIN_SEL Bit29 OSC_TEST Bit30 NU Bit31 EN 3dB Attn MIX_LO_TRIM<0,1> LO_TRIM<0,1> MIX_BUFF_TRIM<0,1> ILOAD_b<0,5> FLTR_TRIM<0,1> OUT_BUFF_TRIM<0,1> Cal_clk_sel Bit8 Bit9 Bit10 Bit11 Bit13 Bit14 Bit15 Bit16 Bit21 Bit22 Bit22 Bit23 Bit23 Bit26 Bit25 QLOAD_b<0,5> Bit26 Bit27 Bit28 Bit28 Bit31 DC_OFFSET_Q<0,7> Bit24 Bit27 Bit30 NU Bit12 Bit21 Bit29 Osc_trim<0,2> Bit7 Bit20 NU ID<0,1> Bit6 Bit19 Bit24 Clk_div_ratio<0,2> Bit5 Bit18 QLOAD_a<0,5> ADDR<3,4> Bit4 Bit17 Bit25 ADDR<0,2> Bit3 Bit18 Bit20 LPFADJ_<0,7> ADDR<3,4> Bit17 Bit19 Bit20 ADDR<3,4> Bit11 Bit13 Bit1 Bit2 Bit10 Bit12 Reg 0 Bit0 Bit5 Bit12 (1) Bit # Bit2 Bit3 Bit26 Reg 5 Bit0 Bit1 Bit25 Reg 3 Bypass DC_OFFSET_I<0,7> Bit29 Bit30 Fltr Ctrl_b<0,1> Bit31 Register 4 is not used. Table 2. Register 1 Device Setup REGISTER 1 NAME RESET VALUE WORKING DESCRIPTION Bit0 ADDR<0> 1 Bit1 ADDR<1> 0 Bit2 ADDR<2> 0 Bit3 ADDR<3> 1 Bit4 ADDR<4> 0 Bit5 PWD_MIX 0 Mixer power down (Off = 1) Bit6 NU 0 Not used Bit7 PWD_BUF 1 Mixer out test buffer power down (Off = 1) Bit8 PWD_FILT 0 Baseband filter power down (Off = 1) Bit9 NU 0 Not used Bit10 PWD_DC_OFF_DIG 1 DC offset calibration power down (Off = 1) Register address SPI bank address Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 39 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com Table 2. Register 1 Device Setup (continued) REGISTER 1 NAME RESET VALUE WORKING DESCRIPTION Bit11 NU 1 Bit12 BBGAIN_0 1 Bit13 BBGAIN_1 1 Bit14 BBGAIN_2 1 Bit15 BBGAIN_3 1 Bit16 BBGAIN_4 0 Bit17 LPFADJ_0 0 Bit18 LPFADJ_1 0 Bit19 LPFADJ_2 0 Bit20 LPFADJ_3 0 Bit21 LPFADJ_4 0 Bit22 LPFADJ_5 0 Bit23 LPFADJ_6 0 Bit24 LPFADJ_7 1 Bit25 EN_FLT_B0 0 Bit26 EN_FLT_B1 0 Selects dc offset detector filter bandwidth. Setting {00, 01, 11} = {10 MHz, 10 kHz, 1 kHz} Bit27 EN_FASTGAIN 0 Enable external fast-gain control Bit28 GAIN_SEL 0 Fast-gain control multiplier bit (x2 = 1) Bit29 OSC_TEST 0 Enables OSC out on readback pin if = 1 Bit30 NU 0 Not used Bit31 EN 3dB Attn 0 Enables output 3-dB attenuator Not used Baseband gain setting. Default = 15. Range is from 0 (minimum gain setting) to 24 (maximum gain setting). See the Application Information section for more information on gain setting and fast gain control options. Sets programmable low-pass filter corner frequency. Range = 255 (lowest corner frequency) to 0 (highest corner frequency). Default value is 128. EN_FLT_B0/1: These bits control the bandwidth of the detector used to measure the dc offset during the automatic calibration. There is an RC filter in front of the detector that can be fully bypassed. EN_FLT_B0 controls the resistor (bypass = 1), while EN_FLT_B1 controls the capacitor (bypass = 1). The typical 3-dB cutoff frequencies of the detector bandwidth are summarized in the following table (see the Application Information section for more detail on the dc offset calibration and the detector bandwidth). EN_FLT_B1 EN_FLT_B0 TYPICAL 3-dB CUTOFF FREQ X 0 10 MHz NOTES Maximum bandwidth, bypass R, C 0 1 10 kHz Enable R 1 1 1 kHz Minimum bandwidth, enable R, C Table 3. Register 2 Device Setup 40 REGISTER 2 NAME RESET VALUE Bit0 ADDR<0> 0 Bit1 ADDR<1> 1 Bit2 ADDR<2> 0 Bit3 ADDR<3> 1 Bit4 ADDR<4> 0 Bit5 EN_AUTOCAL 0 WORKING DESCRIPTION Register address SPI bank address Enable autocal when = 1; reset to 0 when done. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 Table 3. Register 2 Device Setup (continued) REGISTER 2 NAME RESET VALUE Bit6 IDAC_BIT0 0 Bit7 IDAC_BIT1 0 Bit8 IDAC_BIT2 0 WORKING DESCRIPTION Bit9 IDAC_BIT3 0 Bit10 IDAC_BIT4 0 Bit11 IDAC_BIT5 0 Bit12 IDAC_BIT6 0 Bit13 IDAC_BIT7 1 Bit14 QDAC_BIT0 0 Bit15 QDAC_BIT1 0 Bit16 QDAC_BIT2 0 Bit17 QDAC_BIT3 0 Bit18 QDAC_BIT4 0 Bit19 QDAC_BIT5 0 Bit20 QDAC_BIT6 0 Bit21 QDAC_BIT7 1 Bit22 IDET_B0 1 Bit23 IDET_B1 1 Set reference current for digital calibration; Settings {00 to 11} = {50 A to 200 A}. Setting 00 = highest resolution. Bit24 CAL_SEL 1 DC offset calibration select. 0 = manual cal; 1 = autocal. Bit25 Clk_div_ratio<0> 0 Bit26 Clk_div_ratio<1> 0 Bit27 Clk_div_ratio<2> 0 Bit28 Cal_clk_sel 1 Bit29 Osc_trim<0> 1 Bit30 Osc_trim<1> 1 Bit31 Osc_trim<2> 0 I-DAC bits to be set during manual dc offset cal Q-DAC bits to be set during manual dc offset cal Clk divider ratio. Setting {000 to 111} = {1, 8, 16, 128, 256, 1024, 2048, 16,684}. A higher div ratio (slower clk) improves cal accuracy and reduces speed. Select internal oscillator when 1, SPI clk when 0 Internal oscillator frequency trimming; setting {000} = ~300 kHz; Setting {111} = ~1.8 MHz. Nominal setting {110} = ~900 kHz. Table 4. Register 3 Device Setup REGISTER 3 NAME RESET VALUE Bit0 ADDR<0> 1 Bit1 ADDR<1> 1 Bit2 ADDR<2> 0 Bit3 ADDR<3> 1 Bit4 ADDR<4> 0 Bit5 ILOAD_a<0> 0 Bit6 ILOAD_a<1> 0 Bit7 ILOAD_a<2> 0 Bit8 ILOAD_a<3> 0 Bit9 ILOAD_a<4> 0 Bit10 ILOAD_a<5> 0 Bit11 ILOAD_b<0> 0 Bit12 ILOAD_b<1> 0 Bit13 ILOAD_b<2> 0 Bit14 ILOAD_b<3> 0 Bit15 ILOAD_b<4> 0 Bit16 ILOAD_b<5> 0 WORKING DESCRIPTION Register address SPI bank address I mixer offset side A I mixer offset side B Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 41 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com Table 4. Register 3 Device Setup (continued) REGISTER 3 NAME RESET VALUE WORKING DESCRIPTION Bit17 QLOAD_a<0> 0 Bit18 QLOAD_a<1> 0 Bit19 QLOAD_a<2> 0 Bit20 QLOAD_a<3> 0 Bit21 QLOAD_a<4> 0 Bit22 QLOAD_a<5> 0 Bit23 QLOAD_b<0> 0 Bit24 QLOAD_b<1> 0 Bit25 QLOAD_b<2> 0 Bit26 QLOAD_b<3> 0 Bit27 QLOAD_b<4> 0 Bit28 QLOAD_b<5> 0 Bit29 Bypass 0 Engage filter bypass Bit30 Fltr Ctrl_b<0> 1 Bit31 Fltr Ctrl_b<1> 0 Used to adjust for filter peaking response; set to 0 in bypass mode, 1 otherwise Q mixer offset side A Q mixer offset side B I/Q Mixer Load A/B: These bits adjust the load on the mixer output. All values should be 0. No modification is necessary. Register 4: No programming required for register 4 Table 5. Register 5 Device Setup 42 REGISTER 5 NAME RESET VALUE Bit0 ADDR<0> 1 Bit1 ADDR<1> 0 Bit2 ADDR<2> 1 Bit3 ADDR<3> 1 Bit4 ADDR<4> 0 Bit5 MIX_GM_TRIM<0> 1 Bit6 MIX_GM_TRIM<1> 0 Bit7 MIX_LO_TRIM<0> 1 Bit8 MIX_LO_TRIM<1> 0 Bit9 LO_TRIM<0> 1 Bit10 LO_TRIM<1> 0 Bit11 MIX_BUFF_TRIM<0> 1 Bit12 MIX_BUFF_TRIM<1> 0 Bit13 FLTR_TRIM<0> 1 Bit14 FLTR_TRIM<1> 0 Bit15 OUT_BUFF_TRIM<0> 1 Bit16 OUT_BUFF_TRIM<1> 0 WORKING DESCRIPTION Register address SPI bank address Mixer gm current trim Mixer switch core VCM trim LO buffers current trim Mixer output buffer current trim Filter current trim Filter output buffer current trim Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 Table 5. Register 5 Device Setup (continued) REGISTER 5 NAME RESET VALUE Bit17 0 Bit18 0 Bit19 0 Bit20 0 Bit21 0 Bit22 0 Bit23 WORKING DESCRIPTION 0 Bit24 NU 0 Bit25 0 Bit26 0 Bit27 0 Bit28 0 Bit29 0 Bit30 0 Bit31 0 Not used Trims: the trim values allow for minor bias adjustments of internal stages. Generally it is recommended to leave all trim values at the default value of 1. Linearity performance improvement over a small band of frequencies is possible by selective adjustment of the trim values. Optimized intercept point within the band 2.5 GHz to 2.7 GHz is achieved by setting trim values MIX_GM_TRIM<0,1>, MIX_LO_TRIM<0,1>, LO_TRIM<0,1>, MIX_BUFF_TRIM<0,1>, FLTR_TRIM<0,1>, OUT_BUFF_TRIM<0,1> to: 2, 3, 0, 1, 2, 1, respectively. Readback (Write Command) 0 0 0 1 0 Bit0 Bit1 Bit2 Bit3 Bit4 Zero Fill Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Zero fill Bit16 Bit17 Bit18 Bit19 Bit20 Bit21 Bit13 Bit14 Register address Bit22 Bit23 Bit24 Bit25 Bit26 Bit27 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit21 Bit22 Bit23 Bit24 Bit25 Bit26 Bit15 1 Bit28 Bit29 Bit30 Bit31 Bit12 Bit13 Bit14 Bit15 Bit29 Bit30 Bit31 Reg 0:DAC/Device ID Readback Register Address Bit0 Bit1 Bit2 Bit16 Bit17 Bit18 SPI Bank Addr Bit3 ID Bit4 NU DC offset Q DAC Bit19 DC offset I DAC Bit20 Bit27 Bit28 Table 6. Register 0 Device Setup (Read-Only) READBACK REGISTER NAME RESET VALUE Bit0 ADDR<0> 0 Bit1 ADDR<1> 0 Bit2 ADDR<2> 0 Bit3 ADDR<3> 1 Bit4 ADDR<4> 0 Bit5 ID<0> 1 Bit6 ID<1> 0 WORKING DESCRIPTION Select SPI reg 1 to 5 Select SPI bank 1 to 3 Version ID: 01 = -25 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 43 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com Table 6. Register 0 Device Setup (Read-Only) (continued) READBACK REGISTER NAME RESET VALUE Bit7 0 Bit8 0 Bit9 0 Bit10 0 Bit11 NU 0 Bit12 0 Bit13 0 Bit14 0 Bit15 44 WORKING DESCRIPTION Not used 0 Bit16 DC_OFFSET_Q<0> 0 Bit17 DC_OFFSET_Q<1> 0 Bit18 DC_OFFSET_Q<2> 0 Bit19 DC_OFFSET_Q<3> 0 Bit20 DC_OFFSET_Q<4> 0 Bit21 DC_OFFSET_Q<5> 0 Bit22 DC_OFFSET_Q<6> 0 Bit23 DC_OFFSET_Q<7> 1 Bit24 DC_OFFSET_I<0> 0 Bit25 DC_OFFSET_I<1> 0 Bit26 DC_OFFSET_I<2> 0 Bit27 DC_OFFSET_I<3> 0 Bit28 DC_OFFSET_I<4> 0 Bit29 DC_OFFSET_I<5> 0 Bit30 DC_OFFSET_I<6> 0 Bit31 DC_OFFSET_I<7> 1 DC offset DAC Q register DC offset DAC I register Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 APPLICATION INFORMATION Gain Control The TRF371135 integrates a baseband programmable-gain amplifier (PGA) that provides 24 dB of gain range with 1-dB steps. The PGA gain is controlled through SPI by a 5-bit word (register 1 bits<12,16>). Alternatively, the PGA can be programmed by a combination of five bits programmed through the SPI and three parallel external bits (pins Gain_B2, Gain_B1, Gain_B0). The external bits are used to reduce the PGA setting quickly without having to reprogram the SPI registers. The fast gain control multiplier bit (register 1 bit 28) sets the step size of each bit to either 1 dB or 2 dB. This allows a fast gain reduction of 0 dB to 7 dB in 1-dB steps or 0 dB to 14 dB in 2-dB steps. The PGA gain control word (BBGAIN<0,4>) can be programmed to a setting between 0 and 24. This word is the SPI programmed gain (register 1 bits<12,16>) minus the parallel external 3 bits as shown in Figure 56. Note that the PGA gain setting rails at 0 and does not go any lower. Typical applications set the nominal PGA gain setting to 17 and use the fast-gain control bits to protect the analog-to-digital converter in the event of a strong input jammer signal. Composite PGA Setting (min: 0, max 24) + SPI X (x1, x2) Gain_B0 Gain_B1 Gain_B2 Fast Gain Select B0386-01 Figure 56. PGA Gain Control Word For example, if a PGA gain setting of 19 is desired, then the SPI can be programmed directly to a value of 19. Alternatively, the SPI gain register can be programmed to 24 and the parallel external bits set to 101 (binary) corresponding to 5-dB reduction. Automated DC Offset Calibration The TRF371135 provides an automatic calibration procedure for adjusting the dc offset in the baseband I/Q paths. The internal calibration requires a clock in order to function. The TRF371135 can use the internal relaxation oscillator or the external SPI clock. Using the internal oscillator is the preferred method, which is selected by setting the Cal_clk_sel (register 2, bit 28) to 1. The internal oscillator frequency is set through the Osc_trim bits (register 2, bits <29,31>). The frequency of the oscillator is detailed in Table 7; however, it is expected the actual frequency of operation can vary plus or minus 35% due to process variations. The oscillator frequency can be monitored on the READBACK pin when the Osc_test register (register 1, bit 29) is set to 1. Table 7. Internal Oscillator Frequency Control Osc_trim<2> Osc_trim<1> Osc_trim<0> FREQUENCY 0 0 0 300 kHz 0 0 1 500 kHz 0 1 0 700 kHz 0 1 1 900 kHz 1 0 0 1.1 MHz 1 0 1 1.3 MHz 1 1 0 1.5 MHz 1 1 1 1.8 MHz Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 45 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com The default setting of these registers corresponds to a 900-kHz oscillator frequency. This is sufficient for autocalibration; modification is not required except for faster calibration convergence. The output full-scale range of the internal dc offset correction DACs is programmable (IDET_B<0,1>, register 2 bits<22,23>). The range is shown in Table 8. Table 8. DC Offset Correction DAC Programmable Range IDET_B0 IDET_B1 Full Scale 0 0 50 A 0 1 100 A 1 0 150 A 1 1 200 A The I- and Q-channel output maximum dc offset correction range can be calculated by multiplying the values in the table by the baseband PGA gain. The LSB of the digital correction is dependent on the programmed maximum correction range. For optimum resolution and best correction, the dc offset DAC range should be set to 50 A with the PGA gain set for the nominal condition. The dc offset correction DAC output is affected by a change in the PGA gain, but if the initial calibration yields optimum results, then the adjustment of the PGA gain during normal operation does not significantly impair the dc offset balance. For example, if the optimized calibration yields a dc offset balance of 2 mV at a gain setting of 17, then the dc offset maintains less than 10 mV balance as the gain is adjusted 7 dB. The dc offset correction DACs are programmed from the internal registers when the CAL_SEL bit (register 2, bit 24) is set to 1. At start-up, the internal registers are loaded at half-scale, corresponding to a decimal value of 128. The auto-cal is initiated by toggling the EN_AUTOCAL bit (register 2, bit 5) to 1. When the calibration is over, this bit is automatically reset to 0. During calibration, the RF local oscillator must be applied. The dc offset DAC state is stored in the internal registers and maintained as long as the power supply is kept on or until a new calibration is started. The required clock speed for the optimum calibration is determined by the internal detector behavior (integration bandwidth, gain, sensitivity). The input bandwidth of the detector can be adjusted by changing the cutoff frequency of the RC low-pass filter in front of the detector (register 1, bits 25-26). EN_FLT_B0 controls the resistor (bypass = 1) and EN_FLT_B1 controls the capacitor (bypass = 1). The typical 3-dB cutoff frequencies of the detector bandwidth are summarized in Table 9. The speed of the clock can be slowed down by selecting a clock divider ratio (register 2, bits 25-27). Table 9. Detector Bandwidth Settings EN_FLT_B1 EN_FLT_B0 TYPICAL 3-dB CUTOFF FREQUENCY NOTES X 0 10 MHz Maximum bandwidth, bypass R, C 0 1 10 kHz Enable R 1 1 1 kHz Minimum bandwidth, enable R, C The detector has more averaging time with a slower clock; hence, it is desirable to slow down the clock speed for a given condition to achieve optimum results. For example, if there is no RF present on the RF input port, the detection filter can be left wide (10 MHz) and the clock divider can be left at div-by-128. The autocalibration yields a dc offset balance between the differential baseband output ports (I and Q) that is less than 15 mV. Some minor improvement may be obtained by increasing the averaging of the detector by increasing the clock divider up to 256 or 1024. On the other hand, if there is a modulated RF signal present at the input port, it is desirable to reduce the detector bandwidth to filter out most of the modulated signal. The detector bandwidth can be set to a 1-kHz corner frequency. With the modulated signal present and with the detection bandwidth reduced, additional averaging is required to get the optimum results. A clock divider setting of 1024 yields optimum results. Of course, an increase in the averaging is possible by increasing the clock divider at the expense of longer converging time. The convergence time can be calculated by the following: (Auto_Cal_Clk_Cycles) (Clk_Divider) tc = Osc_Freq (1) 46 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 The dc offset calibration converges in approximately nine cycles. For the case with a clock divider of 1024 and with the nominal oscillator frequency of 900 kHz, the convergence time is: (9) (1024) tc = = 10.24 ms 900 kHz (2) Alternate Method for Adjusting DC Offset The internal registers controlling the internal dc current DAC are accessible through the SPI, providing a user-programmable method for implementing the dc offset calibration. To employ this option the CAL_SEL bit must be set to 0. During this calibration, an external instrument monitors the output dc offset between the I/Q differential outputs and programs the internal registers (IDAC_BIT<0,7> and QDAC_BIT<0,7> bits) to cancel the dc offset. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 47 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com PCB Layout Guidelines The TRF371135 device is fitted with a ground slug on the back of the package that must be soldered to the PCB ground with adequate ground vias to ensure a good thermal and electrical connection. The recommended via pattern and ground pad dimensions are shown in Figure 57. The recommended via diameter is 8 mils (0.2 mm). The ground pins of the device can be directly tied to the ground slug pad for a low-inductance path to ground. Additional ground vias may be added if space allows. The no-connect (NC) pins can also be tied to the ground plane. Decoupling capacitors at each of the supply pins is recommended. The high-frequency decoupling capacitors for the RF mixers (VCCMIX) should be placed close to their respective pins. The value of the capacitor should be chosen to provide a low-impedance RF path to ground at the frequency of operation. Typically, this value is around 10 pF or lower. The other decoupling capacitors at the other supply pins should be kept as close to their respective pins as possible. The device exhibits symmetry with respect to the quadrature output paths. It is recommended that the PCB layout maintain that symmetry in order to ensure the quadrature balance of the device is not impaired. The I/Q output traces should be routed as differential pairs and their lengths all kept equal to each other. Decoupling capacitors for the supply pins should be kept symmetrical where possible. The RF differential input lines related to the RF input and the LO input should also be routed as differential lines with their respective lengths kept equal. If an RF balun is used to convert a single-ended input to a differential input, then the RF balun should be placed close to the device. Implement the RF balun layout per the manufacturer's guidelines to provide best gain and phase balance to the differential outputs. On the RF traces, maintain proper trace widths to keep the characteristic impedance of the RF traces at a nominal 50 . 0.200 (5.08) 0.025 (0.635) O0.008 (0.203) 0.025 (0.635) 0.0125 (0.318) 0.200 (5.08) Note: Dimensions are in inches (mm) M0177-01 Figure 57. PCB Layout Guidelines 48 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 Application Schematic The typical application schematic is shown in Figure 58. The RF bypass capacitors and coupling capacitors on the supply pins should be adjusted to provide the best high-frequency bypass based on the frequency of operation. To Microcontroller RFin READBACK NC Gain_B2 Gain_B1 Gain_B0 NC NC MIXIoutn STROBE MIXIoutp DATA CLOCK To Microcontroller 48 47 46 45 44 43 42 41 40 39 38 37 36 GNDDIG 1 VCCDIG 2 35 GND CHIP_EN 3 34 BBIoutn VCCMIX1 4 33 BBIoutp GND 5 32 GND MIXinp 6 31 LOip VCCBBI To ADC I LOin TRF371135 MIXinn 7 30 LOin GND 8 29 VCCLO VCCMIX2 9 28 BBQoutp NC 10 27 BBQoutn NC 11 26 GND To ADC Q VCCBBQ NC VCM GNDBIAS VCCBIAS REXT NC NC MIXQoutn GND MIXQoutp GND GND 25 12 13 14 15 16 17 18 19 20 21 22 23 24 GND 30 kW Figure 58. TRF371135 Application Schematic The RF input port and the RF LO port require differential input paths. Single-ended RF inputs to these ports can be converted with an RF balun that is centered at the band of interest. Linearity performance of the TRF371135 is dependent on the amplitude and phase balance of the RF balun; hence, care should be taken with the selection of the balun device and with the RF layout of the device. The recommended RF balun devices are listed in Table 10. Table 10. RF Balun Devices MANUFACTURER PART NUMBER FREQUENCY RANGE UNBALANCE IMPEDANCE BALANCE IMPEDANCE Murata LDB211G8005C-001 1800 MHz 100 MHz 50 50 Murata LDB211G9005C-001 1900 MHz 100 MHz 50 50 Murata LDB212G4005C-001 2.3 GHz to 2.7 GHz 50 50 Johanson 3600BL14M050E 3.3 GHz to 3.8 GHz 50 50 Johanson 5400BL15B050E 4.9 GHz to 5.9 GHz 50 50 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 49 TRF371135 SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 www.ti.com Application for a High-Performance RF Receiver Signal Chain The TRF371135 is the centerpiece component in a high-performance direct-downconversion receiver. The device is a highly integrated direct-downconversion demodulator that requires minimal additional devices to complete the signal chain. A signal chain block diagram example is shown in Figure 59. ADS62P42 TRF371135 14 0 90 LNA 14 TRF3761 Figure 59. Block Diagram of Direct-Downconvert Receiver The lineup requires a low-noise amplifier (LNA) that operates at the frequency of interest with typical 1- to 2-dB noise figure (NF) performance. An RF band-pass filter (BPF) is selected at the frequency band of interest to eliminate unwanted signals and images outside the band from reaching the demodulator. The TRF371135 incorporates the direct-downconvert demodulation, baseband filtering, and baseband gain-control functions. An external synthesizer, such as the TRF3761, is used to provide the local oscillator (LO) source to the TRF371135. The differential outputs of the TRF3761 directly mate with LO input of the TRF371135. The quadrature outputs (I/Q) of the TRF371135 directly drive the input to the analog-to-digital converter (ADC). A dual ADC like the ADS62P42 14-bit 65-MSPS ADC mates perfectly with the differential I/Q output of the TRF371135. The baseband output pins (pins 27, 28, 33, 34) can be connected directly to the corresponding input pins of typical ADCs. The positive and negative terminal connections between the TRF371135 and the ADC can be swapped to facilitate a clean routing layout. The swapped connection can be reversed by flipping the signals in the digital domain, if desired. In addition, the common-mode output voltage generated by the ADC is fed directly into the common-mode port (pin 24) to ensure the optimum dynamic range of the ADC is maintained. EVALUATION TOOLS An evaluation module is available to test the TRF371135 performance. The TRF371135EVM can be configured with different baluns to enable operation in various frequency bands. The TRF371135EVM is available for purchase through the Texas Instruments web site at www.ti.com. 50 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 TRF371135 www.ti.com SLWS220A - FEBRUARY 2010 - REVISED MARCH 2010 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (February, 2010) to Revision A Page * Corrected product name discussed throughout document ................................................................................................... 1 * Added Evaluation Tools ...................................................................................................................................................... 50 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TRF371135 51 PACKAGE OPTION ADDENDUM www.ti.com 22-Mar-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TRF371135IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TRF371135IRGZT ACTIVE VQFN RGZ 48 250 CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TRF371135IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 TRF371135IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TRF371135IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 TRF371135IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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