©2002 Fairchild Semiconductor Corporation
IRF540N Rev. C
IRF540N
33A, 100V, 0.040 Ohm, N-Channel, Power
MOSFET
Packaging
Symbol
Features
• Ultra Low On-Resistance
-r
DS(ON)
= 0.040
Ω,
V
GS
=
10V
• Simulation Models
- Temperature Compensated PSPICE™ and SABER
©
Electrical Models
- Spice and SABER
©
Thermal Impedance Models
- www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Ordering Information
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
JEDEC TO-220AB
DRAIN
(FLANGE)
DRAIN
SOURCE
GATE
IRF540N
D
G
S
PART NUMBER PACKAGE BRAND
IRF540N TO-220AB IRF540N
IRF540N UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
100 V
Drain to Gate Voltage (R
GS
= 20k
Ω
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
100 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
±
20 V
Drain Current
Continuous (T
C
= 25
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
C
= 100
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
33
23
Figure 4
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
0.80
W
W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 175
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
L
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
NOTES:
1. T
J
= 25
o
C to 150
o
C.
CAUTION:
Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Data Sheet January 2002
©2002 Fairchild Semiconductor Corporation IRF540N Rev. C
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BV
DSS
I
D
= 250
µ
A, V
GS
= 0V (Figure 11) 100 - - V
Zero Gate Voltage Drain Current I
DSS
V
DS
= 95V, V
GS
= 0V - - 1
µ
A
V
DS
= 90V, V
GS
= 0V, T
C
= 150
o
C - - 250
µ
A
Gate to Source Leakage Current I
GSS
V
GS
=
±
20V - -
±
100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= 250
µ
A (Figure 10) 2 - 4 V
Drain to Source On Resistance r
DS(ON)
I
D
= 33A, V
GS
= 10V (Figure 9) - 0.033 0.040
Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case R
θ
JC
TO-220 - - 1.25
o
C/W
Thermal Resistance Junction to
Ambient
R
θ
JA
--62
o
C/W
SWITCHING SPECIFICATIONS
(V
GS
= 10V)
Turn-On Time t
ON
V
DD
= 50V, I
D
= 33A
V
GS
=
10V,
R
GS
= 9.1
Ω
(Figures 18, 19)
- - 100 ns
Turn-On Delay Time t
d(ON)
- 9.5 - ns
Rise Time t
r
-57-ns
Turn-Off Delay Time t
d(OFF)
-40-ns
Fall Time t
f
- 55 - ns
Turn-Off Time t
OFF
- - 145 ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Q
g(TOT)
V
GS
= 0V to 20V V
DD
= 50V,
I
D
= 33A,
I
g(REF)
= 1.0mA
(Figures 13, 16, 17)
-6679nC
Gate Charge at 10V Q
g(10)
V
GS
= 0V to 10V - 35 42 nC
Threshold Gate Charge Q
g(TH)
V
GS
= 0V to 2V - 2.4 2.9 nC
Gate to Source Gate Charge Q
gs
- 5.4 - nC
Gate to Drain "Miller" Charge Q
gd
-13-nC
CAPACITANCE SPECIFICATIONS
Input Capacitance C
ISS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
(Figure 12)
- 1220 - pF
Output Capacitance C
OSS
- 295 - pF
Reverse Transfer Capacitance C
RSS
- 100 - pF
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage V
SD
I
SD
= 33A - - 1.25 V
I
SD
= 17A - - 1.00 V
Reverse Recovery Time t
rr
I
SD
= 33A, dI
SD
/dt = 100A/
µ
s - - 112 ns
Reverse Recovered Charge Q
RR
I
SD
= 33A, dI
SD
/dt = 100A/
µ
s - - 400 nC
IRF540N
©2002 Fairchild Semiconductor Corporation IRF540N Rev. C
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs
CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. PEAK CURRENT CAPABILITY
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 175
0.2
0.4
0.6
0.8
1.0
1.2
125 150
20
30
40
50 75 100 125 150
025
I
D
, DRAIN CURRENT (A)
T
C
, CASE TEMPERATURE (
o
C)
V
GS
= 10V
175
10
0.1
1
2
10-4 10-3 10-2 10-1 100101
0.01
10-5
t, RECTANGULAR PULSE DURATION (s)
ZθJC, NORMALIZED
THERMAL IMPEDANCE
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
100
600
20
10-4 10-3 10-2 10-1 100101
10-5
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
TC = 25oC
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
IRF540N
©2002 Fairchild Semiconductor Corporation IRF540N Rev. C
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
Typical Performance Curves (Continued)
10
100
10 300
300
1
1
100µs
10ms
1ms
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
TJ = MAX RATED
TC = 25oC
SINGLE PULSE
100
100
200
0.001 0.01 0.1 1
I
AS
, AVALANCHE CURRENT (A)
t
AV
, TIME IN AVALANCHE (ms)
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R ≠ 0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
10
0
20
40
60
234 6
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
TJ = 175oC
TJ = 25oC
TJ = -55oC
5
0
20
40
60
01234
I
D
, DRAIN CURRENT (A)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
=5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
V
GS
= 7V
V
GS
= 6V
V
GS
= 20V
V
GS
= 10V
0.5
1.0
1.5
2.0
3.0
-80 -40 0 40 80 120 200
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
VGS = 10V, ID = 33A
PULSE DURATION =
80µs
DUTY CYCLE = 0.5% MAX
160
2.5
0.6
0.8
1.0
1.2
-80 -40 0 40 80 120 200
NORMALIZED GATE
T
J
, JUNCTION TEMPERATURE (
o
C)
V
GS
= V
DS
, I
D
= 250µA
THRESHOLD VOLTAGE
160
IRF540N
©2002 Fairchild Semiconductor Corporation IRF540N Rev. C
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves (Continued)
0.9
1.0
1.1
1.2
-80 -40 0 40 80 120 200
T
J
, JUNCTION TEMPERATURE (
o
C)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
I
D
= 250µA
160160
20
100
1000
4000
0.1 1.0 10 100
C, CAPACITANCE (pF)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
≅ C
DS
+ C
GD
0
2
4
6
8
10
010 20 30 40
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
DD
= 50V
Q
g
, GATE CHARGE (nC)
I
D
= 33A
I
D
= 17A
WAVEFORMS IN
DESCENDING ORDER:
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
IRF540N
©2002 Fairchild Semiconductor Corporation IRF540N Rev. C
FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM
Test Circuits and Waveforms (Continued)
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20V
VDS
VGS
Ig(REF)
0
0
Qgs Qgd
VGS
RL
RGS
DUT
+
-
VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
IRF540N
©2002 Fairchild Semiconductor Corporation IRF540N Rev. C
PSPICE Electrical Model
.SUBCKT IRF540N 2 1 3 ; rev 19 July 1999
CA 12 8 1.95e-9
CB 15 14 1.90e-9
CIN 6 8 1.12e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 112.8
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1.0e-9
LGATE 1 9 6.19e-9
LSOURCE 3 7 2.18e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.00e-2
RGATE 9 20 1.77
RLDRAIN 2 5 10
RLGATE 1 9 26
RLSOURCE 3 7 11
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 6.5e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*71),3.5))}
.MODEL DBODYMOD D (IS = 1.20e-12 RS = 4.2e-3 XTI = 5 TRS1 = 1.3e-3 TRS2 = 8.0e-6 CJO = 1.50e-9 TT = 7.47e-8 M = 0.63)
.MODEL DBREAKMOD D (RS = 4.2e-1 TRS1 = 8e-4 TRS2 = 3e-6)
.MODEL DPLCAPMOD D (CJO = 1.45e-9 IS = 1e-30 M = 0.82)
.MODEL MMEDMOD NMOS (VTO = 3.11 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.77)
.MODEL MSTROMOD NMOS (VTO = 3.57 KP = 33.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.68 KP = 0.09 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 17.7 )
.MODEL RBREAKMOD RES (TC1 =1.05e-3 TC2 = -5e-7)
.MODEL RDRAINMOD RES (TC1 = 9.40e-3 TC2 = 2.93e-5)
.MODEL RSLCMOD RES (TC1 = 3.5e-3 TC2 = 2.0e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.8e-3 TC2 = -8.6e-6)
.MODEL RVTEMPMOD RES (TC1 = -3.0e-3 TC2 =1.5e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.2 VOFF= -3.1)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.1 VOFF= -6.2)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.0 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
IRF540N
©2002 Fairchild Semiconductor Corporation IRF540N Rev. C
SABER Electrical Model
REV 19 July 1999
template IRF540N n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 1.20e-12, cjo = 1.50e-9, tt = 7.47e-8, xti = 5, m = 0.63)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 1.45e-9, is = 1e-30, m = 0.82)
m..model mmedmod = (type=_n, vto = 3.11, kp = 5, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.57, kp = 33.5, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.68, kp = 0.09, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.2, voff = -3.1)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -3.1, voff = -6.2)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.0)
c.ca n12 n8 = 1.95e-9
c.cb n15 n14 = 1.90e-9
c.cin n6 n8 = 1.12e-9
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 6.19e-9
l.lsource n3 n7 = 2.18e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -5.0e-7
res.rdbody n71 n5 = 4.2e-3, tc1 = 1.30e-3, tc2 = 8.0e-6
res.rdbreak n72 n5 = 4.2e-1, tc1 = 8.0e-4, tc2 = 3.0e-6
res.rdrain n50 n16 = 2.00e-2, tc1 = 9.40e-3, tc2 = 2.93e-5
res.rgate n9 n20 = 1.77
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 26
res.rlsource n3 n7 = 11
res.rslc1 n5 n51 = 1e-6, tc1 = 3.5e-3, tc2 = 2.0e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 6.5e-3, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -3.0e-3, tc2 = 1.5e-7
res.rvthres n22 n8 = 1, tc1 = -1.8e-3, tc2 = -8.6e-6
spe.ebreak n11 n7 n17 n18 = 112.8
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/71))** 3.5))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
IRF540N
©2002 Fairchild Semiconductor Corporation IRF540N Rev. C
SPICE Thermal Model
REV 26 July 1999
IRF540NT
CTHERM1 th 6 2.60e-3
CTHERM2 6 5 8.85e-3
CTHERM3 5 4 7.60e-3
CTHERM4 4 3 7.65e-3
CTHERM5 3 2 1.22e-2
CTHERM6 2 tl 8.70e-2
RTHERM1 th 6 9.00e-3
RTHERM2 6 5 1.80e-2
RTHERM3 5 4 9.15e-2
RTHERM4 4 3 2.43e-1
RTHERM5 3 2 3.10e-1
RTHERM6 2 tl 3.21e-1
SABER Thermal Model
SABER thermal model IRF540NT
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.60e-3
ctherm.ctherm2 6 5 = 8.85e-3
ctherm.ctherm3 5 4 = 7.60e-3
ctherm.ctherm4 4 3 = 7.65e-3
ctherm.ctherm5 3 2 = 1.22e-2
ctherm.ctherm6 2 tl = 8.70e-2
rtherm.rtherm1 th 6 = 9.00e-3
rtherm.rtherm2 6 5 = 1.80e-2
rtherm.rtherm3 5 4 = 9.15e-2
rtherm.rtherm4 4 3 = 2.43e-1
rtherm.rtherm5 3 2 = 3.10e-1
rtherm.rtherm6 2 tl = 3.21e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
IRF540N
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
Rev. H4
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™
SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET
STAR*POWER is used under license
VCX™