HIGH SPEED IDT71321SA/LA 2K X 8 DUAL-PORT IDT71421SA/LA STATIC RAM WITH INTERRUPTS Features * High-speed access * MASTER 1DT71321 easily expands data bus width to 16-or- - Commercial: 20/25/35/55ns (max.} more-bits using SLAVE 1D171421 - Industrial: 55ns (max.) * Low-power operation ~ IDT71321NDT71421SA Active: 325mW (typ.) Standby: 5mW (typ.) On-chip port arbitration logic (1DT71321 only) BUSY output flag on 1DT71321; BUSY input on (DT71421 Fully asynchronous operation from either port Battery backup operation - 2V data retention (LA only) TTL-compatible, single 5V +10% power supply - IDT71321/421LA Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP Active: 325mW (typ.) Industrial temperature range (-40 T to +85 C) is available Standby: ImW (typ.) for selected speeds * Two INT flags for port-to-port communications Oh OmhhUh%Hm6UlhUhO Functional Block Diagram OEL OER CEL CER R/WL R/Wr VOo- VOr. VOor-/O7A Vo ie) Control Control Busy." BuSsya A 3 MEMORY AtoR Ao ARRAY Aor ARBITRATION and INTERRUPT LOGIC inte? INTR 2691 drw 01 NOTES: 1. 1DT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 2700. 10771421 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor of 2700. MARCH 1999 1999 integrated Device Technology, Inc. DSC-2691/8 1LOR SA KYA EY NO Sec OAR RC PRET Ce) High Speed 2h x 8 Dual-Port Sialic HAR with Interrupts Description The 1DT71321/IDT71421 are high-speed 2K x 8 Dual-Port Static RAMs with internal interrupt logic for interprocessor communications. The IDT/1321 is designed to be used as a stand-alone 8-bit Dual- Port Static RAM or as a "MASTER" Dual-Port Static RAM together with the [DT71421 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port Static RAM ap- proach in 16-or-more-bit memory system applications results in full speed, error-free operation without the need for additional discrete logic. icia) femperature Flanges address, and i/O pins that permit independent, asynchronous access for reads of writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Fabricated using IDTs CMOS high-performance technology, these devices typically operate on only 325mW of power. Low-power (LA) versions offer battery backup data retention capability, with each Dual- Port typically consuming 200)W from a 2V battery. The 1DT71321ADT71421 devices are packaged in 52-pin PLCCs, Both devices provide two independent ports with separate control, 54-pin TQFPs, and 64-pin STQFPs. Pin Configurations 2?) rc a c |\>- 4 a ,- | 4 o 2 an ,f x dw SES | 8 yt | | Bs INDEX SB zee Sse se sees antlg? 6 5 4 3 2 0 52 51 50 49 48.47 -) OF, Aa Jo 45(7] Aor As. (10 44] air A4L [111 43] azr Asi f012 42T7] Asr AeL[L]13 IDT71321/421J 417] Aaa A7. [14 J52-14) 40] Asr As. [F115 PLCC 39f-} Aer Ag 16 Top View(5) 387] A7r VOo (717 37E-] Asr VOi.[7118 36C7] Aor yO2a.7119 35] nc VO 3. [120 34(7] \/o7R 1 4 1 33 \ FLELELAL RAPALA AS / : ; SBBEFODEERES SE rae Bis ce oe PQLee=F,qggggggO cose Bed 3 gGSee S09 SSSS SOB ESESEE SSIEB SH SSmEBEESS INDEX, Of = 2 % OER Ao. ==] 2 Aor Ave 3 AIR Ao. my 4 459 Aor As. = 5 44 Asr An 6 1DT71321/421PF or TF 43 foeme 1 6 Aud 7 PN64-1 / PP64-1(4 42k Ase Ac = 8 . 41" Ace NC= 9 64-Pin TQFP 4 NIC 64-Pin STQFP Az. mmyi0 Top Views) sop A7A As yt 38" Asa Ag = 12 37 AQR NOTES: NC =pi3 NwC 1. All Vcc pins must be connected to power supply. Oo. = 14 35 NC 2. Ail GND pins must be connected to ground supply. ; yOu. 5 34 /O7R 3. J52-1 package body is approximately .75 in x .75 in x .17 in. _ 3 Os PN64-1 package body is approximately 14mm x 14mm x 1.4mm. VOz mI a 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PP64-1 package body is approximately 10mm x 10mm x 1.4mm. 2891 dew 08 4. This package code is used to reference the package diagram. BOsgseseROgGaOTC LE FoOLES 5. This text does not indicate orientation of the actual part-marking. 92E0902 6 6 S OQ S S 2 S SIDT7 1321S AAA and IDT?71421SA'LA High Speed 2h x & Qual-Port Staiie HAR) wills iulercupls Capacitance (TA = +25C, f = 1.0MHz) TQFP Only Symbol Parameter Conditions? | Max. | Unit Cin Input Capacitance VIN = 3dV 9 pF Cout | Output Capacitance Vout = 3dV 10 pF 2684 thi 00 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch fram OV to 3V or from 3V to OV. Absolute Maximum Ratings Symbol Rating Commercial Unit & Industrial VierM?) Terminal Voltage 0.5 to +7.0 Vv with Respect to GND Teas Temperature -55 to +125 C Under Bias Ts1G Storage -55 to +125 C Temperature lout DC Output 50 mA Current 2691 bi 1 NOTES: 1. Stresses greater than those fisted under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VrERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of Vrerm > Vcc + 10%. ndusteal and Conn al lemperature Ranges Recommended Operating Temperature and Supply Voltage) Grade Ambient GND Vec Temperature Commercial OC to +70C OV 5.0V + 10% Industrial 40C to +85C ov 5.0V + 10% NOTES: saree 1. This is the parameter Ta. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office. Recommended DC Operating Conditions Symbol Parameter Min. | Typ. | Max | Unit vec | Supply Voltage 45 | 50 | 55 [| Vv GND = | Ground 0 0 9 V ViH_ | Input High Voltage 2.2 | 607] Vv Vit | Input Low Voltage O50 | 0.8 Vv 2691 thi C3 NOTES: 1. Vie (min) = -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%.PRP AMPALT Tw ees mek ed High Speed 24 x 6 Quai lempera i; rake ler DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Rangd'* (vcc = 5.0v + 10%) 71321X20 71321X25 71421X20 71421X25 Gom'l Only Com'l Only Symbol Parameter Test Condition Version Typ. Max Typ. Max. | Unit Icc | Dynamic Operating CE. and CER = Vit, COM'L SA] 110 250 110 220 | mA Current Outputs Open LA | 410 | 200 10 470 (Both Ports Active) f= fuax?) IND SA LA lsa1 | Standby Current CEL and GER = Vin COM'L SA w 6 30 65 mA (Both Ports - TTL f = fMax?) LA 30 45 30 45 Level Inputs) IND SA LA isa2_| Standby Current CEw = Vi and CEs: = Vit? COM'L SA| 65 165 65 150 | ma (One Port - TIL Active Port Outputs Open, LA 65 125 65 115 Level Inputs) fefuax?) IND SA tA fss3 | Full Standby Current CEL and COM'L SA] 1.0 15 1.0 15 | mA (Both Ports - CEr > Vcc - 0.2V, LA 0.2 5 0.2 5 CMOS Level Inputs} Vin > Vee - 0.2V of Vin 0.2V, f= 00} IND SA LA ispa | Full Standby Current CE < 0.2V and COM'L SA 60 155 60 145 mA (One Port - CE > Voc - 0.2ve iA | 115 60 405 CMOS Level Inputs) Vin 2 Vcc - 0.2V or Vins 0.2V ND SA Active Port uts Open, f= fa) Outputs Op LA 2631 tl Oda 71321X35 71321X55 71421X35 71421X55 Com! Only Com'! & Ind Symbol Parameter Test Condition Version Typ. Max. Typ. Max. | Unit kc Dynamic Operating CEL and CEr = Vi, COM'L SA 80 165 65 155 mA Current Outputs Open LA 80 120 65 110 (Both Ports Active) f= fMax?) IND SA 65 190 LA 65 140 isa1_| Standby Current CEL and CEr = Vii COML SA | 25 65 20 65 mA (Both Ports - TIL f= fax?) tA 25 45 20 35 Level Inputs) IND SA 20 65 LA 20 46 saz | Standby Current CE = Vi and GEe = Vet COM'L SA| 50 125 40 110 | mA (One Port - TTL Active Port Outputs Open, LA 50 90 40 75 Level inputs) fefmad? IND SA 40 125 LA 40 90 'ss3_| Full Standby Current CEL and COML SA 4.0 15 1.0 45 mA Both Ports - CER > Vec - 0.2V, LA |] 02 4 02 4 CMOS Level Inputs} Vin 2 Vec - 0.2V or Vn < 0.2V, f= 08 IND SA 4.0 30 LA 0.2 10 Isea | Full Standby Current CEs < 0.2V and COM'L SA 45 410 40 400 mA (One Port - CEs > Voc - 0.28) tA] 45 85 40 70 CMOS Level Inputs) Vin > Voc - 0.2V or Vin < 0.2V Active Port Outputs Open, IND SA 40 110 f= fax?) LA 40 85 2691 thi O4b NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). 2. Atf = fax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycie of I/trc, and using "AC TEST CONDITIONS of input levels of GND to 3V. 3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 4. Vec = SV, Ta=+25 C for Typ and is not production tested. Vcc pc = 100mA (Typ) 5. Port "A" may be either left or right pont. Port "B" is opposite from pont A. 6. Industrial temperature: for other speeds, packages and powers contact your sales office.[PRP e Ket ewes) Ar eee High Speed 2k x Dual-Po Temperature and Supply Voltage Range (Uc = 5.0V + 10%) Race eb C0T Rte ISM MOS STEROL ELS s Reis il imperative Manges DC Electrical Characteristics Over the Operating 713218A 71321LA 71421SA 71421LA Symbol Parameter Test Conditions Min. Max. Min. Max. Unit (hu Input Leakage Current Voc = 5.5V, Vin = OV to Veco ~ 10 - 5 pA hol Output Leakage Current" CE = Vin, Vout = OV to Vcc, ~ 10 5 pA Vec - 5.5V Vo. Qutput Low Voltage (/Oo-VO7) lon = 4mA - 0.4 ~ 04 Vv Vou Open Drain Output__ lo. = 16mA - 05 - 0.5 Vv Low Voltage (BUSY/INT} VoH Output High Voltage lon = -4mA 2.4 ~ 24 ~ V NOTE: 2691 tbl 05 1. At Vec < 2.0V leakages are undefined. Data Retention Characteristics (LA Version Only) Symbol Parameter Test Condition Min. | Typ." Max. | Unit VDR Vcc for Data Retention 2.0 _ 0 V locoR Data Retention Current Voc = 2.0V, CE 2 Vcc - 0.2V COM'L _ 100 1500 yA Vin > Vec - 0.2V or VINS 0.2V IND 100 4000 HA tcor) Chip Deselect to Data Retention Time 0 _ ns RO) Operation Recovery Time trc) ns NOTES: 2591 BI 6 1. Vee = 2V, Ta = +25 , and is not production tested. 2. irc = Read Cycle Time 3. This parameter is guaranteed but not production tested. Data Retention Waveform DATA RETENTION MOD | Vcc VDR > 2.0V 4.5V {CDR tR a VDR CE VIH VIH 2691 drw 04IDT71321SA/LA and IDT71421S ATA High Speed 2K x 8 Dual-Port Siaiic WAN) wilh Interrupts AC Test Conditions Input Pulse Leveis GND to 3.0V input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1,2 and 3 2891 1 07 V. 5 12502 DATA ouT 775Q. 30pF* *100pF for 55ns versions Figure 1. AC Output Test Load SV. 2702 BUSY or INT = 30pF* *100pF for 55ns versions Figure 3. BUSY and INT AC Output Test Load lel vecs tar: Lacon SMe Sas seth alc. en tc LMR eat S) Lee Le] Cae ETAL? ok) 5V 1250Q DATA ouT Figure 2. Output Test Load (for tuz, tz, twz, and tow) * Including scope and jig. 2691 drw 05IDT71321SAILA andIDT7t421SA'LA High Speed 2K x & Duai-Port Static HAM with imerrupts AC Electrical Characteristics Over the Operating Temperature Supply Voitage Rangd**) BRASIL eR ASMLZU MCL IALE OR OR SHA LCE tae LARS) 1 -Sec LT cnn ech 71321X20 71321X25 71421X20 71421X25 Com'l Only Com'! Only Symbol Parameter Min. Max. Min. Max. Unit READ CYCLE tre Read Cycle Time 2 25 - ns tA Address Access Time _ 20 ~ 25 ns tace Chip Enable Access Time 20 _ 25 ns tAOE Output Enable Access Time "1 12 ns toH Output Hold from Address Change 3 - 3 -- ns hz Output Low-Z Time''*! 0 0 aoa ns tHZ Output High-Z Time) _ 10 10 ns PU Chip Enable to Power Up Time 0 _ 0 - ns PD Chip Disable to Power Down Time _ 20 _ 25 ns 2691 tbl 08a 71321X35, 71321X55 71424X35 74421X55 Com! Only Com'l & Ind Symbol Parameter Min. Max. Min. Max. Unit READ CYCLE fRC Read Cycle Time 35 Of 55 = ns tAA Address Access Time _ 35 - 55 ns tACE Chip Enable Access Time _ 35 55 ns taoe Output Enable Access Time _ 20 25 ns tou Output Hold from Address Change 3 3 ns iz Output Low-Z Time") 0 ~ 5 ns Hz Output High-Z Time") 15 ~ 25 ns Pu Chip Enable to Power Up Time 0 - 0 ~ ns (PD Chip Disable to Power Down Time! 35 50 ns 2691 tbl O8b NOTES: 1. Transition is measured +500mV from Low or High-impedance voltage Output Test Load (Figure 2). 2. 'X' in part numbers indicates power rating (SA or LA). 3. This parameter is guaranteed by device characterization, but is not production tested. 4. Industrial temperature: for other speeds, packages and powers contact your sales office.IPA RYeL eS ick ele ar yet we High Speed 2K x 8 Dual-Port Static FAM witht iiderrupts industhatara Cou iciai Temiperdiuie Ranges Timing Waveform of Read Cycle No. 1, Either Sid") - tRC ~ ADDRESS x * taAA m7 t OH # tOH ~~" DATAouT PREVIOUS DATA VALID YY DATA VALID BUSYoutT AAA M teppH ) sere NOTES: 1. RW = Vin, CE = Vi, and is OE = Vi. Address is valid prior to the coincidental with CE transition LOW. 2. tpoo delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relationship to valid output data. 3. Start of valid data depends on which timing becomes effective last tace, lace, taa, and tepp. Timing Waveform of Read Cycle No. 2, Either Sidd* tace CE OE tHz?) VALID DATA ipo DATAoutT lec tpu->| CURRENT j 50% 50% Iss qa tz 2091 drw 07 NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, OE or CE. 3. RAW = Vin and OE = Vu, and the address is valid prior to or coincidental with CE wansition LOW. 4. Start of valid data depends on which timing becomes effective fast tae, LACE, laa, and tB00.IDT7IBZISA/LA and IDT7V4AZISATLA High Speed 2K x Dual-Pori Slave KAW SOLE LSEt TRACE Sle) EALSIeE MAELO MA Ltn TAN TET CLOT CE Tare les) AC Electrical Characteristics Over the Operating Temeprature and Supply Voltage Rang**) 71321X20 71321X25 74421X20 74421X25 Com'l Only Com't Only Symbol Parameter Min. Max. Min. Max Unit WRITE CYCLE two Write Cycie Time 20 25 - ns tew Chip Enable to End-of- Write 15 - 20 ns taw Address Valid to End-of-Write 15 --- 20 ns tas Address Setup Time 0 ~~ 0 ~ ns twe Write Pulse Width) 15 15 _ ns twR Write Recovery Time 0 0 ns tow Data Valid to End-of-Write 10 12 ns HZ Output High-Z Time!) ~ 10 - 10 ns {oH Data Hold Time 0 0 -~ ns twz Write Enable to Output in High-2 10 - 10 ns tow Output Active from End-of Write 0 0 - ns 2691 tbi 08a 71321X35 71321X55 71421X35 71421X55 Com'l Only Com'l & Ind Symbol Parameter Min. Max. Min. Max. Unit WRITE CYCLE twe Write Cycle Time! 36 55 ns tew Chip Enable to End-of-Write 30 40 ns taw Address Valid to End-of Write 3% 40 ns tas Address Setup Time 0 - 0 ~ ns twp Write Pulse Width) 25 - 30 - ns wR Write Recovery Time 0 0 _ ns tow Data Valid to End-of-Write 15 20 | -- ns tz Output High-Z Time _ 15 - 25 ns (DH Data Hold Time 0 _ 0 a ns twz Write Enable to Output in High-2 _ 15 ~- 30 ns tow Output Active from End-of Write 8 0 ~ ns NOTES: 2691 tbl 09b 1. Transition is measured +500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but is not production tested. 2. For Master/Slave combination, twc = teaa + twe, since RAW = Va must occur after tBaa . 3. if OE is LOW during a RAW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off data to be placed on the bus for the required tow. if OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twr. 4. X' in part numbers indicates power tating (SA or LA). 5. Industrial temperature: for other speeds, packages and powefs contact your sales office.ADDRESS x * DATA OUT ~< a (4) ible reca ears LiesLabemm Oc orstriy 1000 LME AIRS 1 S40: FOOL cMie Flee 22-) Timing Waveform of Write Cycle No. 1, (RW Controlled Timing}":*) {wc + tas twe) + twa?) tHz'? >} + tw? > tow *] DATAIN + 2691 drw 08 Timing Waveform of Write Cycle No. 2, CE Controlled Timing)" twc = ADDRESS XK x taw CE XK }e~ tas) rhe tew? >| twre RAW \ SL +_~ tow ___> + tbH -- DATAIN 2691 drw 09 NOTES: NOON & WR RAW or CE must be HIGH during all address transitions. A write occurs during the overlap (tew or twr) of CE = Vi. and RAW= VIL twe is measured from the earlier of CE or RAW going HIGH to the end of the write cycle. During this period, the /O pins are in the output state and input signals must not be applied. if the CE LOW transition occurs simultaneousty with or after the RAW LOW tansition, the outputs remain in the High-impedance state. Timing depends on which enable signal (CE or RW) is asserted fast. This parameter is determined to be device characterization, but is not production tested. Transition is measured +500mV from steady state with the Output Test Load (Figure 2). if OE is LOW during a RW controlled write cycle, the write pulse width must be the larger of twe or (twz + tow) to allow the 1/0 drivers to turn off data to be placed on the bus for the required tow. If OE is HIGH during a RW controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twr.IDT7 1321S A/LA and iDT7t High Speed 2K x 8 Dual-t AC Electrical Characteristics Over the eTeECRSCRTcL Ursin (SE WES TObTsl 1 aie]: Operating Temperature and Supply Voltage Rangd) leimperature Ranges 71321X20 71321X25 71421X20 71421X25 Com Only Com'! Only Symbol Parameter Min. | Max. Min. Max. Unit BUSY TIMING (For MASTER 71321} {BAA BUSY Access Time from Address 20 20 ns {BDA BUSY Disable Time from Address 20 20 ns {Bac BUSY Access Time from Chip Enable 20 20 ns tepc BUSY Disable Time from Chip Enable 20 20 ns we Write Hold After BUSY) 12 15 ns twoo Write Pulse to Data Delay! 50 50 ns too Write Data Valid to Read Data Delay!" % 35 ns taps Arbitration Priority Setup Time 5 5 ns tBDD BUSY Disable to Valid Data 25 36 ns BUSY INPUT TIMING (For SLAVE 71421) twe Write to BUSY Input 0 0 ns twH Write Hold After BUSY 12 : 18 ns twoo Writs Pulse to Data Delay"? - 40 50 ns tooo Write Data Valid to Read Data Delay" 30 35 ns 2684 thl 10a 71321X35 71321X55 71421X35 71421X55 Cam'l Only Com'| & Ind Symbol Parameter Min. Max Min. | Max. Unit BUSY TIMING (For MASTER 71321) {BAA BUSY Access Time from Address 20 30 ns t8DA BUSY Disable Time from Address 20 30 ns taac BUSY Access Time from Chip Enable 20 30 ns tpoc BUSY Disable Time from Chip Enabie 2 - 30 ns twH Write Hold After BUSY 20 20 : ns twop Write Pulse to Data Delay"? 60 80 ns {ppp Write Data Valid to Read Data Delay' 35 55 ns taps Arbitration Priority Setup Time 5 5 ns teop BUSY Disable to Valid Data % : 50 ns BUSY INPUT TIMING (For SLAVE 71421) twe Write to BUSY input* 0 0 ns WH Write Hold After BUSY) 20 20 ns twoo Write Pulse to Data Delay 60 - 80 ns tbop Write Data Valid to Read Data Delay! : 35 55 ns NOTES: wee 1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to Timing Waveform of Write with Port-to-Port Read and BUSY. 2. To ensure that the earlier of the two ports wins. 3. tspo is a calculated parameter and is the greater of 0, twon twp (actual) or top - tow (actual). 4. To ensure that a write cycle is inhibited on port "B during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part numbers indicates power rating (SA or LA). 7. Industrial temperature: for other speeds, packages and powers contact your sales office.me SUeCaT ESL EDS" LBM SLE RerolUestar-L MrcDiTs meres ith i-1kear: TBO ctia] Ae Lets ae stele | 2) Timing Waveform of Write with Port-to-Port Read andBUSY@:**) ?+ twc ADDRa" >< MATCH <t- twp BVA! RWear R ev + - 1>w DH DATAwN'A" K VALID He taps! ADDRs" ~ MATCH } tBAA taps >] ts0p BUSY'B" YOR < twoD \ DATAouT's" OK vaup _ topo > NOTES: 601 aw? 1. To ensure that the earlier of the two ports wins. taps is ignored for Slave (71421). Bet dw 30 2. CE. = CEr = Vn 3. O = Vu for the reading port. 4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port A. Timing Waveform of Write withBUSY < {we > nite SX, twa?) BUSYs" twa) RW." S \ \ / (2) NOTES: _ 2691 dew 11 1. twH must be met for both BUSY input (71421, slave) or output (71321, Masier). 2. BUSY is asserted on port B blocking RAW's", until BUSY-s- goes HIGH. 3. tw is only for the slave version (71421). 4. All timing is the same for the feft and right ports. Port "A" may be either the left or right port. Port "B is opposite from port A.IDT71321SA/LA and IDT714215 414 High Speed 2K x 8 Dual-Port Static FAN with Imieriupts ndustial ang Commercial femperature Ranges Timing Waveform of BUSY Arbitration Controlled byCE Timing ADDR " AND 8* x ADDRESSES MATCH <x CE's" t x taps) CE*a" tBAC h* tBDC BUSY'a" 2691 drw 12 Timing Waveform of BUSY Arbritration Controlled by Address Match Timing tac or two ADDR'a* ADDRESSES MATCH x ADDRESSES DO NOT MATCH x taps ADDF *s: B xX h+ {BAA h+ tepa BUSYs" 2691 drw 13 NOTES: 1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B is the opposite from port "A". 2. if taps is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (71321 only). AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Rangd') 74321X20 71321X25 71421X20 71421X25 Com'l Only Com'l Only Symbol Parameter Min. | Max. Min. Max Unit INTERRUPT TIMING tas Address Set-up Time 0 -- 0 -~ ns {wR Write Recovery Time 0 0 ns Ns interrupt Set Time 20 _ 25 ns tNR Interrupt Reset Time _ 20 25 ns 2691 bt tia NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). 2. Industrial temperature: for other speeds, packages and powers contact your sales office.IDT7 1321S A/LA andlDT71421SA'LA High Speed 2K x 8 Dual-Port State HAR wilh infer upts arervech i atcimet anon wnelanealicireti: tae EAb Cl stsand eth t at TPT (3) AC Electrical Characteristics Over the Operating Temperature Supply Voltage Ranged":) 71321X35 71321X55 71421X35 71421X55 Com'l Only Com) & ind Symbol Parameter Min. Max Min. Max. Unit INTERRUPT TIMING tas Address Set-up Time 0 0 -_ ns twR Write Recovery Time 0 0 ae ns tiINS Interrupt Set Time 25 45 ns tNR Interrupt Reset Time _ 25 45 ns NOTES: 2691 th! 1b 1. 'X' in part numbers indicates power rating (SA or LA). 2. Industrial temperature: for other speeds, packages and powers contact your sales office. Timing Waveform of Interrupt Modd SET INT L two ~~ ADDR'a INTERRUPT ADDRESS 4 x tas twr RAW*A tins) INT*B" 2691 drw 14 CLEAR INT < tRC | appre X X XX KX KK KKK INTERRUPT CLEAR ADDRESS > se ta) OES" ANAAAAAKA AA N J tinA) | INT-a" 2691 drw 15 NOTES: 1. All timing is the same for left and right ports. Port "A" may be either feft or right port. Port "B is the opposite from port A. 2. See Interrupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last, 4, Timing depends on which enable signal (CE or R/W) is de-asserted first.lOT71IZ21SA/LA and IDT714215A'LA High Speed 2K x 3 Duai-Port Static HAM with Inerrupis eS IeesEate Leche mOrelt sbt tere Maca ine) eshte td Mat Li ne oT Truth Tables Truth Table I. Non-Contention Read/Write Controf Left or Right Port! RW cE OE Dor Function x H xX Zz Port Disabled and in Power-Down Mode, iSBz or ISBs X H x Zz CER = CEL = Vin, Power-Down Mode, ISB: or ISB3 L L X DATAin _| Data on Port Written into Memory! H L L DATAour | Data in Memory Output on Port H L H Z High Impedance Outputs NOTES: mare 1. Aot_~ Arai # AOR - AIOR. 2. if BUSY = L, data is not written. 3. if BUSY = L, data may not be valid, see two and topo timing. 4. 'H = Vin, U = Vi, 'X' = DON'T CARE, '2Z' = HIGH IMPEDANCE Truth Table Il. Interrupt Flag Left Port Right Port Ri. CE OEL AtoL-Aot INTL RiWR CER OER Ator-Aor INTR Function L L X 7FF X X X X X L? | Set Right INTr Flag x x x x X x L L 7FF H | Reset Right INTR Flag X X X X Le L L Xx 7FE X Set Left INTL Flag x L L 7FE H) x x x x x Reset Left INTi Flag NOTES: ve 1. Assumes BUSY: = BUSYr = Vi 2. if BUSY. = Vil, then No Change. 3. if BUSYr = Vil, then No Change. 4. 'H' = HIGH, 'L = LOW, 'X' = DON'T CARE Truth Table lll Address BUSY Arbitration Inputs Outputs AoL-Atot CE. | CER Aor-Ator BUSY." | BUSYe' Function X xX NO MATCH H H Normal H xX MATCH H H Normal Xx H MATCH H H Normal L L MATCH (2) 2) Write Inhibit? NOTES: 2691 ti 14 1. Pins BUSY: and BUSYR are both outputs for 71321 (Master), Both are inputs for 71421 (Slave). BUSYx outputs on the 71321 are open drain, not push-pull outputs. On slaves the BUSYx input internally inhibits writes. 2. Lif the inputs to the opposite port were stable prior to the address and enable inputs of this post. 'H if the pla the opposite port became stable after the address and enable inputs of this port. If taes is not met, either BUSY: or BUSYr = LOW will result. BUSY. and BUSYe outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSY; outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.ULM Ary ehcy Ti meen Os RL eRe T See High Speed 2K x 8 Duai-Part Static HAN with inieicupis Functional Description The IDT71321ADT71421 provides two ports with separate control, address and I/O pins that permitindependentaccess for reads or writes to any location in memory. The 1DT71321/1DT71421 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective portto go into a standby mode whennotselected (CE = Vix). Whena portis enabled, access tothe entire memory atrayis permitted. Interrupts Ifthe user chooses the interruptfunction, amemory location (mail box of message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FE (HEX), whereawriteis defined as the CEr = RWR = Vi per Truth Table il. Theleft portclearsthe interrupt by accessing address location 7F E when CEL = OEL= Vi, RW is a don'tcare. Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FF (HEX) andtoclear the interrupt flag (INTR), theright port must access the memory location 7FF. The message (8 bits) at 7FE or 7FF isuser-defined, sinceitisanaddressable SRAMiocation. Ifthe interruptfunction isnotused, address locations 7FE and 7FF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table Il for the interrupt operation. Busy Logic Busy Logic provides.a hardware indication thatboth ports of the RAM haveaccessed the same location atthe same time. Italso allows one of the twoaccesses to proceed and signals the other side thatthe RAMis "Busy. The BUSY pin can then be used to stall the access until the operation on the other side is compieted. Ifa write operation has been attempted from the side thatreceives a busy indication, the write signal is gatedinternally to prevent the write from proceeding. The use of BUSY Logicis notrequired or desirable for all applications. Insome cases itmay be useful tologically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of anillegal orillogical operation. in slave mode the BUSY pin operates solely as awrite inhibitinput pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented toa port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT71321 (Master) are open drain type outputs and require open drain resistors to operate. Ifthese SRAMs are nidustodl and Cammercial Jempercature Ranges being expanded in depth, then the BUSY indication for the resulting array does not require the use of an external AND gate. Width Expansion with Busy Logic Master/Slave Arrays When expanding an SRAM array in width while using BUSY logic, one master part is used to decide which side of the SRAM array will receive a BUSY indication, andto output that indication. Any number of slavesto be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus onthe IDT71321/1DT71421 SRAMs the BUSY pinis an outputif the partis Master (IDT7132), andthe BUSY pin is an input if the partis a Slave (IDT7142) as shown in Figure 3. fam 5y, MASTER GE SLAVE cE a Dual Port Dual Port Q| Sv o700 SRAM SRAM w BUSY: BUSYR BUSYL BUSYA 2702 i ba MASTER GE SLAVE CE Dual Port Duat Port SRAM SRAM BUSY. BUSYA BUSY. BUSYR + BUSY BUSYL 2691 dw 16 Figure 3. Busy and chip enable routing for both width and depth expansion with 10171321 (Master) and (Slave) 10171421 SRAMs. Iftwo or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibitthe write operations from one portfor part of a word and inhibitthe write operations fromthe other port for the other partofthe word. The BUSY arbitration, on a Master, is based on the chip enable and address signals only. !tignores whether an access is a read or write. in a master/slave array, both address and chip enable must be valid long enough for a BUSY flagtobe output from the master before the actual write pulse can beinitiated with either the RWW signal or the byteenables, Failure to observe this timing canresultin a glitched internal write inhibit signal and corrupted data in the slave.IDT71421S5/LA and IDT714215 ALA High Speed 2K x 8 Oual-Port Static RAM woth imenupt. EARCECES) arc Uc AALOMReLOLetisa aR eat: LAER -thal 912071 C0 CE ats ]e le 23) Ordering Information IDT XXXX A. _999 _A_ A Device Type Power Speed Package Process/ Temperature Range BLANK Commercial (0C to +70C) " Industrial (-40C to +85C) J 52-pin PLCC (J52-1) PF 64-pin TQFP (PN64-1) TE 64-pin STQFP (PP64-1) 20 Commercial Only 25 Commercial Only ; 35 Commercial Only Speed in nanoseconds 55 Commercial & Industrial LA Low Power | TSA Standard Power | 71321 16K (2K x 8-Bit) MASTER Dual-Port SRAM w/ interrupt | 71421 16K (2K x 8-Bit) SLAVE Dual-Port SRAM w/ Interrupt 2691 drw 17 NOTE: 1. Industrial temperature range is available in selected PLCC packages in standard power. For other speeds, packages and powers contact your sales office. Datasheet Document History 3/24/99: Initiated datasheet documenthistory Converted to new format Cosmetic typographical corrections Pages 2 and 3 Added additional notes to pin configurations CORPORATE HEADQUARTERS for SALES: for Tech Support: > i 2975 Stender Way 800-345-7015 or 408-727-6116 831-754-4613 Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com www.idt.com The IDT logo is a registered wademark of integrated Device Technology, Inc.