RT8290
1
DS8290-02 March 2011 www.richtek.com
General Description
The RT8290 is a high efficiency synchronous step-down
DC/DC converter that can deliver up to 3A output current
from 4.5V to 23V input supply . The RT8290's current mode
architecture and external compensation allow the transient
response to be optimized over a wide range of loads a nd
output capacitors. Cycle-by-cycle current limit provides
protection against shorted outputs and soft-start eliminates
input current surge during start-up. The RT8290 also
provides output under voltage protection and thermal
shutdown protection. The low current (<3μA) shutdown
mode provides output disconnection, enabling easy power
management in battery-powered systems. The RT8290
is awailable in a n SOP-8 (Exposed Pa d) pa ckage.
3A, 23V, 340kHz Synchronous Step-Down Converter
Features
zz
zz
z4.5V to 23V Input Voltage Range
zz
zz
z1.5% High Accuracy Feedback Voltage
zz
zz
z3A Output Current
zz
zz
zIntegrated N-MOSFET Switches
zz
zz
zCurrent Mode Control
zz
zz
zFixed Frequency Operation : 340kHz
zz
zz
zOutput Adjustable from 0.925V to 20V
zz
zz
zUp to 95% Efficiency
zz
zz
zProgrammable Soft-Start
zz
zz
zStable with Low-ESR Ceramic Output Capacitors
zz
zz
zCycle-by-Cycle Over Current Protection
zz
zz
zInput Under Voltage Lockout
zz
zz
zOutput Under Voltage Protection
zz
zz
zThermal Shutdown Protection
zz
zz
zThermally Enhanced SOP-8 (Exposed Pad) Package
zz
zz
zRoHS Compliant and Halogen Free
Applications
zIndustrial a nd Commercial Low Power System s
zComputer Peripherals
zLCD Monitors and TVs
zGreen Electronics/Applia nces
zPoint of Load Regulation of High-Performance DSPs,
FPGAs a nd ASICs.
Ordering Information
Note :
Richtek products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
Pin Configurations
(TOP VIEW)
SOP-8 (Exposed Pad)
SS
BOOT
VIN
GND
SW FB
EN
COMP
2
3
45
8
7
6
GND
9
Typical Application Circuit
VIN
EN
GND
BOOT
FB
SW
7
5
2
3
1L1
10µH
10nF
22µFx2
R1
26.1k
R2
10k
VOUT
3.3V/3A
10µFx2
VIN
4.5V to 23V RT8290
SS
8
CSS
0.1µF
COMP
CC
3.9nF RC
6.8k
CP
NC
6
4,
9 (Exposed Pad)
CBOOT
COUT
CIN
100k
REN
Package Type
SP : SOP-8 (Exposed Pad-Option 1)
RT8290
Lead Plating System
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with
Halogen Free and Pb free)
RT8290
2DS8290-02 March 2011www.richtek.com
Marking Information
RT8290GSP : Product Number
YMDNN : Date Code
Functional Pin Description
Pin No. Pin Name Pin Function
1 BOOT
Bootstrap for High Side Gate D river. Connect a 10nF or greater ceramic capacitor
from the BOOT pin to SW pin.
2 VIN
Voltage Supply Input. The input voltage range is from 4.5V to 23V. A suitable large
capacitor must be bypassed with this pin.
3 SW Switching Node. C onnect the output LC filter between the SW pin and output load.
4,
9 (Exposed Pad) GND Ground. The exposed pad must be soldered to a lar ge PCB and connected to
GND for maximum power dissipation.
5 FB
Output Voltage Feedback Input. The feedback reference voltage is 0.925V
typic ally.
6 COMP
Compensation Node. This pin is used for compensating the regulation control
loop. A series RC network is required to be connected from COMP to GND. If
needed, an additional capacitor can be connected from COMP to GND.
7 EN
Enable In put. A logic h igh enable s the co nv er te r, a lo gic low for ces the c on vert er
into sh utdo wn mo de re duc in g t h e su pply c urr en t to les s th an 3μA. For automatic
sta rtup , connect this pin to VIN with a 100kΩ pull u p re sist or.
8 SS
Soft-S tart Control Input. The soft-start period can be set by c onnecting a capacitor
from SS to G ND. A 0.1 μF capacitor sets the soft-start period to 15.5ms typically.
VOUT (V) R1 (kΩ) R2 (kΩ) RC (kΩ) CC (nF) L (μH) COUT (μF)
15 153 10 30 3.9 33 22 x 2
10 97.6 10 20 3.9 22 22 x 2
8 76.8 10 15 3.9 22 22 x 2
5 45.3 10 13 3.9 15 22 x 2
3.3 26.1 10 6.8 3.9 10 22 x 2
2.5 16.9 10 6.2 3.9 6.8 22 x 2
1.8 9.53 10 4.3 3.9 4.7 22 x 2
1.2 3 10 3 3.9 3.6 22 x 2
Table 1. Recommended Component Selection
RT8290
GSPYMDNN
RT8290ZSP : Product Number
YMDNN : Date Code
RT8290
ZSPYMDNN
RT8290
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DS8290-02 March 2011 www.richtek.com
Function Block Diagram
Absolute Maximum Ratings (Note 1)
zSupply Voltage, VIN ------------------------------------------------------------------------------------------ −0.3V to 25V
zSwitching Voltage, SW ------------------------------------------------------------------------------------- −0.3V to (VIN + 0.3V)
zBOOT V oltage------------------------------------------------------------------------------------------------- (VSW − 0.3V) to (VSW + 6V)
zThe Other Pins ------------------------------------------------------------------------------------------------ −0.3V to 6V
zPower Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) -------------------------------------------------------------------------------------- 1.333W
zPa ckage Thermal Resista nce (Note 2)
SOP-8 (Exposed Pad), θJA --------------------------------------------------------------------------------- 75°C/W
SOP-8 (Exposed Pad), θJC -------------------------------------------------------------------------------- 15°C/W
zJunction T emperature---------------------------------------------------------------------------------------- 150°C
zLead T emperature (Soldering, 10 sec.)------------------------------------------------------------------ 2 60°C
zStorage T emperature Range ------------------------------------------------------------------------------- −65°C to 150°C
zESD Susceptibility (Note 3)
HBM (Human Body Mode) --------------------------------------------------------------------------------- 2kV
MM (Ma chine Mode) ----------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 4)
zSupply Voltage, VIN ------------------------------------------------------------------------------------------ 4.5V to 23V
zEna ble Voltage, VEN ----------------------------------------------------------------------------------------- 0V to 5.5V
zJunction T emperature Range------------------------------------------------------------------------------- −40°C to 125°C
zAmbient T emperature Range------------------------------------------------------------------------------- −40°C to 85°C
VA
+
-
+
-
+
-
UV
Comparator
Oscillator
Foldback
Control
0.5V
Internal
Regulator
+
-
2.5V
Shutdown
Comparator
Current Sense
Amplifier
BOOT
VIN
GND
SW
FB
EN
COMP
3V
5k
VA VCC
Slope Comp
Current
Comparator
SS
7µA
VCC
+
-EA
0.925V
S
R
Q
Q
+
-
1.2V
Lockout
Comparator
+
100mΩ
85mΩ
RT8290
4DS8290-02 March 2011www.richtek.com
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of
JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the
package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Electrical Characteristics
Parameter Symbol Test Conditions Min Typ Max Unit
S hut down Su pply Cur re nt V EN = 0V -- 0. 3 3 μA
S upply Curr ent V EN = 3 V, VFB = 1V -- 0. 8 1. 2 mA
Feedback Voltage VFB 4.5V ≤ VIN ≤ 23V 0. 911 0. 925 0. 939 V
Error Amplifier Transconductance GEA ΔIC = ±10μA -- 940 -- μA/V
Hi gh Si de Switch O n-Resistance RDS(ON)1 -- 100 -- mΩ
Low Si de Sw i tch On- Resi s t ance R DS(ON)2 -- 85 -- mΩ
Hi gh Si de Sw itch Leakage Curr ent VEN = 0 V, VSW = 0V -- 0 10 μA
U pper Sw itch Curren t Lim i t Min. Duty Cycle
VBOOT − VSW = 4.8V -- 5.1 -- A
Lowe r Sw itch Curren t Lim i t Fro m Dra in t o Sourc e -- 1. 5 - - A
C O MP to C ur re nt S ense
Transconductance GCS -- 5.4 -- A/V
O scill ati on Frequency fOSC1 300 340 380 kHz
S hor t C ircuit O scil la tion Fr equency fOSC2 V
FB = 0V - - 100 -- kHz
Ma ximu m Duty Cy cle DMAX V
FB = 0.8V -- 90 -- %
Minimum On Time tON -- 100 -- ns
Logic-High VIH 2.7 -- --
E N I nput Thr eshold
Voltage Logic-Low VIL -- -- 0.4
V
Input U nder Vol tage Lockout
Threshold VUVLO V
IN Ri sin g 3.8 4. 2 4. 5 V
Input U nder Vol tage Lockout
Thre s hol d Hysteresis ΔVUVLO -- 320 -- mV
Soft -Start Curre n t ISS V
SS = 0V -- 6 -- μA
Soft -Start Period tSS C
SS = 0.1μF -- 15.5 -- ms
Therma l Sh ut down TSD -- 150 -- °C
(VIN = 12V, TA = 25°C unless otherwise specified)
RT8290
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DS8290-02 March 2011 www.richtek.com
Typical Operating Characteristics
Reference Voltage vs. Temperature
0.910
0.915
0.920
0.925
0.930
0.935
0.940
-50 -25 0 25 50 75 100 125
Tempera ture (°C)
Reference Vol tage ( V)
Reference Voltage vs. Input Voltage
0.920
0.922
0.924
0.926
0.928
0.930
0.932
4 6 8 1012141618202224
In put V oltage (V)
Reference Voltage (V)
Frequency vs. Temperature
300
305
310
315
320
325
330
335
340
345
350
-50 -25 0 25 50 75 100 125
Temperature (°C)
Frequency (kHz) 1
VIN = 4.5V
VIN = 12V
VIN = 23V
VOUT = 3.3V, IOUT = 0A
Frequency vs. Input Voltage
300
305
310
315
320
325
330
335
340
345
350
4 6 8 1012141618202224
In put Voltage ( V)
Fr equency (kHz) 1
VOUT = 3.3V, IOUT = 0A
Output Voltage vs. Output Current
3.300
3.303
3.305
3.308
3.310
3.313
3.315
3.318
3.320
0 0.5 1 1.5 2 2.5 3
Output Current (A)
Output Voltage (V)
VIN = 4.5V
VIN = 12V
VIN = 23V
VOUT = 3.3V
Efficiency vs. Output Current
0
10
20
30
40
50
60
70
80
90
100
00.511.522.53
Output Current (A)
Effici ency (%)
VIN = 4.5V
VIN = 12V
VIN = 23V
VOUT = 3.3V
RT8290
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Current Limit vs. Temperature
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
-50 -25 0 25 50 75 100 125
Temprature (°C)
Current Limit (A)
VOUT = 3.3V, VIN = 12V
Load Transient Response
Time (100μs/Div)
IOUT
(2A/Div)
VOUT
(200mV/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 0A to 3A
Time (5ms/Div)
Power On from VIN
IL
(2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 3A
VIN
(5V/Div)
VOUT
(2V/Div)
Power Off from VIN
Time (5ms/Div)
IL
(2A/Div)
VIN
(5V/Div)
VOUT
(2V/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 3A
Load Transient Response
Time (100μs/Div)
IOUT
(2A/Div)
VOUT
(200mV/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 1.5A to 3A
Switching Waveform
Time (1μs/Div)
VOUT
(10mV/Div)
VSW
(10V/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 3A
IL
(2A/Div)
RT8290
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DS8290-02 March 2011 www.richtek.com
Power On from EN
Time (10ms/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 3A
IOUT
(2A/Div)
VEN
(2V/Div)
VOUT
(2V/Div)
Power Off from EN
Time (10ms/Div)
IOUT
(2A/Div)
VEN
(2V/Div)
VOUT
(2V/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 3A
RT8290
8DS8290-02 March 2011www.richtek.com
Application Information
The RT8290 is a synchronous high voltage buck converter
that can support the input voltage range from 4.5V to 23V
a nd the output current ca n be up to 3A.
Output Voltage Setting
The resistive voltage divider allows the FB pin to sense
the output voltage a s shown in Figure 1.
Figure 1. Output Voltage Setting
The output voltage is set by a n external resistive voltage
divider a ccording to the following equation :
⎛⎞
+
⎜⎟
⎝⎠
OUT FB R1
V = V1
R2
where VFB is the feedback reference voltage (0.925V typ.).
External Bootstrap Diode
Connect a 10nF low ESR cera mic ca pa citor between the
BOOT pin and SW pin. This capacitor provides the gate
driver voltage for the high side MOSFET.
It is recommended to add an external bootstrap diode
between a n extern al 5V and the BOOT pin for ef ficiency
improvement when input voltage is lower than 5.5V or duty
ratio is higher than 65%. The bootstrap diode can be a
low cost one such as 1N4148 or BAT54.
The external 5V ca n be a 5V fixed input from system or a
5V output of the RT8290. Note that the external boot
voltage must be lower tha n 5.5V .
Figure 2. External Bootstra p Diode
Soft-Start
The RT8290 contains an external soft-start clamp that
gradually raises the output voltage. The soft-start timing
Inductor Selection
The inductor value and operating frequency determine the
ripple current according to a specific input and output
voltage. The ripple current ΔIL increases with higher VIN
and decreases with higher inductance.
OUT OUT
LIN
VV
I = 1
fL V
⎡⎤⎡ ⎤
Δ×−
⎢⎥⎢ ⎥
×
⎣⎦⎣ ⎦
Having a lower ripple current reduces not only the ESR
losses in the output ca pacitors but also the output voltage
ripple. High frequency with small ripple current can achieve
highest efficiency operation. However , it requires a large
inductor to a chieve this goal.
For the ripple current selection, the value of ΔIL = 0.2375
(IMAX) will be a rea sonable starting point. The largest ripple
current occurs at the highest VIN. To guarantee that the
ripple current stays below the specified maximum, the
inductor value should be chosen according to the following
equation :
OUT OUT
L(MAX) IN(MAX)
VV
L = 1
fI V
⎡⎤⎡ ⎤
×−
⎢⎥⎢ ⎥
×Δ
⎣⎦⎣ ⎦
Inductor Core Selection
The inductor type must be selected once the value for L
is known. Generally spea king, high efficiency converters
can not afford the core loss found in low cost powdered
iron cores. So, the more expensive ferrite or
mollypermalloy cores will be a better choice.
The selected inductance rather than the core size for a
fixed inductor value is the key for a ctual core loss. As the
inductance increa ses, core losses decrease. Unfortunately,
increase of the inductance requires more turns of wire
a nd therefore the copper losses will increase.
Ferrite designs are preferred at high switching frequency
due to the characteristics of very low core losses. So,
design goals can focus on the reduction of copper loss
and the saturation prevention.
can be programmed by the external capacitor between
SS pin and GND. The chip provides a 6μA charge current
for the extern al capa citor . If a 0.1μF capa citor is used to
set the soft-start, the period will be 15.5ms (typ.).
R1
R2
VOUT
RT8290
GND
FB
5V
10nF
RT8290
SW
BOOT
RT8290
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DS8290-02 March 2011 www.richtek.com
Ferrite core material saturates “hard”, which mea ns that
inductance collapses abruptly when the peak design
current is exceeded. The previous situation results in a n
abrupt increa se in inductor ripple current and consequent
output voltage ripple.
Do not allow the core to saturate!
Different core materi als and sha pes will cha nge the size/
current and price/current relationship of a n inductor .
T oroid or shielded pot cores in ferrite or permalloy materials
are small and do not radiate energy. However, they are
usually more expensive than the similar powdered iron
inductors. The rule for inductor choice mainly depends
on the price vs. size requirement and any radiated field/
EMI requirements.
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the
tra pezoidal current at the source of the high side MOSFET .
To prevent large ripple current, a low ESR input ca pacitor
sized for the maximum RMS current should be used. The
RMS current is given by :
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief.
Choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design.
For the input capacitor, a 10μF x 2 low ESR ceramic
capacitor is recommended. For the recommended
ca p a citor , plea se refer to ta ble 3 for more detail.
The selection of COUT is determined by the required ESR
to minimize voltage ripple.
Moreover, the amount of bulk capacitance is also a key
for COUT selection to ensure that the control loop is stable.
Loop stability can be checked by viewing the load transient
response as described in a later section.
The output ripple, ΔVOUT , is determined by :
OUT IN
RMS OUT(MAX) IN OUT
VV
I = I 1
VV
−
OUT L OUT
1
VIESR
8fC
⎡⎤
Δ≤Δ +
⎢⎥
⎣⎦
The output ripple will be highest at the maximum input
voltage since ΔIL increases with input voltage. Multiple
capacitors placed in parallel may be needed to meet the
ESR and RMS current handling requirement. Dry tantalum,
special polymer, aluminum electrolytic and ceramic
capacitors are all available in surface mount packages.
Special polymer capacitors offer very low ESR value.
However, it provides lower ca pacitance density than other
types. Although Tantalum capacitors have the highest
ca p a cita nce density, it is importa nt to only use types that
pass the surge test for use in switching power supplies.
Aluminum electrolytic ca pacitors have significantly higher
ESR. However, it can be used in cost-sensitive applications
for ripple current rating and long term reliability
considerations. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coefficient
and audible piezoelectric effects. The high Q of ceramic
ca pacitors with trace inductance can also lead to significant
ringing.
Higher values, lower cost ceramic capacitors are now
becoming available in smaller ca se sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However , care must
be taken when these capacitors are used at input and
output. When a ceramic capacitor is used at the input
a nd the power is supplied by a wall ada pter through long
wires, a load step at the output can induce ringing at the
input, VIN. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at VIN large enough to damage the
part.
Checking Transient Response
The regulator loop response can be checked by looking
at the load tra nsient response. Switching regulators ta ke
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an a mount
equal to ΔILOAD (ESR) and COUT also begins to be charged
or discharged to generate a feedba ck error signal for the
regulator to return VOUT to its steady-state value. During
this recovery time, VOUT can be monitored for overshoot or
ringing that would indicate a stability problem.
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Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125°C. The maximum
power dissipation depends on the thermal resistance of
IC pa ckage, PCB layout, the rate of surroundings airflow
and temperature difference between junction to a mbient.
The maximum power dissipation can be calculated by
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resista nce.
For recommended operating conditions specification of
RT8290, the maximum junction temperature is 125°C. The
junction to ambient thermal resistance θJA is layout
dependent. For SOP-8 (Exposed Pad) package, the
thermal resistance θJA is 75°C/W on the standard JEDEC
51-7 four-layers thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by following
formula :
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for
SOP-8 (Exposed Pad) pa ckage
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal
resistance θJA. For RT8290 pa ckage, the derating curve
in Figure 3 allows the designer to see the effect of rising
a mbient temperature on the maxi mum power dissipation.
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of the RT8290.
`Keep the tra ces of the main current paths a s short a n d
wide as possible.
`Put the input ca pacitor a s close as possible to the device
pins (VIN and GND).
`SW node is with high frequency voltage swing and
should be kept in a small area. Keep sensitive
components away from the SW node to prevent stray
ca pa citive noise pick-up.
`Pla ce the feedba ck components a s close to the FB pin
a nd COMP pin as possible.
`The GND pin and Exposed Pad should be connected to
a strong ground plane for heat sinking and noise
protection.
Figure 3. Derating Curve for RT8290 Package
VIN
GND
CIN
2
3
45
8
7
6
GND
SS
BOOT
VIN
GND
SW FB
EN
COMP
GND
CS
CP
CC
RC
SW
VOUT
COUT
L1
Input capacitor must be placed
as close to the IC as possible.
SW should be connected to inductor by
wide and short trace. Keep sensitive
components away from this trace.
The feedback
components must be
connected as close to
the device as possible.
R1
R2 VOUT
Figure 4. PCB Layout Guide
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0 25 50 75 100 125
Ambien t Tempera tu re ( °C )
Maximum Power Di ssipation (W ) 1
Four-Layer PCB
RT8290
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Table 3. Suggested Capacitors for CIN and COUT
Component Supplier Series Dimensions (mm)
TDK VLF10045 10 x 9.7 x 4.5
TAIYO YUDEN NR8040 8x8x4
Table 2. Suggested Inductors for Typical Application Circuit
Component Supplier Part No. Capacitance (μF) Case Size
MURATA GRM31CR61E106K 10 1206
TDK C3225X5R1E106K 10 1206
TAIYO YUDEN TMK316BJ106ML 10 1206
MURATA GRM31CR60J476M 47 1206
TDK C3225X5R0J476M 47 1210
TAIYO YUDEN EMK325BJ476MM 47 1210
MURATA GRM32ER71C226M 22 1210
TDK C3225X5R1C226M 22 1210
RT8290
12 DS8290-02 March 2011www.richtek.com
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com
Outline Dimension
A
B
J
F
H
M
C
D
I
Y
X
EXPOSED THERMAL PAD
(Bottom of Package)
8-Lead SOP (Exposed Pad) Plastic Package
Dimensions In Millimeters Dimensions In Inches
Symbol Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 4.000 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.510 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010
I 0.000 0.152 0.000 0.006
J 5.791 6.200 0.228 0.244
M 0.406 1.270 0.016 0.050
X 2.000 2.300 0.079 0.091
Option 1 Y 2.000 2.300 0.079 0.091
X 2.100 2.500 0.083 0.098
Option 2 Y 3.000 3.500 0.118 0.138
