TAS5751MDCAR - TEXAS INSTRUMENTS

July, 2014 − Rev. 6 1Publication Order Number:

PCA9306/D

PCA9306

Dual Bidirectional I2C-bus

and SMBus Voltage-Level

Translator

The PCA9306 is a dual bidirectional I2C−bus and SMBus

voltage−level translator with an enable (EN) input.

Features

•2−bit Bidirectional Translator for SDA and SCL Lines in

Mixed−Mode I2C−Bus Applications

•Standard−Mode, Fast−Mode, and Fast−Mode Plus I2C−Bus and

SMBus Compatible

•Less Than 1.5 ns Maximum Propagation Delay to Accommodate

Standard−Mode and Fast−Mode I2C−Bus Devices and Multiple

Masters

•Allows Voltage Level Translation Between:

♦1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2)

♦1.2 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2)

♦1.8 V Vref(1) and 3.3 V or 5 V Vbias(ref)(2)

♦2.5 V Vref(1) and 5 V Vbias(ref)(2)

♦3.3 V Vref(1) and 5 V Vbias(ref)(2)

•Provides Bidirectional Voltage Translation With No Direction Pin

•Low 3.5 W ON−State Connection Between Input and Output Ports

Provides Less Signal Distortion

•Open−Drain I2C−Bus I/O Ports (SCL1, SDA1, SCL2 and SDA2)

•5 V Tolerant I2C−Bus I/O Ports to Support Mixed−Mode Signal

Operation

•High−Impedance SCL1, SDA1, SCL2 and SDA2 Pins for

EN = LOW

•Lock−Up Free Operation

•Flow Through Pinout for Ease of Printed−Circuit Board Trace

Routing

•Packages Offered:

♦TSSOP−8, US8, UQFN8, UDFN8

•ESD Performance: 4000 V Human Body Model,

400 V Machine Model

•NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

•These are Pb−Free Devices

http://onsemi.com

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

TSSOP−8

DT SUFFIX

CASE 948AL

AAF

YWW-

AK MG

US8

US SUFFIX

CASE 493

UQFN8

MU SUFFIX

CASE 523AN AQ MG

AAF, AK, AQ, P = Specific Device Code

A = Assembly Location

Y = Year

WW = Work Week

M = Date Code

G= Pb−Free Package

UDFN8

1.45 x 1.0

CASE 517BZ

P M

PCA9306

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Function Description

The PCA9306 is a dual bidirectional I2C−bus and SMBus

voltage−level translator with an enable (EN) input, and is

operational from 1.0 V to 3.6 V (Vref(1)) and 1.8 V to 5.5 V

(Vbias(ref)(2)).

The PCA9306 allows bidirectional voltage translations

between 1.0 V and 5 V without the use of a direction pin. The

low ON−state resistance (Ron) of the switch allows

connections to be made with minimal propagation delay.

When E N i s HIGH, the translator switch is on, and the SCL1

and SDA1 I/O are connected to the SCL2 and SDA2 I/O,

respectively, allowing bidirectional data flow between

ports. When EN is LOW, the translator switch is off, and a

high−impedance state exists between ports.

The PCA9306 is not a bus buffer that provides both level

translation and physical capacitance isolation to either side

of the bus when both sides are connected. The PCA9306

only isolates both sides when the device is disabled and

provides voltage level translation when active.

The PCA9306 can be used to run two buses, one at

400 kHz operating frequency and the other at 100 kHz

operating frequency. If the two buses are operating at

different frequencies, the 100 kHz bus must be isolated

when the 400 kHz operation of the other bus is required. If

the master is running at 400 kHz, the maximum system

operating frequency may be less than 400 kHz because of

the delays added by the translator.

As with the standard I2C−bus system, pull−up resistors are

required to provide the logic HIGH levels on the translator’s

bus. The PCA9306 has a standard open−collector

configuration of the I2C−bus. The size of these pull−up

resistors depends on the system, but each side of the

translator must have a pull−up resistor. The device is

designed t o work with Standard−mode, Fast−mode and Fast

mode Plus I2C−bus devices in addition to SMBus devices.

The maximum frequency is dependent on the RC time

constant, but generally supports > 2 MHz.

When the SDA1 or SDA2 port is LOW, the clamp is in the

ON−state and a low resistance connection exists between the

SDA1 and SDA2 ports. Assuming the higher voltage is on

the SDA2 port, when the SDA2 port is HIGH, the voltage on

the SDA1 port is limited to the voltage set by VREF1. When

the SDA1 port is HIGH, the SDA2 port is pulled to the drain

pull−up supply voltage (Vpu(D)) by the pull−up resistors.

This functionality allows a seamless translation between

higher and lower voltages selected by the user without the

need for directional control. The SCL1/SCL2 channel also

functions as the SDA1/SDA2 channel.

All channels have the same electrical characteristics and

there is minimal deviation from one output to another in

voltage or propagation delay. This is a benefit over discrete

transistor voltage translation solutions, since the fabrication

of the switch is symmetrical. The translator provides

excellent ESD protection to lower voltage devices, and at the

same time protects less ESD−resistant devices.

FUNCTIONAL DIAGRAM

Figure 1. Logic Diagram

PCA9306

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PIN ASSIGNMENTS

Figure 2. TSSOP−8 / US8 Pinouts Figure 3. UQFN8 Pinout (Top Thru View)

Figure 4. UDFN8 Pinout (Top Thru View)

Table 1. PIN DESCRIPTION

Pin Description

GND Ground

VREF1 Low−voltage side reference supply voltage for SCL1 and SDA1

SCL1 Serial clock, low−voltage side; connect to VREF1 through a pull−up resistor

SDA1 Serial data, low−voltage side; connect to VREF1 through a pull−up resistor

SDA2 Serial data, high−voltage side; connect to VREF2 through a pull−up resistor

SCL2 Serial clock, high−voltage side; connect to VREF2 through a pull−up resistor

VREF2 High−voltage side reference supply voltage for SCL2 and SDA2

EN Switch enable input; connect to VREF2 and pull−up through a high resistor

Table 2. FUNCTION TABLE

Input EN (Note 1) Function

Low Disconnect

High SCL1 = SCL2; SDA1 = SDA2

1. EN is controlled by the Vbias(ref)(2) logic levels and should be at least 1 V higher than Vref(1) for best translator operation.

PCA9306

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Table 3. MAXIMUM RATINGS

Symbol Parameter Value Unit

Vref(1) Reference Voltage (Note 2) −0.5 to +7.0 V

Vbias(ref)(2) Reference Bias Voltage (Note 3) −0.5 to +7.0 V

VIN Input Voltage −0.5 to +7.0 V

VI/O Input / Output Pin Voltage −0.5 to +7.0 V

ICH DC Channel Current 128 mA

IIK DC Input Diode Current VIN < GND −50 mA

TSTG Storage Temperature Range −65 to +150 °C

TLLead Temperature, 1 mm from Case for 10 Seconds TL = 260 °C

TJJunction Temperature Under Bias TJ = 150 °C

qJA Thermal Resistance (Note 2) qJA = 150 °C/W

PDPower Dissipation in Still Air at 85°C PD = 833 mW

MSL Moisture Sensitivity Level 1

FRFlammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

VESD ESD Withstand Voltage Human Body Mode (Note 3)

Machine Model (Note 4)

Charged Device Model (Note 5)

> 4000

> 400

N/A

ILATCHUP Latchup Performance Above VCC and Below GND at 125 °C (Note 6) ±100 mA

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.

3. Tested to EIA / JESD22−A114−A.

4. Tested to EIA / JESD22−A115−A.

5. Tested to JESD22−C101−A.

6. Tested to EIA / JESD78.

Table 4. RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

Vref(1) Reference Voltage (1) (Note 7) VREF1 0 5.5 V

Vbias(ref)(2) Reference Bias Voltage (2) (Note 7) VREF2 0 5.5 V

VI/O Input / Output Pin Voltage SCL1, SDA1, SCL2, SDA2 0 5.5 V

VI(EN) Control Pin Input Voltage EN 0 5.5 V

Isw(pass) Pass Switch Current 0 64 mA

TAOperating Free−Air Temperature −55 +125 °C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

7. V(ref)(1) ≤ Vbias(ref)(2) −1 V for best results in level shifting applications.

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Table 5. DC ELECTRICAL CHARACTERISTICS

Symbol Parameter Conditions

TA = −555C to +1255C

Unit

Min Typ

(Note 8) Max

VIK Input Clamping Voltage II = −18 mA; VI(EN) = 0 V −1.2 V

IIH High−Level Input Current VI = 5 V; VI(EN) = 0 V 5mA

Ci(EN) EN Pin Input Capacitance VI = 3 V or 0 V 7.1 pF

Ci/O(off) OFF−State I/O Pin Capacitance

SCLn, SDAn VO = 3 V or 0 V; VI(EN) = 0 V 4 6 pF

Ci/O(on) ON−State I/O Pin Capacitance

SCLn, SDAn VO = 3 V or 0 V;

VI(EN) = 3 V 9.3 12.5 pF

RON ON−State Resistance(2)(3) SCLn, SDAn VI = 0 V; IO = 64 mA

VI(EN) = 4.5 V

VI(EN) = 3 V

VI(EN) = 2.3 V

VI(EN) = 1.5 V

2.4

3.0

3.8

9.0

5.0

6.0

8.0

VI = 2.4 V; IO = 15 mA

VI(EN) = 4.5 V

VI(EN) = 3 V 4.8

46 7.5

VI = 1.7 V; IO = 15 mA

VI(EN) = 2.3 V 40 80

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

8. All typical values are at TA = 25°C.

9. Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals at the indicated current through the switch.

ON−state resistance is determined by the lowest voltage of the two terminals.

10.Guaranteed by design.

Table 6. AC ELECTRICAL CHARACTERISTICS (Translating Down) − Values Guaranteed by Design

Symbol Parameter Test Condition Load

Condition

TA = −555C to +1255C

Unit

Min Max

SEE FIGURE 4 LOAD SWITCH AT S2 POSITION

tPLH Low−to−High Propagation De-

lay, from (input) SCL2 or

SDA2 to (output) SCL1 or

SDA1

VI(EN) = 3.3 V; VIH = 3.3 V;

VIL = 0 V; VM = 1.15 V CL = 15 pF 0 0.6 ns

CL = 30 pF 0 1.2

CL = 50 pF 0 2.0

tPHL High−to−Low Propagation De-

lay, from (input) SCL2 or

SDA2 to (output) SCL1 or

SDA1

CL = 15 pF 0 0.75

CL = 30 pF 0 1.5

CL = 50 pF 0 2.0

tPLH Low−to−High Propagation De-

lay, from (input) SCL2 or

SDA2 to (output) SCL1 or

SDA1

VI(EN) = 2.5 V; VIH = 2.5 V ;

VIL = 0 V; VM = 0.75 V CL = 15 pF 0 0.6 ns

CL = 30 pF 0 1.2

CL = 50 pF 0 2.0

tPHL High−to−Low Propagation De-

lay, from (input) SCL2 or

SDA2 to (output) SCL1 or

SDA1

CL = 15 pF 0 0.75

CL = 30 pF 0 1.5

CL = 50 pF 0 2.5

PCA9306

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Table 7. AC ELECTRICAL CHARACTERISTICS (Translating Up) − Values Guaranteed by Design

Symbol Parameter Test Condition Load Condition

TA =

−555C to +1255C

Unit

Min Max

SEE FIGURE 4 LOAD SWITCH AT S1 POSITION

tPLH Low−to−High Propagation De-

lay, from (input) SCL1 or

SDA1 to (output) SCL2 or

SDA2

VI(EN) = 3.3 V; VIH = 2.3 V ;

VIL = 0 V; VTT = 3.3 V;

VM = 1.15 V

RL = 300 W, CL = 15 pF 0 0.5 ns

RL = 300 W, CL = 30 pF 0 1.0

RL = 300 W, CL = 50 pF 0 1.75

tPHL High−to−Low Propagation De-

lay, from (input) SCL1 or

SDA1 to (output) SCL2 or

SDA2

RL = 300 W, CL = 15 pF 0 0.8

RL = 300 W, CL = 30 pF 0 1.65

RL = 300 W, CL = 50 pF 0 2.75

tPLH Low−to−High Propagation De-

lay, from (input) SCL1 or

SDA1 to (output) SCL2 or

SDA2

VI(EN) = 2.5 V; VIH = 1.5 V ;

VIL = 0 V; VTT = 2.5 V;

VM = 0.75 V

RL = 300 W, CL = 15 pF 0 0.5 ns

RL = 300 W, CL = 30 pF 0 1.0

RL = 300 W, CL = 50 pF 0 1.75

tPHL High−to−Low Propagation De-

lay, from (input) SCL1 or

SDA1 to (output) SCL2 or

SDA2

RL = 300 W, CL = 15 pF 0 1.0

RL = 300 W, CL = 30 pF 0 2.0

RL = 300 W, CL = 50 pF 0 3.3

A. Load Circuit B. Timing Diagram

S1 = translating up; S2 = translating down.

CL includes probe and jig capacitance.

All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 W; tr ≤ 2 ns; tf ≤ 2 ns.

The outputs are measured one at a time, with one transition per measurement.

Figure 5. Load Circuit for Outputs

from output under test

input

output

S2 (open)

VTT

VIH

VIL

VOH

VOL

ORDERING INFORMATION

Device Package Shipping†

PCA9306DTR2G TSSOP−8

(Pb−Free) 4000 / Tape & Reel

PCA9306AMUTCG UQFN−8

(Pb−Free) 3000 / Tape & Reel

PCA9306FMUTAG UDFN8

(Pb−Free) 3000 / Tape & Reel

PCA9306FMUTCG UDFN8

(Pb−Free) 3000 / Tape & Reel

PCA9306USG US8

(Pb−Free) 3000 / Tape & Reel

NLV9306USG*

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

PCA9306

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APPLICATION INFORMATION

1. The applied voltages at Vref(1) and Vpu(D) should be such that Vbias(ref)(2) is at least 1 V higher than Vref(1) for best translator

operation. Figure 6. Typical Application (Switch Always Enabled)

SCL1

SDA1

VREF1

GND

VREF2

SCL2

SDA2

PCA9306

200 kW

SCL

GND

SCL

SDA

GND

I2C−Bus

MASTER I2C−Bus

DEVICE

SDA

RPU RPU

VREF(1) = 1.8 V

(Note 1)

VPU(D) = 3.3 V

(Note 1)

VCC VCC

2. In the Enabled mode, the applied enable voltage and the applied voltage at Vref(1) should be such that Vbias(ref)(2) is at least 1 V

higher than Vref(1) for best translator operation.

Figure 7. Typical Application (Switch Enable Control)

SCL1

SDA1

VREF1

GND

VREF2

SCL2

SDA2

PCA9306

200 kW

SCL

SDA

GND

SCL

SDA

GND

VCC VCC

VREF(1) = 1.8 V

(Note 2)

VPU(D) = 3.3 V

RPU RPU

3.3 V Enable Signal (Note 2)

ONOFF

I2C−Bus

MASTER I2C−Bus

DEVICE

Bidirectional Translation

For the bidirectional clamping configuration (higher

voltage to lower voltage or lower voltage to higher voltage),

the EN input must be connected to VREF2 and both pins

pulled to HIGH side Vpu(D) through a pull−up resistor

(typically 200 kW). This allows VREF2 to regulate the EN

input. A filter capacitor on VREF2 is recommended. The

I2C−bus master output can be totem−pole or open−drain

(pull−up resistors may be required) and the I2C−bus device

output can be totem−pole or open−drain (pull−up resistors

are required to pull the SCL2 and SDA2 outputs to Vpu(D)).

However, if either output is totem−pole, data must be

unidirectional or the outputs must be 3−stateable and be

controlled by some direction−control mechanism to prevent

HIGH−to−LOW contentions in either direction. If both

outputs are open−drain, no direction control is needed.

The reference supply voltage (Vref(1)) is connected to the

processor core power supply voltage. When VREF2 is

connected through a 200 kW resistor to a 3.3 V to 5.5 V

Vpu(D) power supply, and Vref(1) is set between 1.0 V and

(Vpu(D) − 1 V), the output of each SCL1 and SDA1 has a

maximum output voltage equal to VREF1, and the output of

each SCL2 and SDA2 has a maximum output voltage equal

to Vpu(D).

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Table 8. APPLICATION OPERATING CONDITIONS Refer to Figure 6.

Symbol Parameter Conditions Min Typ(1) Max Unit

Vbias(ref)(2) Reference Bias Voltage (2) Vref(1) + 0.6 2.1 5 V

VI(EN) EN Pin Input Voltage Vref(1) + 0.6 2.1 5 V

Vref(1) Reference Voltage (1) 0 1.5 4.4 V

Isw(pass) Pass Switch Current 14 mA

Iref Reference Current Transistor 5 mA

Tamb Ambient Temperature Operating in free−air −55 +125 °C

11.All typical values are at Tamb = 25 °C.

Sizing Pull−up Resistor

The pull−up resistor value needs to limit the current

through the pass transistor when it is in the ON state to about

15 mA. This ensures a pass voltage of 260 mV to 350 mV.

If the current through the pass transistor is higher than

15 mA, the pass voltage also is higher in the ON state. To set

the current through each pass transistor at 15 mA, the

pull−up resistor value is calculated as:

RPU +

VPU(D) *0.35 V

0.015 A (eq. 1)

The following table summarizes resistor reference

voltages and currents at 15 mA, 10 mA, and 3 mA. The

resistor values shown in the +10% column or a larger value

should be used to ensure that the pass voltage of the

transistor would be 350 mV or less. The external driver must

be able to sink the total current from the resistors on both

sides o f the PCA9306 device at 0.175 V, although the 15 mA

only applies to current flowing through the PCA9306

device.

Table 9. PULLUP RESISTOR VALUES Calculated for VOL = 0.35 V; assumes output driver VOL = 0.175 V at stated current.

Vpu(D)

Pullup Resistor Value (W)

15 mA 10 mA 3 mA

Nominal +10% (Note 12) Nominal +10%(1) Nominal +10% (Note 12)

5 V 310 341 465 512 1550 1705

3.3 V 197 217 295 325 983 1082

2.5 V 143 158 215 237 717 788

1.8 V 97 106 145 160 483 532

1.5 V 77 85 115 127 383 422

1.2 V 57 63 85 94 283 312

12.+10% to compensate for VCC range and resistor tolerance.

Maximum Frequency Calculation

The maximum frequency is totally dependent upon the

specifics of the application and the device can operate >

33 MHz. Basically, the PCA9306 behaves like a wire with

the additional characteristics of transistor device physics

and should be capable of performing at higher frequencies

if used correctly.

Here are some guidelines to follow that will help

maximize the performance of the device:

•Keep trace length to a minimum by placing the

PCA9306 close to the processor.

•The trace length should be less than half the time of

flight to reduce ringing and reflections.

•The faster the edge of the signal, the higher the chance

for ringing.

•The higher the drive strength (up to 15 mA), the higher

the frequency the device can use.

In a 3.3 V to 1.8 V direction level shift, if the 3.3 V side

is being driven by a totem pole type driver no pull−up

resistor i s needed on the 3.3 V side. The capacitance and line

length of concern is on the 1.8 V side since it is driven

through the ON resistance of the PCA9306. If the line length

on the 1.8 V side is long enough there can be a reflection at

the chip/terminating end of the wire when the transition time

is shorter than the time of flight of the wire because the

PCA9306 looks like a high−impedance compared to the

wire. If the wire is not too long and the lumped capacitance

is not excessive the signal will only be slightly degraded by

the series resistance added by passing through the PCA9306.

If the lumped capacitance is large the rise time will

deteriorate, the fall time is much less affected and if the rise

time is slowed down too much the duty cycle of the clock

will be degraded and at some point the clock will no longer

be useful. So the principle design consideration is to

minimize the wire length and the capacitance on the 1.8 V

side for the clock path. A pull−up resistor on the 1.8 V side

can also be used to trade a slower fall time for a faster rise

time and can also reduce the overshoot in some cases.

PCA9306

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PACKAGE DIMENSIONS

TSSOP8, 4.4x3

CASE 948AL

ISSUE O

E1 E

TOP VIEW

SIDE VIEW END VIEW

L1 L

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-153.

SYMBOL

MIN NOM MAX

0º 8º

0.05

0.80

0.19

0.09

0.50

2.90

6.30

4.30

0.65 BSC

1.00 REF

1.20

0.15

1.05

0.30

0.20

0.75

3.10

6.50

4.50

0.90

0.60

3.00

6.40

4.40

PCA9306

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PACKAGE DIMENSIONS

US8

CASE 493−02

ISSUE B

DIM

AMIN MAX MIN MAX

INCHES

1.90 2.10 0.075 0.083

MILLIMETERS

B2.20 2.40 0.087 0.094

C0.60 0.90 0.024 0.035

D0.17 0.25 0.007 0.010

F0.20 0.35 0.008 0.014

G0.50 BSC 0.020 BSC

H0.40 REF 0.016 REF

J0.10 0.18 0.004 0.007

K0.00 0.10 0.000 0.004

L3.00 3.20 0.118 0.126

M0 6 0 6

N5 10 5 10

P0.23 0.34 0.010 0.013

R0.23 0.33 0.009 0.013

S0.37 0.47 0.015 0.019

U0.60 0.80 0.024 0.031

V0.12 BSC 0.005 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION “A” DOES NOT INCLUDE MOLD

FLASH, PROTRUSION OR GATE BURR.

MOLD FLASH. PROTRUSION AND GATE

BURR SHALL NOT EXCEED 0.140 MM

(0.0055”) PER SIDE.

4. DIMENSION “B” DOES NOT INCLUDE

INTER−LEAD FLASH OR PROTRUSION.

INTER−LEAD FLASH AND PROTRUSION

SHALL NOT E3XCEED 0.140 (0.0055”) PER

SIDE.

5. LEAD FINISH IS SOLDER PLATING WITH

THICKNESS OF 0.0076−0.0203 MM.

(300−800 “).

6. ALL TOLERANCE UNLESS OTHERWISE

SPECIFIED ±0.0508 (0.0002 “).

SEATING

DETAIL E

NR 0.10 TYP

−Y−

−X−

−T−

DETAIL E

0.10 (0.004) XY

T0.10 (0.004)

____

PLANE

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ǒmm

inchesǓ

SCALE 8:1

3.8

0.15

0.50

0.0197

1.0

0.0394

0.30

0.012

1.8

0.07

PCA9306

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PACKAGE DIMENSIONS

ÉÉ

UQFN8, 1.6x1.6, 0.5P

CASE 523AN

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.15 AND

0.30 mm FROM THE TERMINAL TIP.

BOTTOM VIEW

0.10 B

0.05

CNOTE 3

0.10 C

PIN ONE

REFERENCE

TOP VIEW

0.10 C

(A3)

0.05 C

CSEATING

PLANE

SIDE VIEW

DIM MIN MAX

MILLIMETERS

A0.45 0.60

A1 0.00 0.05

A3 0.13 REF

b0.15 0.25

D1.60 BSC

L1 −−− 0.15

E1.60 BSC

e0.50 BSC

L0.35 0.45

DETAIL A

ÇÇ

ÉÉ

DETAIL B

OPTIONAL

MOLD CMPD

EXPOSED Cu

CONSTRUCTION

OPTIONAL

CONSTRUCTION

DETAIL B

DET AIL A

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

PITCH

0.35

DIMENSIONS: MILLIMETERS

0.25

1.70

0.50

L3 0.25 0.35

(0.10) (0.15)

0.53

PCA9306

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PACKAGE DIMENSIONS

ÉÉ

UDFN8, 1.45x1, 0.35P

CASE 517BZ

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.20 MM FROM TERMINAL TIP.

4. PACKAGE DIMENSIONS EXCLUSIVE OF

BURRS AND MOLD FLASH.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

RECOMMENDED

DIM MIN MAX

MILLIMETERS

A0.45 0.55

A1 0.00 0.05

A3 0.13 REF

b0.15 0.25

D1.45 BSC

E1.00 BSC

e0.35 BSC

L0.25 0.35

L1 0.30 0.40

A B

0.10 C

PIN ONE

REFERENCE

TOP VIEW

0.10 C

0.05 C

CSEATING

PLANE

SIDE VIEW

BOTTOM VIEW

L7X

e/2

DIMENSIONS: MILLIMETERS

0.22

0.48 8X

1.18

0.53 PITCH

0.35

PKG

OUTLINE

0.10 B

0.05

CNOTE 3

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