AS4C64M16D2B-25BCN Revision History 1Gb AS4C64M16D2B-25BCN 84 ball FBGA PACKAGE Revision Rev 1.0 Details Preliminary datasheet Date Apr. 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Features Description - The AS4C64M16D2B-25BCN is an eight bank DDR DRAM organized as 8 banks x 8Mbit x 16 (168). The AS4C64M16D2B-25BCN achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is designed to comply with the following key DDR2 SDRAM features:(1) posted CAS with additive latency, (2) write latency = read latency-1, (3) On Die Termination. All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O s are synchro-nized with a pair of bidirectional strobes (DQS, DQS) in a source synchronous fashion. Operating the eight memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. High speed data transfer rates with system frequency up to 400 MHz - 8 internal banks for concurrent operation - 4-bit prefetch architecture - Programmable CAS Latency: 3, 4 ,5 , 6 and 7 - Programmable Additive Latency:0, 1, 2, 3 , 4, 5 and 6 - Write Latency = Read Latency -1 - Programmable Wrap Sequence: Sequential or Interleave - Programmable Burst Length: 4 and 8 - Automatic and Controlled Precharge Command - Power Down Mode - Auto Refresh and Self Refresh - Refresh Interval: 7.8 us at 0oC Tcase 85oC, 3.9 us at 85oC < Tcase 105oC - ODT (On-Die Termination) - Weak Strength Data-Output Driver Option - Bidirectional differential Data Strobe (Single-ended datastrobe is an optional feature) - On-Chip DLL aligns DQ and DQs transitions with CK transitions - DQS can be disabled for single-ended data strobe - Differential clock inputs CK and CK - JEDEC Power Supply 1.8V 0.1V - VDDQ =1.8V 0.1V - Available in 84-ball FBGA for x16 component - RoHS compliant PASR Partial Array Self Refresh tRAS lockout supported Table 1. Ordering Information Part Number Org Temperature MaxClock (MHz) Package AS4C64M16D2B-25BCN 64Mx16 Commercial 0C to +95C 400 MHz 84-ball FBGA Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency DDR2-800 400 MHz 5 Confidential - 2 of 69 - tRCD (ns) 12.5 tRP (ns) 12.5 Rev.1.0 April 2017 AS4C64M16D2B-25BCN 64Mx16 DDR2 PIN CONFIGURATION (Top view: see balls through package) 8 9 2 VD D NC VS S A VSS Q UD QS VD DQ DQ1 4 VSSQ UDM B UDQS VS SQ DQ1 5 VD DQ DQ9 VD DQ C VDD Q DQ8 VD DQ DQ1 2 VSSQ DQ1 1 D DQ10 VS SQ DQ1 3 VD D NC VS S E VSS Q LD QS VD DQ DQ6 VSSQ LD M F LD QS VS SQ DQ7 VD DQ DQ1 VD DQ G VDD Q DQ0 VD DQ DQ4 VSSQ DQ3 H DQ2 VS SQ DQ5 VD DL VRE F VS S J VSS DL CK VD D CKE WE K RA S CK ODT BA 0 BA1 L CAS CS A1 0/AP A1 M A2 A0 A3 A5 N A6 A4 A7 A9 P A11 A8 A1 2 NC R NC NC BA2 VS S VDD Confidential 7 3 1 - 3 of 69 - VD D VS S Rev.1.0 April 2017 AS4C64M16D2B-25BCN Signal Pin Description Pin Type Function CK, CK Input The system clock input. All inputs except DQs and DMs are sampled on the rising edge of CK. CKE Input Activates the CK signal when high and deactivates the CK signal when low, thereby initiates either the Power Down mode, or the Self Refresh mode. CS Input CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE Input When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. A0 - A12 Input During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge . During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled at the rising clock edge.CAn depends on the SDRAM organization: 64M x 16 DDR CAn = CA9 In addition to the column address, A10(=AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10(=AP) is used in conjunction with BA0, BA1and BA2 to control which bank(s) to precharge. If A10 is high, all eight banks will be precharged simultaneously regardless of state of BA0 , BA1 and BA2. BA0-BA2 Input DQx Input/ Output Data Input/Output pins operate in the same manner as on conventional DRAMs. DQ0-DQ15. DQS, (DQS) LDQS, (LDQS) UDQS, (UDQS) RDQS, (RDQS) Input/ Output Data Strobe, output with read data, input with write data. Edge-aligned with read data, centered in write data. For x16 device, LDQS corresponds to the data on DQ0-DQ7; UDQS coresponds to the data on DQ8-DQ15. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode or paired with optional complimentary signals DQS, LDQS, UDQS, and RDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables all complementary data strobe signals. DM, LDM,UDM Input DM is an input mask signal for write data. Input data is masked when DM is sampled high along with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading is designed to match that of DQ and DQS pins. LDM is DM for lower byte DQ0-DQ7 and UDM is DM for upper byte DQ8-DQ15. VDD, VSS Supply Power and ground for the input buffers and the core logic. VDDQ, VSSQ Supply Isolated power supply and ground for the output buffers to provide improved noise immunity. VREF Input VDDL, VSSDL Supply ODT Input Confidential Selects which bank is to be active. SSTL Reference Voltage for Inputs Isolated power supply and ground for the DLL to provide improved noise immunity. On Die Termination Enable. It enables termination resistance internal to the DRAM. ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM and LDM signal. ODT will be ignored if EMRS disable the function. - 4 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Simplified State Diagram Initialization Sequence CKEL OCD calibration Self Refreshing SRF CKEH PR Setting MRS EMRS MRS Idle REF All banks precharged CKEL ACT CKEH Activating CKEL Refreshing CKEL Precharge Power Down CKEL CKEL Active Power Down Automatic Sequence Command Sequence CKEH CKEL Bank Active Write Write Read Read WRA Writing RDA Read Write Reading RDA WRA RDA Writing with Autoprecharge PR, PRA PR, PRA PR, PRA Precharging Reading with Autoprecharge CKEL = CKE low, enter Power Down CKEH = CKE high, exit Power Down, exit Self Refresh ACT = Activate WR(A) = Write (with Autoprecharge) RD(A) = Read (with Autoprecharge) PR(A) = Precharge (All) MRS = (Extended) Mode Register Set SRF = Enter Self Refresh REF = Refresh Note: Use caution with this diagram. It is intended to provide a floorplan of the possible state transitions and the commands to control them, not all details. In particular situations involving more than one bank, enabling/disabling on-die termination, Power Down entry/exit - among other things - are not captured in full detail. Confidential - 5 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Basic Functionality Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Power up and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power-up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE below 0.2*VDDQ and ODT*1 at a low state (all other inputs may be undefined.) - VDD, VDDL and VDDQ are driven from a single power converter output, AND - VTT is limited to 0.95V max, AND - Vref tracks VDDQ/2. or - Apply VDD before or at the same time as VDDL. - Apply VDDL before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & Vref. at least one of these two sets of conditions must be met. 2. Start clock and maintain stable condition. 3. For the minimum of 200us after stable power and clock (CK, CK), then apply NOP or deselect & take CKE high. 4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns period. 5. Issue EMRS(2) command. (To issue EMRS(2) command, provide "Low" to BA0, "High" to BA1.) 6. Issue EMRS(3) command. (To issue EMRS(3) command, provide "High" to BA0 and BA1.) 7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to BA1 and A12.) 8. Issue a Mode Register Set command for "DLL reset". (To issue DLL reset command, provide "High" to A8 and "Low" to BA0-1) 9. Issue precharge all command. 10. Issue 2 or more auto-refresh commands. 11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating parameters without resetting the DLL. 12. At least 200 clocks after step 8, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD Exit command (A9=A8=A7=0) must be issued with other operating parameters of EMRS. Confidential - 6 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN 13. The DDR2 SDRAM is now ready for normal operation. *1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin. Initialization Sequence after Power Up tCH tCL CK /CK tIS CKE ODT Command PRE ALL NOP 400ns tRP PRE ALL MRS EMRS tMRD tMRD DLL ENABLE DLL RESET REF tRP MRS REF tRFC tRFC EMRS tMRD EMRS ANY CMD Enable OCD Defaults min. 200 Cycle OCD Default OCD EXIT Programming the Mode Register For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (tWR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance, additive CAS latency, single-ended strobe and ODT (On Die Termination) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register (MR) or Extended Mode Registers (EMR(#)) can be altered by re-executing the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array contents. 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LQQV DQGURXQGLQJXSDQRQLQWHJHUYDOXHWR WKHQH[WLQWHJHU :5>F\FOHV@ W:5 QV W&. QV 7KHPRGHUHJLVWHUPXVWEHSURJUDPPHGWRWKLVYDOXH7KLVLV DOVRXVHGZLWKW53WRGHWHUPLQHW'$/ Confidential - 8 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN DDR2 SDRAM Extended Mode Register Set EMRS(1) The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT value selection and additive latency. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power-up for proper operation. Extended mode register(1) is written by asserting low on CS, RAS, CAS, WE and high on BA0 and low on BA1, and control-ling rest of pins A0 ~ A12. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register. Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling reduced strength data-output drive. A3~A5 determines the additive latency. A2 and A6 are used for ODT value selection, A7~A9 are used for OCD control, A10 is used for DQS disable and A11 is used for RDQS enable. DLL Enable / Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. Confidential - 9 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN EMRS(1) Programming BA2 BA1 BA0 A15*1~A13 A12 0 0 0*1 1 A11 A10 A9 Qoff RDQS DQS A8 A7 A6 Rtt OCD program MRS mode A5 A4 A2 A1 A0 Additive latency Rtt D.I.C DLL A6 A2 Rtt (NOMINAL) 0 0 MRS 0 0 2'7'LVDEOH 0 1 EMRS(1) 0 1 75 ohm 1 0 EMRS(2) 1 0 1 1 (056 5HVHUYHG 1 1 150 ohm 50 ohm BA1 BA0 Address Field A3 Extended Mode Register A0 DLL En able 0 Enable 1 Disable A9 A8 A7 2&'RSHUDWLRQ A5 A4 A3 0 0 0 O&'H[LW 0 0 0 0 0 0 1 5HVHUYHG 0 0 1 1 0 1 0 5HVHUYHG 0 1 0 2 1 0 0 5HVHUYHG 0 1 1 3 1 1 1 (QDEOH2&'GHIDXOWV 1 0 0 4 1 0 1 1 1 0 1 1 1 Reserved $IWHU VHtting to default, OCD mode needs to be exited by setting A9-A7 WR A 12 Qoff (Optional) Additive Latency Outpu t Dri ver Impe denc e Control Driver Size 0 Output buffer enabled A1 1 Output buffer disabled 0 Normal 100% 1 Weak 60% 2XWSXWs disabled - DQs, DQSs, DQSs, 5'46 RDQS. This feature is used in conjunction with dimm IDD meaurements when IDDQ is not desired to be included. A10 0 DQS Enable 1 Disable A11 0 1 RDQS Enable Disable Enable ,I5'QS is enabled, the '0IXQFtion is disabled. RDQS is active for reads and don't care for writes. Strob e Fun cti on M atrix A11 (RDQS Enable) A10 (DQS Enable) RDQS/DM RDQS DQS DQS 0 (Disable) 0 (Enable) DM Hi-z DQS DQS 0 (Disable) 1 (Disable) DM Hi-z DQS Hi-z 1 (Enable) 0 (Enable) RDQS RDQS DQS DQS 1 (Enable) 1 (Disable) RDQS Hi-z DQS Hi-z A14 and A15 is reserved for future usage. Confidential - 10 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN 1 * EMRS(2) Programming: PASR BA2 BA1 BA0 A15 *2 ~ A13 1 0 0 A12 A11 A10 A9 0 *2 A8 A7 A6 A5 A4 A3 A2 0*1 A1 A0 Extended Mode Register(2) PASR A7 High Temperature Self Refresh rate enable 0 Commercial temperature default 1 Industrial temperature option: use if Tc exceeds 85 o C Address Field *1 : BA0 , BA1, and BA2 must be programmed to 0 when setting the mode register during initialization. *2 : A14 and A15 is reserved for future usage. O *3 : While Tc > 85 C, Double refresh rate (tREFI: 3.9us) is required, and to enter self refresh mode at this temperature range it must be required an EMRS command to change itself refresh rate. The PASR bits allows the user to dynamically customize the memory array size to the actual needs. This feature allows the device to reduce standby current by refreshing only the memory arrays that contain essential data.The refresh options are full array, one-half array, one-quarter array, three-fourth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map. Please see the following table. P ASR[2] P ASR[1] P ASR[0] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ACTIVE SECTION Full array 1/2 array (Banks 0,1, 2, 3) 1/4 array (Bank 0, 1) 1/8 array (Bank 0) 3/4 array (Banks 2,3,4,5,6,7) 1/2 array (Banks 4, 5, 6, 7) 1/4 array (Bank 6,7) 1/8 array (Bank 7) EMRS(3) Programming: Reserved*1 BA2 0 BA1 BA0 A15 *2 ~ A13 1 1 0 *2 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field Extended Mode Register(3) 0*1 *1 : EMRS(3) is reserved for future use and all bits except BA0, BA1, BA2 must be programmed to 0 when setting the mode register during initialization. *2 : A14 and A15 is reserved for future usage. Confidential - 11 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN ODT (on-die termination) On Die Termination (ODT) is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQS/DQS, RDQS/RDQS configurations via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function is supported for ACTIVE and STANDBY modes. ODT is turned off and not supported in SELF REFRESH mode. VDDQ sw1 Rval1 VDDQ VDDQ sw2 Rval2 sw3 Rval3 DRAM Input Buffer Input Pin Rval1 sw1 VSSQ Rval2 sw2 VSSQ Rval3 sw3 VSSQ Switch (sw1, sw2, sw3) is enabled by ODT pin. Selection among sw1, sw2, and sw3 is determined by "Rtt (nominal)" in EMR. Termination included on all DQs, DM, DQS, DQS, RDQS, and RDQS pins. Functional representation of ODT Confidential - 12 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN ODT Truth Table The ODT Truth Table shows which of the input pins are terminated depending on the state of address bit A10and A11 in the EMRS. To activate termination of any ofthese pins, the ODT function has to be enabled in the EMRS by address bits A6 and A2. EMRS Adress Bit A10 EMRS Adress Bit A11 DQ0~DQ7 X X DQ8~DQ15 X X LDQS X X LDQS 0 X UDQS X X UDQS 0 X LDM X X UDM X X Input Pin X=Don't Care 0=Signal Low 1=Signal High Confidential - 13 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN DC Electrical Characteristics and Operation Conditions : Parameter / Condition Symbol min. nom. max. Units Notes Rtt eff. impedance value for EMRS(A6,A2)= 0,1; 75 ohm Rtt1(eff) 60 75 90 ohm 1 Rtt eff. impedance value for EMRS(A6,A2)= 1,0; 150 ohm Rtt2(eff) 120 150 180 ohm 1 Rtt eff. impedance value for EMRS(A6,A2)= 1,1; 50 ohm Rtt3(eff) 40 50 60 ohm 1 Deviation of VM with respect to VDDQ/2 delta VM -6 +6 % 2 1) Measurement Definition for Rtt(eff) : Apply VIHac and VILac to test pin seperately, then measure current I(VIHac) and I(VILac) respectively Rtt(eff) = (VIHac - VILac) /( I(VIHac) - I(VILac)) 2) Measurement Definition for VM : Measure voltage (VM) at test pin (midpoint) with no load: delta VM = (( 2* VM / VDDQ) - 1 ) x 100% AC Electrical Characteristics and Operation Conditions : For speed 800 Symbol tAOND tAON tAONPD tAOFD tAOF tAOFPD Parameter / Condition ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Mode) min. max. Units 2 2 tCK tAC(min) tAC(max) + 0.7 ns 1 tAC(min) + 2 2 tCK + tAC(max) + 1 ns 3 2.5 2.5 tCK tAC(min) tAC(max) + 0.6 ns 2 tAC(min) + 2 2.5 tCK + tAC(max) + 1 ns 3 X tCK 4 tCK 4 tANPD ODT to Power Down Mode Entry Latency 3 tAXPD ODT Power Down Exit Latency 8 Notes 1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max. is when the ODT resistance is fully on. Both are measured from tAOND. 2) ODT turn off time min. is when the device stars to turn-off ODT resistance. ODT turn off time max. is when the bus is in high impedance. Both are measured from tAOFD. 3) For Standard Active Power-down - with MRS A12 ="0" - the non power-down timings ( tAOND, tAON, tAOFD and tAOF ) apply 4) tANPD and tAXPD define the timing limit when either Power Down Mode Timings (tAONPD, tAOFPD) or Non-Power Down Mode timings (tAOND, tAOFD) have to be applied. Confidential - 14 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN ODT Timing for Active / Standby (Idle) Mode and Standard Acti ve Power-Do wn Mode T-n T-5 T-6 T-4 T-3 T-2 T-1 T0 CK, CK tIS CKE tIS tAXPD tIS tIS ODT tANPD tAOND tAOFD Rtt tAON(min) DQ tAOF(min) tAOF(max) tAON(max) ODT1 1) Both ODT to Power Down Entry and Exit Latency timing parameter tANPD and tAXPD are met, therefore Non-Power Down Mode timings have to be applied. 2) ODT turn-on time (tAON,min) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max. (tAON,max) is when the ODT resistance is fully on. Both are measured from tAOND. 3) ODT turn off time min. ( tAOF,min) is when the device starts to turn off the ODT resistance.ODT turn off time max. (t AOF,max) is when the bus is in high impedance. Both are measured from tAOFD. ODT Timing for Precha rge Power-Down and Lo w Power Power -Down Mode T-7 T-5 T-6 T-4 T-3 T-2 T-1 T0 T1 CK, CK CKE ODT tAXPD tIS tIS tANPD tAOFPD,min tAOFPD,max DQ tAONPD,min tAONPD,max Rtt ODT2 1) Both ODT to Power Down Entry and Exit Latencies tANPD and tAXPD are not met, therefore Power-Down Mode timings have to be applied. Confidential - 15 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Bank Activate Command The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The bank addresses of BA0 - BA2 are used to select the desired bank. The row addresses A0 through A12 are used to determine which row to activate in the selected bank . The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command (with or without Auto-Precharge) on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay the R/W command which is internally issued to the device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0,1,2,3,4,5 and 6 are supported. Once a bank has been activated, it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined (tRC). The minimum time interval between Bank Active commands, to any other bank, is the Bank A to Bank B delay time (tRRD). B ank A c tivate C ommand C yc le: tR C D = 3, A L = 2, tR P = 3, tR R D = 2 T0 T1 T2 T3 T4 Tn Tn+1 T n+2 T n+3 CK, CK Internal R AS -C AS delay tR C Dmin. Addres s B ank A B ank A B ank B C ol. Addr. R ow Addr. R ow Addr. B ank A to B ank B delay tR R D. additive latency AL=2 R AS -R AS delay tR R D. C ommand B ank A Activate P os ted C AS R ead A B ank B Activate B ank B C ol. Addr. B ank A Addr. B ank B Addr. B ank A R ow Addr. B ank A P recharge B ank B P recharge B ank A Activate R ead A B egins P os ted C AS R ead B tR P R ow P recharge T ime (B ank A) tR AS R ow Active T ime (B ank A) tR C R ow C ycle T ime (B ank A) AC T Confidential - 16 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Read and Write Commands and Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock's rising edge. WE must also be defined at this time to determine whether the access cycle is a read operation ( WE high ) or a write operation ( WE low ). The DDR2 SDRAM provides a wide variety of fast access modes. The boundary of the burst cycle is restricted to specific segments of the page length. A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. Therefore the minimum CAS to CAS delay (tCCD) is a minimum of 2 clocks for read or write cycles. For 8 bit burst operation ( BL = 8 ) the minimum CAS to CAS delay (tCCD) is 4 clocks for read or write cycles. Burst interruption is allowed with 8 bit burst operation. For details see the "Burst Interrupt" - Section of this datasheet. Read Burst Timing Example : (CL = 3, AL = 0, RL = 3, BL = 4) T0 T1 T2 T3 T4 T5 T6 T7 T12 CK, CK C MD R E AD A NOP tC C D R E AD B NOP R E AD C NOP NO P NO P NO P NO P tC C D DQS , DQS DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout B 0 Dout B 1 Dout B 2 Dout B 3 Dout C 0 Dout C 1 Dout C 2 Dout C 3 RB Confidential - 17 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the RAS bank activate command (or any time during the RAS to CAS delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCDmin, then AL greater than 0 must be written into the EMRS. The Write Latency (WL) is always defined as RL - 1 (Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus CAS latency (RL=AL+CL). If a user chooses to issue a Read command after the tRCDmin period, the Read Latency is also defined as RL = AL + CL. Read followed by a write to the same bank, Activate to Read delay < tRCDmin: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4 -1 2 0 1 Activate Bank A R ead B ank A 3 4 5 6 7 8 9 10 11 12 CK, CK C MD W rite B ank A AL = 2 DQS , DQS WL = R L -1 = 4 CL = 3 tR C D R L = AL + C L = 5 DQ Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 " tR AC " P os tC AS 1 Read followed by a write to the same bank, Activate to Read delay < tRCDmin: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8 2 0 1 Activate B ank A R ead Ba nk A 3 4 5 6 7 8 9 10 11 12 CK, CK C MD DQS , DQS W rite Bank A AL = 2 W L = R L -1 = 4 CL = 3 tR C D R L = AL + C L = 5 DQ Dout0 Dout1 Dout2 Dout3 Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 " tR AC " P os tC AS 3 Confidential - 18 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN R ead followed by a write to the s a me bank , A c tiv ate to R ea d delay > tR C Dmin: A L = 1, C L = 3, R L = 4, W L = 3, B L = 4 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 CK, CK C MD R ead Bank A Activate B ank A W rite Bank A tR C D>tR C Dmin. WL = 3 DQS , DQS RL = 4 DQ Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 "tR AC " P ostC AS 5 Confidential - 19 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations ( write cycle ), or from memory locations ( read cycle ). The parameters that define how the burst mode will operate are burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burstmode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst length is programmable and defined by the addresses A0 ~ A2 of the MRS. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS. Seamless burst read or write operations are supported. Interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a read or write burst when burst length = 8 is used, see the "Burst Interruption" section of this datasheet. A Burst Stop command is not supported on DDR2 SDRAM devices. Burst Length and Sequence Burst Length 4 8 Starting Address ( A2 A1 A0 ) Sequential Addressing (decimal) Interleave Addressing (decimal) x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 Note: 1) Page length is a function of I/O organization and column addressing. 2) Order of burst access for sequential addressing is "nibble-based" and therefore different from SDR or DDR components. Confidential - 20 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS). The AL is defined by the Extended Mode Register Set (EMRS). Basic Burst Read Timing tC H tC L CK CK, CK CK DQS DQS , DQS DQS tR PST tR PR E DQ DO DO DO DO t DQS Qmax tQH tDQS Qmax don't care tQ H Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK C MD P os t C A S R EAD A NO P NOP NO P NO P NO P NO P NO P NOP <= tDQ S C K DQS , DQS AL = 2 DQ CL = 3 RL = 5 Dout A 0 Dout A 1 Dout A 2 Dout A 3 B R ead523 Confidential - 21 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Burst Read Operation: RL = 3 (AL = 0, CL = 3, BL = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK C MD R E AD A NO P NOP NO P NO P NO P NO P NO P NO P <= tDQ S C K DQS , DQS CL = 3 RL = 3 DQ's Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 BR ead303 B urs t R ead followed by B urs t W rite : R L = 5, W L = (R L -1) = 4, B L = 4 T0 T3 T1 T4 T5 T6 T7 T8 T9 CK, CK C MD P os ted C AS R E AD A NOP NO P P os ted C AS W R IT E A NOP NO P NO P NOP NOP B L/2 + 2 DQS , DQS WL = R L - 1 = 4 RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 Din A0 Din A1 Din A2 Din A3 BR B W 514 The minimum time from the burst read command to the burst write command is defined by a read-to-write turn-around time, which is BL/2 + 2 clocks. Confidential - 22 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN S eamles s B urs t R ead O pera tion : R L = 5, A L = 2, C L = 3, B L = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK C MD P os t C AS R E AD A NO P P ost C AS R E AD B NO P NO P NO P NO P NO P NO P DQS , DQS AL = 2 CL = 3 RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout B 0 Dout B 1 Dout B 2 Dout B 3 S B R 523 The seamless burst read operation is supported by enabling a read command at every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. Seamless Burst Read Operation : RL = 3, AL = 0, CL = 3, BL = 8 (non interrupting) T0 T1 T2 T3 T4 T5 T6 T7 T9 T8 CK, CK C MD P ost C AS R E AD A NO P NO P NO P P ost C AS R E AD B NO P NO P NO P NO NO P DQS , DQS CL = 3 DQ RL = 3 Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A4 Dout A7 Dout B 0 Dout B 1 Dout B 2 Dout B 3 Dou S B R _B L8 The seamless, non interrupting 8-bit burst read operation is supported by enabling a read command at every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. Confidential - 23 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Burst Write Command The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is named "write recovery time" (tWR) and is the time needed to store the write data into the memory array. tWR is an analog timing parameter (see the AC table in this specification) and is not the programmed value for WR in the MRS. Basic Burst Write Timing t DQSH t DQSL DQS DQS, DQS DQS t WPRE t WPST Din Din Din Din t DS t DH Burst Write Operation : RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 Tn CK, CK CMD Post CAS WRITE A NOP NOP NOP NOP NOP <= tDQSS DQS, DQS NOP Precharge Completion of the Burst Write tWR WL = RL-1 = 4 DQ NOP DIN A0 DIN A1 DIN A2 DIN A3 BW543 Confidential - 24 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Burst Write Operation : RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4 T0 T1 T2 T3 T4 T5 T6 Tm Tn CK, CK CMD Post CAS WRITE A NOP NOP NOP NOP <= tDQSS NOP Bank A Activate Completion of the Burst Write DQS, DQS tRP tWR WL = RL-1 = 2 DQ Precharge NOP DIN A0 DIN A1 DIN A2 DIN A3 BW322 Burst Write followed by Burst Read : RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T9 T8 CK, CK Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6 CMD NOP NOP NOP Post CAS READ A NOP DQS, DQS AL=2 tWTR WL = RL - 1 = 4 DQ NOP DIN A0 DIN A1 DIN A2 DIN A3 NOP NOP NOP CL=3 RL=5 BWBR The minimum number of clocks from the burst write command to the burst read command is (CL - 1) +BL/2 + tWTR where tWTR is the write-to-read turn-around time tWTR expressed in clock cycles. The tWTR is not a write recovery time (tWR) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array. Confidential - 25 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Seamless Burst Write Operation: RL=5, WL=4, BL=4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK C MD P ost C AS W R IT E A NO P P ost C AS W R IT E B NO P NO P NO P NO P NO P NO P DQS , DQS WL = R L - 1 = 4 DQ DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B 2 DIN B3 SBR The seamless burst write operation is supported by enabling a write command every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. Seamless Burst Write Operation: RL=3, WL=2, BL=8, noninterrupting T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK C MD W R IT E A NO P NOP NO P W R IT E B NOP NO P NOP NO P DQS , DQS WL = R L - 1 = 2 DQ DIN A0 DIN A1 DIN A2 DIN A3 DIN A4 DIN A5 DIN A5 DIN A7 DIN B 0 DIN B 1 DIN B 2 DIN B3 DIN B4 DIN B5 DIN S BW _B L8 The seamless, non interrupting 8-bit burst write operation is supported by enabling a write command at every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. Confidential - 26 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Write Data Mask Two write data mask inputs (LDM, UDM) for x16 components are supported on DDR2 SDRAMs, consistent with the implementation on DDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. Data mask is not used during read cycles. If DM is high during a write burst coincident with the write data, the write data bit is not written to the memory. Write Data Mask Timing t DQSH t DQSL DQS DQS, DQS DQS t WPRE DQ t WPST Din Din t DS Din Din t DH DM don't care Burst Write Operation with Data Mask : RL = 3 (AL = 0, CL = 3), WL = 2, tWR = 3 , BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 Tn CK, CK CMD WRITE A NOP NOP NOP NOP NOP NOP Bank A Activate Precharge <= tDQSS DQS, DQS WL = RL-1 = 2 DQ tWR tRP DIN A0 DIN A1 DIN A2 DIN A3 DM DM Confidential - 27 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Burst Interruption Interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions: 1. A Read Burst of 8 can only be interrupted by another Read command. Read burst interruption by a Write or Precharge Command is prohibited. 2. A Write Burst of 8 can only be interrupted by another Write command. Write burst interruption by a Read or Precharge Command is prohibited. 3. Read burst interrupt must occur exactly two clocks after the previous Read command. Any other Read burst interrupt timings are prohibited. 4. Write burst interrupt must occur exactly two clocks after the previous Write command. Any other Read burst interrupt timings are prohibited. 5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM. 6. Read or Write burst with Auto-Precharge enabled is not allowed to be interrupted. 7. Read burst interruption is allowed by a Read with Auto-Precharge command. 8. Write burst interruption is allowed by a Write with Auto-Precharge command. 9. All command timings are referenced to burst length set in the mode register. They are not referenced to the actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). Minimum Write to Precharge timing is WL + BL/ 2 + tWR, where tWR starts with the rising clock after the un-interrupted burst end and not form the end of the actual burst end. Read Burst Interrupt Timing Example : (CL = 3, AL = 0, RL = 3, BL = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK C MD R E AD A NO P R E AD B NO P NOP NO P NO P NO P NO P DQS , DQS DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout B 0 Dout B 1 Dout B 2 Dout B 3 Dout B 4 Dout B 5 Dout B 6 Dout B R BI Confidential - 28 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN W rite B urs t Interrupt T iming E xample : ( C L = 3, AL = 0, W L = 2, B L = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK C MD NO P W R IT E A NO P W R IT E B NOP NO P NO P NO P NO P DQS , DQS DQ Din A0 Din A1 Din A2 Din A3 Din B 0 Din B 1 Din B 2 Din B 3 Dout B 4 Din B 5 Din B 6 Din B 7 W BI Confidential - 29 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank independently or all banks simultaneously. Four address bits A10, BA2, BA1 and BA0 are used to define which bank to precharge when the command is issued. Bank Selection for Precharge by Address Bits A 10 BA0 B A1 B A2 P rec harge B ank(s ) A 10 BA0 B A1 B A2 P rec harge B ank(s ) LOW LOW LOW LOW B ank 0 only LOW HIG H LOW HIG H B ank 5 only LOW HIG H LOW LOW B ank 1 only LOW LOW HIG H HIG H B ank 6 only LOW LOW HIG H LOW B ank 2 only LOW HIG H HIG H HIG H B ank 7 only LOW HIG H HIG H LOW B ank 3 only HIG H Don't C are Don't C are Don't C are LOW LOW LOW HIG H B ank 4 only All B anks Burst Read Operation Followed by a Precharge The following rules apply as long as the tRTP timing parameter - Internal Read to Precharge Command delay time - is less or equal two clocks, which is the case for operating frequencies less or equal 266 Mhz (DDR2 400 speed sorts): Minimum Read to Precharge command spacing to the same bank = AL + BL/2 clocks. For the earliest possible precharge, the precharge command may be issued on the rising edge which is "Additive Latency (AL) + BL/2 clocks" after a Read Command, as long as the minimum tRAS timing is satisfied. A new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously: (1) The RAS precharge time (tRP) has been satisfied from the clock at which the precharge begins. (2) The RAS cycle time (tRCmin) from the previous bank activation has been satisfied. For operating frequencies higher than 266 MHz, tRTP becomes > 2 clocks and one additional clock cycle has to be added for the minimum Read to Precharge command spacing, which now becomes AL + BL/2 + 1 clocks. Confidential - 30 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Bu rs t Read Operati on Followed by Prech arg e: RL = 4 (AL = 1, CL = 3), BL = 4, tRTP <= 2 cl ocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP NOP NOP NOP Precharge Bank A Activate NOP NOP tRP AL + BL/2 clks DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 >=tRAS Dout A1 Dout A2 Dout A3 CL = 3 >=tRC >=tRTP Bu rs t Read Operati on Followed by Prech arg e: RL = 4 (AL = 1, CL = 3), BL = 8, tRTP <= 2 cl ocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP NOP NOP NOP Precharge AL + BL/2 clks Bank A Activate NOP NOP tRP DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 >=tRAS Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 CL = 3 >=tRC >=tRTP first 4-bit prefetch Confidential second 4-bit prefetch - 31 of 69 - BR-P413(8) Rev.1.0 April 2017 AS4C64M16D2B-25BCN Burst Read operation Followed by Precharge: RL=5(AL=2, CL=3), BL=4, tRTP<=2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK C MD P ost C AS R E AD A NOP NO P NO P NOP P recharge AL + B L/2 clks NOP B ank A Activate NOP tR P DQS , DQS CL = 3 AL = 2 RL = 5 DQ Dout A0 >=tR AS Dout A1 Dout A2 Dout A3 CL = 3 >=tR C >=tR T P B R -P 523 Burst Read operation Followed by Precharge: RL=6(AL=2, CL=4), BL=4, tRTP<=2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK C MD P ost C AS R E AD A NO P NO P P recharge A NOP AL + B L/2 clocks NO P NO P B ank A Activate NO P tR P DQS , DQS AL = 2 CL = 4 RL = 6 DQ Dout A0 >=tR AS Dout A1 Dout A2 Dout A3 CL = 4 >=tR C >=tR T P Confidential B R -P 624 - 32 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Burst Read Operation Followed by Precharge: RL=4, (AL=0, CL=4), BL=8, tRTP>2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD READ A NOP NOP NOP NOP Precharge AL + BL/2 clks + 1 Bank A Activate NOP NOP tRP DQS, DQS CL = 4 RL = 4 DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 >=tRAS >=tRTP first 4-bit prefetch Confidential BR-P404(8) second 4-bit prefetch - 33 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Burst Write followed by Precharge Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued. This delay is known as a write recovery time (t WR ) referenced from the completion of the burst write to the Precharge command. No Precharge command should be issued prior to the tWR delay, as DDR2 SDRAM does not support any burst interrupt by a Precharge command. tWR is an analog timing parameter (see the AC table in this datasheet) and is not the programmed value for tWR in the MRS. Burst Write followed by Precharge : WL = (RL - 1) = 3, BL = 4, tWR = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK C MD P os t C AS W R IT E A NO P NO P NO P NOP NOP P recharge A NOP NOP C ompletion of the B urs t Write DQS , DQS tW R WL =3 DQ DIN A0 DIN A1 DIN A2 DIN A3 BW -P 3 B urs t W rite followed by P rec ha rge : W L = (R L - 1) = 4, B L = 4, tW R = 3 T0 T1 T2 T3 T4 T5 T6 T7 T9 CK, CK C MD P os t C AS W R IT E A NO P NO P NO P NOP NO P NO P P recharge A C ompletion of the B urs t Write DQS , DQS tW R WL =4 DQ NO P DIN A0 DIN A1 DIN A2 DIN A3 B W -P 4 Confidential - 34 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN A uto-P rec harge Operation B efore a new row in an active bank can be opened, the a ctive bank mus t be precharged us ing either the P recharge C ommand or the Auto-P recha rge function. W hen a R ead or a Write C ommand is given to the DDR 2 S DR AM, the C AS timing accepts one extra addres s , column a ddres s A10, to a llow the active ba nk to automa tically begin precharge a t the earlies t pos s ible moment during the burs t read or write cycle. If A10 is low when the R ead or W rite C ommand is is sued, then normal R ead or Write burs t operation is executed and the bank remains active at the completion of the burs t s equence. If A10 is high when the R ead or Write C omma nd is is s ued, then the Auto-P recharge function is ena bled. During Auto-P recharge, a R ea d C omma nd will execute as normal with the exception that the active bank will begin to precharge internally on the rising edge which is C AS L atency (C L) clock cycles before the end of the rea d burs t. Auto-P recharge is als o implemented for Write C ommands.T he precharge operation enga ged by the Auto-P recharge command will not begin until the las t datga of the write burs t s equence is properly s tored in the memory array. T his feature allows the precharge operation to be pa rtially or completely hidden during burst rea d cycles (dependent upon C AS Latency) thus improving sys tem performance for random data acces s. T he R AS lockout circuit internally dela ys the P recharge operation until the a rray res tore operation has been completed s o that the Auto-P recharge comma nd may be is s ied with any read or write command. B urs t R ead with A uto-P rec harge If A10 is high when a R ead C ommand is is s ued, the R ead with Auto-P recharge function is engaged. T he DDR 2 S DR AM s tarts an Auto-P recharge operation on the ris ing edge which is (AL + B L/2) cycles la ter from the R ea d with AP command if tR AS (min) and tR T P are s atis fied. If tR AS (min) is not s atis fied at the edge, the s tart point of Auto-P recharge operation will be delayed until tR AS (min) is s atis fied. If tR T P (min) is not s atis fied a t the edge, the s tart point of Auto-precharge operation will be delayed until tR T P (min) is s atis fied. In cas e the internal precharge is pushed out by tR T P, tR P s tarts at the point where the interna l precharge happens (not a t the next ris ing clock edge after this event). S o for B L = 4 the minimum time from R ea d with Auto-P recharge to the next Activate command becomes AL + tR T P + tR P. F or B L = 8 the time from R ead with Auto-P recharge to the next Activate command is AL + 2 + tR T P + tR P. Note tha t both parameters tR T P a nd tR P have to be rounded up to the next integer value. In any event interna l precharge does not s tart earlier tha n two clocks after the las t 4-bit prefetch. A new bank active (command) may be is s ued to the sa me ba nk if the following two conditions are s atis fied s imultaneous ly: (1) T he R AS precharge time (tR P ) has been s atisfied from the clock at which the Auto-P recharge begins . (2) T he R AS cycle time (tR C ) from the previous bank activation has been s atis fied. Confidential - 35 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN B urs t R ead with A uto-P rec harge followed by an ac tivation to the S ame B ank (tR C L imit) R L = 5 (A L = 2, C L = 3), B L = 4, tR T P <= 2 c loc ks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK C MD P osted C AS R E AD w/AP NO P NOP NO P NO P NO P NO P NOP B ank Activate A10 ="high" AL + B L/2 Auto-P recharge B egins DQS , DQS AL = 2 CL = 3 tR P RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 tR AS tR C min. BR -AP 5231 B urs t R ead with A uto-P rec harge followed by an A c tivation to the S ame B ank (tR A S L imit): R L = 5 ( A L = 2, C L = 3), B L = 4, tR T P <= 2 c loc ks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK C MD P osted C AS R E AD w/AP NO P NOP NO P NO P NO P B ank Activate NO P NOP A10 ="high" tR AS (min) Auto-P recharge B egins DQS , DQS AL = 2 CL = 3 tR P RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 tR C B R -AP 5232 Confidential - 36 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Burst Read with Auto-Precharge followed by an Activation to the Same Bank: RL=4(AL=1, CL=3), BL=8, tRTP<=2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK C MD P os ted C AS R E AD w/AP NO P NO P NOP A10 ="high" NO P NOP NO P AL + B L/2 NOP B ank Activate tR P Auto-P recharge B egins DQS , DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 >= tR TP B R -AP 413(8)2 second 4-bit prefetch firs t 4-bit prefetch Burst Read with Auto-Precharge followed by an Activation to the Same Bank: RL=4(AL=1, CL=3), BL=4, tRTP>2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK C MD P os ted C AS R E AD w/AP A10 ="high" NO P NO P NOP NO P NOP NO P B ank Activate NO P AL + tR TP + tR P Auto-P recharge B egins DQS , DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 Dout A1 Dout A2 Dout A3 tR P tR TP B R -AP 4133 firs t 4-bit prefetch Confidential - 37 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN B urs t W rite with A uto-P rec harge If A10 is high when a Write C ommand is is s ued, the W rite with Auto-P recharge function is engaged. T he DDR 2 S DR AM automa tically begins precharge operation after the completion of the write burst plus the write recovery time delay (W R ), programmed in the MR S regis ter, as long a s tR AS is s atis fied. T he bank undergoing Auto-P recharge from the completion of the write burst may be reactiva ted if the following two conditions are s atis fied. (1) T he las t data-in to bank a ctivate delay time (tDAL = W R + tR P ) has been s atis fied. (2) T he R AS cycle time (tR C ) from the previous bank activation has been s atis fied. In DDR 2 S DR AMs the write recovery time delay (W R ) has to be programmed into the MR S mode regis ter. As long as the analog tW R timing parameter is not violated, W R can be programmed between 2 and 6 clock cycles. Minimum W rite to Activate comma nd s pacing to the s ame bank = W L + B L /2 + tDA L . E xamples : B urs t W rite with A uto-P rec harge (tR C L imit) : W L = 2, tDA L = 6 (W R = 3, tR P = 3) , B L = 4 T0 T1 T2 T3 T4 T5 T6 T7 CK, CK C MD W R IT E A NO P A10 ="high" NO P NO P NO P NOP NOP C ompletion of the B urst W rite NO P B ank A Activate Auto-P recharge B egins DQS , DQS WR W L = R L-1 = 2 tR P tDAL DQ DIN A0 DIN A1 DIN A2 DIN A3 tR C min. >=tR AS min. B W -AP 223 Confidential - 38 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Burst Write with Auto-Precharge (WR+tRP Limit): WL=4, tDAL=6(WR=3, tRP=3), BL=4 T0 T3 T4 T5 T6 NO P NO P NO P T7 T8 T 12 T9 CK, CK C MD P os ted C AS W R IT E A A10 ="high" NOP NO P NO P B ank A Activate NO P C ompletion of the B urst W rite Auto-P recharge B egins DQS , DQS tR P WR W L = R L-1 = 4 tDAL DQ DIN A0 DIN A1 DIN A2 DIN A3 >=tR C >=tR AS BW -AP 423 Confidential - 39 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Concurrent Auto-Precharge DDR2 devices support the "concurrent Auto-Precharge" feature. A read with Auto-Precharge enabled, or a write with Auto-Precharge enabled, may be followed by any command to the other bank, as long as that command does not interrupt the read or write data transfer, and all other related limitations (e.g. contention between Read data and Write data must be avoided externally and on the internal data bus. The minimum delay from a read or write command with Auto-Precharge enabled, to a command to a different bank, is summarized in the table below. As defined, the WL = RL - 1 for DDR2 devices which allows the command gap and corresponding data gaps to be minimized. F rom C ommand W R IT E w/AP To C ommand (different bank , non-interrupting command) Minimum Delay with C oncurrent A uto-P recharge S upport Units R ead or R ead w/AP (C L -1) + (B L /2) + tWT R tC K Write ot W rite w/AP B L /2 tC K 1 tC K R ead or R ead w/AP B L /2 tC K Write or Write w/AP B L/2 + 2 tC K 1 tC K P recharge or Activate R ead w/AP P recharge or Activate Confidential - 40 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Refresh SDRAMs require a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of two ways : by an explicit Auto-Refresh command, or by an internally timed event in Self-Refresh mode. Dividing the number of device rows into the rolling 64 ms interval defined the average refresh interval tREFI, which is a guideline to controlles for distributed refresh timing. For example, a 512Mbit DDR2 SDRAM has 8192 rows resulting in a tREFI of 7,8 s. Auto-Refresh Command Auto-Refresh is used during normal operation of the DDR2 SDRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an Auto-Refresh command. The DDR2 SDRAM requires Auto-Refresh cycles at an average periodic interval of tREFI (maximum). When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the AutoRefresh mode. All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Auto-Refresh Command can be applied. An internal address counter supplies the addresses during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto-Refresh Command and the next Activate Command or subsequent Auto-Refresh Command must be greater than or equal to the Auto-Refresh cycle time (tRFC). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any Auto-Refresh command and the next Auto-Refresh command is 9 * tREFI. T0 T1 T2 T3 CK, CK "high" CKE C MD P recharge NO P > = tR F C > = tR F C > = tR P NOP AUT O R E FR E SH NO P AUT O R E FR E SH NO P NOP ANY AR Confidential - 41 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Self-Refresh Command The Self-Refresh command can be used to retain data, even if the rest of the system is powered down. When in the Self-Refresh mode, the DDR2 SDRAM retains data without external clocking. The DDR2 SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS command. Once the command is registered, CKE must be held low to keep the device in SelfRefresh mode. When the DDR2 SDRAM has entered Self-Refresh mode, all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self-Refresh Operation to save power. The user may change the external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, how-ever, the clock must be restarted and stable before the device can exit Self-Refresh operation. Once Self-Refresh Exit command is registered, a delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device. CKE must remain high for the entire SelfRefresh exit period (tXSNR or tXSRD) for proper operation. NOP or DESELECT commands must be registered on each positive clock edge during the Self-Refresh exit interval. Since the ODT function is not supported during Self-Refresh operation, ODT has to be turned off before entering Self-Refresh Mode (tAOFD) and can be turned on again when the tXSRD timing is satisfied. T0 T1 T2 T4 T3 T5 Tm Tn Tr C K /C K tR P * tis tis CKE tis tAOF D >=tXS R D >= tXS NR ODT C MD S elf R efres h E ntry NOP C K /C K may be halted Non-R ea d C ommand R ead C omma nd C K /C K mus t be s table * = Device must be in the "All banks idle" sta te to entering S elf R efres h mode. ODT mus t be turned off prior to entering S elf R efres h mode. tX S R D ha s to be s atis fied for a R ead or a R ead with Auto-P recharge command. tX S NR ha s to be s atis fied for any command except a R ead or a R ea d with Auto-P recharge comma nd. Confidential - 42 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Power-Down Power-down is synchronously entered when CKE is registered low along with NOP or Deselect command. No read or write operation may be in progress when CKE goes low. These operations are any of the following: read burst or write burst and recovery. CKE is allowed to go low while any of other operations such as row activation, precharge or autoprecharge, mode register or extended mode register command time, or autorefresh is in progress. The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation. If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For Active Power-down two different power saving modes can be selected within the MRS register, address bit A12. When A12 is set to "low" this mode is referred as "standard active power-down mode" and a fast power-down exit timing defined by the tXARD timing parameter can be used. When A12 is set to "high" this mode is referred as a power saving "low power active power-down mode". This mode takes longer to exit from the power-down mode and the tXARDS timing parameter has to be satisfied. Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon entering precharge power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and all other input signals are "Don't Care". Power-down duration is limited by 9 times tREFI of the device. The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command). A valid, executable command can be applied with power-down exit latency, tXP, tXARD or tXARDS, after CKE goes high. Power-down exit latencies are defined in the AC spec table of this data sheet. Power-Down Entry Active Power-down mode can be entered after an activate command. Precharge Power-down mode can be entered after a precharge, precharge-all or internal precharge command. It is also allowed to enter powermode after an Auto-Refresh command or MRS / EMRS command when tMRD is satisfied. Active Power-down mode entry is prohibited as long as a Read Burst is in progress, meaning CKE should be kept high until the burst operation is finished. Therefore Active Power-Down mode entry after a Read or Read with Auto-Precharge command is allowed after RL + BL/2 is satisfied. Active Power-down mode entry is prohibited as long as a Write Burst and the internal write recovery is in progress. In case of a write command, active power-down mode entry is allowed when WL + BL/2 + tWTR is satisfied. In case of a write command with auto-precharge, power-down mode entry is allowed after the internal precharge command has been executed, which is WL + BL/2 + WR starting from the write with auto-precharge command. In case the DDR2 SDRAM enters the Precharge Power-down mode. Confidential - 43 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN A c tiv e P ower-Down Mode E ntry a nd E xit after an A c tivate C ommand T0 T1 T2 Tn Tn+1 Tn+2 C K, C K C MD NOP Activate NO P V a lid C ommand NO P NOP NOP tIS CKE tIS tX AR D or tX AR DS *) Act.P D 0 Active P ower-Down E xit Active P ower-Down E ntry note: Active Power-Down mode exit timing tX AR D ("fast exit") or tX AR DS ("slow exit") depends on the programmed s tate in the MR S , address bit A12. A c tiv e P ower-Down Mode E ntry a nd E xit after a R ead B urs t: R L = 4 (A L = 1, C L =3), B L = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 Tn T n+1 T n+2 CK, CK C MD R E AD R E AD w/AP NO P NO P NO P NO P NO P NO P NO P NO P NO P NO P V alid C ommand tIS CKE R L + B L/2 tIS DQ S , DQ S AL = 1 DQ tX AR D or tX AR DS *) CL = 3 RL = 4 Dout A0 Dout A1 Dout A2 Dout A3 Active P ower-Down E ntry Active P ower-Down E xit Act.P D 1 note: Active Power-Down mode exit timing tX AR D ("fas t exit") or tX AR DS ("s low exit") depends on the programmed s tate in the MR S , addres s bit A12. Confidential - 44 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Acti ve Power -Down Mode Entr y and Exit after a Write Bu rst: WL = 2, tWTR = 2, BL = 4 T0 T1 T2 T3 T4 T5 T6 Tn T7 Tn+1 Tn+2 CK, CK CMD NOP WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP Valid Comman tIS CKE WL + BL/2 + tWTR tIS DQS, DQS WL = RL - 1 = 2 DQ tWTR Dout A0 Dout A1 Dout A2 tXARD or tXARDS *) Dout A3 Active Power-Down Exit Active Power-Down Entry Act.P note: Active Power-Down mode exit timing tXARD ("fast exit") or tXARDS ("slow exit") depends on the programmed state in the MRS, address bit A12. Precharge Power Down Mode Entry and Exit T0 T1 T2 T3 Tn Tn+1 Tn+2 CK, CK CMD Precharge *) NOP NOP NOP NOP NOP NOP Valid Command NOP tIS CKE tIS tXP 1 x tCK Precharge Power-Down Entry Precharge Power-Down Exit *) "Precharge" may be an external command or an internal precharge following Write with AP. Confidential - 45 of 69 - PrePD Rev.1.0 April 2017 AS4C64M16D2B-25BCN No Operation Command The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don't care. Input Clock Frequency Change During operation the DRAM input clock frequency can be changed under the following conditions: a) During Self-Refresh operation b) DRAM is in precharged power-down mode and ODT is completely turned off. The DDR2-SDRAM has to be in precharged power-down mode and idle. ODT must be allready turned off and CKE must be at a logic "low" state. After a minimum of two clock cycles after tRP and tAOFD have been satisfied the input clock frequency can be changed. A stable new clock frequency has to be provided, before CKE can be changed to a "high" logic level again. After tXP has been satisfied a DLL RESET command via EMRS has to be issued. During the following DLL re-lock period of 200 clock cycles, ODT must remain off. After the DLL-re-lock period the DRAM is ready to operate with the new clock frequency. Clock Frequency Change in Precharge Power Down Mode T0 T1 T2 NOP NOP T4 Tx Tx+1 Ty Ty+1 Ty+2 Ty+3 Ty+4 Tz CK CK RAS, CS CAS, WE CKE NOP NOP Frequency Change Occurs here DLL RESET NOP Valid 200 Clocks ODT tRP tXP ODT is off during DLL RESET tAOFD Minmum 2 clocks required before changing frequency Confidential Stable new clock before power down exit - 46 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Asynchronous CKE Low Event DRAM requires CKE to be maintained "high" for all valid operations as defined in this data sheet. If CKE asynchronously drops "low" during any valid operation DRAM is not guaranteed to preserve the contents of the memory array. If this event occurs, the memory controller must satisfy a time delay ( tdelay ) before turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised "high" again. The DRAM must be fully re-initialized as described the the initialization sequence starting with step 4. The DRAM is ready for normal operation after the initialization sequence. The minimum time clocks needs to be ON after CKE asynchronously drops low (the tdelay timing parameter) is equal to tIS + tCK + tIH. A s ync hronous C K E L ow E vent s table clocks CK, CK tdelay CKE C K E drops low due to an asynchronous res et event Confidential C locks can be turned off after this point - 47 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Command Truth Table CKE Function CS RAS CAS WE BA0 Axx9-A11 A10 BAx9 A9 - A0 Notes Previous Cycle Current Cycle (Extended) Mode Register Set H H L L L L BA Refresh (REF) H H L L L H X X X X 1 Self Refresh Entry H L L L L H X X X X 1,8 H X X X Self Refresh Exit L H X X X X 1,7,8 L H H H OP Code 1,2 Single Bank Precharge H H L L H L BA X L X 1,2 Precharge all Banks H H L L H L X X H X 1 Bank Activate H H L L H H BA Write H H L H L L BA Column L Column 1,2,3, Write with Auto Precharge H H L H L L BA Column H Column 1,2,3, Read H H L H L H BA Column L Column 1,2,3 Read with Auto-Precharge H H L H L H BA Column H Column 1,2,3 No Operation H X L H H H X X X X 1 Device Deselect H X H X X X X X X X 1 H X X X Power Down Entry H L X X X X 1,4 L H H H H X X X X X X X 1,4 L H H H Power Down Exit L H Row Address 1,2 NOTE 1 All DDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock. NOTE 2 Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register. NOTE 3 Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" in section 2.6 for details. NOTE 4 The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements outlined in section 2.9. NOTE 5 The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See section 2.4.4. NOTE 6 "X" means "H or L (but a defined logic level)" NOTE 7 Self refresh exit is asynchronous. NOTE 8 VREF must be maintained during Self Refresh operation. NOTE 9 BAx and Axx refers to the MSBs of bank addresses and addresses, respectively, per device density. Confidential - 48 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Clock enable (CKE) truth table for synchronous transitions CKE Current State 2 Command (N) 3 Action (N) 3 Notes X Maintain Power-Down 11, 13, 14 H DESELECT or NOP Power Down Exit 4, 8, 11,13 L L X Maintain Self Refresh 11, 14,15 L H DESELECT or NOP Self Refresh Exit 4, 5, 9, 15 H L DESELECT or NOP Active Power Down Entry 4, 8, 10, 11, 13 H L DESELECT or NOP Precharge Power Down Entry 4, 8, 10, 11,13 H L REFRESH Self Refresh Entry 6, 9, 11,13 H H Previous Cycle 1 (N-1) Current Cycle 1 (N) RAS, CAS, WE, CS L L L Power Down Self Refresh Bank(s) Active All Banks Idle Refer to the Command Truth Table 7 NOTE 1 NOTE 2 NOTE 3 NOTE 4 NOTE 5 CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N). All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. NOTE 6 NOTE 7 NOTE 8 NOTE 9 NOTE 10 Self Refresh mode can only be entered from the All Banks Idle state. Must be a legal command as defined in the Command Truth Table. Valid commands for Power Down Entry and Exit are NOP and DESELECT only. Valid commands for Self Refresh Exit are NOP and DESELECT only. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set operations or Precharge operations are in progress. See section Power-down and Self refresh operation for a detailed list of restrictions. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined in Refresh command section. "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in Power Down if the ODT function is enabled (Bit A2 or A6 set to "1" in EMR(1) ). VREF must be maintained during Self Refresh operation. NOTE 11 NOTE 12 NOTE 13 NOTE 14 NOTE 15 DM truth table Name (Functional) DM DQs Note Write enable L Valid 1 Write inhibit H X 1 NOTE 1 Confidential Used to mask write data, provided coincident with the corresponding data - 49 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Absolute maximum DC ratings Symbol Rating Units Notes Voltage on VDD pin relative to Vss - 1.0 V ~ 2.3 V V 1,3 VDDQ Voltage on VDDQ pin relative to Vss - 0.5 V ~ 2.3 V V 1,3 VDDL Voltage on VDDL pin relative to Vss - 0.5 V ~ 2.3 V V 1,3 Voltage on any pin relative to Vss - 0.5 V ~ 2.3 V V 1 -55 to +100 C 1, 2 VDD VIN, VOUT TSTG Parameter Storage Temperature NOTE 1 Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability NOTE 2 Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. NOTE 3 When VDD and VDDQ and VDDL are less than 500 mV, Vref may be equal to or less than 300 mV. AC & DC operating conditions Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the speechified initialization sequence before normal operation can continue. Recommended DC operating conditions (SSTL_1.8) Symbol Parameter Rating Min. Typ. Max. Units Notes VDD Supply Voltage 1.7 1.8 1.9 V 1 VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 5 VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 1, 5 VREF Input Reference Voltage 0.49 x VDDQ 0.50 x VDDQ 0.51 x VDDQ mV 2. 3 VREF - 0.04 VREF VREF + 0.04 V 4 VTT Termination Voltage NOTE 1 There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all conditions VDDQ must be less than or equal to VDD. NOTE 2 The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. NOTE 3 Peak to peak ac noise on VREF may not exceed +/-2 % VREF(dc). NOTE 4 VTT of transmitting device must track VREF of receiving device. NOTE 5 VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together Confidential - 50 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Measurement Definition for VM: Measure voltage (VM) at test pin (midpoint) with no load. 2 x Vm VM = VDDQ -1 x 100% Input DC logic level Symbol VIH(dc) VIL(dc) Parameter Min. Max. Units dc input logic HIGH VREF + 0.125 VDDQ + 0.3 V dc input logic LOW - 0.3 VREF - 0.125 V Notes Input AC logic level Unit DDR2-800 Symbol Parameter Min Max VIH(ac) ac input logic HIGH VREF+0.200 VDDQ+Vpeak V VIL(ac) ac input logic LOW VSSQ-Vpeak VREF-0.200 V AC input test conditions Symbol Condition Value Units Notes 0.5 x VDDQ V 1 Input signal maximum peak to peak swing 1.0 V 1 Input signal minimum slew rate 1.0 V/ns 2, 3 VREF Input reference voltage VSWING(MAX) SLEW NOTE 1 Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test. NOTE 2 The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure. NOTE 3 AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. VDDQ VIH(ac) min VIH(dc) min VSWING(MAX) VREF VIL(dc) max VIL(ac) max TF Falling Slew = TR VREF - VIL(ac) max Rising Slew = TF VSS VIH(ac) min - VREF TR AC input test signal waveform Confidential - 51 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN AC & DC operating conditions (cont'd) Differential input AC logic level DDR2-800 Symbol Parameter Min Max Unit Notes V 1 V 2 Symbol Parameter Min. VID(ac) ac differential input voltage 0.5 VDDQ 0.5 VID (ac) ac differential input voltage VIX(ac) ac differential crosspoint voltage 0.5xVDDQ 0.5xVDDQ VIX (ac) - 0.175 ac differential crosspoint voltage -0.175 0.5 x VDDQ +0.175 VDDQ VTR Crossing point VID VIX or VOX VCP VSSQ NOTE 1 VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - V IL(AC). NOTE 2 The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross. Differenti al signal levels Dif ferential AC output parameters Symbol VOX (ac) Parameter ac differential crosspoint voltage Min. Max. Units Notes 0.5 x VDDQ - 0.125 0.5 x VDDQ + 0.125 V 1 NOTE 1 The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at which differential output signals must cross. Overshoot/undershoot specification AC overshoot/undershoot specification for address and control pins: A0-A15, BA0-BA2, CS, RAS, CAS, WE, CKE, ODT DDR2-800 Unit Maximum peak amplitude allowed for overshoot area 0.5(0.9)1 V Maximum peak amplitude amplitudeallowed allowedfor forundershoot undershoot area Maximum peak area (S 0.5(0.9)1 V Maximum overshoot area above Maximum overshoot area above VDD (SeeVDDQ Figure 74). 0.66 V-ns Maximum undershoot area below (See Figure 74). Maximum undershoot areaVSS below VSSQ 0.66 V-ns Parameter NOTE 1 The maximum requirements for peak amplitude were reduced from 0.9V to 0.5V. Register vendor data sheets will specify the maximum over/undershoot induced in specific RDIMM applications. DRAM vendor data sheets will also specify the maximum overshoot/undershoot that their DRAM can tolerate. This will allow the RDIMM supplier to understand whether the DRAM can tolerate the overshoot that the register will induce in the specific RDIMM application. Confidential - 52 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN AC & DC operating conditions (cont'd) Maximum Amplitude Overshoot Area VDD Volts VSS (V) Maximum Amplitude Undershoot Area Time (ns) AC overshoot and undershoot definition for address and control pins AC overshoot/undershoot specification for clock, data, strobe, and mask pins: DQ, (U/L/R)DQS, (U/L/R)DQS, DM, CK, CK DDR2-800 Unit Maximum amplitude allowed allowedfor forovershoot overshootarea area Maximum peak peak amplitude ( 0.5 V Maximumpeak peakamplitude amplitude allowed allowed for Maximum for undershoot undershootarea area( 0.5 V Maximum overshoot area above VDDQ 0.23 V.ns Maximum undershoot area below VSSQ 0.23 V.ns Parameter Maximum Amplitude Overshoot Area VDDQ Volts VSSQ (V) Maximum Amplitude Undershoot Area Time (ns) AC overshoot and undershoot definition for clock, data, strobe, and mask pins Power and ground clamps are required on the following input only pins: a) BA0-BAx e) WE b) A0-Axx f) CS c) RAS g) ODT d) CAS h) CKE Confidential - 53 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN AC & DC operating conditions (cont'd) V-I characteristics for input-only pins with clamps Voltage across Clamp (V) Minimum Power Clamp Current (mA) Minimum Ground Clamp Current (mA) 0.0 0 0 0.1 0 0 0.2 0 0 0.3 0 0 0.4 0 0 0.5 0 0 0.6 0 0 0.7 0 0 0.8 0.1 0.1 0.9 1.0 1.0 1.0 2.5 2.5 1.1 4.7 4.7 1.2 6.8 6.8 1.3 9.1 9.1 1.4 11.0 11.0 1.5 13.5 13.5 1.6 16.0 16.0 1.7 18.2 18.2 1.8 21.0 21.0 Output buffer characteristics Output AC test conditions Symbol VOTR Parameter Output Timing Measurement Reference Level SSTL_18 Units Notes 0.5 x VDDQ V 1 NOTE 1 The VDDQ of the device under test is referenced. Output DC current drive Symbol Parameter IOH(dc) Output Minimum Source DC Current IOL(dc) Output Minimum Sink DC Current SSTl_18 Units Notes - 13.4 mA 1, 3, 4 13.4 mA 2, 3, 4 NOTE 1 VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 for values of VOUT between VDDQ and VDDQ - 280 mV. NOTE 2 VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 for values of VOUT between 0 V and 280 mV. NOTE 3 The dc value of VREF applied to the receiving device is set to VTT NOTE 4 The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (see Section 3.3 of JESD8-15A) along a 21 load line to define a convenient driver current for measurement. Confidential - 54 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Table 1. Full Strength Default Pulldown Driver Characteristics Pulldow n Current (mA) Voltage (V) Minimum (23.4 Ohms) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 8.5 12.1 14.7 16.4 17.8 18.6 19.0 19.3 19.7 19.9 20.0 20.1 20.2 20.3 20.4 20.6 Nominal Default Low (18 ohms) Nominal Default High (18 ohms) 11.3 16.5 21.2 25.0 28.3 30.9 33.0 34.5 35.5 36.1 36.6 36.9 37.1 37.4 37.6 37.7 37.9 11.8 16.8 22.1 27.6 32.4 36.9 40.9 44.6 47.7 50.4 52.6 54.2 55.9 57.1 58.4 59.6 Maximum (12.6 Ohms) 60.9 15.9 23.8 31.8 39.7 47.7 55.0 62.3 69.4 75.3 80.5 84.6 87.7 90.8 92.9 94.9 97.0 99.1 101.1 Figure 1. DDR2 Default Pulldown Characteristics for Full Strength Driver 120 Pulldown current (mA) 100 Maximum 80 Nominal Default High 60 Nominal Default Low 40 20 Minimum 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 VOUT to VSSQ (V) Confidential - 55 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Table 2. Full Strength Default Pullup Driver Characteristics Pullup Current (mA) Voltage (V) Minimum (23.4 Ohms) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Nominal Default Low (18 ohms) Nominal Default High (18 ohms) -11.1 -16.0 -20.3 -24.0 -27.2 -29.8 -31.9 -33.4 -34.6 -35.5 -36.2 -36.8 -37.2 -37.7 -38.0 -38.4 -38.6 -11.8 -17.0 -22.2 -27.5 -32.4 -36.9 -40.8 -44.5 -47.7 -50.4 -52.5 -54.2 -55.9 -57.1 -58.4 -59.6 -60.8 -8.5 -12.1 -14.7 -16.4 -17.8 -18.6 -19.0 -19.3 -19.7 -19.9 -20.0 -20.1 -20.2 -20.3 -20.4 -20.6 Maximum (12.6 Ohms) -15.9 -23.8 -31.8 -39.7 -47.7 -55.0 -62.3 -69.4 -75.3 -80.5 -84.6 -87.7 -90.8 -92.9 -94.9 -97.0 -99.1 -101.1 Figure 2. DDR2 Default Pullup Characteristics for Full Strength Output Driver 0 Pullup current (mA) -20 Minimum -40 Nominal Default Low -60 Nominal Default High -80 -100 Maximum -120 0.2 0.4 0.3 0.6 0.5 0.8 0.7 1.0 0.9 1.2 1.1 1.4 1.3 1.6 1.5 1.8 1.7 1.9 VDDQ to VOUT (V) Confidential - 56 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN DDR2 SDRAM Default Output Driver V-I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS1 bits A7-A9 = '111'. Figures 1 and 2 show the driver characteristics graphically, and tables 1 and 2 show the same data in tabular format suitable for input into simulation tools. The driver characteristics evaluation conditions are: Nominal Default 25C (T case), VDDQ = 1.8V, typical process Minimum 85C (T case), VDDQ = 1.7 V, slow - slow process Maximum 0C (T case), VDDQ = 1.9V, fast - fast process Default Output Driver Characteristic Curves Notes: 1) The full variation in driver current from minimum to maximum process, temperature, and voltage will lie within the outer bounding lines of the V-I curve of figures 1 and 2. 2) It is recommended that the "typical" IBIS V-I curve lie within the inner bounding lines of the V-I curves of figures 1 and 2. Table 3. Full Strength Calibrated Pulldown Driver Characteristics Calibrated Pulldow n Current (mA) Voltage (V) Nominal Minimum (21 ohms) 0.2 0.3 0.4 9.5 14.3 18.7 Nominal Low (18.75 ohms) Nominal (18 ohms) 10.7 16.0 21.0 Nominal High (17.2 ohms) 11.5 16.6 21.6 Nominal Maximum (15 ohms) 11.8 17.4 23.0 13.3 20.0 27.0 Nominal Maximum (15 ohms) Table 4. Full Strength Calibrated Pullup Driver Characteristics Calibrated Pullup Current (mA) Confidential Voltage (V) Nominal Minimum (21 ohms) Nominal Low (18.75 ohms) Nominal (18 ohms) Nominal High (17.2 ohms) 0.2 0.3 0.4 -9.5 -14.3 -18.7 -10.7 -16.0 -21.0 -11.4 -16.5 -21.2 -11.8 -17.4 -23.0 - 57 of 69 - -13.3 -20.0 -27.0 Rev.1.0 April 2017 AS4C64M16D2B-25BCN DDR2 SDRAM Calibrated Output Driver V-I Characteristics Tables 3 and 4 show the data in tabular format suitable for input into simulation tools. The nominal points represent a device at exactly 18 ohms. The nominal low and nominal high values represent the range that can be achieved with a maximum 1.5 ohm step size with no calibration error at the exact nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). Real system calibration error needs to be added to these values. It must be understood that these V-I curves as represented here or in supplier IBIS models need to be adjusted to a wider range as a result of any system calibration error. Since this is a system specific phenomena, it cannot be quantified here. The values in the calibrated tables represent just the DRAM portion of uncertainty while looking at one DQ only. If the calibration procedure is used, it is possible to cause the device to operate outside the bounds of the default device characteristics tables and figures. In such a situation, the timing parameters in the specification cannot be guaranteed. It is solely up to the system application to ensure that the device is calibrated between the minimum and maximum default values at all times. If this can't be guaranteed by the system calibration procedure, re-calibration policy, and uncertainty with DQ to DQ variation, then it is recommended that only the default values be used. The nominal maximum and minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimum conditions. If calibrated at an extreme condition, the amount of variation could be as much as from the nominal minimum to the nominal maximum or vice versa. The driver characteristics evaluation conditions are: Nominal 25C (T case), VDDQ = 1.8 V, typical process Nominal Low and Nominal High 25C (T case), VDDQ = 1.8 V, any process Nominal Minimum 85C (T case), VDDQ = 1.7 V, any process Nominal Maximum 0C (T case), VDDQ = 1.9 V, any process Confidential - 58 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN AC & DC operating conditions(cont'd) IDD specification parameters and test conditions (IDD values are for full operating range of Voltage and Temperature, Notes 1 - 6,VDDQ=1.8V+/-0.1V; VDD=1.8V+/-0.1V) Symbol IDD0 Conditions Max Units Notes 100 mA 1,2 115 mA 1,2 30 mA 1,2 50 mA 1,2 55 mA 1,2 60 mA 1,2 50 mA 1,2 80 mA 1,2 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD1 Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W IDD2P Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING IDD2Q Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD3P Active power-down current; Fast PDN Exit MRS(12) = 0 All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Slow PDN Exit MRS(12) = 1 Data bus inputs are FLOATING IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Confidential - 59 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN AC & DC operating conditions(cont'd) IDD specification parameters and test conditions (IDD values are for full operating range of Voltage and Temperature, Notes 1 - 6,VDDQ=1.8V+/-0.1V; VDD=1.8V+/-0.1V) Symbol IDD4W Conditions Max Units Notes 250 mA 1,2 180 mA 1,2 165 mA 1,2 Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD6 Self refresh current; mA CK and CK at 0 V; _ 0.2 V; CKE < Other control and address bus inputs are FLOATING; 10 1,2 Data bus inputs are FLOATING IDD7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) - 1 x tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1 x tCK(IDD); 100 mA 1 CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following pages for detailed timing conditions Confidential - 60 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN IDD specification parameters and test conditions (IDD values are for full operating range of Voltage and Temperature, Notes 1 - 6) Symbol Conditions Max Units Notes NOTE 1 IDD specifications are tested after the device is properly initialized NOTE 2 Input slew rate is specified by AC Parametric Test Condition NOTE 3 IDD parameters are specified with ODT disabled. NOTE 4 Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. NOTE 5 For DDR2-800 testing, tCK in the Conditions should be interpreted as tCK(avg) NOTE 6 Definitions for IDD LOW = HIGH = STABLE = FLOATING = SWITCHING = _ VILAC(max) Vin < _ VIHAC(min) Vin > inputs stable at a HIGH or LOW level inputs at VREF = VDDQ/2 inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. IDD testing parameters For purposes of IDD testing, the parameters in the IDD testing parameters table are to be utilized IDD testing parameters Speed Bin(CL-tRCD-tRP) DDR2-800 Unit 5-5-5 CL(IDD) 5 tCK tRCD(IDD) 15 ns tRC(IDD) 60 ns tRRD(IDD)-1KB 7.5 ns tRRD(IDD)-2KB 10 ns tFAW(IDD)-1KB 37.5 ns tFAW(IDD)-2KB 50 ns tCK(IDD) 2.5 ns tRASmin(IDD) 45 ns tRASmax(IDD) 70000 ns 12.5 ns 127.5 ns tRP(IDD) tRFC(IDD)-1Gb Confidential - 61 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN AC & DC operating conditions(cont'd) Detailed IDD7 The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification. Legend: A = Active; RA = Read with Autoprecharge; D = Deselect IDD7: Operating Current: All Bank Interleave Read operation All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) and tFAW(IDD) using a burst length of 4. Control and address bus inputs are STABLE during DESELECTs. IOUT = 0 mA Timing Pattern -DDR2-800 all bins: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D Input/output capacitance DDR2-800 Parameter Symbol Min Max Units Input capacitance, CK and CK CCK 1.0 2.0 pF Input capacitance delta, CK and CK CDCK x 0.25 pF CI 1.0 1.75 pF Input capacitance delta, all other input-only pins CDI x 0.25 pF Input/output capacitance, DQ, DM, DQS, DQS CIO 2.5 3.5 pF Input/output capacitance delta, DQ, DM, DQS, DQS CDIO x 0.5 pF Input capacitance, all other input-only pins Confidential - 62 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN AC Characteristics (AC operating conditions unless otherwise noted) Parameter (DDR2-800) -25 Symbol Unit Min Max Note Row Cycle Time tRC 57.5 - ns Auto Refresh Row Cycle Time tRFC 127.5 - ns 11 Row Active Time tRAS 45 70K ns 21 Row Address to Column Address Delay tRCD 12.5 - ns 20 Row Active to Row Active Delay tRRD 10 - ns Four Activate Window tFAW 45 - ns tCCD 2 - CLK Row Precharge Time tRP 12.5 - ns Write Recovery Time tWR 15 - ns Auto Precharge Write Recovery + Precharge Time tDAL tWR +tRP - ns 12 CAS Latency = 3 - - ns 2 CAS Latency = 4 3.75 8 ns 2 2.5 8 ns 2 Column Address to Column Address Delay System Clock Cycle Time CAS Latency = 5 tCK CAS Latency = 6 2.5 8 ns 2 CAS Latency = 7 - - ns 2 Clock High Level Width tCH 0.48 0.52 CLK Clock Low Level Width tCL 0.48 0.52 CLK Data-Out edge to Clock edge Skew tAC -0.40 0.40 ns DQS-Out edge to Clock edge Skew tDQSCK -0.35 0.35 ns tDQSQ - 0.20 ns Data-Out hold time from DQS tQH tHPmin -tQHS - ns Data hold skew factor tQHS - 300 ps DQS-Out edge to Data-Out edge Skew Confidential - 63 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN (DDR2-800) -25 Unit Note - ns 5 175 - ps 15,17 tIH 250 - ps 15,17 tIPW 0.60 - CLK Write DQS High Level Width tDQSH 0.35 CLK Write DQS Low Level Width tDQSL 0.35 CLK CLK to First Rising edge of DQS-In tDQSS -0.25 tCK +0.25 tCK CLK Data-In Setup Time to DQS-In (DQ & DM) tDS (base) 50 - ps 16,17, 18 Data-in Hold Time to DQS-In (DQ & DM) tDH (base) 125 - ps 16,17, 18 DQS falling edge to CLK rising Setup Time tDSS 0.2 - CLK DQS falling edge from CLK rising Hold Time tDSH 0.2 - CLK DQ & DM Input Pulse Width tDIPW 0.35 - CLK Read DQS Preamble Time tRPRE 0.9 1.1 CLK Read DQS Postamble Time tRPST 0.4 0.6 CLK Write DQS Preamble Time tWPRE 0.35 - CLK 10 Write DQS Postamble Time tWPST 0.4 0.6 CLK 10 Internal read to precharge command delay tRTP 7.5 - ns Internal write to read command delay tWTR 7.5 - ns 13 Data out high impedance time from CLK/CLK tHZ - tAC ns 7 DQS/DQS low impedance time from CLK/CLK tLZ(DQS) ns 7 DQ low impedance time from CLK/CLK tLZ(DQ) ns 7 Mode Register Set Delay 9 MRS command to ODT update delay Symbol Min Max Clock Half Period tHP tCH/L min Input Setup Time (fast slew rate) tIS Input Hold Time (fast slew rate) Parameter Input Pulse Width Confidential (max) tAC tAC (min) (max) 2*tAC tAC (min) (max) tMRD 2 - CLK tMOD 0 12 ns - 64 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN (DDR2-800) -25 Unit Note - ns 19 200 - CLK tXP 2 - CLK Exit Active Power Down to Read Command tXARD 2 - CLK Exit Active Power Down to Read Command (Slow exit, Lower Power) tXARDS 8-AL - CLK Minimum time clocks remains ON after CKE asynchronously drops LOW tDelay tIS+tCK +tIH CKE minimum high and low pulse width tCKE 3 - CLK Average Periodic Refresh Interval, 0C < T < 85C tREFI - 7.8 us 18 Average Periodic Refresh Interval, 85C < T < 105C tREFIT - 3.9 us 18 Period Jitter tJITPER -100 100 ps 22 Duty Cycle Jitter tJITDTY -100 100 ps 22 Cycle to Cycle tJITCC -200 200 ps 22 Cumulative error, 2 cycles tERR(2PER) -150 150 ps 22 Cumulative error, 3 cycles tERR(3PER) -175 175 ps 22 Cumulative error, 4 cycles tERR(4PER) -200 200 ps 22 Cumulative error, 5 cycles tERR(5PER) -200 200 ps 22 Cumulative error, 6-10 cycles tERR -300 300 ps 22 (6-10PER) Cumulative error, 11-50cycles -450 450 ps 22 (11-50PER) Symbol Min Max Exit Self Refresh to NonRead Command tXSNR tRFC+10 Exit Self Refresh to Read Command tXSRD Parameter Exit Precharge Power Down to any non-Read Command Confidential tERR 14 ns - 65 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Notes for Electrical Characteristics & AC Timing 1. Input slew rate is 1 V/ns and AC timings are guaranteed for linear signal transitions. For other slew rates see the de-rating tables on the next pages. 2. The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross:the DQS /DQS input reference level is the crosspoint when in differential strobe mode; the input reference level for signals other than CK/CK, or DQS / DQS is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as LOW. 4. The output timing reference voltage level is VTT. 5. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH. 6. For input frequency change during DRAM operation. 7. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8. These parameters guarantee device timing, but they are not necessarily tested on each device. 9. The specific requirement is that DQS and DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previ-ous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. When programmed in differential strobe mode, DQS is always the logic complement of DQS except when both are in high-Z. 10. The maximum limit for this parameter is not a device limit. The device operate with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 11. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. (Note : tRFC depends on DRAM density) 12. For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 13. tWTR is at least two clocks independent of operation frequency. 14. User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active power-down mode" (MRS, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MRS, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied. 15. Timings are guaranteed with command / address input slew rate of 1.0 V/ns. 16. Timings are guaranteed with data / mask input slew rate of 1.0 V/ns. 17. Timings are guaranteed with CK /CK differential slew rate 2.0 V/ns, and DQS/DQS ( and RDQS/RDQS) differential slew rate 2.0 V/ns in differential strobe mode. 18. If refresh timing or tDS / tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 19. In all circumstances, tXSNR can be satisfied using tXSNR = tRFC + 10 ns. 20. The tRCD timing parameter is valid for both activate command to read or write command with and without Auto Pre-charge. Therefore a separate parameter tRAP for activate command to read or write command with Auto-Precharge is not necessary anymore. 21. tRAS(max) is calculated from the maximum amount of time a DDR2 device can operate without a Refresh command which is equal to 9 * tREFI. Confidential - 66 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Reference Loads, Slew Rates and Slew Rate Derating Reference Load for Timing Measurements The figure represents the timing reference load used in defining the relevant timing parameters of the device. It is not intended to either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. This load circuit is also used for output slew rate measurements. VDDQ CK, CK DQ DQS DQS RDQS RDQS DUT 25 Ohm Vtt = VDDQ / 2 Timing Reference Points Note: The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. Slew Rate Measurements Output Slew Rate Output slew rate is characterized under the test conditions as shown in the figure below VDDQ DUT DQ DQS RDQS 25 Ohm Vtt = VDDQ / 2 Test Point Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals.For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS = + 500 mV.Output slew rate is guaranteed by design, but is not necessarilty tested on each device. Input Slew Rate Input slew for single ended signals is measured from dc-level to ac-level from VREF to VIH(AC),min for rising and from VREF to VIL(AC), min or falling edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK -CK = +500 mV (250 mV to -500 mV for falling edges). Test conditions are the same as for timing measurements. Confidential - 67 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Package Dimension 84-Ball Fine Pitch Ball Grid Array Outline Solder ball: Lead free (Sn-Ag-Cu) Confidential Unit: mm - 68 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN PART NUMBERING SYSTEM AS4C 64M16D2B 25 DRAM 64M16=64Mx16 D2=DDR2 B=B die 25=400MHz B C N B = FBGA C=Commercial (0C~+95C) Indicates Pb and Halogen Free Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright (c) Alliance Memory All Rights Reserved (c) Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. 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Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. Confidential - 69 of 69 - Rev.1.0 April 2017