1
®
FN4655.6
HI5960
14-Bit, 130MSPS, High Speed D/A
Converter
The HI5960 is a 14-bit, 130MSPS (Me ga Samples Per
Second), high speed, low power, D/A converter which is
implemented in an advanced CMOS process. Operating
from a single +3V to +5V supply, the converter pro vides
20mA of full scale output current and includes edge-
triggered CMOS input data la tches. Low glitch energy and
excellent frequency domain performance are achieved using
a segmented current source architecture.
This device complements the HI5x60 and HI5x28 family of
high speed converters, which includes 8, 10, 12, and 14-bit
devices.
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .130MSPS
• Low Power (at 100MSPS) at 5V . . . . . . . . . . . . . .175mW
at 3V. . . . . . . . . . . . . . . .32mW
• Adjustable Full Scale Output Current. . . . . 2mA to 20mA
• Internal 1.2V Bandgap Voltage Reference
• Single Power Supply from +5V to +3V
• Power Down Mode
• CMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
(77dBc, fS = 50MSPS, fOUT = 2.51MHz)
• Excellent Multitone Inte rmodulation Distortion
•Pb-Free Available (RoHS Compliant)
Applications
• Cellular Basestations
• WLL, Basestation and Subscriber Units
• Medical/Test Instrumentation
• Wireless Communications Systems
• Direct Digital Frequency Synthesis
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
Pinout HI5960 (SOIC, TSSOP)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE
(oC) PACKAGE PKG.
DWG. # CLOCK
SPEED
HI5960IB -40 to 85 28 Ld SOIC M28.3 130MHz
HI5960IBZ
(See Note) -40 to 85 28 Ld SOIC
(Pb-free) M28.3 130MHz
HI5960IA -40 to 85 28 Ld TSSOP M28.173 130MHz
HI5960IAZ
(See Note) -40 to 85 28 Ld TSSOP
(Pb-free) M28.173 130MHz
HI5960IA-T -40 to 85 28 Ld TSSOP
Tape and Reel M28.173 130MHz
HI5960IAZ-T
(See Note) -40 to 85 28 Ld TSSOP
Tape and Reel
(Pb-free)
M28.173 130MHz
HI5960SOICEVAL1 25 Evaluation Platform 130MHz
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D13 (MSB)
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
DCOM
ACOM
AVDD
COMP2
IOUTB
COMP1
FSADJ
REFIO
REFLO
SLEEP
DVDD
IOUTA
ACOM
Data Sheet March 31, 2005
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
2
Typical Applications Circuit
Functional Block Diagram
D11 (3)
D10 (4)
D9 (5)
D8 (6)
D7 (7)
D6 (8)
D5 (9)
D4 (10)
D11
D10
D9
D8
D7
D6
D5
D4
DCOM (26)
CLK (28) (19) COMP1
(24) AVDD
D/A OUT
(22) IOUTA
(21) IOUTB
50Ω
(18) FSADJ
(16) REFLO
HI5960
DVDD (27)
0.1µF
50Ω
10µF
(20) ACOM
50Ω
(15) SLEEP
(17) REFIO
0.1µF
1.91kΩ
FERRITE
10µH
0.1µF
(23) COMP2
0.1µF
D/A OUT
+
BEAD
RSET
D3
D2
D1
D0
D3 (11)
D2 (12)
D1 (13)
D0 (LSB) (14)
0.1µF
10µH
+
BEAD
(25) ACOM
ACOM
DCOM
10µF
D13 (1)
D12 (2)
D13
D12
+5V OR +3V (VDD)
UPPER
VOLTAGE
REFERENCE
(LSB) D0
D1
D2
D3
D4
D5
D6
D9
CLK
D7
D8
5-BIT
DECODER
REFIO
LATCH
AVDD ACOM DVDD DCOM
LATCH
CASCODE
CURRENT
SOURCE
SWITCH
MATRIX
BIAS
GENERATION
INT/EXT
FSADJ
REFERENCE
INT/EXT
SELECT
REFLO
31
40 40
31 MSB
SEGMENTS
9 LSBs +
COMP2
COMP1
SLEEP
IOUTA IOUTB
D10
D11
D12
(MSB) D13
HI5960
3
Pin Descriptions
PIN NO. PIN NAME DESCRIPTION
1-14 D13 (MSB) Through
D0 (LSB) Digital Data Bit 13, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
15 SLEEP Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep
pin has internal 20µA active pulldown current.
16 REFLO Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal
reference.
17 REFIO Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is
enabled. U se 0 .1µF cap to ground when internal reference is enabled.
18 FSADJ Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current = 32 x VFSADJ/RSET.
19 COMP1 For use in reducing bandwidth/noise. Recommended: connect 0.1µF to AVDD.
21 IOUTB The complimentary current output of the device. Full scale output current is achieved when all input bits
are set to binary 0.
22 IOUTA Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
23 COMP2 Connect 0.1µF capacitor to ACOM.
24 AVDD Analog Supply (+3V to +5V).
20, 25 ACOM Connect to Analog Ground.
26 DCOM Connect to Digital Ground.
27 DVDD Digital Supply (+3V to +5V).
28 CLK Clock Input. Input data to the DAC passes through the “master” latches when the clock is low and is
latched into the “master” latches when the clock is high. Data presented to the “slave” latch passes
through when the clock is logic high and is latched into the “slave” latches when the clock is logic low.
Adequate setup time must be allowed for the MSBs to pass through the thermometer decoder before the
clock goes high. This master-slave arrangement comprises an edge-triggered flip-flop, with the DAC
being updated on the rising clock edge. It is recommended that the clock edge be skewed such that setup
time is larger than the hold time.
HI5960
4
Absolute Maximum Ratings Thermal Information
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AVDD to ACOM . . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . DVDD + 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
HI5960IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1) θJA(oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
SYSTEM PERFORMANCE
Resolution 14 - - Bits
Integral Linearity Error, INL “Best Fit” Straight Line (Note 8) -5 ±2.5 +5 LSB
Differential Linearity Error, DNL (Note 8) -3 ±1.5 +3 LSB
Offset Error, IOS (Note 8) -0.025 +0.025 % FSR
Offset Drift Coefficient (Note 8) - 0.1 - ppm
FSR/oΧ
Full Scale Gain Error, FSE With External Reference (Notes 2, 8) -10 ±2+10% FSR
With Internal Reference (Notes 2, 8) -10 ±1+10% FSR
Full Scale Gain Drift With External Reference (Note 8) - ±50 - ppm
FSR/οΧ
With Internal Reference (Note 8) - ±100 - ppm
FSR/οΧ
Full Scale Output Current, IFS 2-20mA
Output Voltage Compliance Range (Note 3, 8) -0.3 - 1.25 V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, fCLK (Note 3) 130 - - MHz
Output Settling Time, (tSETT) ±0.05% (±8 LSB) (Note 8) - 35 - ns
Singlet Glitch Area (Peak Glitch) RL = 25Ω (Note 8) - 5 - pV•s
Output Rise Time Full Scale Step - 2.5 - ns
Output Fall Time Full Scale Step - 2.5 - ns
Output Capacitance -10- pF
Output Noise IOUTFS = 20mA - 50 - pA/√Hz
IOUTFS = 2mA - 30 - pA/√Hz
AC CHARACTERISTICS
+5V Power Supply
Spurious Free Dynamic Range,
SFDR Within a Window
fCLK = 100MSPS, fOUT = 20.2MHz, 30MHz Spa n (Notes 4, 8) - 77 - dBc
fCLK = 100MSPS, fOUT = 5.04MHz, 8MHz Span (Notes 4, 8) - 97 - dBc
fCLK = 50MS PS, fOUT = 5.02MH z, 8MHz Sp an (Not es 4, 8) - 97 - dBc
HI5960
5
+5V Power Supply
Total Harmonic Distortion (THD) to
Nyquist
fCLK = 100MSPS, fOUT = 4.0MHz (Notes 4, 8) - -71 - dBc
fCLK = 50MSPS, fOUT = 2.0MHz (Notes 4, 8) - -75 - dBc
fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8) - -77 - dBc
+5V Power Supply
Spurious Free Dynamic Range,
SFDR to Nyquist (fCLK/2)
fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 8) - 56 - dBc
fCLK = 130MSPS, fOUT = 10.1MHz (Notes 4, 8) - 67 - dBc
fCLK = 130MSPS, fOUT = 5.02MHz, T = 25oC (Notes 4, 8) 68 74 - dBc
fCLK = 130MSPS, fOUT = 5.02MHz, T = Min to Max (No tes 4, 8) 66 - - dBc
fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 8) - 55 - dBc
fCLK = 100MSPS, fOUT = 20.2MHz (Notes 4, 8) - 63 - dBc
fCLK = 100MSPS, fOUT = 5.04MHz, T = 25oC (Notes 4, 8) 68 74 - dBc
fCLK = 100MSPS, fOUT = 5.04MHz, T = Min to Max (No tes 4, 8) 66 - dBc
fCLK = 100MSPS, fOUT = 2.51MHz (Notes 4, 8) - 76 - dBc
fCLK = 50MS PS, fOUT = 20.2MHz (Notes 4, 8) - 65 - dBc
fCLK = 50MS PS, fOUT = 5.02MHz, T = 25oC (Notes 4, 8) 68 74 - dBc
fCLK = 50MS PS, fOUT = 5.02MHz, T = Min to Max (Notes 4, 8) 66 - - dBc
fCLK = 50MS PS, fOUT = 2.51MHz (Notes 4, 8) - 77 - dBc
fCLK = 50MS PS, fOUT = 1.00MHz (Notes 4, 8) - 79 - dBc
fCLK = 25MS PS, fOUT = 1.0MHz (N otes 4, 8 ) - 79 - dBc
+5V Power Supply
Multitone Power Ratio fCLK = 20MSPS, fOUT = 2. 0 M H z t o 2 . 9 9 M Hz , 8 Tones at 110kHz
Spacing (Notes 4, 8) -76- dBc
fCLK = 100MSPS, fOUT = 10 MH z t o 1 4. 9 5M Hz , 8 Tones at 530kHz
Spacing (Notes 4, 8) -76- dBc
+3V Power Supply
Spurious Free Dynamic Range,
SFDR Within a Window
fCLK = 100MSPS, fOUT = 20.2MHz, 30MHz Spa n (Notes 4, 8) - 80 - dBc
fCLK = 100MSPS, fOUT = 5.04MHz, 8MHz Span (Notes 4, 8) - 95 - dBc
fCLK = 50MS PS, fOUT = 5.02MH z, 8MHz Sp an (Not es 4, 8) - 95 - dBc
+3V Power Supply
Total Harmonic Distortion (THD) to
Nyquist
fCLK = 100MSPS, fOUT = 4.0MHz (Notes 4, 8) - -70 - dBc
fCLK = 50MSPS, fOUT = 2.0MHz (Notes 4, 8) - -74 - dBc
fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8) - -76 - dBc
Electrical Specifications AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
HI5960
6
+3V Power Supply
Spurious Free Dynamic Range,
SFDR to Nyquist (fCLK/2)
fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 8) - 48 - dBc
fCLK = 130MSPS, fOUT = 10.1MHz (Notes 4, 8) - 66 - dBc
fCLK = 130MSPS, fOUT = 5.02MHz (Notes 4, 8) - 74 - dBc
fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 8) - 49 - dBc
fCLK = 100MSPS, fOUT = 20.2MHz (Notes 4, 8) - 59 - dBc
fCLK = 100MSPS, fOUT = 5.04MHz (Notes 4, 8) - 72 - dBc
fCLK = 100MSPS, fOUT = 2.51MHz (Notes 4, 8) - 77 - dBc
fCLK = 50MS PS, fOUT = 20.2MHz (Notes 4, 8) - 56 - dBc
fCLK = 50MS PS, fOUT = 5.02MHz, T = 25oC (Notes 4, 8) 68 73 - dBc
fCLK = 50MS PS, fOUT = 5.02MHz, T = Min to Max (Notes 4, 8) 66 - - dBc
fCLK = 50MS PS, fOUT = 2.51MHz (Notes 4, 8) - 76 - dBc
fCLK = 50MS PS, fOUT = 1.00MHz (Notes 4, 8) - 79 - dBc
fCLK = 25MS PS, fOUT = 1.0MHz (N otes 4, 8 ) - 78 - dBc
+3V Power Supply
Multitone Power Ratio fCLK = 20MSPS, fOUT = 2. 0 M H z t o 2 . 9 9 M Hz , 8 Tones at 110kHz
Spacing (Notes 4, 8) -75- dBc
fCLK = 100MSPS, fOUT = 10 MH z t o 1 4. 9 5M Hz , 8 Tones at 530kHz
Spacing (Notes 4, 8) -77- dBc
VOLTAGE REFERENCE
Internal Reference Voltage, VFSADJ Pin 18 Voltage with Internal Reference 1.13 1.2 1.28 V
Internal Reference Voltage Drift -±60 - ppm/οΧ
Internal Reference Output Current
Sink/Source Capability -±50 - µA
Reference Input Impedance -1-MΩ
Reference Input Multiplying Bandwidth (Note 8) - 1.4 - MHz
DIGITAL INPUTS D11-D0, CLK
Input Logic High Voltage with
5V Supply, VIH (Note 3) 3.5 5 - V
Input Logic High Voltage with
3V Supply, VIH (Note 3) 2.1 3 - V
Input Logic Low Voltage with
5V Supply, VIL (Note 3) - 0 1.3 V
Input Logic Low Voltage with
3V Supply, VIL (Note 3) - 0 0.9 V
Sleep Input Current, IIH -25 - +25 µA
Input Logic Current, IIH -20 - +20 µA
Input Logic Current, IIL -10 - +10 µA
Digital Input Capacitance, CIN -5- pF
TIMING CHARACTERISTICS
Data Setup Time, tSU See Figure 4 (Note 3) - 1.5 - ns
Data Hold Time, tHLD See Fig ure 4 (Note 3) - 1.2 - ns
Propagation Delay Time, tPD See Figure 4 - 2.5 - ns
CLK Pulse Width, tPW1, tPW2 See Figure 4 (Note 3) 4 - - ns
Electrical Specifications AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
HI5960
7
POWER SUPPLY CHARACTERISTICS
AVDD Power Supply (Notes 9) 2.7 5.0 5.5 V
DVDD Power Supply (Notes 9) 2.7 5.0 5.5 V
Analog Supply Current (IAVDD) 5V or 3V, IOUTFS = 20mA - 23 - mA
5V or 3V, IOUTFS = 2mA - 5 - mA
Digital Supply Current (IDVDD) 5V (Note 5) - 7 - mA
5V (Note 6) - 13 - mA
5V (Note 7) - 10 - mA
3V (Note 5) - 2 - mA
3V (Note 6) - 6 - mA
3V (Note 7) - 5 - mA
Supply Current (IAVDD) Sleep Mode 5V or 3V, IOUTFS = Don’t Care - 2.7 - mA
Power Dissipation 5V, IOUTFS = 20mA (Note 5) - 150 - mW
5V, IOUTFS = 20mA (Note 6) - 180 200 mW
5V, IOUTFS = 20mA (Note 7) - 165 - mW
5V, IOUTFS = 2mA (Note 6) - 80 - mW
3V, IOUTFS = 20mA (Note 5) - 75 - mW
3V, IOUTFS = 20mA (Note 6) - 87 100 mW
3V, IOUTFS = 20mA (Note 7) - 84 - mW
3V, IOUTFS = 2mA (Note 6) - 32 - mW
Power Supply Rejection Single Supply (Note 8) -0.2 - +0.2 % FSR/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625 µA). Ideally the
ratio should be 32.
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential transformer coupled output and no external filtering.
5. Measured with the clock at 50MSPS and the output frequency at 10MHz.
6. Measured with the clock at 100MSPS and the output frequency at 40MHz.
7. Measured with the clock at 130MSPS and the output frequency at 10MHz.
8. See “Definition of Specifications”.
9. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DVDD and AVDD
do not have to be equal.
Electrical Specifications AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
HI5960
8
Definition of Specifications
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Full Scale Gain Drift, is measured by setting the data inputs
to be all logic high (all 1s) and measuring the output voltage
through a known resistance as the temperature is varied
from TMIN to TMAX. It is defined as the ma ximum deviation
from the value measured at room temperature to the value
measured at either TMIN or TMAX. The units are ppm of FSR
(full scale range) per oC.
Full Scale Gain Error, is the error from an ideal ratio of 32
between the output current and the full scale ad just current
(through RSET).
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Internal Reference Voltage Drift, is defined as the
maximum deviation from the value measured at room
temperature to the value measured at either TMIN or TMAX.
The units are ppm per oC.
Offset Drift, is measured by setting the data inputs to all
logic low (all 0s) and measuring the output voltage through a
known resistance as the temperature is varied from TMIN to
TMAX. It is defined as the maximum deviation from the value
measured at room temperature to the value measured at
either TMIN or TMAX. The units are ppm of FSR (ful l scale
range) per degree oC.
Offset Error, is measured by setting the data inputs to all
logic low (all 0s) and measuring the output voltage through a
known resistance. Offset error is defined as the maximum
deviation of the output current from a value of 0mA.
Output Settlin g Ti me , is the time required for the output
voltage to settle to within a specified erro r band measured
from the beginning of the output transition. The
measurement is done by switching quarter scale.
Termination impedance was 25Ω due to the parallel
resistance of the 50Ω loading on the output and the
oscilloscope’s 50Ω input. This al so ai ds th e abil ity t o resolv e
the specified error band without overdriving the oscilloscope.
Output Voltage Compliance Ran ge, is the voltage limit
imposed on the output. The output impedance should be
chosen such that the voltage developed does not violate the
compliance range.
Power Supply Rejection, is measured using a single power
supply. The supply’s nominal +5V is varied ±10% and the
change in the DAC full scale output is noted .
Reference Input Multiplying Bandwidth, is defined as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference
with the digital inputs set to all 1s. The frequency is
increased until the amplitude of the output waveform is
0.707 (-3dB) of its original value.
Singlet Glitch Area, is the switching transient appearing on
the output during a code transition. It is measured as the
area under the overshoot portion of the curve and is
expressed as a Volt-Time specification. This is tested using
a single code transition across a major current source.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental signal to the largest
harmonically or non-harmonically related spur within the
specified frequency wi ndow.
Total Harmonic Distortion, THD, is the ratio of the RMS
value of the fundamental output signal to the RMS sum of
the first five harmonic components.
Detailed Description
The HI5960 is a 14-bit, current out, CMOS, digital to analog
converter. Its maximum update rate is 130MSPS and can be
powered by either single or dual power supplies in the
recommended range of +3V to +5V. Operation with clock
rates higher than 130MSPS is possible; please contact the
factory for more information. It consumes less than 180mW
of power when using a +5V supply with the data switching at
130MSPS. The architecture is based on a segmented
current source arrangement that reduces glitch by reducing
the amount of current switching at any one time. In previous
architectures that contained all binary weighted current
sources or a binary weighted resistor ladde r, the converter
might have a substantially larg er amount of curre nt turning
on and off at certain, worst-case transition points such as
midscale and quarter scale transitions. By greatly reducing
the amount of current switching at certain “major” transitions,
the overall glitch of the converter is dramatically reduced,
improving settling time, transient problems, and accuracy.
Digital Inputs and Termination
The HI5960 digital inputs are guaranteed to CMOS levels.
However, TTL compatibility can be achieved by lowering the
supply voltage to 3V due to the digital threshold of the input
buffer being approximately half of the supply voltage. The
internal register is update d on the rising edge of the clock.
To minimize reflections, proper termination should be
implemented. If the lines drivi ng the clock and the digital
inputs are long 50Ω lines, then 50Ω termination resistors
should be placed as close to the converter inputs as possible
connected to the digital ground pl ane (if separate grounds
are used). These termination resistors are not li kely needed
as long as the digital waveform source is within a few inches
of the DAC.
Ground Planes
Separate digital and analog ground planes should be used.
All of the digital functions of the device and their
HI5960
9
corresponding components should be located over the
digital ground plane and terminate d to the digital ground
plane. The same is true for the analog componen ts and the
analog ground plane. Consult Application Note 9853.
Noise Reduction
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the converter’s power supply
pins, AVDD and DVDD. Also, the layout should be designed
using separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
DVDD and to the analog gr ound for AVDD. Additional
filtering of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a no minal
value of +1.2V with a ±60ppm/oC drift coefficient over the
full temperature range of the converter. It is re commended
that a 0.1 µF capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO pin
(16) selects the reference. The internal reference can be
selected if pin 16 is tied low (ground). If an external
reference is desired, then pin 16 should be tied high (the
analog supply voltage) and the external reference driven into
REFIO, pin 17. The full scale output current of the converter
is a function of the voltage reference used and the value of
RSET. IOUT should be within the 2mA to 20mA range,
though operation below 2mA is possi ble, with performance
degradation.
If the internal reference is used, VFSADJ will equal
approximately 1.2V (pin 18). If an external reference is used,
VFSADJ will equal the external reference. The calculation for
IOUT (Full Scale) is:
IOUT(Full Scale) = (VFSADJ/RSET) X 32.
If the full scale output curren t is set to 20mA by using the
internal voltage reference (1.2V) and a 1.91kΩ RSET
resistor, then the input coding to output current will resemble
the following:
Outputs
IOUTA and IOUTB are complementary current outputs. The
sum of the two currents is always equal to the full scale
output current minus one LSB. If singl e ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the output voltage
compliance range of -0.3V to 1.25V. RLOAD (the impedance
loading each current output) should be chosen so that the
desired output voltage is produced in conjunction with the
output full scale current. If a known line impedance is to be
driven, then the output load resistor should be chosen to
match this impedance. The output voltage equa tion is:
VOUT = IOUT X RLOAD.
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmon ic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 21
and 22 will be biased at zero volts. The loading as shown in
Figure 1 will result in a 500mV signal at the outp ut of th e
transformer if the full scale output current of the DAC is set
to 20mA.
VOUT = 2 x IOUT x REQ, where REQ is ~12.5Ω. Allowing the
center tap to float will result in identical transformer output,
however the output pins of the DAC will have positive DC
offset. Since the DAC’s output voltage compliance range is -
0.3V to +1.25V, the center tap may need to be left floating or
DC offset in order to increase the amount of signal swing
available. The 50Ω load on the output of the transformer
represents the spectrum analyzer’s input impedance.
TABLE 1. INPUT CODING vs OUTPUT CURRENT
INPUT CODE (D13-D0) IOUTA (mA) IOUTB (mA)
1111 11111 11111 20 0
1000 00000 00000 10 10
0000 00000 00000 0 20
PIN 21
PIN 22 100Ω
HI5960
50Ω
50Ω
50Ω
FIGURE 1.
IOUTB
IOUTA
VOUT = (2 x IOUT x REQ)V
REQ IS THE IMPEDANCE
LOADING EACH OUTPUT
SPECTRUM ANALYZER
50Ω REPRESENTS THE
HI5960
10
Timing Diagrams
FIGURE 2. OUTPUT SETTLING TIME DIAGRAM FIGURE 3. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
FIGURE 4. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
CLK
D13-D0
IOUT
50%
tSETT
ERROR BAND
tPD
V
t(ps)
HEIGHT (H)
WIDTH (W)
GLITCH AREA = 1/2 (H x W)
CLK
IOUT
50%
tPW1 tPW2
tSU
tHLD
tSU tSU
tPD
tPD tPD
tHLD tHLD
tSETT
tSETT tSETT
D13-D0
HI5960
11
HI5960
Small Outline Plastic Packages (SOIC)
α
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H0.25(0.010) BM M
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.6969 0.7125 17.70 18.10 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.01 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N28 287
α0o8o0o8o-
Rev. 0 12/93
12
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is grant ed by impl icati on or ot herwise under any pate nt or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
HI5960
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004) c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AE, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M28.173
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.051 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.378 0.386 9.60 9.80 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N28 287
α0o8o0o8o-
Rev. 0 6/98
