Low Distortion
Differential RF/IF Amplifier
Data Sheet AD8351
Rev. D Document Feedback
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FEATURES
−3 dB bandwidth of 2.2 GHz for AV = 12 dB
Single resistor programmable gain: 0 dB ≤ AV ≤ 26 dB
Differential interface
Low noise input stage 2.7 nV/√Hz at AV = 10 dB
Low harmonic distortion
−79 dBc second at 70 MHz
−81 dBc third at 70 MHz
OIP3 of 31 dBm at 70 MHz
Single-supply operation: 3 V to 5.5 V
Low power dissipation: 28 mA at 5 V
Adjustable output common-mode voltage
Fast settling and overdrive recovery
Slew rate of 13,000 V/μs
Power-down capability
APPLICATIONS
Differential ADC drivers
Single-ended-to-differential conversion
IF sampling receivers
RF/IF gain blocks
SAW filter interfacing
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The AD8351 is a low cost differential amplifier useful in RF and
IF applications up to 2.2 GHz. The voltage gain can be set from
unity to 26 dB using a single external gain resistor. The AD8351
provides a nominal 150 Ω differential output impedance. The
excellent distortion performance and low noise characteristics
of this device allow for a wide range of applications.
The AD8351 is designed to satisfy the demanding performance
requirements of communications transceiver applications. The
device can be used as a general-purpose gain block, an ADC
driver, and a high speed data interface driver, among other
functions. The AD8351 can also be used as a single-ended-to-
differential amplifier with similar distortion products as in the
differential configuration. The exceptionally good distortion
performance makes the AD8351 an ideal solution for 12-bit and
14-bit IF sampling receiver designs.
Fabricated in Analog Devices, Inc., high speed XFCB process,
the AD8351 has high bandwidth that provides high frequency
performance and low distortion. The quiescent current of the
AD8351 is 28 mA typically. The AD8351 amplifier comes in a
compact 10-lead MSOP package or in a 16-lead LFCSP package,
and operates over the temperature range of −40°C to +85°C.
VOCM
VPOS
OPHI
OPLO
COMM
PWUP
RGP1
INHI
INLO
RGP2
AD8351
BIAS CELL
0
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
+
23
AD8351 WITH 10dB OF
GAIN DRIVING THE
AD6645 (RL = 1k)
ANALOG INPUT = 70MHz
ENCORE = 80MHz
SNR = 69.1dB
FUND = –1.1dBFS
HD2 = –78.5dBc
HD3 = –80.7dBc
THD = –75.9dBc
SFDR = 78.2dBc
25
R
G
200
100nF
25
100nF
AD8351 AD6645
14-BIT
ADC
INHI
INLO
03145-001
AD8351 Data Sheet
Rev. D | Page 2 of 19
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 12
Basic Concepts ............................................................................ 12
Gain Adjustment ........................................................................ 12
Common-Mode Adjustment .................................................... 12
Input and Output Matching ...................................................... 12
Single-Ended-to-Differential Operation ................................. 13
ADC Driving ............................................................................... 13
Analog Multiplexing .................................................................. 14
I/O Capacitive Loading ............................................................. 14
Transmission Line Effects ......................................................... 15
Characterization Setup .............................................................. 16
Evaluation Board ............................................................................ 17
Outline Dimensions ....................................................................... 19
Ordering Guide ............................................................................... 19
REVISION HISTORY
1/15—Rev. C to Rev. D
Changes to Noise Distortion Parameter, Table 1 .......................... 3
Changes to Ordering Guide .......................................................... 19
3/14—Rev. B to Rev. C
Updated Format .................................................................. Universal
Added 16-Lead LFCSP Package................................... Throughout
Changes to Features .......................................................................... 1
Changes to Table 3 and Added Figure 3; Renumbered
Sequentially ....................................................................................... 6
Updated Outline Dimensions; Added Figure 52 ........................ 19
Moved, Changes to Ordering Guide ............................................ 19
2/04—Rev. A to Rev. B
Changes to Ordering Guide ............................................................ 4
Changes to TPC 4 ............................................................................. 5
3/03—Rev. 0 to Rev. A
Changes to Ordering Guide ............................................................ 4
Change to Table 3 ........................................................................... 15
3/03—Revision 0: Initial Version
Data Sheet AD8351
Rev. D | Page 3 of 19
SPECIFICATIONS
VS = 5 V, RL = 150 , RG = 110 (AV = 10 dB), f = 70 MHz, T = 25°C, parameters specified differentially, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth GAIN = 6 dB, VOUT ≤ 1.0 V p-p 3,000 MHz
GAIN = 12 dB, VOUT ≤ 1.0 V p-p 2,200 MHz
GAIN = 18 dB, VOUT ≤ 1.0 V p-p 600 MHz
Bandwidth for 0.1 dB Flatness 0 dB ≤ GAIN ≤ 20 dB, VOUT ≤ 1.0 V p-p 200 MHz
Bandwidth for 0.2 dB Flatness 0 dB ≤ GAIN ≤ 20 dB, VOUT ≤ 1.0 V p-p 400 MHz
Gain Accuracy Using 1% resistor for RG, 0 dB ≤ AV ≤ 20 dB ±1 dB
Gain Supply Sensitivity VS ± 5% 0.08 dB/V
Gain Temperature Sensitivity −40°C to +85°C 3.9 mdB/°C
Slew Rate RL = 1 kΩ, VOUT = 2 V step 13,000 V/μs
R
L = 150 Ω, VS = 2 V step 7,500 V/μs
Settling Time 1 V step to 1% <3 ns
Overdrive Recovery Time VIN = 4 V to 0 V step, VOUT ≤ ±10 mV <2 ns
Reverse Isolation (S12) −67 dB
INPUT/OUTPUT CHARACTERISTICS
Input Common-Mode Voltage Adjustment Range 1.2 to 3.8 V
Max Output Voltage Swing 1 dB compressed 4.75 V p-p
Output Common-Mode Offset 40 mV
Output Common-Mode Drift −40°C to +85°C 0.24 mV/°C
Output Differential Offset Voltage 20 mV
Output Differential Offset Drift −40°C to +85°C 0.13 mV/°C
Input Bias Current ±15 μA
Input Resistance1 5 kΩ
Input Capacitance1 0.8 pF
CMRR 43 dB
Output Resistance1 150 Ω
Output Capacitance1 0.8 pF
POWER INTERFACE
Supply Voltage 3 5.5 V
PWUP Threshold 1.3 V
PWUP Input Bias Current PWUP at 5 V 100 μA
PWUP at 0 V 25 μA
Quiescent Current 28 32 mA
NOISE/DISTORTION
10 MHz
Second/Third Harmonic Distortion2 R
L = 1 kΩ, VOUT = 2 V p-p −95/−93 dBc
R
L = 150 Ω, VOUT = 2 V p-p −80/−69 dBc
Third-Order IMD RL = 1 kΩ, f1 = 9.5 MHz, f2 = 10.5 MHz,
VOUT = 2 V p-p composite
−90 dBc
RL = 150 Ω, f1 = 9.5 MHz, f2 = 10.5 MHz,
VOUT = 2 V p-p composite
−70 dBc
Output Third-Order Intercept f1 = 9.5 MHz, f2 = 10.5 MHz 33 dBm
Noise Spectral Density (RTI) 2.65 nV/√Hz
1 dB Compression Point 13.5 dBm
AD8351 Data Sheet
Rev. D | Page 4 of 19
Parameter Test Conditions/Comments Min Typ Max Unit
70 MHz
Second/Third Harmonic Distortion2 R
L = 1 kΩ, VOUT = 2 V p-p −79/−81 dBc
R
L = 150 Ω, VOUT = 2 V p-p −65/−66 dBc
Third-Order IMD RL = 1 kΩ, f1 = 69.5 MHz, f2 = 70.5 MHz,
VOUT = 2 V p-p composite
−85 dBc
RL = 150 Ω, f1 = 69.5 MHz, f2 = 70.5 MHz,
VOUT = 2 V p-p composite
−69 dBc
Output Third-Order Intercept f1 = 69.5 MHz, f2 = 70.5 MHz 31 dBm
Noise Spectral Density (RTI) 2.70 nV/√Hz
1 dB Compression Point 13.3 dBm
140 MHz
Second/Third Harmonic Distortion2 R
L = 1 kΩ, VOUT = 2 V p-p −69/−69 dBc
R
L = 150 Ω, VOUT = 2 V p-p −54/−53 dBc
Third-Order IMD RL = 1 kΩ, f1 = 139.5 MHz, f2 = 140.5 MHz,
VOUT = 2 V p-p composite
−79 dBc
RL = 150 Ω, f1 = 139.5 MHz, f2 = 140.5 MHz,
VOUT = 2 V p-p composite
−67 dBc
Output Third-Order Intercept f1 = 139.5 MHz, f2 = 140.5 MHz 29 dBm
Noise Spectral Density (RTI) 2.75 nV/√Hz
1 dB Compression Point 13 dBm
240 MHz
Second/Third Harmonic Distortion2 R
L = 1 kΩ, VOUT = 2 V p-p −60/−66 dBc
R
L = 150 Ω, VOUT = 2 V p-p −46/−50 dBc
Third-Order IMD RL = 1 kΩ, f1 = 239.5 MHz, f2 = 240.5 MHz,
VOUT = 2 V p-p composite
−76 dBc
RL = 150 Ω, f1 = 239.5 MHz, f2 = 240.5 MHz,
VOUT = 2 V p-p composite
−62 dBc
Output Third-Order Intercept f1 = 239.5 MHz, f2 = 240.5 MHz 27 dBm
Noise Spectral Density (RTI) 2.90 nV/√Hz
1 dB Compression Point 13 dBm
1 Values are specified differentially.
2 See the Single-Ended-to-Differential Operation section for single-ended-to-differential performance.
Data Sheet AD8351
Rev. D | Page 5 of 19
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage VPOS 6 V
PWUP Voltage VPOS
Internal Power Dissipation 320 mW
θJA 125°C/W
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range (Soldering 60 sec) 300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
AD8351 Data Sheet
Rev. D | Page 6 of 19
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 2. 10-Lead MSOP Pin Configuration Figure 3. 16-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Description
10-Lead MSOP 16-Lead LFCSP
1 16 PWUP Apply a positive voltage (1.3 V ≤ VPWUP ≤ VPOS) to activate device.
2 1 RGP1 Gain Resistor Input 1.
3 2 INHI Balanced Differential Input. Biased to midsupply, typically ac-coupled.
4 3 INLO Balanced Differential Input. Biased to midsupply, typically ac-coupled.
5 4 RGP2 Gain Resistor Input 2.
6 9 COMM Device Common. Connect to low impedance ground.
7 10 OPLO Balanced Differential Output. Biased to VOCM, typically ac-coupled.
8 11 OPHI Balanced Differential Output. Biased to VOCM, typically ac-coupled.
9 12 VPOS Positive Supply Voltage. 3 V to 5.5 V.
10 13 VOCM
Voltage applied to this pin sets the common-mode voltage at both the input and
output. Typically decoupled to ground with a 0.1 μF capacitor.
5, 6, 7, 8, 14, 15 NC No connect. Do not connect to this pin.
EPAD
Exposed Pad. The exposed pad is internally connected to GND and must be soldered
to a low impedance ground plane.
PWUP
1
RGP1
2
INHI
3
INLO
4
RGP2
5
VOCM
10
VPOS
9
OPHI
8
OPLO
7
COMM
6
AD8351
TOP VIEW
(Not to Scale)
03145-050
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
RGP1
INHI
INLO
RGP2
VPOS
VOCM
NC
NC
PWUP
OPHI
OPLO
COMM
NC
NC
NC
NC
AD8351
TOP VIEW
(Not to Scale)
03145-002
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO
GND AND MUST BE SOLDERED TO A LOW
IMPEDANCE GROUND PLANE.
Data Sheet AD8351
Rev. D | Page 7 of 19
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, T = 25°C, unless otherwise noted.
Figure 4. Gain vs. Frequency for a 150 Ω Differential Load
(AV = 6 dB, 12 dB, and 18 dB)
Figure 5. Gain vs. Gain Resistor, RG (f = 100 MHz,
RL = 150 Ω, 1 kΩ, and Open)
Figure 6. Gain vs. Temperature at 100 MHz (AV = 10 dB
Figure 7. Gain vs. Frequency for a 1 kΩ Differential Load
(AV = 10 dB, 18 dB, and 26 dB)
Figure 8. Gain Flatness vs. Frequency
(RL = 150 Ω and 1 kΩ, AV = 10 dB)
Figure 9. Isolation vs. Frequency (AV = 10 dB)
20
–5
0
5
10
15
1 10 100 1000 10000
GAIN (dB)
FREQUENCY (MHz)
R
G
= 20
R
G
= 80
R
G
= 200
03145-003
35
30
25
20
15
10
5
0
–10
–5
10 100 1k 10k
GAIN (dB)
R
G
()
R
L
= OPEN
R
L
= 150
R
L
= 1k
03145-004
10.75
9.25
9.50
9.75
10.00
10.25
10.50
10.50
9.00
9.25
9.50
9.75
10.00
10.25
–50 –30 –10 10 30 50 70 90 110
GAIN; R
L
= 1k (dB)
GAIN; R
L
= 150 (dB)
TEMPERATURE (°C)
03145-005
30
25
20
0
5
10
15
1 10 100 1000 10000
GAIN (dB)
FREQUENCY (MHz)
R
G
= 10
R
G
= 50
R
G
= 200
03145-006
1 10 100 1000
GAIN FLATNESS (dB)
FREQUENCY (MHz)
0.8
0.4
0
–0.4
–0.8
–1.0
0.6
0.2
–0.2
–0.6
0.5
0.1
–0.3
–0.7
–0.9
0.7
0.3
–0.1
–0.5
0.9
1.0
R
L
= 150
R
L
= 1k
03145-007
01000900800700600500400300200100
ISOLATION (dB)
FREQUENCY (MHz)
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
03145-008
AD8351 Data Sheet
Rev. D | Page 8 of 19
Figure 10. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 1 kΩ
(AV = 10 dB, at 3 V and 5 V Supplies)
Figure 11. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 150 Ω
(AV = 10 dB)
Figure 12. Noise Spectral Density (RTI) vs. Frequency
(RL = 150 Ω, 5 V Supply, AV = 10 dB)
Figure 13. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 1 kΩ Using
Single-Ended Input (AV = 10 dB)
Figure 14. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 150 Ω
Using Single-Ended Input (AV = 10 dB)
Figure 15. Noise Spectral Density (RTI) vs. Frequency
(RL = 150 Ω, 3 V Supply, AV = 10 dB)
–
30
–40
–50
–60
–70
–80
–90
–100
–
45
–55
–65
–75
–85
–95
–105
–115
0 250225200175150125100755025
HARMONIC DISTORTION; VPOS = 5V (dBc)
HARMONIC DISTORTION; VPOS = 3V (dBc)
FREQUENCY (MHz)
DIFFERENTIAL INPUT
HD3
HD3
HD2
HD2
03145-009
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
–
20
–110
–100
–90
–80
–70
–60
–50
–40
–30
0 250225200175150125100755025
HARMONIC DISTORTION; VPOS = 5V (dBc)
HARMONIC DISTORTION; VPOS = 3V (dBc)
FREQUENCY (MHz)
DIFFERENTIAL INPUT
HD3
HD3
HD2
HD2
03145-010
3.00
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
2.95
0 25020015010050
NOISE SPECTRAL DENSITY (nV/Hz)
FREQUENCY (MHz)
03145-011
–
50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
010080604020 9070503010
HARMONIC DISTORTION (dBc)
FREQUENCY (MHz)
SINGLE-ENDED INPUT
HD2
HD3
03145-012
–
50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
010080604020 9070503010
HARMONIC DISTORTION (dBc)
FREQUENCY (MHz)
SINGLE-ENDED INPUT
HD2
HD3
03145-013
3.00
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
2.95
0 25020015010050
NOISE SPECTRAL DENSITY (nV/Hz)
FREQUENCY (MHz)
03145-014
Data Sheet AD8351
Rev. D | Page 9 of 19
Figure 16. Output Compression Point, P1 dB, vs. Frequency
(RL = 150 Ω and 1 kΩ, AV = 10 dB, at 3 V and 5 V Supplies)
Figure 17. Output Compression Point, P1 dB, vs. RG (f =100 MHz,
RL = 150 Ω, AV = 10 dB, at 3 V and 5 V Supplies)
Figure 18. Output Compression Point Distribution
(f = 70 MHz, RL = 150 Ω, AV = 10 dB)
Figure 19. Third-Order Intermodulation Distortion vs. Frequency for a 2 V p-p
Composite Signal into RL = 1 kΩ (AV = 10 dB, at 5 V Supplies)
Figure 20. Third-Order Intermodulation Distortion vs. Frequency for a 2 V p-p
Composite Signal into RL = 150 Ω (AV = 10 dB, at 5 V Supplies)
Figure 21. Third-Order Intermodulation Distortion Distribution
(f = 70 MHz, RL = 150 Ω, AV = 10 dB)
16
14
12
10
8
6
4
2
0
025020015010050 2251751257525
OUTPUT 1dB COMPRESSION (dBm)
FREQUENCY (MHz)
R
L
= 150
VPOS = 5V
R
L
= 1k
R
L
= 150
VPOS = 3V
R
L
= 1k
03145-015
16
14
12
10
8
6
4
2
0
10 1000100
OUTPUT 1dB COMPRESSION (dBm)
GAIN RESISTOR ()
VPOS = 5V
VPOS = 3V
03145-016
OUTPUT 1dB COMPRESSION (dB)
13.29
13.31
13.33
13.34
13.30
13.32
13.35
13.36
13.37
13.38
13.39
13.40
13.41
03145-017
–
70
–75
–80
–85
–90
–95
025020015010050 2251751257525
THIRD-ORDER IMD (dBc)
FREQUENCY (MHz)
03145-018
–
50
–55
–60
–65
–70
–75
025020015010050 2251751257525
THIRD-ORDER IMD (dBc)
FREQUENCY (MHz)
03145-019
THIRD-ORDER INTERMODULATION DISTORTION (dBc)
–68.0 –68.2 –68.4 –68.6 –68.8 –69.0 –69.2 –69.4 –69.6 –70.0–69.8
03145-020
AD8351 Data Sheet
Rev. D | Page 10 of 19
Figure 22. Input Impedance vs. Frequency
Figure 23. Output Impedance vs. Frequency
Figure 24. Phase and Group Delay (AV = 10 dB, at 5 V Supplies)
Figure 25. Input Reflection Coefficient vs. Frequency (RS = RL = 100 Ω With
and Without 50 Ω Terminations)
Figure 26. Output Reflection Coefficient vs. Frequency (RS = RL = 100 Ω)
4000
3500
3000
2500
2000
1500
1000
500
0
0
–100
–75
–50
–25
10 1000100
IMPEDANCE MAGNITUDE ()
PHASE (Degrees)
FREQUENCY (MHz)
03145-021
160
150
140
130
120
110
100
30
0
15
10
5
20
25
10 1000100
IMPEDANCE MAGNITUDE ()
IMPEDANCE PHASE (Degrees)
FREQUENCY (MHz)
03145-022
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
20
0
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
0250125 225100 20075 17550 15025
PHASE (Degrees)
GROUP DELAY (ps)
FREQUENCY (MHz)
03145-023
10MHz
3GHz
3GHz
10MHz
WITHOUT
TERMINATIONS
WITH 50
TERMINATIONS
500MHz 500MHz
03145-024
3GHz
10MHz
500MHz
03145-025
Data Sheet AD8351
Rev. D | Page 11 of 19
Figure 27. Common-Mode Rejection Ratio, CMRR (RS = 100 Ω)
Figure 28. Transient Response Under Capacitive Loading
(RL = 150 Ω, CL = 0 pF, 2 pF, 5 pF, 10 pF)
Figure 29. 2× Output Overdrive Recovery (RL = 150 Ω, AV = 10 dB)
Figure 30. Overdrive Recovery Using Sinusoidal Input Waveform RL = 150 Ω
(AV = 10 dB, at 5 V Supplies)
Figure 31. Large Signal Transient Response for a 1 V p-p Output Step
(AV = 10 dB, RIP = 25 Ω)
Figure 32. 1% Settling Time for a 2 V p-p Step (AV = 10 dB, RL = 150 Ω)
1 10 100 1000
CMRR (dB)
FREQUENCY (MHz)
20
80
70
60
50
40
30
R
L
= 150
R
L
= 1k
03145-026
15 25242322212019181716
VOLTAGE (V)
TIME (ns)
–0.6
0.6
0.4
0.2
0
–0.2
–0.4
0pF
5pF
10pF
2pF
03145-027
0403530252015105
OUTPUT (V)
TIME (ns)
5.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.5
03145-028
05045403530252015105
VOLTAGE (V)
TIME (ns)
3
2
1
0
–1
–2
–3
V
IN
V
OUT
03145-029
04.03.53.02.52.01.51.00.5
VOLTAGE (V)
TIME (ns)
1.00
–1.00
–0.75
–0.50
–0.25
0
0.25
0.50
0.75
03145-030
01512963
SETTLING (%)
TIME (ns)
5
–5
–4
–3
–2
–1
0
1
2
3
4
03145-031
AD8351 Data Sheet
Rev. D | Page 12 of 19
THEORY OF OPERATION
BASIC CONCEPTS
Differential signaling is used in high performance signal chains,
where distortion performance, signal-to-noise ratio, and low
power consumption is critical. Differential circuits inherently
provide improved common-mode rejection and harmonic
distortion performance as well as better immunity to
interference and ground noise.
Figure 33. Differential Circuit Representation
Figure 33 illustrates the expected input and output waveforms
for a typical application. Usually the applied input waveform is a
balanced differential drive, where the signal applied to the INHI
and INLO pins are equal in amplitude and differ in phase by 180°.
In some applications, baluns may be used to transform a single-
ended drive signal to a differential signal. The AD8351 may also
be used to transform a single-ended signal to a differential signal.
GAIN ADJUSTMENT
The differential gain of the AD8351 is set using a single external
resistor, RG, which is connected between the RGP1 pin and the
RGP2 pin. The gain can be set to any value between 0 dB and 26 dB
using the resistor values specified in Figure 5, with common gain
values provided in Table 4. The board traces used to connect the
external gain resistor must be balanced and as short as possible to
help prevent noise pickup and to ensure balanced gain and stability.
The low frequency voltage gain of the AD8351 can be modeled as
IN
OUT
G
FL
G
L
G
LF
G
L
VV
V
RRRRRR
RRRR
A
395.196.4
2.9)6.5(
where:
RF is 350 Ω (internal).
RL is the single-ended load resistance.
RG is the gain setting resistor.
Table 4. Gain Resistor Selection for Common Gain Values
(Load Resistance Is Specified as Single-Ended)
Gain, AV R
G (RL = 75 Ω) RG (RL = 500 Ω)
0 dB 680 Ω 2 kΩ
6 dB 200 Ω 470 Ω
10 dB 100 Ω 200 Ω
20 dB 22 Ω 43 Ω
COMMON-MODE ADJUSTMENT
The output common-mode voltage level is the dc offset voltage
present at each of the differential outputs. The ac signals are of
equal amplitude with a 180° phase difference but are centered at
the same common-mode voltage level. The common-mode output
voltage level can be adjusted from 1.2 V to 3.8 V by driving the
desired voltage level into the VOCM pin, as illustrated in Figure 34.
Figure 34. Common-Mode Adjustment
INPUT AND OUTPUT MATCHING
The AD8351 provides a moderately high differential input imped-
ance of 5 kΩ. In practical applications, the input of the AD8351
is terminated to a lower impedance to provide an impedance
match to the driving source, as shown in Figure 35. Place the
terminating resistor, RT, as close as possible to the input pins to
minimize reflections due to impedance mismatch. The 150 Ω
output impedance may need to be transformed to provide the
desired output match to a given load. Matching components
can be calculated using a Smith chart or by using a resonant
approach to determine the matching network that results in a
complex conjugate match. The input and output impedances
and reflection coefficients are provided in Figure 22, Figure 23,
Figure 24, and Figure 25. For additional information on reactive
matching to differential sources and loads, refer to the Applications
section of the AD8350 data sheet.
Figure 35. Example of Differential SAW Filter Interface (fC = 190 MHz)
03145-032
R
G
BALANCED
SOURCE R
L
A
A
2A
16
PWUP
15
NC
14
NC
13
VOCM
16
NC
15
NC
14
NC
13
NC
RGP1
INHI
INLO
RGP2
1
2
3
4
VPOS
OPHI
OPLO
COMM
12
11
10
9
03145-033
R
L
BALANCED
SOURCE R
G
0.1µF
V
S
C
DECL
0.1µF
V
OCM
1.2V
TO
3.8V
16
PWUP
15
NC
14
NC
13
VOCM
5
NC
6
NC
7
NC
8
NC
RGP1
INHI
INLO
RGP2
1
2
3
4
VPOS
OPHI
OPLO
COMM
12
11
10
9
BALANCED
SOURCE
R
S
R
S
R
T
R
T
R
S
= R
T
0.1µF
0.1µF
0.1µF
C
P
8pF
L
S
27nF
L
S
27nF
15050
0.1µF
R
G
190MHz SAW
VPOS
AD8351
03145-034
Data Sheet AD8351
Rev. D | Page 13 of 19
Figure 35 illustrates a surface acoustic wave (SAW) filter interface.
Many SAW filters are inherently differential, allowing for a low
loss output match. In this example, the SAW filter requires a 50 Ω
source impedance to provide the desired center frequency and
Q. The series L shunt C output network provides a 150 Ω to
50 Ω impedance transformation at the desired frequency of
operation. The impedance transformation is illustrated on a
Smith chart in Figure 36.
It is possible to drive a single-ended SAW filter by connecting
the unused output to ground using the appropriate terminating
resistance. The overall gain of the system is reduced by 6 dB
because only half of the signal is available to the input of the
SAW filter.
Figure 36. Smith Chart Representation of SAW Filter Output Matching Network
Figure 37. Single-Ended Application
SINGLE-ENDED-TO-DIFFERENTIAL OPERATION
The AD8351 can easily be configured as a single-ended-to-
differential gain block, as illustrated in Figure 37. The input signal
is ac-coupled and applied to the INHI input. The unused input
is ac-coupled to ground. Select the values of C1 through C4 such
that their reactances are negligible at the desired frequency of
operation. To balance the outputs, an external feedback resistor,
RF, is required. To select the gain resistor and the feedback resistor,
refer to Figure 38 and Figure 39. From Figure 38, select an RG for
the required dB gain at a given load. Next, select from Figure 39
an RF resistor for the selected RG and load.
Even though the differential balance is not perfect under these
conditions, the distortion performance is still impressive. Figure 13
and Figure 14 show the second and third harmonic distortion
performance when driving the input of the AD8351 using a
single-ended 50 Ω source.
Figure 38. Gain Selection
Figure 39. Feedback Resistor Selection
ADC DRIVING
The circuit in Figure 40 represents a simplified front end of the
AD8351 driving the AD6645, which is a 14-bit, 105 MSPS ADC.
For optimum performance, the AD6645 and the AD8351 are
driven differentially. The resistors R1 and R2 present a 50 Ω
differential input impedance to the source with R3 and R4
providing isolation from the analog-to-digital input. The gain
setting resistor for the AD8351 is RG. The AD6645 presents a
1 kΩ differential load to the AD8351 and requires a 2.2 V p-p
differential signal between AIN and AIN for a full-scale output.
This AD8351 circuit then provides the gain, isolation, and source
matching for the AD6645. The AD8351 also provides a balanced
input, not provided by the balun, to the AD6645, which is essential
for second-order cancellation. The signal generator is bipolar,
centered around ground. Connecting the VOCM pin (Pin 10 on
the MSOP and Pin 13 on the LFCSP) of the AD8351 to the VREF
pin of the AD6645 sets the common-mode output voltage of the
AD8351 at 2.4 V. This voltage is bypassed with a 0.1 µF capacitor.
Increasing the gain of the AD8351 increases the system noise and
thus decrease the SNR but does not significantly affect the
distortion. The circuit in Figure 40 can provide SFDR performance
of better than −90 dBc with a 10 MHz input and −80 dBc with a
70 MHz input at a gain of 10 dB.
200
0
50150
SERIES L SHUNT C
500
100
50
25
10
100
500
50
25
10
200
03145-035
AD8351 R
L
R
F
R
G
0.1µF0.1µF
0.1µF
50
50
25
0.1µF
03145-036
35
30
25
20
15
10
5
0
10 1000100
GAIN (dB)
R
G
()
R
L
= 1000
R
L
= 150R
L
= 500
03145-037
7
6
5
4
3
2
1
0
10 1000100
RF (k)
RG ()
RL = 1000
RL = 150
RL = 500
03145-038
AD8351 Data Sheet
Rev. D | Page 14 of 19
Figure 40. ADC Driving Application Using Differential Input
The circuit of Figure 41 represents a single-ended input to
differential output configuration of the AD8351 driving the
AD6645. In this case, R1 provides the input impedance. RG is
the gain setting resistor. The resistor RF is required to balance
the output voltages required for second-order cancellation by
the AD6645 and can be selected using a chart (see the Single-
Ended-to-Differential Operation section). The circuit depicted
in Figure 41 can provide SFDR performance of better than −90 dBc
with a 10 MHz input and −77 dBc with a 70 MHz input.
Figure 41. ADC Driving Application Using Single-Ended Input
ANALOG MULTIPLEXING
The AD8351 can be used as an analog multiplexer in applications
where it is desirable to select multiple high speed signals. The
isolation of each device when in a disabled state (PWUP pin
pulled low) is about 60 dBc for the maximum input level of
0.5 V p-p out to 100 MHz. The low output noise spectral density
allows for a simple implementation as depicted in Figure 42.
The PWUP interface can be easily driven using most standard
logic interfaces. By using an N-bit digital interface, up to N devices
can be controlled. Output loading effects and noise need to be
considered when using a large number of input signal paths. Each
disabled AD8351 presents approximately a 700 Ω load in parallel
with the 150 Ω output source impedance of the enabled device.
As the load increases due to the addition of N devices, the
distortion performance will degrade due to the heavier loading.
Distortion better than −70 dBc can be achieved with four devices
muxed into a 1 kΩ load for signal frequencies up to 70 MHz.
Figure 42. Using Several AD8351s to Form an N-Channel Analog MUX
I/O CAPACITIVE LOADING
Input or output direct capacitive loading greater than a few
picofarads can result in excessive peaking and/or oscillation
outside the pass band. This results from the package and bond
wire inductance resonating in parallel with the input/output
capacitance of the device and the associated coupling that results
internally through the ground inductance. For low resistive load
or source resistance, the effective Q is lower, and higher relative
capacitance termination or terminations can be allowed before
oscillation or excessive peaking occurs. These effects can be
eliminated by adding series input resistors (RIP) for high source
capacitance, or series output resistors (ROP) for high load
capacitance. Generally less than 25 Ω is all that is required for I/O
capacitive loading greater than ~2 pF. The higher the C, the smaller
the R parasitic suppression resistor required. In addition, RIP helps
to reduce low gain in-band peaking, especially for light resistive
loads.
Figure 43. Input and Output Parasitic Suppression Resistors, RIP and ROP,
Used to Suppress Capacitive Loading Effects
BALANCE
50
SOURCE
25
25
25
25
100nF
100nF
AD8351
INHI
INLO
R
G
OPHI
OPLO
VOCM
DIGITAL
OUT
AD6645
AIN
AIN VREF
03145-039
SINGLE-
ENDED
50
SOURCE
25
R1
25
25
25
100nF
100nF
AD8351
INHI
INLO
R
G
OPHI
OPLO
100nF
VOCM
DIGITAL
OUT
AD6645
AIN
AIN VREF
R
F
03145-040
AD8351
INHI
R
G
R
G
R
G
RGP1
RGP2
INLO
S
IGNAL
INPUT 1
S
IGNAL
INPUT
2
S
IGNAL
INPUT N
OPLO
OPHI
BIT 1
PWUP
AD8351
INHI
RGP1
RGP2
INLO OPLO
OPHI
BIT 2
PWUP
AD8351
INHI
RGP1
RGP2
INLO OPLO
OPHI
BIT N
PWUP
MUX
OUTPUT
LOAD
N-BIT
DIGITAL
INTERFACE
03145-041
AD8351
R
L
1k
R
IP
R
IP
R
G
R
OP
R
OP
C
STRAY
C
STRAY
C
L
C
L
03145-042
Data Sheet AD8351
Rev. D | Page 15 of 19
Due to package parasitic capacitance on the RG ports, high RG
values (low gain) cause high ac-peaking inside the pass band,
resulting in poor settling in the time domain. As an example,
when driving a 1 kΩ load, using 25 Ω for RIP reduces the peaking
by ~7 dB for RG equal to 200 Ω (AV = 10 dB) (see Figure 44).
Figure 44. Reducing Gain Peaking with Parasitic Suppressing Resistors
(RIP = 25 Ω, RL = 1 kΩ)
It is important to ensure that all I/O, ground, and RG port traces
be kept as short as possible. In addition, the ground plane must
be removed from under the package. Due to the inverse relation-
ship between the gain of the device and the value of the RG resistor,
any parasitic capacitance on the RG ports can result in gain-peaking
at high frequencies. Following the precautions outlined in Figure 45
helps to reduce parasitic board capacitance, thus extending the
bandwidth of the device and reducing potential peaking or
oscillation.
Figure 45. General Description of Recommended Board Layout for
High-Z Load Conditions (10-Lead MSOP Package)
TRANSMISSION LINE EFFECTS
As noted, stray transmission line capacitance, in combination
with package parasitics, can potentially form a resonant circuit
at high frequencies, resulting in excessive gain peaking. RF
transmission lines connecting the input and output networks
must be designed to minimize stray capacitance. The output
single-ended source impedance of the AD8351 is dynamically
set to a nominal value of 75 Ω. Therefore, for a matched load
termination, design the characteristic impedance of the output
transmission lines to be 75 Ω. In many situations, the final load
impedance may be relatively high, greater than 1 kΩ. It is sug-
gested that the board be designed as shown in Figure 45 for high
impedance load conditions. In most practical board designs, this
requires that the printed circuit board traces be dimensioned to
a small width (~5 mils) and that the underlying and adjacent
ground planes are far enough away to minimize capacitance.
Typically the driving source impedance into the device is below
and terminating resistors are used to prevent input reflections.
The transmission line must be designed to have the appropriate
characteristic impedance in the low-Z region. The high impedance
environment between the terminating resistors and device input
pins must not have ground planes underneath or near the signal
traces. Small parasitic suppressing resistors may be necessary at
the device input pins to help desensitize (de-Q) the resonant
effects of the device bond wires and surrounding parasitic board
capacitance. Typically, 25 Ω series resistors (size 0402) adequately
de-Q the input system without a significant decrease in ac
performance.
Figure 46 illustrates the value of adding input and output series
resistors to help desensitize the resonant effects of board parasitics.
Overshoot and undershoot can be significantly reduced with
the simple addition of RIP and ROP.
Figure 46. Step Response Characteristics With and Without Input and Output
Parasitic Suppression Resistors
10 100 1k 10k
2log;
A
V
(dB)
FREQUENCY (MHz)
0
25
20
10
15
5
NO R
IP
R
IP
= 25
03145-043
2
1
3
4
5
9
10
8
7
6
R
IP
R
IP
R
T
R
T
R
G
R
OP
R
OP
HIGH-Z
AGND
AGND
COPLANAR
WAVEGUIDE
OR µSTRIP
03145-044
01234
VOLTAGE (V)
TIME (ns)
–1.5
1.5
1.0
0
0.5
–1.0
–0.5
NO R
IP
OR R
OP
R
IP
= R
OP
= 25
R
OP
= 25
03145-045
AD8351 Data Sheet
Rev. D | Page 16 of 19
CHARACTERIZATION SETUP
The test circuit used for 150 Ω and 1 kΩ load testing is shown
in Figure 47. The evaluation board uses balun transformers to
simplify interfacing to single-ended test equipment. Balun effects
must be removed from the measurements to accurately charac-
terize the performance of the device at frequencies exceeding
1 GHz.
The output L-pad matching networks provide a broadband
impedance match with minimum insertion loss. The input lines
are terminated with 50 Ω resistors for input impedance matching.
The power loss associated with these networks must be accounted
for when attempting to measure the gain of the device. The
required resistor values and the appropriate insertion loss and
correction factors used to assess the voltage gain are shown in
Table 5 .
Table 5. Load Conditions Specified Differentially
Load Condition R1 (Ω) R2 (Ω) Total Insertion Loss (dB) Conversion Factor 20 log (S21) to 20 log (AV)
150 Ω 43.2 86.6 5.8 7.6 dB
1 kΩ 475 52.3 15.9 25.9 dB
Figure 47. Test Circuit
0.1nF
0.1nF 100nF
100nF
R
LOAD
AD8351
DUT
R1
R1
R2
R2
50
50
50 TEST
EQUIPMENT
BALANCED
SOURCE
R
S
50
R
T
50
R
T
50
R
S
50
50 CABLE
50 CABLE
50 CABLE
50 CABLE
03145-046
Data Sheet AD8351
Rev. D | Page 17 of 19
EVALUATION BOARD
An evaluation board is available for experimentation. Various
parameters such as gain, common-mode level, and input and
output network configurations can be modified through minor
resistor changes. The schematic and evaluation board artwork
are presented in Figure 48, Figure 49, and Figure 50.
Figure 48. Component Side Layout
Figure 49. Component Side Silkscreen
Figure 50. Evaluation Board Schematic
03145-047
03145-048
0
3145-049
R2
24.9
R1
100
R5
0
R7
0
R18
0
R17
0
R8
0
R4
24.9
R3
OPEN
R12
0
J1
RF_IN+
J2
RF_IN–
C3
0.1µF
R6
OPEN
C2
100nF
AGND
VPOS
ENBL
VCOM
VPOS
ACOM
P1
W1
T1
C10
100nF
C4
100nF
C5
100nF
C9
100nF
T3
J5
TEST IN2 T4
1:1
ETC1-1-13
(MACOM)
1:1
ETC1-1-13
(MACOM)
1:1
ETC1-1-13
(MACOM)
J6
TEST OUT2
R13
OPEN
T2
J3
RF_OUT+
J4
RF_OUT–
C6
100nF
C7
100nF
1:1
ETC1-1-13
(MACOM)
R15
0
R16
0
R11
61.9
R9
61.9
R14
0
R10
61.9
16
PWUP
15
NC
14
NC
13
VOCM
5
NC
6
NC
7
NC
8
NC
RGP1
INHI
INLO
RGP2
1
2
3
4
VPOS
OPHI
OPLO
COMM
12
11
10
9
AD8351
AD8351 Data Sheet
Rev. D | Page 18 of 19
Table 6. Evaluation Board Configuration Options
Component Function Default Condition
P1-1, P1-2,
VPOS, AGND
Supply and Ground Pins. Not Applicable
P1-3 Common-Mode Offset Pin. Allows for monitoring or adjustment of the output
common-mode voltage.
Not Applicable
W1, R7, P1-4,
R17, R18
Device Enable. Configured such that switch W1 disables the device when Pin 1 is set to
ground. Device can be disabled remotely using Pin 4 of header P1.
W1 = Installed
R7 = 0 Ω (Size 0603)
R17 = R18 = 0 Ω (Size 0603)
R2, R3, R4, R5,
R8, R12, T1, C4,
C5
Input Interface. R3 and R12 are used to ground one side of the differential drive
interface for single-ended applications. T1 is a 1-to-1 impedance ratio balun used to
transform a single-ended input into a balanced differential signal. R2 and R4 are used
to provide a differential 50 Ω input termination. R5 and R8 can be increased to reduce
gain peaking when driving from a high source impedance. The 50 Ω termination
provides an insertion loss of 6 dB. C4 and C5 are used to provide ac coupling.
R2 = R4 = 24.9 Ω (Size 0805)
R3 = Open (Size 0603)
R5 = R8 = R12 = 0 Ω (Size 0603)
C4 = C5 = 10 0 nF (Size 0603)
T1 = Macom™ ETC1-1-13
R9, R10, R11,
R13, R14, R15,
R16, T2, C4, C5,
C6, C7
Output Interface. R13 and R14 are used to ground one side of the differential output
interface for single-ended applications. T2 is a 1-to-1 impedance ratio balun used to
transform a balanced differential signal into a single-ended signal. R9, R10, and R11 are
provided for generic placement of matching components. R15 and R16 allow additional
output series resistance when driving capacitive loads. The evaluation board is configured
to provide a 150 Ω to 50 Ω impedance transformation with an insertion loss of 9.9 dB.
C4 through C7 are used to provide ac coupling.
R9 = R10 = 61.9 Ω (Size 0603)
R11 = 61.9 Ω (Size 0603)
R13 = Open (Size 0603)
R14 = 0 Ω (Size 0603)
R15 = R16 = 0 Ω (Size 0402)
C4 = C5 = 100 nF (Size 0603)
C6 = C7 = 100 nF (Size 0603)
T2 = Macom ETC1-1-13
R1 Gain Setting Resistor. Resistor R1 is used to set the gain of the device. Refer to Figure 5
when selecting gain resistor. When R1 is 100 Ω, the overall system gain of the
evaluation board is approximately −6 dB.
R1 = 100 Ω (Size 0603)
C2 Power Supply Decoupling. The supply decoupling consists of a 100 nF capacitor to ground. C2 = 100 nF (Size 0805)
R6, C3, P1-3 Common-Mode Offset Adjustment. Used to trim common-mode output level. By
applying a voltage to Pin 3 of header P1, the output common-mode voltage can be
directly adjusted. Typically decoupled to ground using a 0.1 μF capacitor.
R6 = 0 Ω (Size 0603)
C3 = 0.1 μF (Size 0805)
T3, T4, C9, C10 Calibration Networks. Calibration path provided to allow for compensation of the
insertion loss of the baluns and the reactance of the coupling capacitors.
T3 = T4 = Macom ETC1-1-13
C9 = C10 = 100 nF (Size 0603)
Data Sheet AD8351
Rev. D | Page 19 of 19
OUTLINE DIMENSIONS
Figure 51. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Figure 52. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-35)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
AD8351ARM −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 JDA
AD8351ARM-REEL7 −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 JDA
AD8351ARMZ −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 #JDA
AD8351ARMZ-REEL7 −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 #JDA
AD8351ACPZ-R7 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-35 Q20
AD8351-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
3.10
3.00 SQ
2.90
0.32
0.25
0.20
1.80
1.70 SQ
1.60
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
EXPOSED
PAD
PIN 1
INDICATOR
(0.30)
0.50
0.40
0.30
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.80
0.75
0.70
COMPLIANT
TO
JEDEC STANDARDS MO-220-WEED-2.
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
10-09-2013-A
PKG-004326
©2003–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03145-0-1/15(D)
