Ultralow Distortion IF VGA
Data Sheet
AD8375
Rev. A
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FEATURES
Bandwidth of 630 MHz (−3 dB)
Gain range: −4 dB to +20 dB
Step size: 1 dB ± 0.2 dB
Differential input and output
Noise figure: 8 dB @ maximum gain
Output IP3 of ~50 dBm at 200 MHz
Output P1dB of 19 dBm at 200 MHz
Provides constant SFDR vs. gain
Parallel 5-bit control interface
Power-down feature
Single 5 V supply operation
24-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
Differential ADC drivers
High IF sampling receivers
Wideband multichannel receivers
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
A2A3A4 A1 A0
POST-AMP
α
REGISTERS
AND
GAIN DECO DE R
VPOS COMM
AD8375
VCOM
VIN+
VIN–
PWUP
OUT+
OUT+
OUT–
OUT–
06724-001
Figure 1.
GENERAL DESCRIPTION
The AD8375 is a digitally controlled, variable gain, wide
bandwidth amplifier that provides precise gain control, high
IP3, and low noise figure. The excellent distortion performance
and high signal bandwidth make the AD8375 an excellent gain
control device for a variety of receiver applications.
Using an advanced high speed SiGe process and incorporating
proprietary distortion cancellation techniques, the AD8375
achieves 50 dBm output IP3 at 200 MHz.
The AD8375 provides a broad 24 dB gain range with 1 dB
resolution. The gain is adjusted through a 5-pin control interface
and can be driven using standard TTL levels. The open-collector
outputs provide a flexible interface, allowing the overall signal
gain to be set by the loading impedance. Thus, the signal
voltage gain is directly proportional to the load.
The AD8375 is powered on by applying the appropriate logic
level to the PWUP pin. The quiescent current of the AD8375 is
typically 130 mA. When powered down, the AD8375 consumes
less than 5 mA and offers excellent input-to-output isolation.
Fabricated on an Analog Devices, Inc., high speed SiGe process,
the AD8375 is supplied in a compact, thermally enhanced,
4 mm × 4 mm, 24-lead LFCSP package and operates over the
temperature range of −40°C to +85°C.
–40
–60
–50
–70
–90
–80
–100
–110
65
55
60
50
40
45
35
30
HARMONIC DISTORTION (dBc), OUTPUT @ 2V p-p
OIP3 (dBm), OUTPUT @ 3dBm/TONE
40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
06724-052
OIP3
HD2
HD3
Figure 2. Harmonic Distortion and Output IP3 vs. Frequency
AD8375 Data Sheet
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Circuit Description ......................................................................... 12
Basic Structure ............................................................................ 12
Applications ..................................................................................... 13
Basic Connections ...................................................................... 13
Single-Ended-to-Differential Conversion............................... 13
Broadband Operation ................................................................ 14
ADC Interfacing ......................................................................... 14
Layout Considerations ............................................................... 17
Characterization Test Circuits .................................................. 17
Evaluation Board ........................................................................ 18
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
10/12—Rev. 0 to Rev. A
Change to Maximum Junction Temperature Parameter,
Table 3 ................................................................................................ 5
Added Exposed Pad Notation, Figure 3 and Exposed Pad
Notation, Table 4 ............................................................................... 6
Added Exposed Pad Notation to Outline Dimensions ............. 22
8/07—Revision 0: Initial Version
Data Sheet AD8375
Rev. A | Page 3 of 24
SPECIFICATIONS
VS = 5 V, T = 25°C, RS = RL = 150 Ω at 140 MHz, 2 V p-p differential output, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VOUT < 2 V p-p (5.2 dBm) 630 MHz
Slew Rate 5 V/ns
INPUT STAGE
Pin VIN+ and Pin VIN−
Maximum Input Swing For linear operation (AV = −4 dB) 8.5 V p-p
Differential Input Resistance Differential 125 150 165 Ω
Common-Mode Input Voltage 1.9 V
CMRR Gain code = 00000 55 dB
GAIN
Amplifier Transconductance Gain code = 00000 0.060 0.067 0.074 S
Maximum Voltage Gain Gain code = 00000 20 dB
Minimum Voltage Gain
Gain code ≥ 11000
−4
dB
Gain Step Size From gain code = 00000 to 11000 0.89 0.98 1.01 dB
Gain Flatness All gain codes, 20% fractional bandwidth for fC < 200 MHz 0.12 dB
Gain Temperature Sensitivity Gain code = 00000 8 mdB/°C
Gain Step Response For VIN = 100 mV p-p, gain code = 10100 to 00000 5 ns
OUTPUT STAGE Pin VOUT+ and Pin VOUT−
Output Voltage Swing At P1dB, gain code = 00000 12.6 V p-p
Output Impedance Differential 16||0.8 kΩ||pF
NOISE/HARMONIC PERFORMANCE
46 MHz Gain code = 00000
Noise Figure 8.3 dB
Second Harmonic
V
OUT
= 2 V p-p
−92
dBc
Third Harmonic VOUT = 2 V p-p −94 dBc
Output IP3 2 MHz spacing, +3 dBm per tone 50 dBm
Output 1 dB Compression Point 22 dBm
70 MHz Gain code = 00000
Noise Figure 8.3 dB
Second Harmonic VOUT = 2 V p-p −98 dBc
Third Harmonic VOUT = 2 V p-p −95 dBc
Output IP3 2 MHz spacing, 3 dBm per tone 51 dBm
Output 1 dB Compression Point 22 dBm
140 MHz Gain code = 00000
Noise Figure
8.3
dB
Second Harmonic VOUT = 2 V p-p −90 dBc
Third Harmonic VOUT = 2 V p-p −100 dBc
Output IP3 2 MHz spacing, 3 dBm per tone 51 dBm
Output 1 dB Compression Point 20 dBm
200 MHz Gain code = 00000
Noise Figure 8.3 dB
Second Harmonic VOUT = 2 V p-p −85 dBc
Third Harmonic VOUT = 2 V p-p −92 dBc
Output IP3 2 MHz spacing, 3 dBm per tone 50 dBm
Output 1 dB Compression Point 19 dBm
AD8375 Data Sheet
Rev. A | Page 4 of 24
Parameter
Conditions
Min
Typ
Max
Unit
POWER INTERFACE
Supply Voltage 4.5 5.0 5.5 V
VPOS and Output Quiescent Current Thermal connection made to exposed paddle under device 120 125 130 mA
vs. Temperature −40°C ≤ TA ≤ +85°C 150 mA
Power-Down Current PWUP low 2.5 mA
vs. Temperature −40°C ≤TA ≤ +85°C 3 mA
POWER-UP/GAIN CONTROL Pin A0 to Pin A4, Pin PWUP
VIH Minimum voltage for a logic high 1.6 V
VIL Maximum voltage for a logic low 0.8 V
Logic Input Bias Current 900 nA
Table 2. Gain Code vs. Voltage Gain Look-Up Table
5-Bit Binary Gain Code Voltage Gain (dB)
00000 +20
00001 +19
00010 +18
00011 +17
00100 +16
00101
+15
00110 +14
00111 +13
01000 +12
01001 +11
01010 +10
01011 +9
01100 +8
5-Bit Binary Gain Code Voltage Gain (dB)
01101 +7
01110 +6
01111 +5
10000 +4
10001 +3
10010
+2
10011 +1
10100 0
10101 −1
10110 −2
10111 −3
11000 −4
>11000 −4
Data Sheet AD8375
Rev. A | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage, VPOS 5.5 V
PWUP, A0 to A4
−0.6 V to (V
POS
+ 0.6 V)
Input Voltage, VIN+, VIN− −0.15 V to +4.15 V
DC Common Mode VCOM ± 0.25 V
VCOM ±6 mA
Internal Power Dissipation 825 mW
θ
JA
(Exposed Paddle Soldered Down)
63.6°C/W
θJC (At Exposed Paddle) 14.6°C/W
Maximum Junction Temperature 140°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD8375 Data Sheet
Rev. A | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1VCOM 2VIN+ 3VIN– 4A4 5A3 6A2
15 VOUT+
16 VOUT–
17 VOUT+
18 VOUT–
14 COMM
13 VPOS
7
A1 8
A0 9
VPOS
11
COMM 12
VPOS
10
VPOS 21 COMM
22 COMM
23 VPOS
24 COMM
20 COMM
19 PWUP
06724-002
AD8375
TOP VIEW
(Not to Scale)
NOTES
1. THE E XPO SE D P AD IS I NTERNALL Y CONNECTED TO GRO UND.
SOLDER TO A LO W IMPE DANCE GROUND PLANE.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VCOM Common-Mode Pin. Typically bypassed to ground using external capacitor.
2 VIN+ Voltage Input Positive.
3 VIN− Voltage Input Negative.
4 A4 MSB for the 5-Bit Gain Control Interface.
5 A3 MSB − 1 for the Gain Control Interface.
6 A2 MSB − 2 for the Gain Control Interface.
7 A1 LSB + 1 for the Gain Control Interface.
8 A0 LSB for the 5-Bit Gain Control Interface.
9, 10, 12, 13, 23 VPOS Positive Supply Pins. Should be bypassed to ground using suitable bypass capacitor.
11, 14, 20, 21, 22, 24 COMM Device Common (DC Ground).
15, 17 VOUT+ Positive Output Pins (Open Collector). Require dc bias of +5 V nominal.
16, 18 VOUT− Negative Output Pins (Open Collector). Require dc bias of +5 V nominal.
19 PWUP Chip Enable Pin. Enabled with a logic high and disabled with a logic low.
EPAD
Exposed Pad. The Exposed Pad is internally connected to ground. Solder to a low impedance
ground plane.
Data Sheet AD8375
Rev. A | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, RS = RL = 150 Ω, 2 V p-p output, maximum gain unless otherwise noted.
25
20
10
15
5
0
–10
–5
GAIN (d B)
–4
11000 0
10100 5
01111 10
01010 15
00101 20
00000
GAIN CODE
06724-003
46MHz
70MHz
140MHz
200MHz
Figure 4. Gain vs. Gain Code at 46 MHz, 70 MHz, 140 MHz, and 200 MHz
25
20
15
10
5
0
–5
–10
GAIN (d B)
10 100 1000
FREQUENCY (MHz)
06724-004
20dB
19dB
18dB
17dB
16dB
15dB
14dB
13dB
12dB
11dB
10dB
9dB
8dB
7dB
6dB
5dB
4dB
3dB
2dB
1dB
0dB
–1dB
–2dB
–3dB
–4dB
Figure 5. Gain vs. Frequency Response
10
8
6
4
2
0
–2
–4
–6
–8
–10
GAIN ERRO R ( dB)
–4
11000 0
10100 5
01111 10
01010 15
00101 20
00000
GAIN CODE
06724-005
25°C
85°C
–40°C
Figure 6. Gain Error over Temperature at 140 MHz
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
GAIN ERRO R ( dB)
–4
11000 0
10100 5
01111 10
01010 15
00101 20
10100
GAIN CODE
06724-006
Figure 7. Gain Step Error, Frequency 140 MHz
25
20
15
10
5
0
OP 1dB (d Bm)
–4 1 6 11 16 21
GAIN (d B)
06724-007
200MHz
140MHz
70MHz
46MHz
INP UT MAX
RATING
BOUNDARY
Figure 8. P1dB vs. Gain at 46 MHz, 70 MHz, 140 MHz, and 200 MHz
25
20
15
10
5
0
OP 1dB (d Bm)
46 100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
06724-008
+25°C
+85°C
–40°C
Figure 9. P1dB vs. Frequency at Maximum Gain, Three Temperatures
AD8375 Data Sheet
Rev. A | Page 8 of 24
52
51
50
49
48
47
46
45
44
43
42
41
4030 50 70 90 110 130 150 170 190 210
FREQUENCY (MHz)
OI P 3 ( dBm)
A
V
= 0dB
A
V
= –4dB
A
V
= +10d B
A
V
= +20d B
06724-009
Figure 10. Output Third-Order Intercept at Four Gains,
Output Level at 3 dBm/Tone
52
51
50
49
48
47
46
45
44
43
42
41
40–4 –3 –2 –1 01 2 3 4 5 6
P
OUT
(d Bm)
OIP3 (dBm)
06274-010
A
V
= 0dB
A
V
= –4dB
A
V
= +10d B
A
V
= +20d B
Figure 11. Output Third-Order Intercept vs. Power
at Four Gains, Frequency 140 MHz
+25°C
+85°C
–40°C
70
60
65
55
45
50
40
30
35
OIP3 (dBm)
40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
06724-011
Figure 12. Output Third-Order Intercept vs. Frequency,
Three Temperatures, Output Level at 3 dBm/Tone
25
30
35
40
45
50
55
–3 –2 –1 0 1 2 3 4 5 35
40
45
50
55
60
65
OIP3 (dBm)
06724-012
P
OUT
PER TONE ( dBm)
OIP3 (dBm)
A
V
= 20dB
A
V
= 0dB
+25°C 20dB
–40°C 20d B
+85°C 20dB
+25°C 0dB
–40°C 0d B
+85°C 0dB
Figure 13. Output Third-Order Intercept vs. Power,
Frequency 140 MHz, Three Temperatures
–70
–80
–75
–85
–95
–90
–100
–110
–105
IM D3 ( dBc)
–4 1611 16
GAIN (d B)
06724-013
46MHz
70MHz
140MHz
200MHz
Figure 14. Two-Tone Output IMD vs. Gain
at 46 MHz, 70 MHz, 140 MHz, and 200 MHz, Output Level at 3 dBm/Tone
+25°C
+85°C
–40°C
–70
–80
–75
–85
–95
–90
–100
–110
–105
IM D3 ( dBc)
40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
06724-014
Figure 15. Two-Tone Output IMD vs. Frequency,
Three Temperatures, Output Level at 3 dBm/Tone
Data Sheet AD8375
Rev. A | Page 9 of 24
–75
–80
–85
–90
–95
–100
–105
–110
–115
–65
–70
–75
–80
–85
–90
–95
–100
–105
HARMO NIC DIS TO RTI ON HD2 (dBc)
HARMO NIC DIS TO RTI ON HD3 (dBc)
40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
06724-015
HD2 –4dB
HD2 0dB
HD2 +10dB
HD2 +20dB
HD3 –4dB
HD3 0dB
HD3 +10dB
HD3 +20dB
Figure 16. Harmonic Distortion vs. Frequency at Four Gain Codes,
VOUT = 2 V p-p
–80
–75
–85
–90
–95
–100
–105
–110
–115
–120
–125
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
HARMO NIC DIS TO RTI ON HD2 (dBc)
HARMO NIC DIS TO RTI ON HD3 (dBc)
–5 –4 –3 –2 –1 0 1 2 3 4 5
P
OUT
(d Bm)
06724-016
HD2 +20dB
HD2 +10dB
HD2 0dB
HD2 –4dB
HD3 +20dB
HD3 +10dB
HD3 0dB
HD3 –4dB
Figure 17. Harmonic Distortion vs. Power at Four Gain Codes,
Frequency 140 MHz
–80
–85
–90
–95
–100
–105
HARMO NIC DIS TO RTI ON HD2 AND HD3 (dBc)
40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
HD2 +25° C
HD3 +25° C
HD2 –40°C
HD3 –40°C
HD2 +85° C
HD3 +85° C
06274-017
Figure 18. Harmonic Distortion vs. Frequency, Three Temperatures,
VOUT = 2 V p-p
–125
–120
–115
–110
–105
–100
–95
–90
–85
–5 –4 –3 –2 –1 0 1 2 3 4 5–110
–105
–100
–95
–90
–85
–80
–75
–70
HARMO NIC DIS TO RTI ON HD3 (dBc)
06724-018
P
OUT
(d Bm)
HARMO NIC DIS TO RTI ON HD2 (dBc)
HD3 +25°C
HD3 +85°C
HD3 –40°C
HD2 –40°C
HD2 +25°C
HD2 +85°C
Figure 19. Harmonic Distortion vs. Power, Frequency 140 MHz,
Three Temperatures
35
30
25
20
15
10
5
0
NOISE FIGURE (dB)
–4 –2 0 2 4 6 8 10 12 14 16 18 20
GAI N ( dB)
06724-019
46MHz
70MHz
140MHz
200MHz
Figure 20. NF vs. Gain at 46 MHz, 70 MHz, 140 MHz, and 200 MHz
45
40
35
30
25
20
15
10
5
00100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
NOISE FIGURE (dB)
06724-020
A
V
= 0dB
A
V
= –4dB
A
V
= +10d B
A
V
= +20d B
Figure 21. NF vs. Frequency
AD8375 Data Sheet
Rev. A | Page 10 of 24
06724-021
CH1 500mV Ω CH2 500mV Ω M10.0ns 10. 0GS/s I T 10.0ps/ pt
A CH1 960mV
1
2
Figure 22. Gain Step Time Domain Response
06724-022
CH1 500mV Ω CH2 500mV Ω M20.0ns 10. 0GS/s I T 20.0ps/ pt
A CH1 960mV
1
2
Figure 23. ENBL Time Domain Response
R4
06724-023
M2.5ns 20. 0GS/s I T 10.0ps/ pt
A CH4 28.0mV
R3
R1
REF1 POSITION
–420mV/DIV
REF1 S CALE
2V
0pF
10pF E ACH S IDE
INPUT
REF1 2.0V 2.5n s
Figure 24. Pulse Response to Capacitive Loading, Gain −4 dB
06724-024
M2.5ns 20. 0GS/s I T 10.0ps/ pt
A CH4 28.0mV
R3
REF3 POSITION
–600mV/DIV
REF3 S CALE
500mV
0pF
INPUT
R1
10pF E ACH S IDE
REF3 500mV 2.5n s
Figure 25. Pulse Response to Capacitive Loading, Gain 20 dB
06724-025
INPUT
OUTPUT
REF1 50.0mV
REF1
CH2 500mV M2. 5ns 20Gsps
IT 2.5ps/pt A CH2 –610mV
2
REF1 POSITION
–1.02/DIV
REF 1 S CALE
50mV
RIS E ( C2) 1.384ns
FALL ( C2) 1.39ns
Figure 26. Large Signal Pulse Response
0
–5
–10
–15
–20
–25
–30
180
120
60
0
–60
–120
–180
10 100 1000
FREQUENCY (MHz)
S11 MAG (d B)
S11 PHAS E ( Degrees)
06724-026
Figure 27. S11 vs. Frequency
Data Sheet AD8375
Rev. A | Page 11 of 24
0
–20
–40
–60
–80
–100
–1200100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
S12 (dB)
06724-027
Figure 28. Reverse Isolation vs. Frequency
0
–20
–40
–60
–80
–100
–1200100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
ISOLATION (dB)
06724-028
Figure 29. Off-State Isolation vs. Frequency
1.00E–09
9.00E–10
8.00E–10
7.00E–10
6.00E–10
5.00E–10
4.00E–10
3.00E–10
2.00E–10
1.00E–10
0.00E+00
DEL AY ( S econds)
0100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
06724-029
+20dB
+10dB
0dB
–4dB
Figure 30. Group Delay vs. Frequency at Gain
80
70
60
50
40
30
20
10
00100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
CMRR (dB)
06724-031
Figure 31. Common-Mode Rejection Ratio vs. Frequency
AD8375 Data Sheet
Rev. A | Page 12 of 24
CIRCUIT DESCRIPTION
BASIC STRUCTURE
The AD8375 is a differential variable gain amplifier consisting
of a 150 Ω digitally controlled passive attenuator followed by a
highly linear transconductance amplifier.
06724-032
gm CO RE
AMP
MUX BUF FERS
AD8375
A0 TO A4
DIGITAL
SELECT
ATTENUATOR
VIN+
VCOM
VIN–
VOUT+
VOUT–
Figure 32. Simplified Schematic
Input System
The dc voltage level at the inputs of the AD8375 is set by an
internal voltage reference circuit to about 2 V. This reference is
accessible at VCOM and can be used to source or sink 100 μA.
For cases where a common-mode signal is applied to the inputs,
such as in a single-ended application, an external capacitor
between VCOM and ground is required. The capacitor improves
the linearity performance of the part in this mode. This capacitor
should be sized to provide a reactance of 10 Ω or less at the
lowest frequency of operation. If the applied common-mode
signal is dc, its amplitude should be limited to 0.25 V from
VCOM (VCOM ± 0.25 V).
The device can be powered down by pulling the PWUP pin
down to below 0.8 V. In the powered down mode, the total
current reduces to 3 mA (typical). The dc level at the inputs and
at VCOM remains at about 2 V, regardless of the state of the
PWUP pin.
Output Amplifier
The gain is based on a 150 Ω differential load and varies as RL is
changed per the following equations:
Voltage Gain = 20 × (log(RL/150) + 1)
and
Power Gain = 10 × (log(RL/150) + 2)
The dependency of the gain on the load is due to the open-
collector architecture of the output stage.
The dc current to the outputs of the amplifier is supplied
through two external chokes. The inductance of the chokes and
the resistance of the load determine the low frequency pole of
the amplifier. The parasitic capacitance of the chokes adds to
the output capacitance of the part. This total capacitance in
parallel with the load resistance sets the high frequency pole of
the device. Generally, the larger the inductance of the choke, the
higher its parasitic capacitance. Therefore, the value and type of
the choke should be chosen keeping this trade-off in mind.
For operation frequency of 15 MHz to 700 MHz driving a
150 Ω load, 1 μH chokes with SRF of 160 MHz or higher are
recommended (such as 0805LS-102XJBB from Coilcraft).
The supply current consists of about 50 mA through the VCC
pin and 80 mA through the two chokes combined. The latter
increases with temperature at about 2.5 mA per 10°C.
There are two output pins for each polarity and they are
oriented in an alternating fashion. When designing the board,
care should be taken to minimize the parasitic capacitance due
to the routing that connects the corresponding outputs together.
A good practice is to avoid any ground or power plane under
this routing region and under the chokes to minimize the
parasitic capacitance.
Gain Control
A 5-bit binary code changes the attenuator setting in 1 dB steps
such that the gain of the device changes from 20 dB (Code 0) to
−4 dB (Code 24 and higher).
The noise figure of the device is about 8 dB at maximum gain
setting and it increases as the gain is reduced. The increase in
noise figure is equal to the reduction in gain. The linearity of
the part measured at the output is first-order independent of
the gain setting. From 0 dB to 20 dB gain, OIP3 is approximately
50 dBm into 150 Ω load at 140 MHz (3 dBm per tone). At gain
settings below 0 dB, it drops to approximately 45 dBm.
Data Sheet AD8375
Rev. A | Page 13 of 24
APPLICATIONS
BASIC CONNECTIONS
Figure 35 shows the basic connections for operating the
AD8375. A voltage between 4.5 V and 5.5 V should be applied
to the supply pins. Each supply pin should be decoupled with at
least one low inductance, surface-mount ceramic capacitor of
0.1 μF placed as close as possible to the device.
The outputs of the AD8375 are open collectors that need to be
pulled up to the positive supply with 1 µH RF chokes. The
differential outputs are biased to the positive supply and require
ac coupling capacitors, preferably 0.1 µF. Similarly, the input
pins are at bias voltages of about 2 V above ground and should
be ac-coupled as well. The ac coupling capacitors and the RF
chokes are the principle limitations for operation at low
frequencies.
To enable the AD8375, the PWUP pin must be pulled high.
Taking PWUP low puts the AD8375 in sleep mode, reducing
current consumption to 5 mA at ambient.
SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION
The AD8375 can be configured as a single-ended input to
differential output driver as shown in Figure 33. A 150 Ω
resistor in parallel with the input impedance of input pin
provides an impedance matching of 50 Ω. The voltage gain and
the bandwidth of this configuration, using a 150 Ω load,
remains the same as when using a differential input.
5
0.1µF
0.1µF
0.1µF
0.1µF
37.5Ω
150Ω
AD8375
1µH
150Ω
A0 TO A4
1µH
+5V
06724-035
VCM
0.1µF
50Ω
AC
Figure 33. Single-Ended-to-Differential Conversion
Using a single-ended input decreases the power gain by 3 dB
and limits distortion cancellation. Consequently, the second-
order distortion is degraded. The third-order distortion remains
low to 200 MHz, as shown in Figure 34.
06724-036
–60
–65
–70
–75
–80
–85
–90
–95
–100
HARMO NIC DIS TO RTI ON (dBc)
0200
15010050 FREQUENCY (MHz)
HD2
HD3
Figure 34. Harmonic Distortion vs. Frequency of
Single-Ended-to-Differential Conversion
PARALLEL CONTROL INTE RFACE
0.1µF
0.1µF
0.1µF
R
S
2
R
S
2
AC
BALANCED
SOURCE
0.1µF 0.1µF +V
S
R
L
BALANCED
LOAD
1µH
1µH
0.1µF
0.1µF
0.1µF
10µF
+V
S
06724-034
COMM VPOS COMM COMM COMM PWUP
1924 23 22 21 20
A1 A0 VPOS VPOS COMM VPOS
127 8 9 10 11
18
17
16
15
14
13
1
2
3
4
5
6
VCOM
VIN+
VIN–
A4
A3
A2
VOUT–
VOUT+
VOUT–
VOUT+
COMM
VPOS
AD8375
Figure 35. Basic Connections
AD8375 Data Sheet
Rev. A | Page 14 of 24
BROADBAND OPERATION
The AD8375 uses an open-collector output structure that
requires dc bias through an external bias network. Typically,
choke inductors are used to provide bias to the open-collector
outputs. Choke inductors work well at signal frequencies where
the impedance of the choke is substantially larger than the target
ac load impedance. In broadband applications, it may not be
possible to find large enough choke inductors that offer enough
reactance at the lowest frequency of interest while offering a
high enough self resonant frequency (SRF) to support the
maximum bandwidth available from the device. The circuit in
Figure 36 can be used when frequency response below 10 MHz
is desired. This circuit replaces the bias chokes with bias resistors.
The bias resistor has the disadvantage of a greater IR drop, and
requires a supply rail that is several volts above the local 5 V
supply used to power the device. Additionally, it is necessary
to account for the ac loading effect of the bias resistors when
designing the output interface. Whereas the gain of the AD8375
is load dependent, RL, in parallel with R1 + R2, should equal the
optimum 150 Ω target load impedance to provide the expected
ac performance depicted in the data sheet. Additionally, to
ensure good output balance and even-order distortion
performance, it is essential that R1 = R2.
5
0.1µF
0.1µF
0.1µF
0.1µF
50Ω
ETC1-1-13
37.5Ω
37.5Ω 5V
AD8375
SET TO
5V
R1
R2
VR
VR
RL
A0 TO A4
06724-037
Figure 36. Single-Ended Broadband Operation with Resistive Pull-Ups
Using the formula for R1 (Equation 1), the values of R1 = R2
that provide a total presented load impedance of 150 Ω can be
found. The required voltage applied to the bias resistors, VR,
can be found by using the VR formula (Equation 2).
150
75
−
×
=
L
L
R
R
R1
(1)
and
5
1040
3
+×
×=
−
R1
VR
(2)
For example, in the extreme case where the load is assumed to
be high impedance, RL = ∞, the equation for R1 reduces to R1 =
75 Ω. Using the equation for VR, the applied voltage should be
VR = 8 V. The measured single-tone low frequency harmonic
distortion for a 2 V p-p output using 75 Ω resistive pull-ups is
provided in Figure 37.
–80
–82
–84
–86
–88
–90
–92
–94
–96
HARMONIC DI S TO RTI ON (d Bc)
0 5 10 15 20
FREQUENCY (MHz)
HD2
HD3
06724-038
Figure 37. Harmonic Distortion vs. Frequency Using Resistive Pull-Ups
ADC INTERFACING
The AD8375 is a high output linearity variable gain amplifier
that is optimized for ADC interfacing. The output IP3 and noise
floor essentially remain constant vs. the 24 dB available gain
range. This is a valuable feature in a variable gain receiver where
it is desirable to maintain a constant instantaneous dynamic
range as the receiver gain is modified. The output noise density
is typically around 20 nV/√Hz, which is comparable to 14-/16-
bit sensitivity limits. The two-tone IP3 performance of the
AD8375 is typically around 50 dBm. This results in SFDR levels
of better than 86 dB when driving the AD9445 up to 140 MHz.
There are several options available to the designer when using
the AD8375. The open-collector output provides the capability
of driving a variety of loads. Figure 38 shows a simplified
wideband interface with the AD8375 driving a AD9445. The
AD9445 is a 14-bit 125 MSPS analog-to-digital converter with a
buffered wideband input, which presents a 2 kΩ differential
load impedance and requires a 2 V p-p differential input swing
to reach full scale.
0.1µF
0.1µF
50Ω
ETC1-1-13
37.5Ω
37.5Ω
0.1µF
0.1µF
0.1µF
0.1µF
82Ω
82Ω
1µH
5V
1µH
5V
33Ω
33Ω
14
AD9445
14-BIT ADC
AD8375
5
A0 TO A4
06724-039
L
(SERIES)
L
(SERIES)
VIN+
VIN–
Figure 38. Wideband ADC Interfacing Example Featuring the AD9445
Data Sheet AD8375
Rev. A | Page 15 of 24
For optimum performance, the AD8375 should be driven
differentially using an input balun or impedance transformer.
Figure 38 uses a wideband 1:1 transmission line balun followed
by two 37.5 Ω resistors in parallel with the 150 Ω input imped-
ance of the AD8375 to provide a 50 Ω differential terminated
input impedance. This provides a wideband match to a 50 Ω
source. The open-collector outputs of the AD8375 are biased
through the two 1 μH inductors and are ac-coupled to the two
82 Ω load resistors. The 82 Ω load resistors in parallel with the
series-terminated ADC impedance yields the target 150 Ω
differential load impedance, which is recommended to provide
the specified gain accuracy of the device. The load resistors are
ac-coupled from the AD9445 to avoid common-mode dc
loading. The 33 Ω series resistors help to improve the isolation
between the AD8375 and any switching currents present at the
analog-to-digital sample and hold input circuitry.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
(dBFS)
0 5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50
FRE Q UE NCY ( MHz)
06724-040
SNR = 64. 93dBc
SFDR = 86. 37dBc
NOI S E F LO O R = –108.1dB
FUND = –1. 053d BFs
SECO ND = –86. 18d Bc
THI RD = –86. 22dBc
1
23
456
+
Figure 39. Measured Single-Tone Performance of the
Circuit in Figure 38 for a 100 MHz Input Signal
The circuit depicted in Figure 38 provides variable gain,
isolation and source matching for the AD9445. Using this
circuit with the AD8375 in a gain of 20 dB (maximum gain) an
SFDR performance of 86 dBc is achieved at 100 MHz, as
indicated in Figure 39.
The addition of the series inductors L (series) in Figure 38
extends the bandwidth of the system and provides response
flatness. Using 100 nH inductors as L (series), the wideband
system response of Figure 40 is obtained. The wideband
frequency response is an advantage in broadband applications
such as predistortion receiver designs and instrumentation
applications. However, by designing for a wide analog input
frequency range, the cascaded SNR performance is somewhat
degraded due to high frequency noise aliasing into the wanted
Nyquist zone.
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
(dBFs)
20 48 76 104 132 160 188 216 244 272 300
FRE Q UE NCY ( MHz)
FIRST POINT = –2.93dBFs
END PO INT = –9. 66dBF s
MID POINT = –2.33dBFs
MIN = –9.66dBFs
MAX = –1.91dBFs
06724-041
Figure 40. Measured Frequency Response of Wideband ADC Interface
Depicted in Figure 38
An alternative narrow-band approach is presented in Figure 41.
By designing a narrow band-pass antialiasing filter between the
AD8375 and the target ADC, the output noise of the AD8375
outside of the intended Nyquist zone can be attenuated, helping
to preserve the available SNR of the ADC. In general, the SNR
improves several dB when including a reasonable order antialias-
ing filter. In this example, a low loss 1:3 input transformer is used
to match the AD8375’s 150 Ω balanced input to a 50 Ω unbal-
anced source, resulting in minimum insertion loss at the input.
AD8375 Data Sheet
Rev. A | Page 16 of 24
Figure 41 is optimized for driving some of Analog Devices
popular unbuffered ADCs, such as the AD9246, AD9640,
and AD6655. Table 5 includes antialiasing filter component
recommendations for popular IF sampling center frequencies.
Inductor L5 works in parallel with the on-chip ADC input
capacitance and a portion of the capacitance presented by C4 to
form a resonant tank circuit. The resonant tank helps to ensure
the ADC input looks like a real resistance at the target center
frequency. Additionally, the L5 inductor shorts the ADC inputs
at dc, which introduces a zero into the transfer function. In
addition, the ac coupling capacitors and the bias chokes
introduce additional zeros into the transfer function. The final
overall frequency response takes on a band-pass characteristic,
helping to reject noise outside of the intended Nyquist zone.
Table 5 provides initial suggestions for prototyping purposes.
Some empirical optimization may be needed to help compensate
for actual PCB parasitics.
5
1nF
1nF
1nF
1nF
50Ω
1:3
AD8375
301Ω C2
A0 TO A4
06724-042
C4
1µH
1µH
L1
L1
L3
L3
CML 165Ω
165Ω
L5
AD9246
AD9640
AD6655
Figure 41. Narrow-Band IF Sampling Solution for Unbuffered ADC Application
Table 5. Interface Filter Recommendations for Various IF Sampling Frequencies
Center Frequency 1 dB Bandwidth L1 C2 L3 C4 L5
96 MHz 27 MHz 390 nH 5.6 pF 390 nH 25 pF 100 nH
140 MHz 30 MHz 330 nH 3.3 pF 330 nH 20 pF 56 nH
170 MHz 32 MHz 270 nH 2.7 pF 270 nH 20 pF 39 nH
211 MHz 32 MHz 220 nH 2.2 pF 220 nH 18 pF 27 nH
Data Sheet AD8375
Rev. A | Page 17 of 24
LAYOUT CONSIDERATIONS
There are two output pins for each polarity, and they are
oriented in an alternating fashion. When designing the board,
care should be taken to minimize the parasitic capacitance due
to the routing that connects the corresponding outputs together.
A good practice is to avoid any ground or power plane under
this routing region and under the chokes to minimize the
parasitic capacitance.
CHARACTERIZATION TEST CIRCUITS
Differential-to-Differential Characterization
The S-parameter characterization for the AD8375 was
performed using a dedicated differential input to differential
output characterization board. Figure 44 shows the layout of
characterization board. The board was designed for optimum
impedance matching into a 75 Ω system. Because both the
input and output impedances of the AD8375 are 150 Ω
differentially, 75 Ω impedance runs were used to match 75 Ω
network analyzer port impedances. On-board 1 μH inductors
were used for output biasing, and the output board traces were
designed for minimum capacitance.
0.1µF
0.1µF
06724-046
L1
1µH L2
1µH
0.1µF
0.1µF
+5V
5
A0 TO A4
AC 75Ω TRACES75Ω TRACES
75Ω
75Ω
75Ω
75Ω
AC
AD8375
Figure 42. Test Circuit for S-Parameters on Dedicated 75 Ω
Differential-to-Differential Board
0.1µF
0.1µF
TC3-1T
06724-047
T1
0.1µF
0.1µF
330Ω
330Ω
25Ω
25Ω
50Ω
+9V
5
A0 TO A4
50Ω
96Ω 96Ω
AC
AD8375
Figure 43. Test Circuit for Time Domain Measurements
06724-044
Figure 44. Differential-to-Differential Characterization Board
Circuit Side Layout
C1
0.1µF
C2
0.1µF
TC3-1T
AD8375
06724-043
T1
L1
1µH L2
1µH C3
0.1µF
C4
0.1µF
R1
62Ω
R2
62Ω
R4
25Ω
R3
25Ω
ETC1-1-13
T2 50Ω
PAD LOSS = 11dB
+5V
5
A0 TO A4
50Ω
AC
Figure 45. Test Circuit for Distortion, Gain, and Noise
AD8375 Data Sheet
Rev. A | Page 18 of 24
EVALUATION BOARD
Figure 46 shows the schematic of the AD8375 evaluation board.
The silkscreen and layout of the component and circuit sides
are shown in Figure 47 through Figure 50. The board is powered
by a single supply in the 4.5 V to 5.5 V range. The power supply
is decoupled by 10 µF and 0.1 µF capacitors at each power supply
pin. Additional decoupling, in the form of a series resistor or
inductor at the supply pins, can also be added. Table 6 details
the various configuration options of the evaluation board.
The output pins of the AD8375 require supply biasing with
1 µH RF chokes. Both the input and output pins must be ac-
coupled. These pins are converted to single-ended with a pair of
baluns (Mini-Circuits TC3-1T+ and M/A-COM ETC1-1-13).
The balun at the input, T1, is used to transform a 50 Ω source
impedance to the desired 150 Ω reference level. The output
balun, T3, and the matching components are configured to
provide a 150 Ω to 50 Ω impedance transformation with an
insertion loss of about 11 dB.
Data Sheet AD8375
Rev. A | Page 19 of 24
WA0
WA1
WA2
WA3WA4
C20
10µF
VPOS C14
0.1µF C13
0.1µF
VPOS
C1
0.1µF
C11
0.1µF
C2
0.1µF
TC3-1T+
T1
R70
R71
R72
R25
30.9Ω
R24
R23
30.9Ω
R2
0Ω
R1 R9
0Ω
R10
0Ω
INP
INN
T3
C8
0.1µF
C7
0.1µF
R20
61.9Ω
R91
0Ω
R19
61.9Ω
L2
1µH L1
1µH
C63
0.1µF
C64
0.1µF
R15
0Ω
R16
0Ω
VPOS
VPOS
R62
C62
0.1µF
ETC1-1-13
R29
R30
0Ω
OUTN
OUTP
C5
VPOS
PU
R13
0Ω
VPOS
06724-045
VXA
COMM VPOS COMM COMM COMM PWUP
1924 23 22 21 20
A1 A0 VPOS VPOS COMM VPOS
127 8 910 11
18
17
16
15
14
13
1
2
3
4
5
6
VCOM
VIN+
VIN–
A4
A3
A2
VOUT–
VOUT+
VOUT–
VOUT+
COMM
VPOS
AD8375
C60
0.1µF
Figure 46. AD8375 Evaluation Board Schematic
AD8375 Data Sheet
Rev. A | Page 20 of 24
Table 6. Evaluation Board Configuration Options
Components Function Default Conditions
C13, C14, C20,
C63, C64, R91
Power Supply Decoupling. Nominal supply decoupling consists a 10 µF
capacitor to ground followed by 0.1 µF capacitors to ground positioned as
close to the device as possible.
C20 = 10 µF (size 3528)
C13, C14, C63, C64 = 0.1 µF
(size 0402)
R91 = 0 Ω (size 0402)
T1, C1, C2, C60,
R1, R2, R9, R10,
R70 to R72
Input Interface. T1 is a 3:1 impedance ratio balun to transform a 50 Ω single-
ended input into a 150 Ω balanced differential signal. R2 grounds one side of
the differential drive interface for single-ended applications. R9, R10, and R70
to R72 are provided for generic placement of matching components. C1 and
C2 are dc blocks.
T1 = TC3-1+ (Mini-Circuits)
C1, C2, C60 = 0.1 µF (size 0402)
R2, R9, R10 = 0 Ω (size 0402)
R1, R70 to R72 = open (size 0402)
T3, C7, C8, C62
L1, L2, R15, R16,
R19, R20, R23 to R25,
R29, R30, R62
Output Interface. C7 and C8 are dc blocks. L1 and L2 provide dc biases for the
output. R19, R20, and R23 to R25 are provided for generic placement of
matching components. The evaluation board is configured to provide a 150 Ω
to 50 Ω impedance transformation with an insertion loss of about 11 dB. T3 is a
1:1 impedance ratio balun to transform the balanced differential signal to a
single-ended signal. R30 grounds one side of the differential output interface
for single-ended applications.
T3 = ETC1-1-13 (M/A-COM)
C7, C8, C62 = 0.1 µF (size 0402)
L1, L2 = 1 µH (size 0805)
R19, R20 = 61.9 Ω (size 0402)
R23, R25 = 30.9 Ω (size 0402)
R15, R16 = 0 Ω (size 0603)
R30 = 0 Ω (size 0402)
R24, R29, R62 = open (size 0402)
PU, R13, C5 Enable Interface. The AD8375 is enabled by applying a logic high voltage to
the PWUP pin. The device is disabled when the PU switch is set in the position
closest to the PU label, connecting the PWUP pin to ground. The device is
enabled when the PU switch is set in the opposite position, connecting the
PWUP to VPOS.
PU = installed
R13 = 0 Ω (size 0603)
C5 = open (size 0603)
WA0 to WA4 Parallel Interface Control. Used to hardwire A0 through A4 to the desired gain.
The bank of switches, WA4 to WA0, set the binary gain code. WA4 represents
the LSB. WA0 represents the MSB.
WA0 to WA4 = installed
C11 Voltage Reference. Input common-mode voltage ac-coupled to ground by
0.1 µF capacitor, C11.
C11 = 0.1 µF (size 0402)
Data Sheet AD8375
Rev. A | Page 21 of 24
06724-048
Figure 47. Component Side Silkscreen
06724-049
Figure 48. Circuit Side Silkscreen
06724-050
Figure 49. Component Side Layout
06724-051
Figure 50. Circuit Side Layout
AD8375 Data Sheet
Rev. A | Page 22 of 24
OUTLINE DIMENSIONS
COMPLIANT
TO
JEDEC S TANDARDS MO-220- V GG D- 2
04-09-2012-A
1
0.50
BSC
PI N 1
INDICATOR
2.50 RE F
0.50
0.40
0.30
TOP VIEW
12° M AX 0.80 MAX
0.65 TYP
SEATING
PLANE COPLANARITY
0.08
1.00
0.85
0.80
0.30
0.23
0.18
0.05 M AX
0.02 NOM
0.20 RE F
0.25 M IN
2.25
2.10 S Q
1.95
24
7
19
12
13
18
6
0.60 M AX
0.60 M AX
PI N 1
INDICATOR
4.10
4.00 S Q
3.90
3.75 BS C
SQ
EXPOSED
PAD
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
BOTTOM VIEW
Figure 51. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD8375ACPZ-WP −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Waffle Pack CP-24-1
AD8375ACPZ-R7 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape and Reel CP-24-1
AD8375-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
Data Sheet AD8375
Rev. A | Page 23 of 24
NOTES
AD8375 Data Sheet
Rev. A | Page 24 of 24
NOTES
©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06724-0-10/12(A)
