To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corpor ation took over all the business of both
companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid
Renesas Electronics document. W e appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas
Electronics products or the technology described in this document for any purpose relating to military applications or use by
the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and
technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Ren esas E lectronics assumes no liability whatsoever for any da mages
incurred by you resulting from errors in or omissions from the information included herein.
7. Renesas Electronics products are classified acco rding to the following three quality grades: “Standard”, “High Quality”, and
“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as
indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular
application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior
written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way
liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an
application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written
consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise
expressly specified in a Renesas Electronics data sheets or data books, et c.
“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electro nic app liances; machine tool s; p ersonal electron ic equipment; and indu strial robots .
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-
crime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”: Aircraft; aerospace equ i pment; submersible repeaters; nu clear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
interven tion (e.g. excision, et c.), and any oth er applications or purposes that pose a direct th reat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific chara cterist ics such as the o ccurren ce of failure at a certai n rate an d malfunct ion s under certai n u se cond ition s. Further,
Renesas Electronics pr oducts are not subject to radiation resi stance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
10. Please contact a Renesas Electronics sales office for det ai ls as to enviro nmental matters such as the en vi ronmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with
applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas
Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this
document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Renesas Electronics” as us ed in this document means Renesas Electronics Corporation and also includes its majo ri ty-
owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
DESCRIPTION
The 7560 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 7560 group has the LCD drive control circuit, an 8-channel
A-D converter, D-A converter, serial I/O and PWM as additional
functions.
The various microcomputers in the 7560 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
For details on availability of microcomputers in the 7560 group, re-
fer the section on group expansion.
FEATURES
•Basic machine-language instructions....................................... 71
•The minimum instruction execution time............................ 0.5 µs
(at 8 MHz oscillation frequency)
•Memory size
ROM ................................................................ 32 K t o 6 0 K bytes
RAM ............................................................... 1024 to 2560 bytes
•Programmable input/output ports ............................................. 55
•Software pull-up resistors .................................................... Built-in
•Output ports ................................................................................. 8
•Input ports .................................................................................... 1
•Interrupts .................................................. 17 sources, 16 vectors
External................ 7 sources (includes key input interr upt)
Internal ................................................................ 9 sources
Software................................................................ 1 source
•Timers ............................................................ 8-bit ✕ 3, 16-bit ✕ 2
•Serial I/O1 ..................... 8-bit ✕ 1 (UART or Clock-synchronous)
•Serial I/O2 .................................... 8-bit ✕ 1 (Clock-synchronous)
•PWM output .................................................................... 8-bit ✕ 1
•A-D converter ................................................ 10-bit ✕ 8 channels
•D-A converter .................................................. 8-bit ✕ 2 channels
•LCD drive control circuit
Bias .........................................................................1/2, 1/3
Duty ..................................................................1/2, 1/3, 1/4
Common output ................................................................ 4
Segment output .............................................................. 40
•2 Clock generating circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
•Watchdog timer ............................................................. 14-bit ✕ 1
•Power source voltage ................................................ 2.2 to 5.5 V
(EPROM and One Time PROM version: 2.5 to 5.5 V)
(Extended operating temperature version: 3.0 to 5.5 V)
•Power dissipation
In high-speed mode ...........................................................32 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode..............................................................45 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
•Operating temperature range ...................................– 20 t o 85°C
(Extended operating temperature version: – 40 to 85°C)
APPLICATIONS
Camera, household appliances, consumer electronics, etc.
7560 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Package type : 100P6S-A
Fig. 1 Pin configuration (Package type: 100P6S-A)
PIN CONFIGURATION (TOP VIEW)
1234567891
01
11
21
314151617181
9202
122232425262
72
82
93
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
45
4
6
4
7
4
8
4
9
5
0
51525
35
45
55
65
7585
96
06
162636
46
56
66
76
86
97
0717
27
37
47
57
67
77
87
98
0
8
1
8
2
8
3
8
4
85
8
6
8
7
8
8
8
9
9
0
9
1
9
2
9
3
9
4
9
5
9
6
9
7
9
8
9
9
10
0
M37560MF-XXXFP
S
E
G
9
P
3
1
/
S
E
G
1
9
P
3
0
/
S
E
G
1
8
P
3
2
/
S
E
G
2
0
P
3
3
/
S
E
G
2
1
P
3
4
/
S
E
G
2
2
S
E
G
1
0
S
E
G
1
1
S
E
G
1
2
S
E
G
1
3
S
E
G
1
4
S
E
G
1
5
P
3
5
/
S
E
G
2
3
P
3
6
/
S
E
G
2
4
P
3
7
/
S
E
G
2
5
P
0
0
/
S
E
G
2
6
P
0
1
/
S
E
G
2
7
P
0
2
/
S
E
G
2
8
P
0
3
/
S
E
G
2
9
P
0
4
/
S
E
G
3
0
P
0
5
/
S
E
G
3
1
P
0
6
/
S
E
G
3
2
P
0
7
/
S
E
G
3
3
P
1
0
/
S
E
G
3
4
P
1
1
/
S
E
G
3
5
P
1
2
/
S
E
G
3
6
P
1
3
/
S
E
G
3
7
P
1
4
/
S
E
G
3
8
P
1
5
/
S
E
G
3
9
C
1
V
L
1
P
6
7
/
A
N
7
P
6
6
/
A
N
6
P
6
5
/
A
N
5
P
6
4
/
A
N
4
P
6
2
/
S
C
L
K
2
1
/
A
N
2
P
6
1
/
S
O
U
T
2
/
A
N
1
P
6
0
/
S
I
N
2
/
A
N
0
P
5
7
/
A
D
T
/
D
A
2
P
5
6
/
D
A
1
P
5
5
/
C
N
T
R
1
P
5
4
/
C
N
T
R
0
P
5
3
/
R
T
P
1
P
5
2
/
R
T
P
0
P
5
1
/
P
W
M
1
P
5
0
/
P
W
M
0
P
4
6
/
S
C
L
K
1
P
4
5
/
T
X
D
P
4
4
/
R
X
D
P
4
3
/φ/
T
O
U
T
P
4
2
/
I
N
T
2
P
4
1
/
I
N
T
1
P
4
0
P
7
7
P
7
6
P
7
5
P
7
4
C
2
V
L
2
V
L
3
C
O
M
0
C
O
M
1
C
O
M
2
V
R
E
F
A
V
S
S
V
C
C
S
E
G
8
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
4
S
E
G
5
S
E
G
6
S
E
G
7
S
E
G
3
P
7
2
P
7
3
P
7
1
P
7
0
/
I
N
T
0
X
CIN
X
COUT
X
IN
X
OUT
V
SS
P
2
7
P
2
6
P
2
5
P2
4
P
2
3
P
2
1
P
1
6
P2
2
P
2
0
P
1
7
R
E
S
E
T
S
E
G
1
6
S
E
G
1
7
C
O
M
3
P
4
7
/
S
R
D
Y
1
P
6
3
/
S
C
L
K
2
2
/
A
N
3
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
2
Package type : 100P6Q-A
PIN CONFIGURATION (TOP VIEW)
Fig. 2 Pin configuration (Package type: 100P6Q-A)
12345678910111
21
31
41
51
61
71
81
92
02
12
22
32
42
5
2
6
2
7
2
8
29
30
31
3
2
33
3
4
35
3
6
3
7
3
8
3
9
4
0
41
42
4
3
4
4
45
4
6
4
7
4
8
4
9
5
0
5
15253545556575859606
1626364656
66
76
86
97
07
17
27
37
47
5
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
0
01
M37560MF-XXXGP
S
E
G
1
2
S
E
G
1
1
S
E
G
1
0
S
E
G
9
S
E
G
8
S
E
G
7
S
E
G
6
SEG
5
S
E
G
4
S
E
G
3
SEG
2
SEG
1
S
E
G
0
V
CC
V
REF
AV
SS
C
O
M
3
C
O
M
2
COM
1
COM
0
V
L
3
V
L2
C
2
C
1
V
L
1
P
6
7
/
A
N
7
P
6
6
/
A
N
6
P
6
5
/
A
N
5
P
6
4
/
A
N
4
P
5
7
/
A
D
T
/
D
A
2
P
5
6
/
D
A
1
P
5
5
/
C
N
T
R
1
P
5
4
/
C
N
T
R
0
P
4
1
/
I
N
T
1
P
4
0
P
4
3
/φ/
T
O
U
T
P
5
3
/
R
T
P
1
P
5
2
/
R
T
P
0
P
5
1
/
P
W
M
1
P
5
0
/
P
W
M
0
P
7
7
P
4
2
/
I
N
T
2
P7
2
P7
3
P7
1
P7
0
/INT
0
X
CIN
X
COUT
X
IN
X
OUT
V
SS
P2
7
P2
6
P2
5
P2
4
P2
3
P2
1
P1
6
P2
2
P2
0
P1
7
RESET
P7
6
P7
5
P7
4
P1
5
/SEG
39
P1
4
/SEG
38
P
3
1
/
S
E
G
1
9
P
3
0
/
S
E
G
1
8
P
3
2
/
S
E
G
2
0
P
3
3
/
S
E
G
2
1
P
3
4
/
S
E
G
2
2
S
E
G
1
3
S
E
G
1
4
S
E
G
1
5
P
3
5
/
S
E
G
2
3
P
3
6
/
S
E
G
2
4
P
3
7
/
S
E
G
2
5
P
0
0
/
S
E
G
2
6
P
0
1
/
S
E
G
2
7
P
0
2
/
S
E
G
2
8
P
0
3
/
S
E
G
2
9
P
0
4
/
S
E
G
3
0
P
0
5
/
S
E
G
3
1
P
0
6
/
S
E
G
3
2
P
0
7
/
S
E
G
3
3
P
1
0
/
S
E
G
3
4
P
1
1
/
S
E
G
3
5
P
1
2
/
S
E
G
3
6
P
1
3
/
S
E
G
3
7
S
E
G
1
6
S
E
G
1
7
P
6
2
/
S
C
L
K
2
1
/
A
N
2
P
6
1
/
S
O
U
T
2
/
A
N
1
P
6
0
/
S
I
N
2
/
A
N
0
P
6
3
/
S
C
L
K
2
2
/
A
N
3
P
4
6
/
S
C
L
K
1
P
4
5
/
T
X
D
P
4
4
/
R
X
D
P
4
7
/
S
R
D
Y
1
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
3
FUNCTIONAL BLOCK DIAGRAM (Package type: 100P6S-A)
Fig. 3 Functional block diagram
I
N
T
1
,
I
N
T
2
C
N
T
R
0
,
C
N
T
R
1
D
A
1
A
D
T
C
P
U
A
X
Y
S
P
C
H
P
C
L
P
S
R
E
S
E
T
V
C
C
V
S
S
(
5
V
)
(
0
V
)
R
O
M
R
A
M
3
5
9
1
4
0
P
4
(
8
)
P
2
(
8
)
P
0
(
8
)
P
1
(
8
)
P
6
(
8
)
P
7
(
8
)
P
3
(
8
)
P
5
(
8
)
1
2
1
0
0
9
9
9
8
9
7
9
6
9
5
9
4
9
0
8
8
8
7
8
6
8
5
8
4
8
3
8
2
8
1
8
0
7
9
7
8
7
7
7
6
7
5
7
4
7
3
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
4
9
5
0
5
1
5
2
5
4
5
5
5
6
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
6
5
6
6
6
7
6
8
6
9
7
0
7
1
7
2
1
9
2
0
2
2
2
3
2
4
2
5
2
6
3
6
3
7
2
7
2
8
2
9
3
0
3
2
3
3
3
4
3
4
5
6
7
8
9
1
0
9
3
9
2
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
X
C
I
N
X
C
O
U
T
X
I
N
O
U
T
X
C
O
U
T
X
X
C
I
N
S
I
/
O
1
(
8
)
V
R
E
F
A
V
S
S
V
L
1
C
1
C
2
V
L
2
V
L
3
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
S
E
G
5
S
E
G
6
S
E
G
7
S
E
G
8
S
E
G
9
S
E
G
1
0
S
E
G
1
1
S
E
G
1
2
S
E
G
1
3
S
E
G
1
4
S
E
G
1
5
S
E
G
1
6
S
E
G
1
7
φ
X
C
I
N
C
O
U
T
X
3
9
S
I
/
O
2
(
8
)
P
W
M
(
8
)
φ
I
N
T
0
D
-
A
2
D
-
A
1
D
A
2
T
O
U
T
L
C
D
d
r
i
v
e
c
o
n
t
r
o
l
c
i
r
c
u
i
t
L
C
D
d
i
s
p
l
a
y
R
A
M
(
2
0
b
y
t
e
s
)
T
i
m
e
r
X
(
1
6
)
T
i
m
e
r
Y
(
1
6
)
T
i
m
e
r
1
(
8
)
T
i
m
e
r
2
(
8
)
T
i
m
e
r
3
(
8
)
D
a
t
a
b
u
s
C
l
o
c
k
g
e
n
e
r
a
t
i
n
g
c
i
r
c
u
i
t
M
a
i
n
c
l
o
c
k
i
n
p
u
t
M
a
i
n
cl
o
c
k
o
u
t
p
u
t
S
u
b
-
c
l
o
c
k
o
u
t
p
u
t
S
u
b
-
c
l
o
c
k
i
n
p
u
t
R
e
s
e
t
K
e
y
i
n
p
u
t
(
K
e
y
-
o
n
w
a
k
e
u
p
)
i
n
t
e
r
r
u
p
t
R
e
a
l
t
i
m
e
p
o
r
t
f
u
n
c
t
i
o
n
A
-
D
c
o
n
v
e
r
t
e
r
(
8
)
I
/
O
p
o
r
t
P
0
I
/
O
p
o
r
t
P
1
I
/
O
p
o
r
t
P
2
I
/
O
p
o
r
t
P
4
I
/
O
p
o
r
t
P
5
I
/
O
p
o
r
t
P
6
O
u
t
p
u
t
p
o
r
t
P
3
I
/
O
p
o
r
t
P
7
R
e
s
e
t
i
n
p
u
t
S
u
b
-
c
l
o
c
k
o
u
t
p
u
t
S
u
b
-
c
l
o
c
k
i
n
p
u
t
W
a
t
c
h
d
o
g
t
i
m
e
r
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
4
PIN DESCRIPTION
Table 1 Pin description (1)
VCC, VSS
FunctionPin Name Function except a port function
•LCD segment output pins
Power source •Apply voltage of 2.2 V to 5.5 V (2.5 to 5.5 V for EPROM and One Time PROM version, 3.0 to 5.5 V
for extended operating temperature version) to VCC, and 0 V to VSS.
VREF
AVSS
RESET
XIN
XOUT
VL1–VL3
C1, C2
COM
0
–COM
3
SEG
0
–SEG
17
P00/SEG26–
P07/SEG33
P10/SEG34–
P15/SEG39
P16, P17
P20 – P27
P3
0
/SEG
18
–
P3
7
/SEG
25
Analog refer-
ence voltage
Analog power
source
Reset input
Clock input
Clock output
LCD power
source
Charge-pump
capacitor pin
Common output
Segment output
I/O port P0
I/O port P1
I/O port P2
Output port P3
•Reference voltage input pin for A-D converter and D-A converter.
•GND input pin for A-D converter and D-A converter.
•Connect to VSS.
•Reset input pin for active “L”.
•Input and output pins for the main clock generating circuit.
•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. A
feedback resistor is built-in.
•Input 0 ≤ VL1 ≤ VL2 ≤ VL3 voltage.
•Input 0 – VL3 voltage to LCD. (0 ≤ VL1 ≤ VL2 ≤ VL3 when a voltage is multiplied.)
•External capacitor pins for a voltage multiplier (3 times) of LCD control.
•LCD common output pins.
•COM2 and COM3 are not used at 1/2 duty ratio.
•COM3 is not used at 1/3 duty ratio.
•LCD segment output pins.
•8-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled.
•I/O direction register allows each 8-bit pin to be pro-
grammed as either input or output.
•6-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled.
•I/O direction register allows each 6-bit pin to be pro-
grammed as either input or output.
•2-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually programmed as either input or output.
•Pull-up control is enabled.
•8-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•8-bit output.
•CMOS 3-state output structure.
•Port output control is enabled.
•Key input (key-on wake-up) interrupt
input pins
•LCD segment output pins
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
5
Table 2 Pin description (2)
FunctionPin Name Function except a port function
P40
P41/INT1,
P42/INT2
P43/φ/TOUT
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
P50/PWM0,
P51/PWM1
P52/RTP0,
P53/RTP1
P54/CNTR0,
P55/CNTR1
P56/DA1
P5
7
/ADT/DA
2
P6
0
/S
IN2
/AN
0,
P6
1
/S
OUT2
/AN
1,
P6
2
/S
CLK21
/AN
2,
P6
3
/S
CLK22
/AN
3
P64/AN4–
P67/AN7
P70/INT0
P71–P77
I/O port P4
I/O port P5
I/O port P6
Input port P7
I/O port P7
Sub-clock output
Sub-clock input
•1-bit I/O port.
•CMOS compatible input level.
•N-channel open-drain output structure.
•I/O direction register allows this pin to be individually programmed as either input or output.
•7-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•8-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•8-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•1-bit input port.
•INTi interrupt input pins
•System clock φ output pin
•Timer 2 output pin
•Serial I/O1 I/O pins
•PWM output pins
•Real time port output pins
•Timer X, Y I/O pins
•D-A converter output pin
•D-A converter output pin
•A-D external trigger input pin
•A-D converter input pins
•Serial I/O2 I/O pins
•A-D converter input pins
XCOUT
XCIN
•INT0 interrupt input pin
•7-bit I/O port.
•CMOS compatible input level.
•N-channel open-drain output structure.
•I/O direction register allows each pin to be individually programmed as either input or output.
•Sub-clock generating circuit I/O pins.
(Connect a oscillator. External clock cannot be used.)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
6
PART NUMBERING
Fig. 4 Part numbering
M
3
7
5
6
0
M
F
D
–
X
X
X
F
P
P
ro
d
uct
ROM/PROM
s
i
ze
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
: 4096
b
ytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
T
h
e
f
i
r
s
t
1
2
8
b
y
t
e
s
a
n
d
t
h
e
l
a
s
t
2
b
y
t
e
s
o
f
R
O
M
a
r
e
r
e
s
e
r
v
e
d
a
r
e
a
s
;
t
h
e
y
c
a
n
n
o
t
b
e
u
s
e
d
.
M
emor y type
M
E :
M
as
k
ROM
vers
i
on
: EPROM and One Time PROM version
ROM
num
b
er
P
a
c
k
a
g
e
t
y
p
e
F
P
G
P
F
S
: 100P6S-A
: 100P6Q-A
: 100D0
D
:
E
xten
d
e
d
operat
i
ng temperature vers
i
on
O
m
i
tte
d
i
n
O
ne
Ti
me
PROM
vers
i
on an
d
EPROM
vers
i
on.
O
m
i
tte
d
i
n stan
d
ar
d
vers
i
on.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
7
GROUP EXPANSION
Mitsubishi expands the 7560 group as follows.
Memory Type
Support for mask ROM version.
Memory Size
ROM size ........................................................... 3 2 K t o 6 0 K bytes
RAM size .......................................................... 1024 to 2560 bytes
Packages
100P6Q-A .................................. 0.5 mm-pitch plastic molded QFP
100P6S-A ................................0.65 mm-pitch plastic molded QFP
Memory Expansion
Fig. 5 Memory expansion
ROM size (bytes)
RAM size (bytes)
256 5
1
27
6
8 1024 1280 1
5
3
6 17921
9
2 2
0
4
82
3
0
4 2560
32K
28K
24K
20K
16K
1
2
K
8
K
4K
5
2
K
4
8
K
4
4
K
4
0
K
3
6
K
5
6
K
6
0
KM
3
7
5
6
0
M
F
M
a
s
s
p
r
o
d
u
c
t
M37560M8
M
a
s
s
p
r
o
d
u
c
t
Currently products are listed below.
Table 3 List of products As of Jan. 2003
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Package
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
Product
M37560M8-XXXFP
M37560M8-XXXGP
M37560MF-XXXFP
M37560MF-XXXGP
RAM size (bytes)
1024
32768
(32638)
61440
(61310)
ROM size (bytes)
ROM size for User in ( )
2560
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
8
GROUP EXPANSION
(One Time and EPROM version)
Mitsubishi expands the 7560 group as follows.
Memory Type
Support for One Time and EPROM version.
Memory Size
ROM size ........................................................................ 60 K bytes
RAM size ....................................................................... 2560 bytes
Packages
100P6Q-A .................................. 0.5 mm-pitch plastic molded QFP
100P6S-A ................................0.65 mm-pitch plastic molded QFP
100D0 .......................................... Ce r a m i c L C C (EPROM version)
Memory Expansion
Fig. 6 Memory expansion
Currently products are listed below.
Table 4 List of products As of Jan. 2003
Remarks
One Time PROM version
One Time PROM version
EPROM version
Package
100P6S-A
100P6Q-A
100D0
Product
M37560EFFP
M37560EFGP
M37560EFFS
RAM size (bytes)
61440
(61310)
ROM size (bytes)
ROM size for User in ( )
2560
R
O
M
s
i
z
e
(
b
y
t
e
s
)
RAM size (bytes)
2
5
65
1
2 768 1
0
2
4 1280 1536 17921
9
2 2
0
4
8 2304 2560
32K
28K
24K
20K
16K
1
2
K
8
K
4K
5
2
K
4
8
K
4
4
K
4
0
K
3
6
K
5
6
K
6
0
KM
3
7
5
6
0
E
F
Mass product
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
9
GROUP EXPANSION
(Extended operating temperature version)
Mitsubishi expands the 7560 group as follows.
Memory Type
Support for extended operating temperature version.
Memory Size
ROM size ........................................................................ 60 K bytes
RAM size ....................................................................... 2560 bytes
Packages
100P6S-A ................................0.65 mm-pitch plastic molded QFP
Memory Expansion
Fig. 7 Memory expansion
Currently products are listed below.
Table 5 List of products As of Jan. 2003
Remarks
Mask ROM version (Extended operating temperature version)
One Time PROM version
(Extended operating temperature version)
Package
Product
M37560MFD-XXXFP
M37560EFDFP
RAM size (bytes)
61440
(61310)
ROM size (bytes)
ROM size for User in ( )
2560 100P6S-A
ROM size (bytes)
RAM size (bytes)
256 512 768 1024 1280 1536 1792192 2048 2304 2560
32K
28K
24K
20K
16K
12K
8
K
4K
5
2
K
48K
44K
4
0
K
36K
56K
60KM37560EFD
M37560MFD
Mass product
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
10
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 7560 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
The central processing unit (CPU) has six registers. Figure 8
shows the 740 Family CPU register structure.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as
arithmetic data transfer, etc., are executed mainly through the ac-
cumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0” , the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
Figure 9 shows the operations of pushing register contents onto
the stack and popping them from the stack. Table 6 shows the
push and pop instructions of accumulator or processor status reg-
ister.
Store registers other than those described in Figure 9 with pro-
gram when the user needs them during interrupts or subroutine
calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
Fig. 8 740 Family CPU register structure
A Accumulator
b7
b7
b7
b7 b0
b7b15 b0
b7 b0
b0
b0
b0
X Index register X
Y Index register Y
S Stack pointer
PC
L
Program counterPC
H
N V T B D I Z C Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
11
Table 6 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Fig. 9 Register push and pop at interrupt generation and subroutine call
N
o
t
e:
C
o
n
d
i
t
i
o
n
f
o
r
a
c
c
e
p
t
a
n
c
e
o
f
a
n
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
h
e
r
e
E
x
e
c
u
t
e
J
S
R
On-going Routin
e
M
(
S
)(
P
C
H
)
(
S
)
(
S
)
–
1
M
(
S
)(
P
C
L
)
E
x
e
c
u
t
e
R
T
S
(PC
L
)M (S)
(
S
)
(
S
)
–
1
(
S
)
(
S
)
+
1
(
S
)
(
S
)
+
1
(PC
H
)M (S)
S
u
b
r
o
u
t
i
n
e
POP return
address from stack
P
u
s
h
r
e
t
u
r
n
a
d
d
r
e
s
s
o
n
s
t
a
c
k
M (S) (PS)
Execute RTI
(
P
S
)M
(
S
)
(S) (S) – 1
(S) (S) + 1
Interrupt
Service Routine
POP conten ts of
processor status
register from stack
M
(
S
)(
P
C
H
)
(S)
(
S
)
–
1
M
(
S
)(
P
C
L
)
(S) (S) – 1
(PC
L
)M (S)
(S) (S) + 1
(S) (S) + 1
(
P
C
H
)M
(
S
)
POP return
address
from stack
I
F
l
a
g
i
s
s
e
t
f
r
o
m
“
0
”
t
o
“
1
”
F
e
t
c
h
t
h
e
j
u
m
p
v
e
c
t
o
r
P
u
s
h
r
e
t
u
r
n
a
d
d
r
e
s
s
o
n
s
t
a
c
k
Push contents of processor
status register on stack
Interrupt request
(
N
o
t
e
)
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
c
o
r
r
e
s
p
o
n
d
i
n
g
t
o
e
a
c
h
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
i
s
“
1
”
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
g
i
s
“
0
”
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
12
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
• Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arith-
metic logic unit (ALU) immediately after an arithmetic operation.
It can also be changed by a shift or rotate instruction.
• Bit 1: Zero flag (Z)
The Z flag is set to “1” if the result of an immediate arithmetic op-
eration or a data transfer is “0”, and set to “0” if the result is
anything other than “0”.
• Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt gener-
ated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
• Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed
when this flag is “0”; decimal arithmetic is executed when it is
“1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
• Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was gen-
erated by the BRK instruction. When the BRK instruction is
generated, the B flag is set to “1” automatically. When the other
interrupts are generated, the B flag is set to “0”, and the proces-
sor status register is pushed onto the stack.
• Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed be-
tween accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled be-
tween memory locations.
• Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set to “1” if the result exceeds +127 to -128.
When the BIT instruction is executed, bit 6 of the memory loca-
tion operated on by the BIT instruction is stored in the V flag.
• Bit 7: Negative flag (N)
The N flag is set to “1” if the result of an arithmetic operation or
data transfer is negative. When the BIT instruction is executed,
bit 7 of the memory location operated on by the BIT instruction is
stored in the negative flag.
Table 7 Instructions to set each bit of processor status register to “0” or “1”
Instruction setting to “1”
Instruction setting to “0”
C flag
SEC
CLC
Z flag
–
–
I flag
SEI
CLI
D flag
SED
CLD
B flag
–
–
T flag
SET
CLT
V flag
–
CLV
N flag
–
–
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
13
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the system clock control bits, etc.
The CPU mode register is allocated at address 003B16.
Fig. 10 Structure of CPU mode register
P
roc essor mo
d
e
bi
ts
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (“1” at reading)
(Write “1” t o this b it a t w riting )
X
C
switch bit
0 : Osci llation stop
1 : X
CIN–XCOUT
oscillating function
Main clock (X
IN
–X
OUT)
stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio select ion bit
0 : f(X
IN)/2 ( high-s peed mode)
1 : f(X
IN)/8 ( m iddle-s peed mode)
System clock selection bit
0 : X
IN–XOUT selected (middle-/high-speed mode)
1 : X
CIN–XCOUT se lected (low-s peed mode)
D
o not se
l
ect
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
(CPUM (CM) : address 003B
16
)
b
7
b
0
1
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
14
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac-
cess to this area with only 2 bytes is possible in the special page
addressing mode.
Fig. 11 Memory map diagram
1
9
2
2
5
6
3
8
4
5
1
2
6
4
0
7
6
8
8
9
6
1
0
2
4
1
5
3
6
2
0
4
8
2
5
6
0
00
FF
16
013F
16
01BF
16
023F
16
02BF
16
033F
16
03BF
16
043F
16
063F
16
083F
16
0A3F
16
R
A
M
a
r
e
a
R
A
M
s
i
z
e
(
b
y
t
e
s
)
A
d
d
r
e
s
s
X
X
X
X
1
6
4
0
9
6
8
1
9
2
1
2
2
8
8
1
6
3
8
4
2
0
4
8
0
2
4
5
7
6
2
8
6
7
2
3
2
7
6
8
3
6
8
6
4
4
0
9
6
0
4
5
0
5
6
4
9
1
5
2
5
3
2
4
8
5
7
3
4
4
6
1
4
4
0
F
0
0
0
1
6
E
0
0
0
1
6
D
0
0
0
1
6
C
0
0
0
1
6
B
0
0
0
1
6
A
0
0
0
1
6
9
0
0
0
1
6
8
0
0
0
1
6
7
0
0
0
1
6
6
0
0
0
1
6
5
0
0
0
1
6
4
0
0
0
1
6
3
0
0
0
1
6
2
0
0
0
1
6
1
0
0
0
1
6
F
0
8
0
1
6
E
0
8
0
1
6
D
0
8
0
1
6
C
0
8
0
1
6
B
0
8
0
1
6
A
0
8
0
1
6
9
0
8
0
1
6
8
0
8
0
1
6
7
0
8
0
1
6
6
0
8
0
1
6
5
0
8
0
1
6
4
0
8
0
1
6
3
0
8
0
1
6
2
0
8
0
1
6
1
0
8
0
1
6
ROM
area
ROM
s
i
ze
(bytes)
A
d
d
r
e
s
s
Y
Y
Y
Y
1
6
A
d
d
r
e
s
s
Z
Z
Z
Z
1
6
0100
16
0000
16
0040
16
FF
00
16
FFDC
16
F
F
F
E
1
6
FFFF
16
XXXX
16
YYYY
16
ZZZZ
16
RAM
R
O
M
0054
16
S
F
R
a
r
e
a
N
o
t
u
s
e
d
I
n
t
e
r
r
u
p
t
v
e
c
t
o
r
a
r
e
a
R
eserve
d
ROM
area
(128 byt es )
Z
e
r
o
p
a
g
e
S
p
e
c
i
a
l
p
a
g
e
LCD
di
sp
l
ay
RAM
area
R
e
s
e
r
v
e
d
R
O
M
a
r
e
a
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
15
Fig. 12 Memory map of special function register (SFR)
0
0
2
01
6
0
0
2
11
6
0
0
2
21
6
0
0
2
31
6
0
0
2
41
6
002516
0
0
2
61
6
0
0
2
71
6
0
0
2
81
6
0
0
2
91
6
0
0
2
A
1
6
0
0
2
B
1
6
002
C
16
002
D
16
0
0
2
E
1
6
002
F
16
0
0
3
01
6
0
0
3
11
6
0
0
3
21
6
0
0
3
31
6
003416
0
0
3
51
6
003616
003716
003816
003916
003
A
16
0
0
3
B
1
6
003
C
16
003
D
16
0
0
3
E
1
6
003
F
16
0
0
0
01
6
0
0
0
11
6
0
0
0
21
6
0
0
0
31
6
0
0
0
41
6
000516
0
0
0
61
6
0
0
0
71
6
0
0
0
81
6
0
0
0
91
6
0
0
0
A
1
6
0
0
0
B
1
6
0
0
0
C
1
6
0
0
0
D
1
6
0
0
0
E
1
6
0
0
0
F
1
6
0
0
1
01
6
0
0
1
11
6
0
0
1
21
6
0
0
1
31
6
001416
0
0
1
51
6
001616
001716
001816
001916
001
A
16
001
B
16
001
C
16
001
D
16
0
0
1
E
1
6
0
0
1
F
1
6
P
o
r
t
P
0
r
e
g
i
s
t
e
r
(
P
0
)
P
o
r
t
P
1
r
e
g
i
s
t
e
r
(
P
1
)
P
ort
P
1
di
rect
i
on reg
i
ster
(P
1
D)
P
o
r
t
P
2
r
e
g
i
s
t
e
r
(
P
2
)
P
o
r
t
P
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
2
D
)
P
ort
P
3 reg
i
ster
(P
3
)
P
o
r
t
P
4
r
e
g
i
s
t
e
r
(
P
4
)
P
o
r
t
P
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
4
D
)
P
o
r
t
P
5
r
e
g
i
s
t
e
r
(
P
5
)
P
o
r
t
P
5
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
5
D
)
P
o
r
t
P
6
r
e
g
i
s
t
e
r
(
P
6
)
P
o
r
t
P
6
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
6
D
)
P
o
r
t
P
7
r
e
g
i
s
t
e
r
(
P
7
)
P
o
r
t
P
7
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
7
D
)
S
e
r
i
a
l
I
/
O
1
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
S
I
O
1
S
T
S
)
S
er
i
a
l
I
/
O
1 cont r o
l
reg
i
ster
(SIO
1
CON)
U
A
R
T
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
U
A
R
T
C
O
N
)
B
au
d
rate generator
(BRG)
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
I
C
O
N
2
)
T
i
m
e
r
3
r
e
g
i
s
t
e
r
(
T
3
)
T
i
m
e
r
X
m
o
d
e
r
e
g
i
s
t
e
r
(
T
X
M
)
I
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
I
N
T
E
D
G
E
)
CPU
mo
d
e reg
i
ster
(CPUM)
I
nterrupt request reg
i
ster 1
(IREQ
1
)
I
nterrupt request reg
i
ster 2
(IREQ
2
)
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
I
C
O
N
1
)
T
i
m
e
r
X
l
o
w
-
o
r
d
e
r
r
e
g
i
s
t
e
r
(
T
X
L
)
T
i
m
e
r
Y
l
o
w
-
o
r
d
e
r
r
e
g
i
s
t
e
r
(
T
Y
L
)
Ti
me r 1 reg
i
ster
(T
1
)
T
i
m
e
r
2
r
e
g
i
s
t
e
r
(
T
2
)
Ti
mer
X
hi
g
h
-or
d
er reg
i
ster
(TXH)
T
i
m
e
r
Y
h
i
g
h
-
o
r
d
e
r
r
e
g
i
s
t
e
r
(
T
Y
H
)
P
U
L
L
r
e
g
i
s
t
e
r
A
(
P
U
L
L
A
)
P
U
L
L
r
e
g
i
s
t
e
r
B
(
P
U
L
L
B
)
T
i
m
e
r
Y
m
o
d
e
r
e
g
i
s
t
e
r
(
T
Y
M
)
Ti
me r 123 mo
d
e reg
i
ster
(T
123
M)
T
O
U
T/φ
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
C
K
O
U
T
)
S
egment out put en a
bl
e reg
i
ster
(SEG)
LCD
mo
d
e reg
i
ster
(LM)
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
D
C
O
N
)
A
-
D
convers
i
on
hi
g
h
-or
d
er
register (ADH)
T
ransm
i
t/
R
ece
i
ve
b
u
ff
er reg
i
ster
(TB
/
RB)
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
K
I
C
)
P
o
r
t
P
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
0
D
)
P
o
r
t
P
3
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
3
C
)
R
eserve
d
area
(N
ote
)
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
I
O
2
C
O
N
)
S
e
r
i
a
l
I
/
O
2
r
e
g
i
s
t
e
r
(
S
I
O
2
)
P
W
M
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
W
M
C
O
N
)
PWM
presca
l
er
(PREPWM)
PWM
reg
i
ster
(PWM)
R
eserve
d
area
(N
ote
)
R
eserve
d
area
(N
ote
)
R
e
s
e
r
v
e
d
a
r
e
a
(
N
o
t
e
)
R
eserve
d
area
(N
ote
)
D
-
A
1
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
D
A
1
)
D
-
A
2 convers
i
on reg
i
ster
(DA
2
)
D
-
A
contro
l
reg
i
ster
(DACON)
W
a
t
c
h
d
o
g
t
i
m
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
W
D
T
C
O
N
)
N
ote:
D
o not wr
i
te to t
h
e a
dd
resses o
f
reserve
d
area.
A
-
D
c
o
n
v
e
r
s
i
o
n
l
o
w
-
o
r
d
e
r
r
e
g
i
s
t
e
r
(
A
D
L
)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
16
I/O PORTS
Direction Registers
The I/O ports (ports P0, P1, P2, P4, P5, P6, P71–P77) have direc-
tion registers. Ports P16, P17, P4, P5, P6, and P71–P77 can be set
to input mode or output mode by each pin individually. P00–P07
and P10-P15 are respectively set to input mode or output mode in
a lump by bit 0 of the direction registers of ports P0 and P1 (see
Figure 13).
When “0” is set to the bit corresponding to a pin, that pin becomes
an input mode. When “1” is set to that bit, that pin becomes an
output mode.
If data is read from a port set to output mode, the value of the port
latch is read, not the value of the pin itself. A port set to input mode
is floating. If data is read from a port set to input mode, the value
of the pin itself is read. If a pin set to input mode is written to, only
the port latch is written to and the pin remains floating.
Port P3 Output Control Register
Bit 0 of the port P3 output control register (address 000716) en-
ables control of the output of ports P30–P37.
When the bit is set to “1”, the port output function is valid.
When resetting, bit 0 of the port P3 output control register is set to
“0” (the port output function is invalid) and pulled up.
Fig. 13 Structure of port P0 direction register, port P1 direc-
tion register
Fig. 14 Structure of port P3 output control register
P
orts
P
00 to
P
07
di
rect
i
on reg
i
ster
0 : Input mode
1 : Output mode
Not used (Undefined at reading)
(If writing to these bits, write “0”.)
P
ort
P
0
di
rect
i
on reg
i
ster
(P0D : address 000116)
b
7
b
0
N
ote:
I
n por ts set to output mo
d
e, t
h
e pu
ll
-up cont r o
l
bi
t
b
ecomes
invalid and pull-up resistor is not connected.
P
orts
P
10 to
P
15
di
rect
i
on reg
i
ster
0 : Input mode
1 : Output mode
Not used (Undefined at reading)
(If writing to these bits, write “0”.)
Port P16 direction register
Port P17 direction register
0 : Input mode
1 : Output mode
P
ort
P
1
di
rect
i
on reg
i
ster
(P1D : address 000316)
b
7
b
0
P
orts
P
3
0
to
P
3
7
output cont ro
l
bi
t
0 : Output function is invalid (Pulled up)
1 : Output function is valid (No pull up)
Not used (Undefined at reading)
(If writing to these bits, write “0”.)
P
ort
P
3 output con tro
l
reg
i
ster
(P3C : address 0007
16
)
b
7
b
0
N
o
t
e
:
I
n
p
i
n
s
s
e
t
t
o
s
e
g
m
e
n
t
o
u
t
p
u
t
b
y
s
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
s
0
,
1
(
b
i
t
s
0
,
1
o
f
s
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
3
8
1
6
)
)
,
t
h
i
s
b
i
t
b
e
c
o
m
e
s
i
n
v
a
l
i
d
a
n
d
p
u
l
l
-
u
p
r
e
s
i
s
t
o
r
i
s
n
o
t
c
o
n
n
e
c
t
e
d
.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
17
Fig. 15 Structure of PULL register A and PULL register B
Pull-up Control
By setting the PULL register A (address 0016 16) or the PULL reg-
ister B (address 001716), ports P0 to P2, P4 to P6 can control
pull-up with a program.
However, the contents of PULL register A and PULL register B do
not affect ports set to output mode and the ports are no pulled up.
The PULL register A setting is invalid for pins selecting segment
output with the segment output enable register and the pins are
not pulled up.
P
00,
P
01 pu
ll
-up contro
l
bi
t
P02, P03 pull-up control bit
P04–P07 pul l-up control bit
P10–P13 pul l-up control bit
P14, P15 pull-up control bit
P16, P17 pull-up control bit
P20–P23 pul l-up control bit
P24–P27 pul l-up control bit
P
U
L
L
r
e
g
i
s
t
e
r
A
(
P
U
L
L
A
:
a
d
d
r
e
s
s
0
0
1
61
6)
b
7
b
0
P
41–
P
43 pu
ll
-up cont r o
l
bi
t
P44–P47 pul l-up control bit
P50–P53 pul l-up control bit
P54–P57 pul l-up control bit
P60–P63 pul l-up control bit
P64–P67 pul l-up control bit
Not used “0” at r eading)
0
:
D
i
s
a
b
l
e
1
:
E
n
a
b
l
e
P
U
L
L
r
e
g
i
s
t
e
r
B
(
P
U
L
L
B
:
a
d
d
r
e
s
s
0
0
1
71
6)
b
7
b
0
N
ote:
Th
e cont ents o
f
PULL
reg
i
ster
A
an
d
PULL
reg
i
ster
B
do not affect ports set to output mode.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
18
PWM output
DA2 output
A-D external trigger
input
DA1 output
Diagram No.
Related SFRs
Input/OutputName
Pin Non-Port Function
I/O Format
Table 8 List of I/O port function (1)
P00/SEG26–
P07/SEG33
P10/SEG34–
P15/SEG39
P16 , P17
P20–P27
P30/SEG18–
P37/SEG25
P40
P41/INT1,
P42/INT2
P43/φ/TOUT
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
P50/PWM0,
P51/PWM1
P52/RTP0,
P53/RTP1
P54/CNTR0
P55/CNTR1
P56/DA1
P57/ADT/
DA2
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Input/output,
byte unit
Input/output,
6-bit unit
Input/output,
individual bits
Input/output,
individual bits
Output
Input/output,
individual bits
Input/output,
individual bits
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS 3-state output
CMOS compatible
input level
N-channel open-drain
output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
LCD segment output
LCD segment output
Key input (key-on
wake-up) interrupt
input
LCD segment output
INTi interrupt input
Timer 2 output
System clock φ output
Serial I/O1 I/O
Real time port output
Timer X I/O
Timer Y input
PULL register A
Segment output enable
register
PULL register A
Segment output enable
register
PULL register A
PULL register A
Interrupt control register 2
Key input control register
Segment output enable
register
Interrupt edge selection
register
PULL register B
Timer 123 mode register
TOUT/φ output control
register
PULL register B
Serial I/O1 control register
Serial I/O1 status register
UART control register
PULL register B
PWM control register
PULL register B
Timer X mode register
PULL register B
Timer X mode register
PULL register B
Timer Y mode register
PULL register B
D-A control register
PULL register B
D-A control register
A-D control register
(1)
(2)
(1)
(2)
(4)
(3)
(13)
(4)
(12)
(5)
(6)
(7)
(8)
(10)
(9)
(11)
(14)
(15)
(15)
Port P3 output control
register
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
19
Pin Name I/O Format Non-Port Function Related SFRS
Diagram No.
Input/Output
Notes 1: How to use double-function ports as function I/O pins, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC before execution of the STP instruction. When an electric potential is at an
intermediate potential, a current will flow from VCC to VSS through the input-stage gate and power source current may increase.
Table 9 List of I/O port function (2)
P60/SIN2/AN0
P61/SOUT2/
AN1
P62/SCLK21/
AN2
P63/SCLK22 /
AN3
P64/AN4–
P67/AN7
P70/INT0
P71–P77
COM0–COM3
SEG0–SEG17
Port P6
Port P7
Common
Segment
Input/
output,
individual
bits
Input
Input/
output,
individual
bits
Output
Output
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS compatible input
level
N-channel open-drain
output
LCD common output
LCD segment output
A-D converter input
Serial I/O2 I/O
A-D converter input
INT0 interrupt input
PULL register B
A-D control register
Serial I/O2 control
register
A-D control register
PULL register B
Interrupt edge
selection register
(17)
(18)
(19)
(20)
(16)
(23)
(13)
(21)
(22)
LCD mode register
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
20
Fig. 16 Port block diagram (1)
(5) Port P4
4
(
4
)
P
o
r
t
s
P
1
6
,
P
1
7
,
P
2
,
P
4
1
,
P
4
2
Pull-up control
V
L
1
/
V
S
S
V
L2
/V
L3
/V
CC
V
L1
/V
SS
V
L
2
/
V
L
3
/
V
C
C
V
L1
/V
SS
V
L
2
/
V
L
3
/
V
C
C
(
1
)
P
o
r
t
s
P
0
1
–
P
0
7
,
P
1
1
–
P
1
5
D
a
t
a
b
u
sP
o
r
t
l
a
t
c
hI
n
t
e
r
f
a
c
e
l
o
g
i
c
l
e
v
e
l
s
h
i
f
t
c
i
r
c
u
i
t
P
u
l
l
-
u
p
P
o
r
t
S
e
g
m
e
n
t
S
e
g
m
e
n
t
/
P
o
r
t
L
C
D
d
r
i
v
e
t
i
m
i
n
g
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
S
e
g
m
e
n
t
d
a
t
a
Port direction register
P
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
2
)
P
o
r
t
s
P
0
0
,
P
1
0
D
a
t
a
b
u
sP
o
r
t
l
a
t
c
hInterface logic level
shift circuit
Port
S
e
g
m
e
n
t
Segment/Port
LCD drive timing
S
e
g
m
e
n
t
d
a
t
a
Port direction register
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Pull-up
D
a
t
a
b
u
sPort latch I
n
t
e
r
f
a
c
e
l
o
g
i
c
l
e
v
e
l
s
h
i
f
t
c
i
r
c
u
i
t
P
o
r
t
S
e
g
m
e
n
t
Segment/Port
LCD drive timing
Segment data
P
o
r
t
P
3
ou
t
p
u
t
c
o
n
t
r
o
l
b
i
t
Pull-up
(
3
)
P
o
r
t
P
3
D
a
t
a
b
u
sPort latch
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Key input interrupt input
INT
1
, INT
2
interrupt input
E
x
c
e
p
t
P
1
6
,
P
1
7
P
u
l
l
-
u
p
c
o
n
t
r
o
l
Data bus Port latch
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
S
e
r
i
a
l
I
/
O
1
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
1
i
n
p
u
t
R
e
c
e
i
v
e
e
n
a
b
l
e
b
i
t
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
Port P3 output
control bit
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
21
Fig. 17 Port block diagram (2)
(6) Port P4
5
(7) Port P4
6
(8) Port P4
7
(9) Ports P5
2
,P5
3
(
1
0
)
P
o
r
t
s
P
5
0
,
P
5
1
P
W
M
f
u
n
c
t
i
o
n
e
n
a
b
l
e
b
i
t
P
W
M
o
u
t
p
u
t
(
1
1
)
P
o
r
t
P
5
4
P ulse output mode
Timer output
CNTR
0
interrupt inpu
t
P
u
l
l
-
u
p
c
o
n
t
r
o
l
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
D
a
t
a
b
u
sP
o
r
t
l
a
t
c
h
S
e
r
i
a
l
I
/
O
1
o
u
t
p
u
t
P
4
5
/
T
x
D
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
1
e
n
a
b
l
e
b
i
t
T
r
a
n
s
m
i
t
e
n
a
b
l
e
b
i
t
Serial I/O1 clock output
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Data bus P
o
r
t
l
a
t
c
h
P
u
l
l
-
u
p
c
o
n
t
r
o
l
S
e
r
i
a
l
I
/
O
1
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
1
c
l
o
c
k
i
n
p
u
t
Serial I/O1 synchronous
clock selection bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
P
u
l
l
-
u
p
c
o
n
t
r
o
l
S
e
r
i
a
l
I
/
O
1
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
1
e
n
a
b
l
e
b
i
t
S
R
D
Y
1
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Data bus Port latch
Serial I/O1 ready output
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Data bus Port latch
Pull-up contro l
Real time port control bit
Real time port data
P
u
l
l
-
u
p
c
o
n
t
r
o
l
Direction
register
Data bus Port latch
P
u
l
l
-
u
p
c
o
n
t
r
o
l
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
D
a
t
a
b
u
sP
o
r
t
l
a
t
c
h
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
22
Fig. 18 Port block diagram (3)
(12) Port P43
T
OUT
/φ output enable bit
Timer 2 T
OUT
output
System clock φ output
T
OUT
/φ output selection bit
(13) Ports P40,P71–P77
(14) Port P55
CNTR
1
interrupt input
(15) Ports P56,P57
A-D external trigger input
D-A converter output
Except P5
6
(16) Ports P64–P67(17) Port P60
Analog input pin selection bit
A-D converter input
Serial I/O2 input
DA
1
, DA
2
output enable bits
Direction
register
Port latch
Data bus
Pull-up control
Direction
register
Port latch
Data bus
Direction
register
Port latch
Data bus
Pull-up control
Direction
register
Port latch
Data bus
Pull-up control
Direction
register
Port latch
Data bus
Pull-up control
Analog input pin selection bit
A-D converter input
Direction
register
Port latch
Data bus
Pull-up control
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
23
Fig. 19 Port block diagram (4)
(18) Port P61(19) Port P62
(
2
0
)
P
o
r
t
P
63
S
e
r
i
a
l
I
/
O
2
o
u
t
p
u
t
Serial I/O2 transmit end signal
Serial I/O2 synchronous clock selection bit
Serial I/O2 port selection bit
P
u
l
l
-
u
p
c
o
n
t
r
o
l
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
A
-
D
c
o
n
v
e
r
t
e
r
i
n
p
u
t
P
61/
SO
U
T
2
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
(
2
1
)
C
O
M0
–C
O
M3
(
2
2
)
S
E
G0–
S
E
G1
7
VL3
VL2
VL1
VSS
VL
2/
VL
3
VL1/VSS
(23) Port P70
I
N
T0
i
n
p
u
t
Serial I/O2 synchronous clock
selection bit
Serial I/O2 clock output S
e
r
i
a
l
I
/
O
2
c
l
o
c
k
i
n
p
u
t
S
e
r
i
a
l
I
/
O
2
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
S
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
o
u
t
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
A-D converter input
S
e
r
i
a
l
I
/
O
2
c
l
o
c
k
o
u
t
p
u
tA-D converter input
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
hD
a
t
a
b
u
s
P
u
l
l
-
u
p
c
o
n
t
r
o
l
Direction
register
P
o
r
t
l
a
t
c
hD
a
t
a
b
u
s
Analog input pin selection bit
Pull-up control
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
hData bus
Analog input pin selection bit
Serial I/O2 synchronous clock selection bit
Serial I/O2 port selection bit
Data bus
T
h
e
g
a
t
e
i
n
p
u
t
s
i
g
n
a
l
o
f
e
a
c
h
t
r
a
n
s
i
s
t
o
r
i
s
c
o
n
t
r
o
l
l
e
d
b
y
t
h
e
L
C
D
d
u
t
y
r
a
t
i
o
a
n
d
t
h
e
b
i
a
s
v
a
l
u
e
.
T
h
e
v
o
l
t
a
g
e
a
p
p
l
i
e
d
t
o
t
h
e
s
o
u
r
c
e
s
o
f
P
-
c
h
a
n
n
e
l
a
n
d
N
-
c
h
a
n
n
e
l
t
r
a
n
s
i
s
t
o
r
s
i
s
t
h
e
c
o
n
t
r
o
l
l
e
d
v
o
l
t
a
g
e
b
y
t
h
e
b
i
a
s
v
a
l
u
e
.
Synchronous clock output pin selection
bit
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
24
INTERRUPTS
Interrupts occur by seventeen sources: seven external, nine inter-
nal, and one software. When an interrupt request is accepted, the
program branches to the interrupt jump destination address set in
the vector address (see Figure 10).
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt is accepted if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
Interrupt enable bits can be set to “0” or “1” by program.
Interrupt request bits can be set to “0” by program, but cannot be
set to “1” by program.
The BRK instruction interrupt and reset cannot be disabled with
any flag or bit. When the interrupt disable (I) flag is set to “1”, all
interrupt requests except the BRK instruction interrupt and reset
are not accepted.
When several interrupt requests occur at the same time, the inter-
rupts are received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt jump destination address is read from the vector
table into the program counter.
3. The interrupt disable flag is set to “1” and the corresponding in-
terrupt request bit is set to “0”.
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset is not an interrupt. Reset has the higher priority than all interrupts.
Table 10 Interrupt vector addresses and priority
Remarks
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At completion of serial I/O1 data
reception
At completion of serial I/O1
transmit shift or when transmis-
sion buffer is empty
Interrupt Source LowHigh
Priority V ector Addresses (Note 1)
Reset (Note 2)
INT0
INT1
Serial I/O1
reception
Serial I/O1
transmission
Timer X
T imer Y
Timer 2
Timer 3
CNTR0
CNTR1
Timer 1
INT2
Serial I/O2
Key input
(Key-on wake-up)
ADT
A-D conversion
BRK instruction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At timer 1 underflow
At detection of either rising or
falling edge of INT2 input
At completion of serial I/O2 data
transmission or reception
At falling of conjunction of input
level for port P2 (at input mode)
At falling edge of ADT input
At completion of A-D conversion
At BRK instruction execution
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O2 is selected
External interrupt
(valid at falling)
Valid when ADT interrupt is selected
External interrupt
(valid at falling)
Valid when A-D interrupt is selected
Non-maskable software interrupt
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
25
Fig. 20 Interrupt control
Fig. 21 Structure of interrupt-related registers
■Notes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
•When switching external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X mode register (address 2716)
Timer Y mode register (address 2816)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt source selection bit of A-D control reg-
ister (bit 6 of address 3416)
When not requiring for the interrupt occurrence synchronous with
these setting, take the following sequence.
➀Set the corresponding interrupt enable bit to “0” (disabled).
➁Set the interrupt edge select bit (polarity switch bit) or the inter-
rupt source selection bit.
➂Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃Set the corresponding interrupt enable bit to “1” (enabled).
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
g
(
I
)
BRK instruction
Rese
t
Interrupt request acceptance
b
7
b
0
I
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
I
N
T
0
i
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
I
N
T
1
i
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
I
N
T
2
i
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
N
o
t
u
s
e
d
(
“
0
”
a
t
r
e
a
d
i
n
g
)
(INTEDGE
: a
dd
ress 003
A
16
)
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
1
I
N
T
0
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
N
T
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
S
e
r
i
a
l
I
/
O
1
r
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
S
e
r
i
a
l
I
/
O
1
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
Y
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
3
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
I
N
T
0
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I
N
T
1
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
1
r
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
1
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
Y
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
2
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
3
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
0
:
N
o
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
1
:
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
(
I
R
E
Q
1
:
a
d
d
r
e
s
s
0
0
3
C
1
6
)
(
I
C
O
N
1
:
a
d
d
r
e
s
s
0
0
3
E
1
6
)
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
2
CNTR
0
i
nterrupt request
bi
t
CNTR
1
interrupt request bit
Timer 1 interrupt request bit
INT
2
interrupt request bit
Serial I/O2 interrupt request bit
Key input interrupt request bit
ADT/AD conversion interrupt request bit
Not used (“0” at reading)
(
I
R
E
Q
2
:
a
d
d
r
e
s
s
0
0
3
D
1
6
)
I
nterr upt cont r o
l
reg
i
ster 2
CNTR
0
i
nterrupt ena
bl
e
bi
t
CNTR
1
interrupt enable bit
Timer 1 interrupt enable bit
INT
2
interrupt enable bit
Serial I/O2 interrupt enable bit
Key input interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (“0” at reading)
(Write “0” to this b it)
0 :
I
nterrupts
di
sa
bl
e
d
1 : Interrupts enabled
(ICON
2 : a
dd
ress 003
F
16
)
0 :
F
a
lli
ng e
d
ge act
i
ve
1 : Risin g edge act iv e
b
7
b
0
b
7
b
0
b
7
b
0
b
7
b
0
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
26
Key Input Interrupt (Key-on Wake Up)
The key input interrupt is enabled when any of port P2 is set to in-
put mode and the bit corresponding to key input control register is
set to “1”.
A Key input interrupt request is generated by applying “L” level
voltage to any pin of port P2 of which key input interrupt is en-
abled. In other words, it is generated when AND of input level
goes from “1” to “0”. A connection example of using a key input in-
terrupt is shown in Figure 22, where an interrupt request is gener-
ated by pressing one of the keys consisted as an active-low key
matrix which inputs to ports P20–P23.
Fig. 22 Connection example when using key input interrupt and port P2 block diagram
P
o
r
t
P
2
0
l
a
t
c
h
P
o
r
t
P
2
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
=
“
0
”
P
o
r
t
P
2
1
l
a
t
c
h
Port P2
1
direction register = “0”
P
o
r
t
P
2
2
l
a
t
c
h
Port P2
2
direction register = “0”
Port P2
3
latch
Port P2
3
direction register = “0”
Port P2
4
latch
Port P2
4
direction register = “1”
Port P2
5
latch
Port P2
5
direction register = “1”
P
o
r
t
P
2
6
l
a
t
c
h
P
o
r
t
P
2
6
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
=
“
1
”
Port P2
7
latch
Port P2
7
direction register = “1”
P
2
0
i
n
p
u
t
P2
1
input
P2
2
input
P
2
3
i
n
p
u
t
P
2
4
o
u
t
p
u
t
P
2
5
o
u
t
p
u
t
P
2
6
o
u
t
p
u
t
P
2
7
o
u
t
p
u
t
P
U
L
L
r
e
g
i
s
t
e
r
A
B
i
t
7
Port P2
Input reading circ uit
P
o
r
t
P
X
x
“
L
”
l
e
v
e
l
o
u
t
p
u
t
✽ P-channel transistor for pull-up
✽ ✽ CMOS output buffer
K
e
y
i
n
p
u
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
P2
7
key input control bi t
P
2
6
k
e
y
i
n
p
u
t
c
o
n
t
r
o
l
b
i
t
✽✽
✽
✽✽ ✽
✽✽
✽
✽✽
✽
✽✽
✽
✽✽ ✽
✽✽ ✽
✽✽
✽
P
2
5
k
e
y
i
n
p
u
t
c
o
n
t
r
o
l
b
i
t
P
2
4
k
e
y
i
n
p
u
t
c
o
n
t
r
o
l
b
i
t
P
2
3
k
e
y
i
n
p
u
t
c
o
n
t
r
o
l
b
i
t
=
“
1
”
P
U
L
L
r
e
g
i
s
t
e
r
A
B
i
t
6
=
“
1
”
P
2
2
k
e
y
i
n
p
u
t
c
o
n
t
r
o
l
b
i
t
=
“
1
”
P
2
1
k
e
y
i
n
p
u
t
c
o
n
t
r
o
l
b
i
t
=
“
1
”
P2
0
key input control bi t = “1”
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
27
The key input interrupt is controlled by the key input control regis-
ter and the port direction register. When enabling the key input
interrupt, set “1” to the key input control bit. A key input can be ac-
cepted from pins set as the input mode in ports P20–P27.
Fig. 23 Structure of key input control register
P
20
k
ey
i
nput c ontro
l
bi
t
P21 key input control bit
P22 key input control bit
P23 key input control bit
P24 key input control bit
P25 key input control bit
P26 key input control bit
P27 key input control bit
0
:
K
e
y
i
n
p
u
t
i
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
d
1
:
K
e
y
i
n
p
u
t
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
d
K
ey
i
nput contro
l
re g
i
ster
(KIC : address 001516)
b
7
b
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
28
TIMERS
The 7560 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0”, an
underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
Fig. 24 Timer block diagram
“1”
P5
5
/CNTR
1
“0”
“
1
0
”
“00”,“01”,“11”
P5
4
/CNTR
0
Q
QT
S
“0”
“1”
“
0
”
Q
D
“
0
”
Q
D
“
1
”
“
0
”
“1”“
1
0
”
QT
S
“
0
”
“
1
”
“0”
“1”
“1”
P4
3
/φ/T
OUT
X
C
I
N
“0”
“1”
CNTR
0
active
edge swi tch bit
T
i
m
e
r
1
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
Real time port
control bit “0”
f
(
X
I
N
)
/
1
6
(
f
(
X
C
I
N
)
/
1
6
w
h
e
n
φ
=
X
C
I
N
/
2
)
C
N
T
R
1
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
Timer Y stop
control bit
Falling edge detection P
e
r
i
o
d
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
Timer Y
interrupt
request
P
u
l
s
e
w
i
d
t
h
H
L
c
o
n
t
i
n
u
o
u
s
l
y
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
R
i
s
i
n
g
e
d
g
e
d
e
t
e
c
t
i
o
n
Timer Y
operating
mode bits
Timer X
interrupt
request
T
i
m
e
r
X
m
o
d
e
r
e
g
i
s
t
e
r
w
r
i
t
e
s
i
g
n
a
l
P
4
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Pulse out put mode
P
5
4
l
a
t
c
h
Timer X stop
control bit Timer X write
control bit
L
a
t
c
h
T
i
m
e
r
X
o
p
e
r
a
t
-
i
n
g
m
o
d
e
b
i
t
s
“
0
0
”
,
“
0
1
”
,
“
1
1
”
Pulse width
measurement
mode C
N
T
R
0
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
Pulse out put mode
P5
4
directi on r egister
T
OUT
output
active edge
switch bit “0”
T
i
m
e
r
2
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
Timer 3 count
source selection bit
Timer 2
interrupt
request
Timer 3
interrupt
request
T
i
m
e
r
2
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
T
i
m
e
r
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
D
a
t
a
b
u
s
R
e
a
l
t
i
m
e
p
o
r
t
c
o
n
t
r
o
l
b
i
t
“
1
”
R
e
a
l
t
i
m
e
p
o
r
t
c
o
n
t
r
o
l
b
i
t
“
1
”
T
i
m
e
r
3
l
a
t
c
h
(
8
)
T
i
m
e
r
3
r
e
g
i
s
t
e
r
(
8
)
Timer 1 latch (8)
Timer 1 register (8)
Timer 2 latch (8)
T
i
m
e
r
2
r
e
g
i
s
t
e
r
(
8
)
Timer X low-order register (8)
Timer X (low) latch (8) Timer X (high) latch (8)
T
i
m
e
r
Y
(
l
o
w
)
l
a
t
c
h
(
8
)T
i
m
e
r
Y
(
h
i
g
h
)
l
a
t
c
h
(
8
)
Latch
P
4
3
l
a
t
c
h
f(X
IN
)/16
(f(X
CIN
)/16 when φ = X
CIN
/2)
f(X
IN
)/16
(f(X
CIN
)/16 when φ = X
CIN
/2)
f(X
IN
)/16
(f(X
CIN
)/16 when φ = X
CIN
/2)
f(X
IN
)/16
(f(X
CIN
)/16 when φ = X
CIN
/2)
P
5
2
/
R
T
P
0
P
5
3
/
R
T
P
1
RTP
0
data for
real time port
RTP
1
data for
real time port
P
5
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
rP
5
2
l
a
t
c
h
P5
3
directi on r egisterP
5
3
l
a
t
c
h
φ
Timer X high-order register (8)
Timer Y low-order register (8) T
i
m
e
r
Y
h
i
g
h
-
o
r
d
e
r
r
e
g
i
s
t
e
r
(
8
)
Q
T
O
U
T
/φ
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
T
O
U
T
/φ
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
T
O
U
T
/φ output
enable bit
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
29
Timer X
Timer X is a 16-bit timer and is equipped with the timer latch. The
division ratio of timer X is given by 1/(n+1), where n is the value in
the timer latch. Timer X is a down-counter. When the contents of
timer X reach “000016”, an underflow occurs at the next count
pulse and the contents of the timer latch are reloaded into the
timer and the count is continued. When the timer underflows, the
timer X interrupt request bit is set to “1”.
Timer X can be selected in one of four modes by the timer X mode
register and can be controlled the timer X write and the real time
port.
(1) Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode,
set the P54/CNTR0 pin to output mode (set “1” to bit 4 of port P5
direction register).
(3) Event counter mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the P54/
CNTR0 pin to input mode (set “0” to bit 4 of port P5 direction reg-
ister).
(4) Pulse width measurement mode
The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If
CNTR0 active edge switch bit is “0”, the timer counts while the
input signal of CNTR0 pin is at “H”. If it is “1”, the timer counts
while the input signal of CNTR0 pin is at “L”. When using a timer in
this mode, set the P54/CNTR0 pin to input mode (set “0” to bit 4 of
port P5 direction register).
●Read and write to timer X high-order, low-order registers
When reading and writing to the timer X high-order and low-order
registers, be sure to read/write both the timer X high- and low-or-
der registers.
When reading the timer X high-order and low-order registers, read
the high-order register first. When writing to the timer X high-order
and low-order registers, write the low-order register first. The timer
X cannot perform the correct operation if the next operation is per-
formed.
•Write operation to the high- or low-order register before reading
the timer X low-order register
•Read operation from the high- or low-order register before writing
to the timer X high-order register
Fig. 25 Structure of timer X mode register
T
i
m
e
r
X
m
o
d
e
r
e
g
i
s
t
e
r
(
T
X
M
:
a
d
d
r
e
s
s
0
0
2
7
1
6
)
Ti
mer
X
wr
i
te cont ro
l
bi
t
0 : Write value in latch and timer
1 : Write value in lat c h o nly
Re al time port control bit
0 : Real time port function invalid
1 : Real time port function valid
RTP
0
data for real time port
RTP
1
data for real time port
Time r X ope ra ti ng mo de bits
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counte r mode
1 1 : Pulse width measurement mode
CNTR
0
acti ve edge swi tch bit
0 : Count at rising edge in event counter mode
Start from “H” out put in puls e out put mo de
Measure “H” p ulse width in puls e wi dth measur ement
mode
Fallin g e dg e active for CNTR
0
interrupt
1 : Count at falling edge in event counter mode
Start from “L” output in pulse output mode
Measure “L” pulse width in pulse width measurement
mode
Ris ing ed ge ac tiv e fo r CNTR
0
interrupt
Ti mer X stop cont rol bit
0 : Cou nt start
1 : Cou nt stop
b
7
b
0
●Timer X Write Control
Which write control can be selected by the timer X write control bit
(bit 0) of the timer X mode register (address 002716), writing data
to both the latch and the timer at the same time or writing data
only to the latch. When the operation “writing data only to the
latch” is selected, the value is set to the timer latch by writing data
to the timer X register and the timer is updated at next underflow.
After reset, the operation “writing data to both the latch and the
timer at the same time” is selected, and the value is set to both
the latch and the timer at the same time by writing data to the
timer X register. The write operation is independent of timer X
count operation, operating or stopping.
When the value is written in latch only, a value is simultaneously
set to the timer X and the timer X latch if the writing in the high-
order register and the underflow of timer X are performed at the
same timing. Unexpected value may be set in the high-order timer
on this occasion.
●Real Time Port Control
While the real time port function is valid, data for the real time port
are output from ports P52 and P53 each time the timer X
underflows. (However, if the real time port control bit is changed
from “0” to “1” after set of the real time port data, data are output
independent of the timer X operation.) If the data for the real time
port is changed while the real time port function is valid, the
changed data are output at the next underflow of timer X.
Before using this function, set the P52/RTP0, P53/RTP1 pins to
output mode (set “1” to bits 2, 3 of port P5 direction register).
■Note on CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
30
Timer Y
Timer Y is a 16-bit timer and is equipped with the timer latch. The
division ratio of timer Y is given by 1/(n+1), where n is the value in
the timer latch. Timer Y is a down-counter. When the contents of
timer Y reach “000016”, an underflow occurs at the next count
pulse and the contents of the timer latch are reloaded into the
timer and the count is continued. When the timer underflows, the
timer Y interrupt request bit is set to “1”.
Timer Y can be selected in one of four modes by the timer Y mode
register.
(1) Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
(2) Period measurement mode
CNTR1 interrupt request is generated at rising or falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down.
Except for this, the operation in period measurement mode is the
same as in timer mode.
The timer value just before the reloading at rising or falling of
CNTR1 pin input signal is retained until the next valid edge is
input.
The rising or falling timing of CNTR1 pin input signal can be
discriminated by CNTR1 interrupt. When using a timer in this
mode, set the P55/CNTR1 pin to input mode (set “0” to bit 5 of port
P5 direction register).
(3) Event counter mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the
P55/CNTR1 pin to input mode (set “0” to bit 5 of port P5 direction
register).
(4) Pulse width HL continuously measure-
ment mode
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the P55/CNTR1 pin to input mode (set “0” to bit 5 of port P5
direction register).
■Note on CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the value of the CNTR1
active edge switch bit. However, in pulse width HL continuously
measurement mode, CNTR1 interrupt request is generated at both
rising and falling edges of CNTR1 pin input signal regardless of
the value of CNTR1 active edge switch bit.
Fig. 26 Structure of timer Y mode register
T
i
m
e
r
Y
m
o
d
e
r
e
g
i
s
t
e
r
(
T
Y
M
:
a
d
d
r
e
s
s
0
0
2
81
6)
b
7
b
0
N
o
t
u
s
e
d
(
“
0
”
a
t
r
e
a
d
i
n
g
)
T
i
m
e
r
Y
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
b
5b
4
00
:
T
i
m
e
r
m
o
d
e
01
:
P
e
r
i
o
d
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
10
:
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
11
:
P
u
l
s
e
w
i
d
t
h
H
L
c
o
n
t
i
n
u
o
u
s
l
y
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
C
N
T
R1
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
0
:
C
o
u
n
t
a
t
r
i
s
i
n
g
e
d
g
e
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
M
e
a
s
u
r
e
t
h
e
f
a
l
l
i
n
g
e
d
g
e
t
o
f
a
l
l
i
n
g
e
d
g
e
p
e
r
i
o
d
i
n
p
e
r
i
o
d
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
F
a
l
l
i
n
g
e
d
g
e
a
c
t
i
v
e
f
o
r
C
N
T
R1
i
n
t
e
r
r
u
p
t
1
:
C
o
u
n
t
a
t
f
a
l
l
i
n
g
e
d
g
e
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
M
e
a
s
u
r
e
t
h
e
r
i
s
i
n
g
e
d
g
e
p
e
r
i
o
d
i
n
p
e
r
i
o
d
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
R
i
s
i
n
g
e
d
g
e
a
c
t
i
v
e
f
o
r
C
N
T
R1
i
n
t
e
r
r
u
p
t
T
i
m
e
r
Y
s
t
o
p
c
o
n
t
r
o
l
b
i
t
0
:
C
o
u
n
t
s
t
a
r
t
1
:
C
o
u
n
t
s
t
o
p
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
31
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers and is equipped with
the timer latch. The count source for each timer can be selected
by the timer 123 mode register.
The division ratio of each timer is given by 1/(n+1), where n is the
value in the timer latch. All timers are down-counters. When the
contents of the timer reach “0016”, an underflow occurs at the next
count pulse and the contents of the timer latch are reloaded into
the timer and the count is continued. When the timer underflows,
the interrupt request bit corresponding to that timer is set to “1”.
When a value is written to the timer 1 register and the timer 3 reg-
ister, a value is simultaneously set as the timer latch and the timer.
When the timer 1 register, the timer 2 register, or the timer 3 regis-
ter is read, the count value of the timer can be read.
●Timer 2 Write Control
Which write can be selected by the timer 2 write control bit (bit 2)
of the timer 123 mode register (address 002916), writing data to
both the latch and the timer at the same time or writing data only
to the latch. When the operation “writing data only to the latch” is
selected, the value is set to the timer 2 latch by writing data to the
timer 2 register and the timer 2 is updated at next underflow. After
reset, the operation “writing data to both the latch and the timer at
the same time” is selected, and the value is set to both the timer 2
latch and the timer 2 at the same time by writing data to the timer
2 register.
If the value is written in latch only, a value is simultaneously set to
the timer 2 and the timer 2 latch when the writing in the high-
order register and the underflow of timer 2 are performed at the
same timing.
●Timer 2 Output Control
When the timer 2 (TOUT) output is enabled by the TOUT/
φ
output
enable bit and the TOUT/
φ
output selection bit, an inversion signal
from the TOUT pin is output each time timer 2 underflows.
In this case, set the P43/
φ
/TOUT pin to output mode (set “1” to bit 3
of port P4 direction register).
■Note on Timer 1 to Timer 3
When the count source of timers 1 to 3 is changed, the timer
counting value may become arbitrary value because a thin pulse
is generated in count input of timer. If timer 1 output is selected as
the count source of timer 2 or timer 3, when timer 1 is written, the
counting value of timer 2 or timer 3 may become undefined value
because a thin pulse is generated in timer 1 output.
Therefore, set the value of timer in the order of timer 1, timer 2
and timer 3 after the count source selection of timer 1 to 3.
Fig. 27 Structure of timer 123 mode register
T
O
U
T
o
u
t
p
u
t
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
0
:
S
t
a
r
t
a
t
“
H
”
o
u
t
p
u
t
1
:
S
t
a
r
t
a
t
“
L
”
o
u
t
p
u
t
T
O
U
T
/φ
o
u
t
p
u
t
e
n
a
b
l
e
l
b
i
t
0
:
T
O
U
T
/φ
o
u
t
p
u
t
d
i
s
a
b
l
e
d
1
:
T
O
U
T
/φ
o
u
t
p
u
t
e
n
a
b
l
e
d
T
i
m
e
r
2
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
0
:
W
r
i
t
e
d
a
t
a
i
n
l
a
t
c
h
a
n
d
c
o
u
n
t
e
r
1
:
W
r
i
t
e
d
a
t
a
i
n
l
a
t
c
h
o
n
l
y
T
i
m
e
r
2
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
T
i
m
e
r
1
o
u
t
p
u
t
s
i
g
n
a
l
1
:
f
(
X
I
N
)
/
1
6
(
o
r
f
(
X
C
I
N
)
/
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
T
i
m
e
r
3
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
T
i
m
e
r
1
o
u
t
p
u
t
s
i
g
n
a
l
1
:
f
(
X
I
N
)
/
1
6
(
o
r
f
(
X
C
I
N
)
/
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
T
i
m
e
r
1
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
f
(
X
I
N
)
/
1
6
(
o
r
f
(
X
C
I
N
)
/
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
1
:
f
(
X
C
I
N
)
N
o
t
u
s
e
d
(
“
0
”
a
t
r
e
a
d
i
n
g
)
Ti
me r 123 mo
d
e reg
i
ster
(T123M :address 0029
16
)
N
ote:
S
ystem c
l
oc
k
φ
i
s
f(X
CIN
)
/2
i
n t
h
e
l
ow-spee
d
mo
d
e.
b
7
b
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
32
SERIAL I/O
Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode is selected by setting the se-
rial I/O1 mode selection bit of the serial I/O1 control register to “1”.
For clock synchronous serial I/O mode, the transmitter and the re-
ceiver must use the same clock as an operation clock.
When an internal clock is selected as an operation clock, transmit
or receive is started by a write signal to the transmit buffer regis-
ter.
When an external clock is selected as an operation clock, serial I/
O1 becomes the state where transmit or receive can be performed
by a write signal to the transmit buffer register. Transmit and re-
ceive are started by input of an external clock.
Fig. 28 Block diagram of clock synchronous serial I/O1
Fig. 29 Operation of clock synchronous serial I/O1 function
P
46/
S
C
L
K
1
P
47/
S
R
D
Y
1
P
44/
R
X
D
P
45/
T
X
D
X
I
N1
/
4
1/4
F
/
F
Serial I/O1 status register
Serial I/O1 control register
R
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
A
d
d
r
e
s
s
0
0
1
81
6
Receive shift register
R
ece
i
ve
b
u
ff
er
f
u
ll
fl
ag
(RBF)
R
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Receive clock control circuit
S
h
i
f
t
c
l
o
c
k
S
er
i
a
l
I
/
O
1 sync
h
ronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rat e generato r
A
d
d
r
e
s
s
0
0
1
C
1
6
BRG
count source se
l
ect
i
on
bi
t
F
a
l
l
i
n
g
-
e
d
g
e
d
e
t
e
c
t
o
r
D
ata
b
us
Add
ress 001816
S
h
i
f
t
c
l
o
c
k
T
ransm
i
t s
hif
t reg
i
ster s
hif
t com p
l
et
i
on
fl
ag
(TSC)
T
ransm
i
t
b
u
ff
er empty
fl
ag
(TBE)
T
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
T
ransm
i
t
i
nterrupt source se
l
ect
i
on
bi
t
Add
ress 001916
D
ata
b
us
A
d
d
r
e
s
s
0
0
1
A
1
6
T
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
T
r
a
n
s
m
i
t
s
h
i
f
t
r
e
g
i
s
t
e
r
T
r
a
n
s
m
i
t
cl
o
c
k
c
o
n
t
r
o
l
c
i
r
c
u
i
t
R
ece
i
ve ena
bl
e s
i
gna
l
S
RDY1
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
RBF
= “1”
TSC = “1”
TBE
= “0”
TBE
= “1”
TSC = “0”
T
r
a
n
s
m
i
t
a
n
d
r
e
c
e
i
v
e
s
h
i
f
t
c
l
o
c
k
(
1
/
2
t
o
1
/
2
0
4
8
o
f
t
h
e
i
n
t
e
r
n
a
l
c
l
o
c
k
,
o
r
a
n
e
x
t
e
r
n
a
l
c
l
o
c
k
)
S
e
r
i
a
l
o
u
t
p
u
t
T
X
D
S
e
r
i
a
l
i
n
p
u
t
R
X
D
W
r
i
t
e
s
i
g
n
a
l
t
o
r
e
c
e
i
v
e
/
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
0
0
1
8
1
6
)
O
v
e
r
r
u
n
e
r
r
o
r
(
O
E
)
d
e
t
e
c
t
i
o
n
N
o
t
e
s1
:
A
f
t
e
r
d
a
t
a
t
r
a
n
s
f
e
r
r
i
n
g
,
t
h
e
T
x
D
p
i
n
k
e
e
p
s
D
7
o
u
t
p
u
t
v
a
l
u
e
.
2
:
I
f
d
a
t
a
i
s
w
r
i
t
t
e
n
t
o
t
h
e
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
w
h
e
n
T
S
C
=
“
0
”
,
t
h
e
t
r
a
n
s
m
i
t
c
l
o
c
k
i
s
g
e
n
e
r
a
t
e
d
c
o
n
t
i
n
u
o
u
s
l
y
a
n
d
s
e
r
i
a
l
d
a
t
a
c
a
n
b
e
o
u
t
p
u
t
c
o
n
t
i
n
u
o
u
s
l
y
f
r
o
m
t
h
e
T
X
D
p
i
n
.
3
:
S
e
l
e
c
t
t
h
e
s
e
r
i
a
l
I
/
O
1
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
f
a
c
t
o
r
b
e
t
w
e
e
n
w
h
e
n
t
h
e
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
h
a
s
e
m
p
t
i
e
d
(
T
B
E
=
“
1
”
)
o
r
a
f
t
e
r
t
h
e
t
r
a
n
s
m
i
t
s
h
i
f
t
o
p
e
r
a
t
i
o
n
h
a
s
e
n
d
e
d
(
T
S
C
=
“
1
”
)
,
b
y
s
e
t
t
i
n
g
t
h
e
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
T
I
C
)
o
f
t
h
e
s
e
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
.
4
:
T
h
e
s
e
r
i
a
l
I
/
O
1
r
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
o
c
c
u
r
s
w
h
e
n
t
h
e
r
e
c
e
i
v
e
b
u
f
f
e
r
f
u
l
l
f
l
a
g
(
R
B
F
)
b
e
c
o
m
e
s
“
1
”
.
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
(
N
o
t
e
1
)
(N
ote
3)
(N
ote
2)
(N
ote
3)
(N
ote 4
)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
33
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) is selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control register
to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
ter, but the two buffers have the same address (001816) in
memory. Since the shift register cannot be written to or read from
directly, transmit data is written to the transmit buffer, and receive
data is read from the receive buffer.
The transmit buffer can also hold the next data to be transmitted
during transmitting, and the receive buffer register can hold re-
ceived one-byte data while the next one-byte data is being re-
ceived.
Fig. 30 Block diagram of UART serial I/O1
Fig. 31 Operation of UART serial I/O1 function
X
IN
1/4
O
E
P
E
F
E
1/16
1
/
1
6
D
ata
b
us
R
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
A
d
d
r
e
s
s
0
0
1
81
6
R
ece
i
ve s
hif
t reg
i
ster
R
e
c
e
i
v
e
b
u
f
f
e
r
f
u
l
l
f
l
a
g
(
R
B
F
)
R
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
B
a
u
d
r
a
t
e
g
e
n
e
r
a
t
o
r
F
r
e
q
u
e
n
c
y
d
i
v
i
s
i
o
n
r
a
t
i
o
1
/
(
n
+
1
)
Add
ress 001
C
16
S
T
/
S
P
/
P
A
g
e
n
e
r
a
t
o
r
Tr ans m it bu ff er r egister
D
a
t
a
b
u
s
T
r
a
n
s
m
i
t
s
h
i
f
t
r
e
g
i
s
t
e
r
Add
ress 001816
T
r
a
n
s
m
i
t
s
h
i
f
t
r
e
g
i
s
t
e
r
s
h
i
f
t
c
o
m
p
l
e
t
i
o
n
f
l
a
g
(
T
S
C
)
T
r
a
n
s
m
i
t
b
u
f
f
e
r
e
m
p
t
y
f
l
a
g
(
T
B
E
)
T
ransm
i
t
i
nterrupt request
Add
ress 001916
S
T
d
e
t
e
c
t
o
r
SP
d
etector
U
A
R
T
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
Add
ress 001
B
16
Ch
aracter
l
engt
h
se
l
ect
i
on
bi
t
A
d
d
r
e
s
s
0
0
1
A
1
6
B
R
G
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
T
ransm
i
t
i
nterrupt source se
l
ect
i
on
bit
S
e
r
i
a
l
I
/
O
1
s
y
n
c
h
r
o
n
i
z
a
t
i
o
n
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
Cl
oc
k
contro
l
c
i
rcu
it
C
h
a
r
a
c
t
e
r
l
e
n
g
t
h
s
e
l
e
c
t
i
o
n
b
i
t
7
b
i
t
s
8
b
i
t
s
S
e
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
P
46/
S
CLK1
S
e
r
i
a
l
I
/
O
1
s
t
a
t
u
s
r
e
g
i
s
t
e
r
P
44/
R
X
D
P
45/
T
X
D
T
S
C
=
“
0
”
T
B
E
=
“
1
”
R
B
F
=
“
0
”
T
B
E
=
“
0
”
TBE
= “0”
R
B
F
=
“
1
”
RBF
= “1”
S
T
D
0
D
1
S
P
D
0
D
1
ST
S
P
T
B
E
=
“
1
”TSC = “1”
✽
ST
D
0
D
1
SP
D
0
D
1
S
T
S
P
T
ransm
i
t
b
u
ff
er reg
i
ster wr
i
te s
i
gna
l
✽
Generated at 2nd bit in 2-stop-bit mode
1 star t
bi
t
7 or 8 data bi ts
1 or 0 pari ty bi t
1 or 2 stop bit (s)
1
:
E
r
r
o
r
f
l
a
g
d
e
t
e
c
t
i
o
n
o
c
c
u
r
s
a
t
t
h
e
s
a
m
e
t
i
m
e
t
h
a
t
t
h
e
R
B
F
f
l
a
g
b
e
c
o
m
e
s
“
1
”
(
a
t
1
s
t
s
t
o
p
b
i
t
f
o
r
r
e
c
e
p
t
i
o
n
)
.
2
:
T
h
e
s
e
r
i
a
l
I
/
O
1
r
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
o
c
c
u
r
s
w
h
e
n
t
h
e
r
e
c
e
i
v
e
b
u
f
f
e
r
f
u
l
l
f
l
a
g
(
R
B
F
)
b
e
c
o
m
e
s
“
1
”
.
3
:
S
e
l
e
c
t
t
h
e
s
e
r
i
a
l
I
/
O
1
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
o
c
c
u
r
r
e
n
c
e
f
a
c
t
o
r
b
e
t
w
e
e
n
w
h
e
n
t
h
e
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
h
a
s
e
m
p
t
i
e
d
(
T
B
E
=
“
1
”
)
o
r
a
f
t
e
r
t
h
e
t
r
a
n
s
m
i
t
s
h
i
f
t
o
p
e
r
a
t
i
o
n
h
a
s
e
n
d
e
d
(
T
S
C
=
“
1
”
)
,
b
y
s
e
t
t
i
n
g
t
h
e
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
T
I
C
)
o
f
t
h
e
s
e
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
.
N
o
t
e
s
S
e
r
i
a
l
o
u
t
p
u
t
T
x
D
S
e
r
i
a
l
i
n
p
u
t
R
x
D
R
ece
i
ve
b
u
ff
er reg
i
ster rea
d
s
i
gna
l
T
ransm
i
t or rece
i
ve c
l
oc
k
(N
otes 1,
2)
(N
otes 1,
2)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
34
[Transmit Buffer/Receive Buffer Register (TB/
RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is write-
only and the receive buffer register is read-only. If a character bit
length is 7 bits, the MSB of data stored in the receive buffer regis-
ter is “0”.
[Serial I/O1 Status Register (SIO1STS)]
001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is set to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set to “1”. A write signal to
the serial I/O1 status register sets all the error flags (OE, PE, FE,
and SE) (bit 3 to bit 6, respectively) to “0”. Writing “0” to the serial
I/O1 enable bit (SIOE) also sets all the status flags to “0”, includ-
ing the error flags.
All bits of the serial I/O1 status register are set to “0” at reset, but
if the transmit enable bit of the serial I/O1 control register has
been set to “1”, the transmit shift register shift completion flag and
the transmit buffer empty flag become “1”.
[Serial I/O1 Control Register (SIO1CON)]
001A16
The serial I/O1 control register contains eight control bits for the
serial I/O1 function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of the bits which set the data
format of an data transmit and receive, and the bit which sets the
output structure of the P45/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator is the 8-bit counter equipped with a
reload register. Set the division value of the BRG count source to
the baud rate generator.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate
generator.
■Notes on serial I/O
When setting the transmit enable bit to “1”, the serial I/O1 transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronous with the transmission en-
abled, take the following sequence.
➀Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
➁Set the transmit enable bit to “1”.
➂Set the serial I/O1 transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➃Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
35
Fig. 32 Structure of serial I/O1 control registers
BRG
count source se
l
ect
i
on
bi
t
(CSS)
0: f(X
IN
)
1: f(X
IN
)/4
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial I/O is
selected.
External clock input divided by 16 when UART is selected.
S
RDY1
outp ut ena bl e bi t (SR D Y)
0: P4
7
pin operate s as or dina ry I/O pin
1: P4
7
pin ope r ates as S
RDY1
out pu t pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmi t enab l e bi t (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P4
4
–P4
7
operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P4
4
–P4
7
operate as serial I/O pins)
S
er
i
a
l
I
/
O
1 contr o
l
reg
i
ster
(SIO1CON : address 001A
16
)
b7 b0
T
r
a
n
s
m
i
t
b
u
f
f
e
r
e
m
p
t
y
f
l
a
g
(
T
B
E
)
0
:
B
u
f
f
e
r
f
u
l
l
1
:
B
u
f
f
e
r
e
m
p
t
y
R
e
c
e
i
v
e
b
u
f
f
e
r
f
u
l
l
f
l
a
g
(
R
B
F
)
0
:
B
u
f
f
e
r
e
m
p
t
y
1
:
B
u
f
f
e
r
f
u
l
l
T
r
a
n
s
m
i
t
s
h
i
f
t
r
e
g
i
s
t
e
r
s
h
i
f
t
c
o
m
p
l
e
t
i
o
n
f
l
a
g
(
T
S
C
)
0
:
T
r
a
n
s
m
i
t
s
h
i
f
t
i
n
p
r
o
g
r
e
s
s
1
:
T
r
a
n
s
m
i
t
s
h
i
f
t
c
o
m
p
l
e
t
e
d
O
v
e
r
r
u
n
e
r
r
o
r
f
l
a
g
(
O
E
)
0
:
N
o
e
r
r
o
r
1
:
O
v
e
r
r
u
n
e
r
r
o
r
P
a
r
i
t
y
e
r
r
o
r
f
l
a
g
(
P
E
)
0
:
N
o
e
r
r
o
r
1
:
P
a
r
i
t
y
e
r
r
o
r
F
r
a
m
i
n
g
e
r
r
o
r
f
l
a
g
(
F
E
)
0
:
N
o
e
r
r
o
r
1
:
F
r
a
m
i
n
g
e
r
r
o
r
S
u
m
m
i
n
g
e
r
r
o
r
f
l
a
g
(
S
E
)
0
:
(
O
E
)
U
(
P
E
)
U
(
F
E
)
=
0
1
:
(
O
E
)
U
(
P
E
)
U
(
F
E
)
=
1
N
o
t
u
s
e
d
(
“
1
”
a
t
r
e
a
d
i
n
g
)
S
e
r
i
a
l
I
/
O
1
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
S
I
O
1
S
T
S
:
a
d
d
r
e
s
s
0
0
1
9
1
6
)
b7 b0
U
A
R
T
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
U
A
R
T
C
O
N
:
a
d
d
r
e
s
s
0
0
1
B
1
6
)
Ch
aracter
l
engt
h
se
l
ect
i
on
bi
t
(CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity ch ec king enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P4
5
/T
X
D P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (“1” at reading)
b7 b0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
36
Serial I/O2
Serial I/O2 can be used only for clock synchronous serial I/O.
For serial I/O2, the transmitter and the receiver must use the
same clock as a synchronous clock. When an internal clock is se-
lected as a synchronous clock, the serial I/O2 is initialized and,
transmit and receive is started by a write signal to the serial I/O2
register.
When an external clock is selected as an synchronous clock, the
serial I/O2 counter is initialized by a write signal to the serial I/O2
register, serial I/O2 becomes the state where transmission or re-
ception can be performed. Write to the serial I/O2 register while
SCLK21 is “H” state when an external clock is selected as an syn-
chronous clock.
Either P62/SCLK21 or P63/SCLK22 pin can be selected as an output
pin of the synchronous clock. In this case, the pin that is not se-
lected as an output pin of the synchronous clock functions as a I/
O port.
[Serial I/O2 Control Register (SIO2CON)] 001D16
The serial I/O2 control register contains eight control bits for the
serial I/O2 functions. After setting to this register, write data to the
serial I/O2 register and start transmit and receive.
Fig. 33 Structure of serial I/O2 control register
Fig. 34 Block diagram of serial I/O2 function
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
I
O
2
C
O
N
:
a
d
d
r
e
s
s
0
0
1
D
1
6
)
b7
Internal synchronous clock select bits
0 0 0: f(X
IN
)/8
0 0 1: f(X
IN
)/16
0 1 0: f(X
IN
)/32
0 1 1: f(X
IN
)/64
1 0 0:
1 0 1:
1 1 0: f(X
IN
)/128
1 1 1: f(X
IN
)/256
Serial I/O2 port selection bit
0: I/O port
1: S
OUT2
,S
CLK21
/S
CLK22
signal output
P6
1
/S
OUT2
P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel op en-drain output
(in output mode)
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Inte rnal clock
Synchronous clock output pin selection bit
0: S
CLK21
1: S
CLK22
b
0
b2 b1 b0
D
o
n
o
t
s
e
l
e
c
t
XI
N
“
1
”
“
0
”
“
0
”
“
1
”
“
0
”
“
1
”
SC
L
K
2
(
N
o
t
e
)
1
/
8
1
/
1
6
1
/
3
2
1
/
6
4
1
/
1
2
8
1
/
2
5
6
D
a
t
a
b
u
s
S
e
r
i
a
l
I
/
O
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
S
e
r
i
a
l
I
/
O
2
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
2
c
o
u
n
t
e
r
(
3
)
S
e
r
i
a
l
I
/
O
2
r
e
g
i
s
t
e
r
(
8
)
S
y
n
c
h
r
o
n
o
u
s
c
i
r
c
u
i
t
S
e
r
i
a
l
I
/
O
2
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
E
x
t
e
r
n
a
l
c
l
o
c
k
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
b
i
t
s
D
i
v
i
d
e
r
P
63
l
a
t
c
h
P
63/
SC
L
K
2
2
P
62/
SC
L
K
2
1
P
61/
SO
U
T
2
P
60/
SI
N
2
P
62
l
a
t
c
h
P
61
l
a
t
c
h
(
N
o
t
e
)
N
o
t
e
:
I
t
i
s
s
e
l
e
c
t
e
d
b
y
t
h
e
s
e
r
i
a
l
I
/
O
2
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
,
t
h
e
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
o
u
t
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
,
a
n
d
t
h
e
s
e
r
i
a
l
I
/
O
2
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
37
Fig. 35 Timing of serial I/O2 function
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
S
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
(
N
o
t
e
1
)
S
e
r
i
a
l
I
/
O
2
o
u
t
p
u
t
S
O
U
T
2
S
e
r
i
a
l
I
/
O
2
i
n
p
u
t
S
I
N
2
Serial I/O2 register
write signal
(
N
o
t
e
s
2
,
3
)
S
e
r
i
a
l
I
/
O
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
=
“
1
”
1
:
W
h
e
n
t
h
e
i
n
t
e
r
n
a
l
c
l
o
c
k
i
s
s
e
l
e
c
t
e
d
a
s
t
h
e
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
,
t
h
e
d
i
v
i
d
e
r
a
t
i
o
c
a
n
b
e
s
e
l
e
c
t
e
d
b
y
s
e
t
t
i
n
g
b
i
t
s
0
t
o
2
o
f
t
h
e
s
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
.
2
:
W
h
e
n
t
h
e
i
n
t
e
r
n
a
l
c
l
o
c
k
i
s
s
e
l
e
c
t
e
d
a
s
t
h
e
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
,
t
h
e
S
O
U
T
2
p
i
n
g
o
e
s
t
o
h
i
g
h
i
m
p
e
d
a
n
c
e
a
f
t
e
r
t
r
a
n
s
f
e
r
c
o
m
p
l
e
t
i
o
n
.
3
:
W
h
e
n
t
h
e
e
x
t
e
r
n
a
l
c
l
o
c
k
i
s
s
e
l
e
c
t
e
d
a
s
t
h
e
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
,
t
h
e
S
O
U
T
2
p
i
n
k
e
e
p
s
D
7
o
u
t
p
u
t
l
e
v
e
l
a
f
t
e
r
t
r
a
n
s
f
e
r
c
o
m
p
l
e
t
i
o
n
. H
o
w
e
v
e
r
,
i
f
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
i
n
p
u
t
a
r
e
c
a
r
r
i
e
d
o
n
,
t
h
e
t
r
a
n
s
m
i
t
d
a
t
a
w
i
l
l
b
e
o
u
t
p
u
t
c
o
n
t
i
n
u
o
u
s
l
y
f
r
o
m
t
h
e
S
O
U
T
2
p
i
n
b
e
c
a
u
s
e
s
h
i
f
t
s
o
f
s
e
r
i
a
l
I
/
O
2
s
h
i
f
t
r
e
g
i
s
t
e
r
i
s
c
o
n
t
i
n
u
e
d
a
s
l
o
n
g
a
s
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
a
r
e
i
n
p
u
t
.
N
o
t
e
s
●Serial I/O2 Operating
The serial I/O2 counter is initialized to “7” by writing to the serial
I/O2 register.
After writing, whenever a synchronous clock changes from “H” to
“L”, data is output from the SOUT2 pin. Moreover, whenever a syn-
chronous clock changes from “L” to “H”, data is taken in from the
SIN2 pin, and 1 bit shift of the serial I/O2 register is carried out si-
multaneously.
When the internal clock is selected as a synchronous clock, it is
as follows if a synchronous clock is counted 8 times.
•Serial I/O2 counter = “0”
•Synchronous clock stops in “H” state
•Serial I/O2 interrupt request bit = “1”
The SOUT2 pin is in a high impedance state after transfer is com-
pleted.
When the external clock is selected as a synchronous clock, if a
synchronous clock is counted 8 times, the serial I/O2 interrupt re-
quest bit is set to “1”, and the SOUT2 pin holds the output level of
D7. However, if a synchronous clock continues being input, the
shift of the serial I/O2 register is continued and transmission data
continues being output from the SOUT2 pin.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
38
PULSE WIDTH MODULATION (PWM)
The 7560 group has a PWM function with an 8-bit resolution,
using f(XIN) or f(XIN)/2 as a count source.
Data Setting
The PWM output pins are shared with ports P50 and P51. Set the
PWM period by the PWM prescaler, and set the period during
which the output pulse is an “H” by the PWM register.
If PWM count source is f(XIN) and the value in the PWM prescaler
is n and the value in the PWM register is m (where n = 0 to 255
and m = 0 to 255) :
PWM period = 255 ✕ (n+1)/f(XIN)
= 31.875 ✕ (n+1) µs (when f(XIN) = 8 MHz)
Output pulse “H” period = PWM period ✕ m/255
= 0.125 ✕ (n+1) ✕ m µs
(when f(XIN) = 8 MHz)
PWM Operation
When either bit 1 (PWM0 function enable bit) or bit 2 (PWM1 func-
tion enable bit) of the PWM control register or both bits are
enabled, operation starts from initializing status, and pulses are
output starting at “H”. When one PWM output is enabled and that
the other PWM output is enabled, PWM output which is enabled to
output later starts pulse output from halfway of PWM period (see
Figure 39).
When the PWM register or PWM prescaler is updated during
PWM output, the pulses will change in the cycle after the one in
which the change was made.
Fig. 36 Timing of PWM cycle
Fig. 37 Block diagram of PWM function
31.875 ✕ m ✕ (n+1)
255 µs
T = [31.875 ✕ (n+1)] µs
PWM output
m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM cycle (when f(X
IN
) = 8 MHz)
D
a
t
a
b
u
s
C
ount sour c e
sel e ct i on bit
“
0
”
“
1
”
P
W
M
p
r
e
s
c
a
l
e
r
p
r
e
-
l
a
t
c
h
P
W
M
r
e
g
i
s
t
e
r
p
r
e
-
l
a
t
c
h
PWM
prescaler latch
P
W
M
r
e
g
i
s
t
e
r
l
a
t
c
h
T
rans
f
er contro
l
c
i
rcu
i
t
PWM
c
i
rcu
i
t
1
/
2
X
I
N
P
W
M
0
f
u
n
c
t
i
o
n
e
n
a
b
l
e
b
i
t
P
51
/
P
W
M
1
P
W
M
p
r
e
s
c
a
l
e
r
PWM
1
f
unct
i
on
enable bit
P
o
r
t
P
51
l
a
c
t
h
P
o
r
t
P
50
l
a
c
t
h
P
50 /
P
W
M
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
39
Fig. 39 PWM output timing when PWM register or PWM prescaler is changed
Fig. 38 Structure of PWM control register
b
7b
0P
W
M
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
W
M
C
O
N
:
a
d
d
r
e
s
s
0
0
2
B1
6)
C
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0:f
(
XI
N)
1:f
(
XI
N)
/
2
P
W
M0
f
u
n
c
t
i
o
n
e
n
a
b
l
e
b
i
t
0:P
W
M0
d
i
s
a
b
l
e
d
1:P
W
M0
e
n
a
b
l
e
d
P
W
M1
f
u
n
c
t
i
o
n
e
n
a
b
l
e
b
i
t
0:P
W
M1
d
i
s
a
b
l
e
d
1:P
W
M1
e
n
a
b
l
e
d
N
o
t
u
s
e
d
(
“
0
”
a
t
r
e
a
d
i
n
g
)
TT2
C
B
T
PWM register
write signal
PWM prescaler
write signal
(Changes from “A” to “B” during “H” period)
(Changes from “T” to “T2” during PWM period)
PWM
(internal)
AB
TC
T2
=
stop
PWM0 function
enable bit
PWM1 function
enable bit
PWM0 output Port
Port
PWM1 output
Port
stop
Port
When the contents of the PWM register or PWM prescaler have changed, the PWM
output will change from the next period after the change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
40
A-D CONVERTER
[A-D Conversion Low-Order Register (ADL)]
001416
[A-D Conversion High-Order Register (ADH)]
003516
The A-D conversion registers are read-only registers that store the
result of an A-D conversion . When reading this register during an
A-D conversion, the previous conversion result is read.
The high-order 8 bits of a conversion result is stored in the A-D
conversion high-order register (address 003516), and the low-or-
der 2 bits of the same result are stored in bit 7 and bit 6 of the A-D
conversion low-order register (address 001416).
Bit 0 of the A-D conversion low-order register is the conversion
mode selection bit. When this bit is set to “0”, that becomes the
10-bit A-D mode. When this bit is set to “1”, that becomes the 8-bit
A-D mode.
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 indi-
cates the completion of an A-D conversion. The value of this bit re-
mains at “0” during an A-D conversion, then it is set to “1” when
the A-D conversion is completed. Writing “0” to this bit starts the
A-D conversion.
Bit 4 is the VREF input switch bit which controls connection of the
resistor ladder and the reference voltage input pin (VREF). The
resistor ladder is always connected to VREF when bit 4 is set to
“1”. When bit 4 is set to “0”, the resistor ladder is cut off from VREF
except for A-D conversion performed. When bit 5, which is the AD
external trigger valid bit, is set to “1”, A-D conversion starts also by
a falling edge of an ADT input. When using an A-D external trigger,
set the P57/ADT pin to input mode (set “0” to bit 7 of port P5 direc-
tion register).
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AVSS and VREF by 256 (when 8-bit A-D mode) or 1024 (when 10-
bit A-D mode), and outputs the divided voltages.
Channel Selector
The channel selector selects one of the input ports P6
7
/AN
7
–P6
0
/AN
0
.
Comparator and Control Circuit
The comparator and control circuit compare an analog input volt-
age with the comparison voltage and store the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
converter interrupt request bit to “1”.
Note that because the comparator consists of a capacitor
coupling, set f(XIN) to 500 kHz or more during an A-D conversion.
Use the clock divided from the main clock f(XIN) as the system clock
φ.
Fig. 40 Structure of A-D converter-related registers
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
D
C
O
N
:
a
d
d
r
e
s
s
0
0
3
41
6)
AD
convers
i
on comp
l
et
i
on
bi
t
0 : Conversion in progress
1 : Conversion completed
A
na
l
og
i
nput p
i
n se
l
ect
i
on
bi
ts
b2b1b0
0 0 0 : P60/AN0
0 0 1 : P61/AN1
0 1 0 : P62/AN2
0 1 1 : P63/AN3
1 0 0 : P64/AN4
1 0 1 : P65/AN5
1 1 0 : P66/AN6
1 1 1 : P67/AN7
V
R
E
F
i
n
p
u
t
s
w
i
t
c
h
b
i
t
0
:
A
U
T
O
1
:
O
N
AD
externa
l
tr
i
gger va
lid
bi
t
0 : A -D extern al trigger invalid
1 : A-D external trigger valid
b
7
b
0
I
nterrupt source se
l
ect
i
on
bi
t
0 : Interrupt request at A-D
conversion completed
1 : Interrupt request at ADT
input falling
N
ot use
d
(
“0” at rea
di
ng
)
A
-
D
c
o
n
v
e
r
s
i
o
n
l
o
w
-
o
r
d
e
r
r
e
g
i
s
t
e
r
(
A
D
L
:
a
d
d
r
e
s
s
0
0
1
41
6)
C
onvers
i
on mo
d
e se
l
ect
i
on
bi
t
0 : 10-bit A-D mode
1 : 8-bit A-D mode
Not used (“0” at reading)
•For 10-bit A-D mode
A-D conversion result
•For 8-bit A-D mode
Not used (undefined at reading)
b
7
b
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
41
Fig. 42 A-D converter block diagram
Fig. 41 Read of A-D conversion register
•
1
0
-
b
i
t
r
e
a
d
i
n
g
(
R
e
a
d
a
d
d
r
e
s
s
0
0
3
51
6
,
t
h
e
n
0
0
1
41
6)
A
-
D
c
o
n
v
e
r
s
i
o
n
h
i
g
h
-
o
r
d
e
r
r
e
g
i
s
t
e
r
(
A
D
H
:
A
d
d
r
e
s
s
0
0
3
51
6)
A
-
D
c
o
n
v
e
r
s
i
o
n
l
o
w
-
o
r
d
e
r
r
e
g
i
s
t
e
r
(
A
D
L
:
A
d
d
r
e
s
s
0
0
1
41
6)b0
b
7b0
b
1
b7 b6 b
5b
4b
3b2
b
7b0
b
9b
8b
7
b6 b
5b
4
b
3b2
b
7b
0(high-order)
(
l
o
w
-
o
r
d
e
r
)
N
o
t
e
:
Bi
t
s
0
t
o
5
o
f
a
d
d
r
e
s
s
0
0
1
41
6
b
e
c
o
m
e
“
0
”
a
t
r
e
a
d
i
n
g
.
b1 b0
•8
-
b
i
t
r
e
a
d
i
n
g
(
R
e
a
d
o
n
l
y
a
d
d
r
e
s
s
0
0
3
51
6)
A
-
D
c
o
n
v
e
r
s
i
o
n
h
i
g
h
-
o
r
d
e
r
r
e
g
i
s
t
e
r
(
A
D
H
:
A
d
d
r
e
s
s
0
0
3
51
6)
C
o
n
v
e
r
s
i
o
n
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
1
0
-
b
i
t
A
-
D
m
o
d
e
1
:
8
-
b
i
t
A
-
D
m
o
d
e
C
o
m
p
a
r
a
t
o
r
A
-
D
contro
l
c
i
rcu
it
ADT
/
A
-
D
interrupt
request
A
V
S
S
V
R
E
F
P
6
0
/
S
I
N
2
/
A
N
0
D
ata
b
u
s
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
b
7
b
0
A
-
D
c
o
n
v
e
r
s
i
o
n
h
i
g
h
-
o
r
d
e
r
r
e
g
i
s
t
e
r
R
es
i
stor
l
a
dd
e
r
C
h
a
n
n
e
l
s
e
l
e
c
t
o
r
P
6
7
/
AN
7
P
6
6
/
AN
6
P
6
5
/
AN
5
P
6
4
/
AN
4
P
6
3
/
S
C
L
K
2
2
/
A
N
3
P
6
2
/
S
C
L
K2
1
/
A
N
2
P
6
1
/
S
O
U
T2
/
A
N
1
P
5
7
/
A
D
T
/
D
A
2
8
3
(
A
d
d
r
e
s
s
0
0
3
5
1
6
)
A
-
D
c
o
n
v
e
r
s
i
o
n
l
o
w
-
o
r
d
e
r
r
e
g
i
s
t
e
r
(
A
d
d
r
e
s
s
0
0
1
4
1
6
)
1
/
2 1
/
4
X
I
N
A
D
C
L
K
A
-
D
C
o
n
v
e
r
t
e
r
C
l
o
c
k
M
a
i
n
c
l
o
c
k
d
i
v
i
s
i
o
n
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
M
i
d
d
l
e
-
s
p
e
e
d
m
o
d
e
H
i
g
h-
s
p
e
e
d
m
o
d
eS
y
s
t
e
m
c
l
o
c
k
φ
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
42
D-A Converter
The 7560 group has a D-A converter with 8-bit resolution and 2
channels (DA1, DA2).
The D-A converter is started by setting the value in the D-A con-
version register. When the DA1 output enable bit or the DA2 output
enable bit is set to “1”, the result of D-A conversion is output from
the corresponding DA pin. When using the D-A converter, set the
P56/DA1 pin and the P57/DA2 pin to input mode (set “0” to bits 6,
7 of port P5 direction register) and the pull-up resistor should be in
the OFF state (set “0” to bit 3 of PULL register B) previously.
The output analog voltage V is determined by the value n (base
10) in the D-A conversion register as follows:
V=VREF ✕ n/256 (n=0 to 255)
Where VREF is the reference voltage.
At reset, the D-A conversion registers are set to “0016”, the DA1
output enable bit and the DA2 output enable bit are set to “0”, and
the P56/DA1 pin and the P57/DA2 pin goes to high impedance
state. The DA converter is not buffered, so connect an external
buffer when driving a low-impedance load.
■ Note on applied voltage to VREF pin
When these pins are used as D-A conversion output pins, the Vcc
level is recommended for the applied voltage to VREF pin.
When the voltage below Vcc level is applied, the D-A conversion
accuracy may be worse.
Fig. 43 Structure of D-A control register
Fig. 44 Block diagram of D-A converter
D
A
1
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
0
:
D
i
s
a
b
l
e
d
1
:
E
n
a
b
l
e
d
D
A
2
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
0
:
D
i
s
a
b
l
e
d
1
:
E
n
a
b
l
e
d
N
o
t
u
s
e
d
(
“
0
”
a
t
r
e
a
d
i
n
g
)
(
W
r
i
t
e
“
0
”
t
o
t
h
e
s
e
b
i
t
s
a
t
w
r
i
t
i
n
g
.
)
b
7b
0D
-
A
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
D
A
C
O
N
:
a
d
d
r
e
s
s
0
0
3
6
1
6
)
000000
D
a
t
a
b
u
s
P5
6
/DA
1
D-A1 conversion register (8)
R
-
2
R
r
e
s
i
s
t
o
r
l
a
d
d
e
r
DA
1
output enable bit
(DA1: address 0032
16
)
P5
7
/DA
2
D-A2 conversion register (8)
R
-
2
R
r
e
s
i
s
t
o
r
l
a
d
d
e
r
DA
2
output enable bit
(DA2: address 0033
16
)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
43
Fig. 45 Equivalent connection circuit of D-A converter
A
V
S
S
V
R
E
F
“
0
”
“
1
”
MSB
“0”“
1
”
R
2
R
R
2R
R
2R
R
2
R
R
2
R
R
2R
R
2
R2R
LSB
2
R
DA
i
D-Ai conversion register
D
A
i
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
44
LCD DRIVE CONTROL CIRCUIT
The 7560 group has the Liquid Crystal Display (LCD) drive control
circuit consisting of the following.
•LCD display RAM
•Segment output enable register
•LCD mode register
•Voltage multiplier
•Selector
•Timing controller
•Common driver
•Segment driver
•Bias control circuit
A maximum of 40 segment output pins and 4 common output pins
can be used.
Up to 160 pixels can be controlled for LCD display. When the LCD
Fig. 46 Structure of segment output enable register and LCD mode register
enable bit is set to “1” (LCD ON) after data is set in the LCD mode
register, the segment output enable register and the LCD display
RAM, the LCD drive control circuit starts reading the display data
automatically, performs the bias control and the duty ratio control,
and displays the data on the LCD panel.
Table 11 Maximum number of display pixels at each duty ratio
Duty ratio Maximum number of display pixel
80 dots
or 8 segment LCD 10 digits
120 dots
or 8 segment LCD 15 digits
160 dots
or 8 segment LCD 20 digits
2
3
4
S
egm ent ou tput ena
bl
e
bi
t 0
0 : Output ports P30–P35
1 : Segment output SEG18–SEG23
Segm ent outp ut ena bl e bi t 1
0 : Output ports P36, P37
1 : Segment output SEG24,SEG25
Segm ent outp ut ena bl e bi t 2
0 : I/O ports P00–P05
1 : Segment output SEG26–SEG31
Segm ent outp ut ena bl e bi t 3
0 : I/O ports P06,P07
1 : Segment output SEG32,SEG33
Segm ent outp ut ena bl e bi t 4
0 : I/O port P10
1 : Segment output SEG34
Segm ent outp ut ena bl e bi t 5
0 : I/O ports P11–P15
1 : Segment output SEG35–SEG39
LCD outp ut ena bl e bi t
0 : Disabled
1 : Enabled
Not used (“0” at reading)
(Write “0” t o this bit at writing.)
S
egm ent ou tput ena
bl
e reg
i
ster
(SEG : address 003816)
b
7
b
0
LCD
mo
d
e reg
i
ster
(L M : address 0 039 16)
D
uty rat
i
o se
l
ect
i
on
bi
ts
b1b0
0 0 : Not used
0 1 : 2 duty (use COM0, COM1)
1 0 : 3 duty (use COM0–COM2)
1 1 : 4 duty (use COM0–COM3)
Bi as contro l bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Voltage multiplier control bit
0 : Voltag e multiplier dis able
1 : Voltag e multiplier enable
LCD circuit divider division ratio selection bits
b6b5
0 0 : Clock input
0 1 : 2 division of Clock input
1 0 : 4 division of Clock input
1 1 : 8 division of Clock input
LCDCK c ou nt s ource selectio n b it (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (f(XCIN)/8192 in low-s peed mo de)
N
ote :
LCDCK
i
s a c
l
oc
k
f
or a
LCD
t
i
m
i
ng con tro
ll
er.
b
7
b
0
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
45
Fig. 47 Block diagram of LCD controller/driver
D
a
t
a
b
u
s
T
i
m
i
n
g
c
o
n
t
r
o
l
l
e
r
L
C
D
d
i
v
i
d
e
rf
(
XI
N)
/
8
1
9
2
(
f
(
XC
I
N)
/
8
1
9
2
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
f
(
XC
I
N)
/
3
2
C
O
M0C
O
M1C
O
M2C
O
M3
VS
SVL
1VL
2VL
3S
E
G3
S
E
G2
S
E
G1S
E
G0
A
d
d
r
e
s
s
0
0
4
01
6A
d
d
r
e
s
s
0
0
4
11
6
“
1
”
“
0
”
L
C
D
C
K
L
C
D
C
K
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
L
C
D
c
i
r
c
u
i
t
d
i
v
i
d
e
r
d
i
v
i
s
i
o
n
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
s
B
i
a
s
c
o
n
t
r
o
l
b
i
t
L
C
D
e
n
a
b
l
e
b
i
t
D
u
t
y
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
s
22
S
e
l
e
c
t
o
rS
e
l
e
c
t
o
rS
e
l
e
c
t
o
rS
e
l
e
c
t
o
rS
e
l
e
c
t
o
rS
e
l
e
c
t
o
r
L
C
D
d
i
s
p
l
a
y
R
A
M
A
d
d
r
e
s
s
0
0
5
31
6
P
14/
S
E
G3
8
P
30/
S
E
G1
8P
15/
S
E
G3
9
L
e
v
e
l
s
h
i
f
tL
e
v
e
l
s
h
i
f
tL
e
v
e
l
s
h
i
f
tL
e
v
e
l
s
h
i
f
tL
e
v
e
l
s
h
i
f
tL
e
v
e
l
s
h
i
f
t
C
o
m
m
o
n
d
r
i
v
e
rC
o
m
m
o
n
d
r
i
v
e
rC
o
m
m
o
n
d
r
i
v
e
rC
o
m
m
o
n
d
r
i
v
e
r
C1C2
V
o
l
t
a
g
e
m
u
l
t
i
p
l
i
e
r
c
o
n
t
r
o
l
b
i
t
L
e
v
e
l
S
h
i
f
tL
e
v
e
l
S
h
i
f
tL
e
v
e
l
S
h
i
f
tL
e
v
e
l
S
h
i
f
t
S
e
g
m
e
n
t
d
r
i
v
e
rS
e
g
m
e
n
t
d
r
i
v
e
rS
e
g
m
e
n
t
d
r
i
v
e
rS
e
g
m
e
n
t
d
r
i
v
e
rS
e
g
m
e
n
t
d
r
i
v
e
rS
e
g
m
e
n
t
d
r
i
v
e
r
B
i
a
s
c
o
n
t
r
o
l
L
C
D
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
VC
C
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
46
Voltage Multiplier (3 Times)
The voltage multiplier performs threefold boosting. This circuit in-
puts a reference voltage for boosting from LCD power input pin
VL1.
Set each bit of the segment output enable register and the LCD
mode register in the following order for operating the voltage mul-
tiplier.
1. Set the segment output enable bits (bits 0 to 5) of the seg-
ment output enable register to “0” or “1”.
2. Set the duty ratio selection bits (bits 0 and 1), the bias con-
trol bit (bit 2), the LCD circuit divider division ratio selection
bits (bits 5 and 6), and the LCDCK count source selection
bit (bit 7) of the LCD mode register to “0” or “1”.
3. Set the LCD output enable bit (bit 6) of the segment output
enable register to “1”. Apply the limit voltage or less to the
VL1 pin.
4. Set the voltage multiplier control bit (bit 4) of the LCD mode
register to “1”. However, be sure to select 1/3 bias for bias
control.
When voltage is input to the VL1 pin during operating the voltage
multiplier, voltage that is twice as large as VL1 occurs at the VL2
pin, and voltage that is three times as large as VL1 occurs at the
VL3 pin.
■Notes on Voltage Multiplier
When using the voltage multiplier, apply the limit voltage or less to
the VL1 pin, then set the voltage multiplier control bit to “1” (en-
abled).
When not using the voltage multiplier, set the LCD output enable
bit to “1”, then apply proper voltage to the LCD power input pins
(VL1–VL3).
When the LCD output enable bit is set to “0” (disabled), the VCC
voltage is applied to the VL3 pin inside of this microcomputer.
Fig. 48 Example of circuit at each bias
Table 12 Bias control and applied voltage to VL1–VL3
Bias value
1/3 bias
1/2 bias
Voltage value
VL3=VLCD
VL2=2/3 VLCD
VL1=1/3 VLCD
VL3=VLCD
VL2=VL1=1/2 VLCD
Note : VLCD is the maximum value of supplied voltage for the
LCD panel.
Bias Control and Applied Voltage to LCD
Power Input Pins
To the LCD power input pins (VL1–VL3), apply the voltage shown
in Table 12 according to the bias value.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
V
L3
V
L
2
C
2
C
1
V
L
1
1
/
3
b
i
a
s
w
h
e
n
u
s
i
n
g
t
h
e
v
o
l
t
a
g
e
m
u
l
t
i
p
l
i
e
r
V
L3
V
L2
C
2
C
1
V
L1
1
/
3
b
i
a
s
w
h
e
n
n
o
t
u
s
i
n
g
t
h
e
v
o
l
t
a
g
e
m
u
l
t
i
p
l
i
e
r
O
p
e
n
O
p
e
n
R
2
R
1
R
3
R
1=
R
2=
R
3
C
o
n
t
r
a
s
t
c
o
n
t
r
o
l
V
L
3
V
L
2
C
2
C
1
V
L
1
1/2
bi
as
O
p
e
n
O
p
e
n
R
4
R
5
R
4
=
R
5
C
o
n
t
r
a
s
t
c
o
n
t
r
o
l
P
X
x
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
47
(frequency of count source for LCDCK)
(divider division ratio for LCD)
f(LCDCK)=
f(LCDCK)
duty ratio
Frame frequency=
Fig. 49 LCD display RAM map
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by
duty ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
After reset, the VCC (VL3) voltage is output from the common pins.
LCD Display RAM
Addresses 004016 to 005316 are the designated RAM for the LCD
display. When “1” are written to these addresses, the correspond-
ing segments of the LCD display panel are turned on.
LCD Drive Timing
The frequency of internal signal LCDCK decided LCD drive timing
and the frame frequency can be determined with the following
equation:
Table 13 Duty ratio control and common pins used
Duty
ratio
2
3
4
Common pins used
Notes 1: COM2 and COM3 are open.
2: COM3 is open.
Bit 1
0
1
1
Bit 0
1
0
1
COM0, COM1 (Note 1)
COM0–COM2 (Note 2)
COM0–COM3
Duty ratio selection bits
Segment Signal Output Pins
Segment signal output pins are classified into the segment-only
pins (SEG0–SEG17), the segment or output port pins (SEG18–
SEG25), and the segment or I/O port pins (SEG26–SEG39).
Segment signals are output according to the bit data of the LCD
RAM corresponding to the duty ratio. After reset, a VCC (=VL3)
voltage is output to the segment-only pins and the segment/out-
put port pins are the high impedance condition and pulled up to
VCC (=VL3) voltage.
Also, the segment/I/O port pins(SEG26–SEG39) are set to input
mode as I/O ports, and VCC (=VL3) is applied to them by pull-up
resistor.
0
0
4
01
6
0
0
4
11
6
0
0
4
21
6
0
0
4
31
6
0
0
4
41
6
0
0
4
51
6
0
0
4
61
6
0
0
4
71
6
0
0
4
81
6
0
0
4
91
6
0
0
4
A1
6
0
0
4
B1
6
0
0
4
C1
6
0
0
4
D1
6
0
0
4
E1
6
0
0
4
F1
6
0
0
5
01
6
0
0
5
11
6
0
0
5
21
6
0
0
5
31
6
B
i
t
A
d
d
r
e
s
s
S
E
G
1
S
E
G3
S
E
G5
S
E
G7
S
E
G9
S
E
G1
1
S
E
G1
3
S
E
G1
5
S
E
G1
7
S
E
G1
9
S
E
G2
1
S
E
G2
3
S
E
G2
5
S
E
G2
7
S
E
G2
9
S
E
G3
1
S
E
G3
3
S
E
G3
5
S
E
G3
7
S
E
G3
9
76543210
C
O
M
3
C
O
M
0
C
O
M
2
C
O
M
1
C
O
M
0
COM
3
COM
2
C
O
M
1
SEG
0
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG14
SEG16
SEG18
SEG20
SEG22
SEG24
SEG26
SEG28
SEG30
SEG32
SEG34
SEG36
SEG38
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
48
Fig. 50 LCD drive waveform (1/2 bias)
I
n
t
e
r
n
a
l
s
i
g
n
a
l
L
C
D
C
K
t
i
m
i
n
g
1/4 duty V
o
l
t
a
g
e
l
e
v
e
l
V
L3
V
L2
=V
L1
V
SS
V
L3
V
SS
COM
0
COM
1
COM
2
COM
3
S
E
G
0
O
F
FO
NOFF ON
C
O
M
3
C
O
M
2
C
O
M
1
C
O
M
0
COM
3
C
O
M
2
C
O
M
1
C
O
M
0
1/3 duty
V
L3
V
L2
=V
L1
V
SS
V
L3
V
SS
O
F
FO
N O
NO
F
FON O
F
F
1/2 duty
COM
0
COM
1
COM
2
S
E
G
0
COM
0
COM
1
SEG
0
V
L3
V
L2
=V
L1
V
SS
V
L3
V
SS
O
F
FO
N O
F
FO
NOFFON O
F
FO
N
C
O
M
0
C
O
M
2
C
O
M
1
C
O
M
0
COM
2
C
O
M
1
C
O
M
0
COM
2
C
O
M
1
C
O
M
0
C
O
M
1
C
O
M
0
COM
1
C
O
M
0
C
O
M
1
COM
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
49
Fig. 51 LCD drive waveform (1/3 bias)
I
n
t
e
r
n
a
l
s
i
g
n
a
l
L
C
D
C
K
t
i
m
i
n
g
1
/
4
d
u
t
yVoltage level
V
L
3
V
S
S
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
S
E
G
0
O
F
FO
N O
F
FO
N
C
O
M
3
COM
2
C
O
M
1
C
O
M
0
C
O
M
3
C
O
M
2
C
O
M
1
COM
0
1/3 duty
OFFON ON OFF ON OFF
1
/
2
d
u
t
y
C
O
M
0
COM
1
C
O
M
2
S
E
G
0
COM
0
COM
1
SEG
0
O
F
FO
N O
F
FO
NOFFON O
F
FON
V
L
3
V
L
2
V
S
S
V
L
1
V
L
3
V
L2
V
SS
V
L1
V
L
3
V
S
S
V
L
3
V
L
2
V
S
S
V
L
1
V
L3
V
SS
COM
0
COM
2
COM
1
COM
0
COM
2
C
O
M
1
C
O
M
0
COM
2
COM
1
C
O
M
0
C
O
M
1
C
O
M
0
COM
1
C
O
M
0
C
O
M
1
COM
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
50
Watchdog Timer
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software runaway).
The watchdog timer consists of an 8-bit watchdog timer L and a 6-
bit watchdog timer H. At reset or writing to the watchdog timer
control register (address 003716), the watchdog timer is set to
“3FFF16”. When any data is not written to the watchdog timer con-
trol register (address 003716) after reset, the watchdog timer is
stopped. The watchdog timer starts to count down from “3FFF16”
by writing to the watchdog timer control register and an internal re-
set occurs at an underflow. Accordingly, when using the watchdog
timer function, write the watchdog timer control register before an
underflow. The watchdog timer does not function when writing to
the watchdog timer control register has not been done after reset.
When not using the watchdog timer, do not write to it. When the
watchdog timer control register is read, the following values are
read:
●value of high-order 6-bit counter
●value of STP instruction disable bit
●value of count source selection bit.
When the STP instruction disable bit is “0”, the STP instruction is
enabled. The STP instruction is disabled when this bit is set to “1”.
If the STP instruction which is disabled is executed, it is processed
as an undefined instruction, so that a reset occurs internally.
This bit can be set to “1” but cannot be set to “0” by program. This
bit is “0” after reset.
When the watchdog timer H count source selection bit is “0”, the
detection time is set to 8.19 s at f(XCIN) = 32 kHz and 32.768 ms
at f(XIN) = 8 MHz.
When the watchdog timer H count source selection bit is “0”, the
detection time is set to 32 ms at f(XCIN) = 32 kHz and 128 µs at
f(XIN) = 8 MHz. There is no difference in the detection time be-
tween the middle-speed mode and the high-speed mode.
Fig. 52 Block diagram of watchdog timer
Fig. 53 Structure of watchdog timer control register
Fig. 54 Timing of reset output
XIN
Data bus
XCIN
“1”
“0”
Internal
system clock
selection bit
(Note)
“0”
“1”
1/16
Watchdog timer H count
source selection bit
Reset circuit
Undefined instruction
Reset
“3F
16
” is set when
watchdog timer is
written to.
Internal reset
RESET Reset release time wait
“FF
16
” is set when
watchdog timer is
written to.
STP instruction
STP instruction disable bit
Watchdog timer
H (6)
Watchdog timer
L (8)
Note: This is the bit 7 of CPU mode register and is used to switch the middle-/high-speed mode and low-speed mode.
b
7 b
0W
a
t
c
h
d
o
g
t
i
m
e
r
r
e
g
i
s
t
e
r
(
W
D
T
C
O
N
:
a
d
d
r
e
s
s
0
0
3
71
6)
S
T
P
i
n
s
t
r
u
c
t
i
o
n
d
i
s
a
b
l
e
b
i
t
0
:
S
T
P
i
n
s
t
r
u
c
t
i
o
n
e
n
a
b
l
e
d
1
:
S
T
P
i
n
s
t
r
u
c
t
i
o
n
d
i
s
a
b
l
e
d
W
a
t
c
h
d
o
g
t
i
m
e
r
H
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
i
o
n
b
i
t
0
:
W
a
t
c
h
d
o
g
t
i
m
e
r
L
u
n
d
e
r
f
l
o
w
1
:
f
(
XI
N)
/
1
6
o
r
f
(
XC
I
N)
/
1
6
Watc hdog timer H ( fo r re ad- out of high- or der 6 bit)
“3FFF16” is set to the watchdog timer by writing values to this address.
I
n
t
e
r
n
a
l
r
e
s
e
t
s
i
g
n
a
l
W
a
t
c
h
d
o
g
t
i
m
e
r
d
e
t
e
c
t
i
o
n
Approx. 1 ms (f(XIN) = 8 MH Z)
f
(
XI
N)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
51
TOUT/φ OUTPUT FUNCTION
The system clock φ or timer 2 divided by 2 (TOUT output) can be
output from port P43 by setting the TOUT/φ output enable bit of the
timer 123 mode register and the TOUT/φ output control register.
Set the P43/φ/TOUT pin to output mode (set “1” to bit 3 of port P4
direction register) when outputting TOUT/φ.
Fig. 55 Structure of TOUT/φφ
φφ
φ output-related registers
T
O
U
T
/φ
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
0
:
S
y
s
t
e
m
c
l
o
c
k
φ
o
u
t
p
u
t
1
:
T
O
U
T
o
u
t
p
u
t
N
o
t
u
s
e
d
(
“
0
”
a
t
r
e
a
d
i
n
g
)
T
OUT
/φ out put con tr o
l
reg
i
ster
(CKO UT : ad dress 002A
16
)
b
7
b
0
Ti
me r 123 mo
d
e reg
i
ster
(T123M : address 0029
16
)
T
OUT
output act
i
ve e
d
ge sw
i
tc
h
bi
t
0 : Start at “H” output
1 : Start at “L” output
T
OUT
/φ output enable bit
0 : T
OUT
/φ out pu t disabled
1 : T
OUT
/φ out pu t enable d
Timer 2 write control bit
0 : Write data in latch and timer
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
1 : f(X
IN
)/16
(or f(X
CIN
)/16 in low-speed mod e)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(X
IN
)/16
(or f(X
CIN
)/16 in low-speed mod e)
Timer 1 count source selection bit
0 : f(X
IN
)/16
(or f(X
CIN
)/16 in low-speed mod e)
1 : f(X
CIN
)
Not used (“0” at reading)
b
7
b
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
52
Fig. 56 Example of reset circuit
RESET CIRCUIT
When the power source voltage is within limits, and main clock
XIN-XOUT is stable, or a stabilized clock is input to the XIN pin, if
the RESET pin is held at an “L” level for 2 µs or more, the micro-
computer is in an internal reset state. Then the RESET pin is
returned to an “H” level, reset is released after approximate 8200
cycles of f(XIN), the program in address FFFD16 (high-order byte)
Fig. 57 Reset Sequence
and address FFFC16 (low-order byte). Make sure that the reset in-
put voltage is less than 0.2 VCC(min.) for the power source voltage
of VCC(min.).
*VCC(min.) = Minimum value of power supply voltage limits
applied to VCC pin
V
C
C
R
E
S
E
TV
C
C
R
E
S
E
T
Power source
voltage detection
circuit
V
C
C
R
E
S
E
T
P
o
w
e
r
o
n
0
.
2
V
C
C
l
e
v
e
l
O
s
c
i
l
l
a
t
i
o
n
s
t
a
b
i
l
i
z
e
d
2
µs
X
I
N
0
V
0
V
0
V
(
N
o
t
e
)
N
o
t
e:
R
e
s
e
t
r
e
l
e
a
s
e
v
o
l
t
a
g
e
V
c
c
=
V
c
c
(
m
i
n
.
)
A
D
L
FFFC
FFFD
A
D
H
,
Undefined
X
I
N
:
A
p
p
r
o
x
.
8
2
0
0
c
y
c
l
e
s
N
o
t
e
:
T
h
e
f
r
e
q
u
e
n
c
y
o
f
s
y
s
t
e
m
c
l
o
c
k
φ
i
s
f
(
X
I
N
)
d
i
v
i
d
e
d
b
y
8
.
R
eset a
dd
ress
f
rom
vector table
R
E
S
E
T
I
n
t
e
r
n
a
l
r
e
s
e
t
Add
ress
D
ata
SYNC
S
y
s
t
e
m
c
l
o
c
k
φ
X
IN
AD
H
AD
L
Undefined U
n
d
e
f
i
n
e
dU
n
d
e
f
i
n
e
d
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
53
Fig. 58 Internal state of microcomputer immediately after reset
N
o
t
e
:
T
h
e
c
o
n
t
e
n
t
s
o
f
a
l
l
o
t
h
e
r
r
e
g
i
s
t
e
r
s
a
n
d
R
A
M
a
r
e
u
n
d
e
f
i
n
e
d
a
f
t
e
r
r
e
s
e
t
,
s
o
t
h
e
y
m
u
s
t
b
e
i
n
i
t
i
a
l
i
z
e
d
b
y
s
o
f
t
w
a
r
e
.
✕
:
U
n
d
e
f
i
n
e
d
R
eg
i
ster contents
A
d
d
r
e
s
s
0
0
0
11
6
0
0
0
31
6
000516
0
0
0
71
6
0
0
0
91
6
0
0
0
B
1
6
000
D
16
0
0
0
F
1
6
001416
001616
0
0
1
71
6
0
0
1
91
6
001
A
16
001
B
16
001
D
16
002016
0
0
2
11
6
0
0
2
21
6
0
0
2
31
6
002416
002516
0
0
2
61
6
0
0
2
71
6
002816
002916
0
0
2
A
1
6
0
0
2
B
1
6
0
0
3
21
6
003316
003416
003616
003716
0
0
3
81
6
0
0
3
91
6
003
A
16
003
B
16
003
C
16
003
D
16
0
0
3
E
1
6
003
F
16
(
P
S
)
(PC
H
)
(PC
L
)
(
1
0
)
(
1
1
)
(
1
2
)
(
1
3
)
(
1
4
)
(
1
5
)
(
16
)
(
1
7
)
(
18
)
(
1
9
)
(
2
0
)
(
2
1
)
(
22
)
(
23
)
(
2
4
)
(
2
5
)
(
26
)
(
27
)
(
2
8
)
(
2
9
)
(
3
0
)
(
31
)
(
32
)
(
3
3
)
(
3
4
)
(
1
)
(
2
)
(
3
)
(
4
)
(
5
)
(
6
)
(
7
)
(
8
)
(
9
)
(
3
5
)
(
3
6
)
(
3
7
)
(
38
)
(
39
)
(
40
)
(
4
1
)
(
4
2
)
(
4
3
)
T
i
m
e
r
Y
l
o
w
-
o
r
d
e
r
r
e
g
i
s
t
e
r
P
o
r
t
P
5
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
P
6
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
U
L
L
r
e
g
i
s
t
e
r
B
T
i
m
e
r
Y
h
i
g
h
-
o
r
d
e
r
r
e
g
i
s
t
e
r
S
e
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
UAR T control register
T
i
m
e
r
X
h
i
g
h
-
o
r
d
e
r
r
e
g
i
s
t
e
r
Timer X low -order register
Timer X mode register
T
i
m
e
r
Y
m
o
d
e
r
e
g
i
s
t
e
r
Tim er 123 mode regis ter
S
e
r
i
a
l
I
/
O
1
s
t
a
t
u
s
r
e
g
i
s
t
e
r
P
o
r
t
P
7
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
A-D control register
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
r
e
g
i
s
t
e
r
L
C
D
m
o
d
e
r
e
g
i
s
t
e
r
P
U
L
L
r
e
g
i
s
t
e
r
A
Int er rup t edge select ion register
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
P
r
o
c
e
s
s
o
r
s
t
a
t
u
s
r
e
g
i
s
t
e
r
P
r
o
g
r
a
m
c
o
u
n
t
e
r
P
o
r
t
P
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
P
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
P
3
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
P
o
r
t
P
1
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
P
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Timer 1 reg ister
Timer 2 reg ister
Timer 3 reg ister
A
D
c
o
n
v
e
r
s
i
o
n
l
o
w
-
o
r
d
e
r
r
e
g
i
s
t
e
r
111000 00
100000 00
001111 11
10010 000
✕1✕✕✕✕✕✕
0
01
6
0016
0016
0
01
6
0
01
6
0
01
6
FF
16
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
FF
16
FF
16
0
01
6
0
01
6
0
01
6
3
F
1
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0016
0
01
6
0
01
6
F
F
1
6
F
F
1
6
Cont ents of address FFFD 16
Cont ents of address FFFC 16
D-
A
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
W
a
t
c
h
d
o
g
t
i
m
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
D
-
A
1
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
D-A2 conversion register
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
T
O
U
T
/φ
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
P
W
M
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
Wat chdo g timer ( high-or der)
(
44
)
Watchdog timer (low-order)
F
F
1
6
0116
0016
00010 000
3
F
16
F
F
1
6
(
4
5
)
001516
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
01
6
✕✕0000 10
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
54
Fig. 59 Oscillator circuit
Fig. 60 External clock input circuit
CLOCK GENERATING CIRCUIT
The 7560 group has two built-in oscillation circuits: main clock
XIN-XOUT oscillation circuit and sub-clock XCIN-XCOUT oscillation
circuit. An oscillation circuit can be formed by connecting an oscil-
lator between XIN and XOUT (XCIN and XCOUT). Use the circuit
constants in accordance with the oscillator manufacturer ’s recom-
mended values. No external resistor is needed between XIN and
XOUT since a feed-back resistor exists on-chip. However, an exter-
nal feed-back resistor is needed between XCIN and XCOUT since a
resistor does not exist between them.
To supply a clock signal externally, input it to the XIN pin and make
the XOUT pin open. The sub-clock oscillation circuit cannot directly
input clocks that are externally generated. Accordingly, be sure to
cause an external oscillator to oscillate.
Immediately after poweron, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins go to high-impedance state.
Frequency Control
(1) Middle-speed mode
The clock input to the XIN pin is divided by 8 and it is used as the
system clock
φ
.
After reset, this mode is selected.
(2) High-speed mode
The clock input to the XIN pin is divided by 2 and it is used as the
system clock
φ
.
(3) Low-speed mode
•The clock input to the XCIN pin is divided by 2 and it is used as
the system clock
φ
.
•A low-power consumption operation can be realized by stopping
the main clock in this mode. To stop the main clock, set the main
clock stop bit of the CPU mode register to “1”.
When the main clock is restarted, after setting the main clock
stop bit to “0”, set enough time for oscillation to stabilize by pro-
gram.
Note: If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The suffi-
cient time is required for the sub clock to stabilize, espe-
cially immediately after poweron and at returning from stop
mode. When switching the mode between middle/high-
speed and low-speed, set the frequency in the condition
that f(XIN) > 3•f(XCIN).
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the system clock φ stops at an
“H” level, and main and sub clock oscillators stop.
In this time, values set previously to timer 1 latch and timer 2 latch
are loaded automatically to timer 1 and timer 2. Before the STP
instruction, set the values to generate the wait time required for
oscillation stabilization to timer 1 latch and timer 2 latch (low-order
8 bits are set to timer 1, high-order 8 bits are set to timer 2). Either
f(XIN) or f(XCIN) divided by 16 is input to timer 1 as count source,
and the output of timer 1 is connected to timer 2.
The bits of the timer 123 mode register except bit 4 are set to “0”.
Set the timer 1 and timer 2 interrupt enable bits to “0” before ex-
ecuting the STP instruction.
Oscillation restarts at reset or when an external interrupt is re-
ceived, but the system clock φ is not supplied to the CPU until
timer 2 underflows. This allows time for the clock circuit oscillation
to stabilize when a ceramic resonator is used.
(2) Wait mode
If the WIT instruction is executed, only the system clock φ stops at
an “H” state. The states of main clock and sub clock are the same
as the state before the executing the WIT instruction, and oscilla-
tion does not stop. Since supply of internal clock
φ
is started im-
mediately after the interrupt is received, the instruction can be ex-
ecuted immediately.
X
C
I
N
C
I
N
C
O
U
T
C
C
I
N
C
C
O
U
T
R
fR
d
X
C
O
U
T
X
I
N
X
O
U
T
XI
N
XO
U
T
E
x
t
e
r
n
a
l
o
s
c
i
l
l
a
t
i
o
n
c
i
r
c
u
i
t
O
p
e
n
VCC
VSS
CC
I
NCC
O
U
T
R
fR
d
XC
I
N
XC
O
U
T
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
55
Fig. 61 Clock generating circuit block diagram
W
I
T
i
n
s
t
r
u
c
t
i
o
n
STP
i
nstruct
i
on
S
ystem c
l
oc
k
φ
S
R
Q
STP
i
nstruct
i
on
S
R
Q
M
a
i
n c
l
oc
k
stop
bi
t
S
R
Q
T
i
m
e
r
2
Ti
me r 1
1
/
21/4
X
I
N
X
O
U
T
X
C
O
U
T
X
CIN
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
R
e
s
e
t
T
i
m
e
r
1
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
Ti
me r 2 co u n t
source selection
bit
L
o
w
-
s
p
e
e
d
m
o
d
e
M
i
d
d
l
e
-
/
H
i
g
h
-
s
p
e
e
d
m
o
d
e
S
y
s
t
e
m
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
(N
o
t
e
)
Middl
e-spee
d
mo
d
e
Hi
g
h
-spee
d
mo
d
e
or Low-speed mode
N
ote:
Wh
en us
i
ng t
h
e su
b
c
l
oc
k
f
or t
h
e system c
l
oc
k
φ, set t
h
e
X
C
sw
i
tc
h
bi
t to “1”.
M
a
i
n
c
l
o
c
k
d
i
v
i
s
i
o
n
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
“
1
”
“
0
”“
1
”
“
0
”
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
g
I
1
/
2
X
C
s
w
i
t
c
h
b
i
t
(N
o
t
e
)
“
1
”“
0
”
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
56
Fig. 62 State transitions of system clock
N
o
t
e
s1
:
S
w
i
t
c
h
t
h
e
m
o
d
e
a
c
c
o
r
d
i
n
g
t
o
t
h
e
a
r
r
o
w
s
s
h
o
w
n
b
e
t
w
e
e
n
t
h
e
m
o
d
e
b
l
o
c
k
s
.
(
D
o
n
o
t
s
w
i
t
c
h
b
e
t
w
e
e
n
t
h
e
m
o
d
e
d
i
r
e
c
t
l
y
w
i
t
h
o
u
t
a
n
a
r
r
o
w
.
)
2
:
T
h
e
a
l
l
m
o
d
e
s
c
a
n
b
e
s
w
i
t
c
h
e
d
t
o
t
h
e
s
t
o
p
m
o
d
e
o
r
t
h
e
w
a
i
t
m
o
d
e
a
n
d
r
e
t
u
r
n
e
d
t
o
t
h
e
s
o
u
r
c
e
m
o
d
e
w
h
e
n
t
h
e
s
t
o
p
m
o
d
e
o
r
t
h
e
w
a
i
t
m
o
d
e
i
s
e
n
d
e
d
.
3
:
W
h
e
n
t
h
e
s
t
o
p
m
o
d
e
i
s
e
n
d
e
d
,
a
d
e
l
a
y
t
i
m
e
c
a
n
b
e
s
e
t
b
y
t
i
m
e
r
1
a
n
d
t
i
m
e
r
2
.
4:
T
i
m
e
r
a
n
d
L
C
D
o
p
e
r
a
t
e
i
n
t
h
e
w
a
i
t
m
o
d
e
.
5
:
W
a
i
t
u
n
t
i
l
o
s
c
i
l
l
a
t
i
o
n
s
t
a
b
i
l
i
z
e
s
a
f
t
e
r
o
s
c
i
l
l
a
t
i
n
g
t
h
e
m
a
i
n
c
l
o
c
k
b
e
f
o
r
e
t
h
e
s
w
i
t
c
h
i
n
g
f
r
o
m
t
h
e
l
o
w
-
s
p
e
e
d
m
o
d
e
t
o
m
i
d
d
l
e
-
/
h
i
g
h
-
s
p
e
e
d
m
o
d
e
.
6
:
T
h
e
e
x
a
m
p
l
e
a
s
s
u
m
e
s
t
h
a
t
8
M
H
z
i
s
b
e
i
n
g
a
p
p
l
i
e
d
t
o
t
h
e
XI
N
p
i
n
a
n
d
3
2
k
H
z
t
o
t
h
e
XC
I
N
p
i
n
.
φ
i
n
d
i
c
a
t
e
s
t
h
e
s
y
s
t
e
m
c
l
o
c
k
.
CM
4 :
X
c sw
i
tc
h
bi
t
0: Os c illation s top
1: XCIN, XCOUT
CM5 : Main clock (XIN–XOUT) stop bit
0: Os c illating
1: Stopped
CM6 : Main clock division ratio selection bit
0: f(XIN)/2 (high-speed mode)
1: f(XIN) /8 (midd le-speed mo de)
CM7 : System clock selection bit
0: XIN–XOUT selected
( m iddle - /high-s peed mode)
1: XCIN–XCOUT selected
(low-speed mode)
CPU
mo
d
e reg
i
ster
(CPUM : address 003B16)
b
7
b
4
R
e
s
e
t
CM
6
“0”“1”
C
M
6“
0
”“
1
”
C
M5“
0
”“
1
”
C
M5“
0
”“
1
”
“
0
”
C
M
5
C
M
6
“
0
”
“
1
”
“
0
”
“
1
”
C
M
5
C
M
6
“
1
”
“
1
”
“
0
”
C
M
6
“0”“1”
C
M7“
0
”
“
1
”
C
M7“
0
”
“
1
”
C
M
7
=
0
(
8
M
H
z
s
e
l
e
c
t
e
d
)
C
M6
=
1
(
M
i
d
d
l
e
-
s
p
e
e
d
)
C
M5
=
0
(
8
M
H
z
o
s
c
i
l
l
a
t
i
n
g
)
C
M4
=
0
(
3
2
k
H
z
s
t
o
p
p
e
d
)
Middl
e-spee
d
mo
d
e
(f(φ) = 1 MHz)
C
M
6
“
0
”“
1
”
C
M4“
0
”
“
1
”
C
M4“
0
”
“
1
”
CM
7 = 0
(
8
MH
z se
l
ecte
d)
CM6 = 0 (High-speed)
CM5 = 0 (8 MHz oscillating )
CM4 = 0 (32 kHz stopped)
Hi
g
h
-spee
d
mo
d
e
(f(φ) = 4 MHz)
CM
7 = 0
(
8
MH
z se
l
ecte
d)
CM6 = 1 (M idd le- spee d)
CM5 = 0 (8 MHz oscillating )
CM4 = 1 (3 2 kHz oscillating)
Middl
e-spee
d
mo
d
e
(f(φ) = 1 MHz)
CM
7 = 0
(
8
MH
z se
l
ecte
d)
CM6 = 0 (High-speed)
CM5 = 0 (8 MHz oscillating )
CM4 = 1 (3 2 kHz oscillating)
Hi
g
h
-spee
d
mo
d
e
(f(φ) = 4 MHz)
C
M
4
C
M
6
“
0
”
“
1
”
“
0
”
“
1
”
C
M
4
C
M
6
“
1
”
“
1
”
“
0
”
“
0
”
CM
7 = 1
(
32
kH
z se
l
ecte
d)
CM6 = 1 (M idd le- spee d)
CM5 = 0 (8 MHz oscillating )
CM4 = 1 (3 2 kHz oscillating)
L
o
w-
s
p
e
e
d
m
o
d
e
(
f
(φ
)
=
1
6
k
H
z
)
CM
7 = 1
(
32
kH
z se
l
ecte
d)
CM6 = 0 (High-speed)
CM5 = 0 (8 MHz oscillating )
CM4 = 1 (3 2 kHz oscillating)
L
o
w-
s
p
e
e
d
m
o
d
e
(
f
(φ
)
=
1
6
k
H
z
)
CM
7 = 1
(
32
kH
z se
l
ecte
d)
CM6 = 1 (M idd le- spee d)
CM5 = 1 (8 M Hz stopped)
CM4 = 1 (3 2 kHz oscillating)
L
o
w-
s
p
e
e
d
m
o
d
e
(
f
(φ
)
=
1
6
k
H
z
)
CM
7 = 1
(
32
kH
z se
l
ecte
d)
CM6 = 0 (High-speed)
CM5 = 1 (8 M Hz stopped)
CM4 = 1 (3 2 kHz oscillating)
L
o
w-
s
p
e
e
d
m
o
d
e
(
f
(φ
)
=
1
6
k
H
z
)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
57
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags (T flag, D flag, etc.) which affect program
execution.
Interrupt
When the contents of an interrupt request bits are changed by the
program, execute a BBC or BBS instruction after at least one in-
struction. This is for preventing executing a BBC or BBS
instruction to the contents before change.
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D) to
“1”, then execute an ADC or SBC instruction. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
The contents of the port direction registers cannot be read.
The following cannot be used:
•LDA instruction
•The memory operation instruction when the T flag is “1”
•The bit-test instruction (BBC or BBS, etc.)
•The read-modify-write instruction (calculation instruction such as
ROR etc., bit manipulation instruction such as CLB or SEB etc.)
•The addressing mode which uses the value of a direction regis-
ter as an index
Serial I/O
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit en-
able bit, the receive enable bit, and the SRDY output enable bit to
“1”.
The TxD pin of serial I/O1 retains the level then after transmission
is completed.
In serial I/O2 selecting an internal clock, the SOUT2 pin goes to
high impedance state after transmission is completed.
In serial I/O2 selecting an external clock, the SOUT2 pin retains the
level then after transmission is completed.
A-D Converter
The input to the comparator is combined by internal capacitors.
Therefore, since conversion accuracy may be worse by losing of
an electric charge when the conversion speed is not enough,
make sure that f(XIN) is at least 500 kHz during an A-D conver-
sion.
The normal operation of A-D conversion cannot be guaranteed
when performing the next operation:
•When writing to CPU mode register during A-D conversion op-
eration
•When writing to A-D control register during A-D conversion op-
eration
•When executing STP instruction or WIT instruction during A-D
conversion operation
Instruction Execution Time
The instruction execution time is obtained by multiplying the fre-
quency of the system clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the system clock φ depends on the main clock
division ratio selection bit and the system clock selection bit.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
58
NOTES ON USE
Countermeasures Against Noise
(1) Shortest wiring length
➀ Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin
as short as possible. Especially, connect a capacitor across the
RESET pin and the VSS pin with the shortest possible wiring
(within 20 mm).
● Reason
The width of a pulse input into the RESET pin is determined by
the timing necessary conditions. If noise having a shorter pulse
width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is com-
pletely initialized. This may cause a program runaway.
Fig. 64 Wiring for clock I/O pins
(2) Connection of bypass capacitor across VSS line and VCC line
In order to stabilize the system operation and avoid the latch-up,
connect an approximately 0.1
µ
F bypass capacitor across the VSS
line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC pin
at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin
with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS
line and VCC line.
• Connect the power source wiring via a bypass capacitor to the
VSS pin and the VCC pin.
Fig. 63 Wiring for the RESET pin
➁ Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins
as short as possible.
• Make the length of wiring (within 20 mm) across the grounding
lead of a capacitor which is connected to an oscillator and the
VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS
patterns.
● Reason
If noise enters clock I/O pins, clock waveforms may be de-
formed. This may cause a program failure or program runaway.
Also, if a potential difference is caused by the noise between
the VSS level of a microcomputer and the VSS level of an oscil-
lator, the correct clock will not be input in the microcomputer.
Fig. 65 Bypass capacitor across the VSS line and the VCC line
RESET
Reset
circuit
Noise
V
SS
V
SS
Reset
circuit
V
SS
RESET
V
SS
N.G.
O.K.
Noise
XIN
XOUT
VSS
XIN
XOUT
VSS
N.G. O.K.
V
SS
V
CC
AA
AA
AA
AA
AA
AA
V
SS
V
CC
AA
AA
AA
AA
AA
AA
AA
AA
AA
N.G. O.K.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
59
(3) Oscillator concerns
In order to obtain the stabilized operation clock on the user system
and its condition, contact the oscillator manufacturer and select
the oscillator and oscillation circuit constants. Be careful espe-
cially when range of voltage or/and temperature is wide.
Also, take care to prevent an oscillator that generates clocks for a
microcomputer operation from being affected by other signals.
➀ Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as
possible from signal lines where a current larger than the toler-
ance of current value flows.
● Reason
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When a
large current flows through those signal lines, strong noise oc-
curs because of mutual inductance.
➁ Installing oscillator away from signal lines where potential levels
change frequently
Install an oscillator and a connecting pattern of an oscillator
away from signal lines where potential levels change frequently.
Also, do not cross such signal lines over the clock lines or the
signal lines which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as
the CNTR pin signal line) may affect other lines at signal rising
edge or falling edge. If such lines cross over a clock line, clock
waveforms may be deformed, which causes a microcomputer
failure or a program runaway.
➀ Keeping oscillator away from large current signal lines
➁ Installing oscillator away from signal lines where potential
levels change frequently Fig. 67 Wiring for the VPP pin of One Time PROM
Fig. 66 Wiring for a large current signal line/
Wiring of signal
lines where potential levels change frequently
(4) Analog input
The analog input pin is connected to the capacitor of a compara-
tor. Accordingly, sufficient accuracy may not be obtained by the
charge/discharge current at the time of A-D conversion when the
analog signal source of high-impedance is connected to an analog
input pin. In order to obtain the A-D conversion result stabilized
more, please lower the impedance of an analog signal source, or
add the smoothing capacitor to an analog input pin.
(5) Difference of memory type and size
When Mask ROM and PROM version and memory size differ in
one group, actual values such as an electrical characteristics, A-D
conversion accuracy, and the amount of proof of noise incorrect
operation may differ from the ideal values.
When these products are used switching, perform system evalua-
tion for each product of every after confirming product
specification.
(6)
Wiring to VPP pin of One Time PROM version and EPROM version
Connect an approximately 5 kΩ resistor to the VPP pin the shortest
possible in series.
Note: Even when a circuit which included an approximately 5 kΩ
resistor is used in the Mask ROM version, the microcom-
puter operates correctly.
● Reason
The VPP pin of the PROM version is the power source input pin for
the built-in PROM. When programming in the built-in PROM, the
impedance of the VPP pin is low to allow the electric current for
writing flow into the built-in PROM. Because of this, noise can en-
ter easily. If noise enters the VPP pin, abnormal instruction codes
or data are read from the built-in PROM, which may cause a pro-
gram runaway.
XI
N
XO
U
T
VS
S
M
i
c
r
o
c
o
m
p
u
t
e
r
Mutual inductance
L
a
r
g
e
c
u
r
r
e
n
t
G
N
D
M
XI
N
XO
U
T
VS
S
C
N
T
R
D
o
n
o
t
c
r
o
s
s
N.G.
P
7
0
/
V
P
P
V
SS
A
b
o
u
t
5
kΩ
S
o
u
r
c
e
s
i
g
n
a
l
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
60
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
1.Mask ROM Order Confirmation Form✽
2.Mark Specification Form✽
3.Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
✽For the mask ROM confirmation and the mark specifications, re-
fer to the “Mitsubishi MCU Technical Information” Homepage
(http://www.infomicom.maec.co.jp/indexe.htm).
Name of Programming Adapter
PCA4738F-100A
PCA4738G-100A
PCA4738L-100A
Package
100P6S-A
100P6Q-A
100D0
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 68 is recommended to verify programming.
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version can be
read or programmed with a general-purpose PROM programmer
using a special programming adapter. Set the address of PROM
pro-grammer in the user ROM area.
Table 14 Special programming adapter
Fig. 68 State transitions of system clock
Programming with P R OM
programmer
S
c
r
e
e
n
i
n
g
(
C
a
u
t
i
o
n
)
(
1
5
0
°
C
f
o
r
4
0
h
o
u
r
s
)
Verification with
PROM programmer
Functional check in
target device
The s cree ning tem per ature is fa r highe
r
than the storage temperature. Neve
r
expose to 150 °C exceeding 100 hours.
Caution :
61
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Table 15 Absolute maximum ratings
RECOMMENDED OPERATING CONDITIONS
Table 16 Recommended operating conditions (1) (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Power source voltage
A-D, D-A conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
5.5
5.5
5.5
VCC
VCC
VCC
VSS
VREF
AVSS
VIA
Symbol Parameter Limits
Min.
V
V
V
V
V
Unit
4.0
2.2
2.2
2.0
AVSS
5.0
5.0
5.0
0
0
Typ. Max.
Power source voltage
VO
VO
VO
Pd
Topr
Tstg
–0.3 to 6.5 V
Power source voltage
Input voltage P00–P07, P10–P17, P20–P27,
P40–P47, P50–P57, P60–P67
Input voltage P70–P77
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage C1, C2
Input voltage RESET, XIN
Output voltage C1, C2
VCC
VI
Symbol Parameter Conditions Ratings Unit
All voltages are based on VSS.
Output transistors are cut off.
VI
VI
VI
VI
VI
VI
VO
VO
VO
Output voltage P00–P07, P10–P15, P30–P37
Output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77
Output voltage VL3
Output voltage VL2, SEG0–SEG17
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
At output port
At segment output
Ta = 25°C
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
VL2 to 6.5
–0.3 to 6.5
–0.3 to VCC +0.3
–0.3 to 6.5
–0.3 to VCC
–0.3 to VL3
–0.3 to VCC +0.3
–0.3 to 6.5
–0.3 to VL3
–0.3 to VCC +0.3
300
–20 to 85
–40 to 125
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mW
°C
°C
High-speed mode f(XIN) = 8 MHz
Middle-speed mode f(XIN) = 8 MHz
Low-speed mode
62
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7560 Group
MITSUBISHI MICROCOMPUTERS
V
V
“H” input voltage P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
“H” input voltage P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
RESET
XIN
“L” input voltage P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
“L” input voltage P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
RESET
XIN
Table 17 Recommended operating conditions (2) (VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol Parameter Limits
Min. Unit
Typ. Max.
“H” input voltage
“H” input voltage
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
“L” input voltage
“L” input voltage
0.7 VCC
0.8 VCC
0.8 VCC
0.8 VCC
0
0
0
0
VCC
VCC
VCC
VCC
0.3 VCC
0.2 VCC
0.2 VCC
0.2 VCC
V
V
V
V
V
V
V
V
“H” input voltage P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
“H” input voltage P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
RESET
XIN
“L” input voltage P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
“L” input voltage P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
RESET
XIN
Table 18 Recommended operating conditions (3) (VCC = 2.2 to 2.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol Parameter Limits
Min. Unit
Typ. Max.
“H” input voltage
“H” input voltage
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
“L” input voltage
“L” input voltage
0.8 VCC
0.95 VCC
0.95 VCC
0.95 VCC
0
0
0
0
VCC
VCC
VCC
VCC
0.2 VCC
0.05 VCC
0.05 VCC
0.05 VCC
V
V
V
V
V
V
63
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P40, P71–P77 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P40, P71–P77 (Note 1)
P00–P07, P10–P15, P30–P37 (Note 2)
“H” peak output current P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 2)
P00–P07, P10–P15, P30–P37 (Note 2)
“L” peak output current P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 2)
P40, P71–P77 (Note 2)
P00–P07, P10–P15, P30–P37 (Note 3)
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 3)
P00–P07, P10–P15, P30–P37 (Note 3)
“L” average output current P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 3)
P40, P71–P77 (Note 3)
–20
–20
20
20
80
–10
–10
10
10
40
–1.0
Table 19 Recommended operating conditions (4) (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Notes1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“L” total average output current
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
Symbol Parameter Limits
Min. mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Unit
Typ. Max.
“H” peak output current
“L” peak output current
“L” peak output current
“H” average output current
“H” average output current
“L” average output current
“L” average output current
IOH(peak)
IOL(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
–5.0
5.0
10
20
–0.5
–2.5
2.5
5.0
mA
mA
mA
mA
mA
mA
mA
mA
IOL(avg) mA
10
64
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7560 Group
MITSUBISHI MICROCOMPUTERS
Table 20 Recommended operating conditions (5) (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Notes1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
Input frequency for timers X and Y
(duty cycle 50%)
f(CNTR0)
f(CNTR1)
Symbol Parameter Limits
Min. MHz
Unit
Typ. Max.
(4.0 V ≤ VCC ≤ 5.5 V)
32.768
4.0
Main clock input oscillation frequency
(Note 1)
Sub-clock input oscillation frequency (Notes 1, 2)
f(XIN)
f(XCIN)
(VCC ≤ 4.0 V)
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
High-speed mode
(2.2 V ≤ VCC ≤ 4.0 V)
Middle-speed mode
(10✕VCC
–4)/9
8.0
(20✕VCC
–8)/9
8.0
50
MHz
MHz
MHz
MHz
kHz
Test conditions
65
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
VCC = 5.0 V, VO = VCC, Pullup ON
Output transistors “off”
VCC = 2.2 V,VO = VCC, Pullup ON
Output transistors “off”
IOL = 10 mA
IOL = 3.0 mA
IOL = 2.5 mA
VCC = 2.2 V
IOL = 5 mA
IOL = 1.5 mA
IOL = 1.25 mA
VCC = 2.2 V
VOL
IOH = –1 mA
IOH = –0.25 mA
VCC = 2.2 V
IOH = –5 mA
IOH = –1.5 mA
IOH = –1.25 mA
VCC = 2.2 V
VVCC–2.0
“H” output voltage
P00–P07, P10–P15, P30–P37
Symbol Parameter Limits
Min. Unit
0.5
Typ. Max.
Test conditions
VOH
2.0
0.5
Table 21 Electrical characteristics (1) (VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
IOL = 10 mA
IOL = 5 mA
VCC = 2.2 V
VI = VCC
VI = VCC
VI = VCC
VI = VSS
Pull-ups “off”
VCC = 5 V, VI = VSS
Pull-ups “on”
VCC = 2.2 V, VI = VSS
Pull-ups “on”
VI = VSS
VI = VSS
“H” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67 (Note 1)
“L” output voltage
P00–P07, P10–P15, P30–P37
“L” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67
“L” output voltage
P40, P71–P77
Hysteresis
INT0–INT2, ADT, CNTR0, CNTR1, P20–P27
Hysteresis SCLK, RXD, SIN2
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20–P27, P40–P47,
P50–P57, P60–P67, P70–P77
“H” input current RESET
“H” input current XIN
“L” input current
P00–P07,P10–P17, P20–P27,P41–P47,
P50–P57, P60–P67
“L” input current P40, P70–P77
“L” input current RESET
“L” input current XIN
Output load current
P30–P37
VOH
VOL
VOL
VT+ – VT–
VT+ – VT–
VT+ – VT–
IIH
IIH
IIH
IIL
IIL
IIL
ILOAD
VCC–2.0
VCC–0.5
–60.0
–5.0
0.5
0.5
4.0
–120.0
–20.0
–4.0
2.0
0.5
0.5
5.0
5.0
–5.0
–240.0
–40.0
–5.0
–5.0
–240.0
–40.0
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
IIL
VCC–0.8
VCC–0.8
V
V
V0.8
V0.8
0.3 V
µA
µA
µA
VO = VCC, Pullup OFF
Output transistors “off”
VO = VSS, Pullup OFF
Output transistors “off”
Output leak current
P30–P37
ILEAK 5.0
–5.0 µA
µA
–120.0
–20.0
–60.0
–5.0
66
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7560 Group
MITSUBISHI MICROCOMPUTERS
Table 22 Electrical characteristics (2) (VCC =2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
V
5.5
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter stop
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Symbol Parameter Limits
Min. Unit
Typ. Max.
Ta = 25 °C
Ta = 85 °C
Test conditions
ICC Power source current
6.4
VRAM RAM retention voltage At clock stop mode 2.0
When using voltage multiplier
VL1 = 1.8 V
VL1
IL1
Power source voltage
Power source current
(VL1) (Note)
Note: When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.
1.3
1.6
35
20
15
4.5
0.1
1.8
4.0
3.2
70
40
22
9.0
1.0
10
2.1
mA
µA
µA
µA
µA
µA
V
mA
13
µA
67
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
Table 23 A-D converter characteristics
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, f(XIN) = 500 kHz to 8 MHz, in middle/high-speed mode unless otherwise noted)
8-bit A-D mode (when conversion mode selection bit (bit 0 of address 0014 16) is “1”)
Symbol Parameter Limits
Min. Unit
Typ. Max.
Test conditions
–Resolution
Absolute accuracy
(excluding quantization error) VCC = VREF = 2.7 to 5.5 V Bits
LSB
35
150
8
±2
tc(ADCLK)
(Note)
Conversion time
Ladder resistor
Reference power source input current
–
tCONV
RLADDER
IVREF
kΩ
µA
Table 25 D-A converter characteristics
(VCC = 2.7 to 5.5 V, VCC = VREF, VSS = AVSS = 0 V, Ta = –20 to 85°C, in middle/high-speed mode unless otherwise noted)
Symbol Parameter Limits
Min. Unit
Typ. Max.
Test conditions
–Resolution VCC = VREF = 5 V
VCC = VREF = 2.7 V
1
Bits
%
%
µs
kΩ
mA
3
2.5
8
1.0
2.0
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding currents flowing through
the A-D resistance ladder.
(Note)
Setting time
Output resistor
–
tsu
RO4
3.2
12
50
Absolute accuracy
Analog port input currentIIA
IVREF Reference power source input current
µA
100
200
5.0
VREF = 5 V
Table 24 A-D converter characteristics
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, f(XIN) = 500 kHz to 8 MHz, in middle/high-speed mode unless otherwise noted)
10-bit A-D mode (when conversion mode selection bit (bit 0 of address 0014 16) is “0”)
49 50
Symbol Parameter Limits
Min. Unit
Typ. Max.
Test conditions
–Resolution
Absolute accuracy
(excluding quantization error) VCC = VREF = 2.7 to 5.5 V Bits
LSB
35
150
10
±4
tc(ADCLK)
(Note)
Conversion time
Ladder resistor
Reference power source input current
–
tCONV
RLADDER
IVREF
kΩ
µA
12
50
Analog port input currentIIA µA
100
200
5.0
VREF = 5 V
61 62
Note: ADCLK is the control clock of the A-D converter. System clock
φ
is used.
Note: ADCLK is the control clock of the A-D converter. System clock
φ
is used.
68
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7560 Group
MITSUBISHI MICROCOMPUTERS
Table 26 Timing requirements 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
2
125
45
40
250
105
105
80
80
800
370
370
220
100
1000
400
400
200
200
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT2 input “H” pulse width
INT0 to INT2 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
Serial I/O2 input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
t
su(R
X
D–S
CLK1
)
th(SCLK1–RXD)
tc(SCLK2)
twH(SCLK2)
twL(SCLK2)
t
su(S
IN2
–S
CLK2
)
th(SCLK2–SIN2)
Symbol Parameter Limits
Min. µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
Table 27 Timing requirements 2 (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
2
125
45
40
900/(VCC-0.4)
tc(CNTR)/2–20
tc(CNTR)/2–20
230
230
2000
950
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT2 input “H” pulse width
INT0 to INT2 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK1)
twH(SCLK1)
Symbol Parameter Limits
Min. µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
t
su(S
IN2
–S
CLK2
)
th(SCLK2–SIN2)
twL(SCLK1)
t
su(R
X
D–S
CLK1
)
th(SCLK1–RXD)
tc(SCLK2)
twH(SCLK2)
twL(SCLK2)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
Serial I/O2 input hold time
950
400
200
2000
950
950
400
300
ns
ns
ns
ns
ns
ns
ns
ns
69
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
Table 28 Switching characteristics 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
140
30
30
0.2 ✕ tC (SCLK2)
40
30
30
Symbol Parameter Limits
Min. ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
tC (SCLK1)/2–30
tC (SCLK1)/2–30
–30
10
10
Typ. Max.
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK2
–S
OUT2
)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Table 29 Switching characteristics 2 (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
350
50
50
0.2 ✕ tC (SCLK2)
50
50
50
Symbol Parameter Limits
Min.
tC (SCLK1)/2–50
tC (SCLK1)/2–50
–30
20
20
Max.
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK2
–S
OUT2
)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Typ.
tC (SCLK2)/2–160
tC (SCLK2)/2–160
0
t
C
(S
CLK2
)/2–240
t
C
(S
CLK2
)/2–240
0
70
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7560 Group
MITSUBISHI MICROCOMPUTERS
V
V
“H” input voltage P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
“H” input voltage P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
RESET
XIN
“L” input voltage P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
“L” input voltage P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
RESET
XIN
“H” input voltage
“H” input voltage
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
“L” input voltage
“L” input voltage
0.7 VCC
0.8 VCC
0.8 VCC
0.8 VCC
0
0
0
0
VCC
VCC
VCC
VCC
0.3 VCC
0.2 VCC
0.2 VCC
0.2 VCC
V
V
V
V
V
V
ELECTRICAL CHARACTERISTICS (EPROM or One Time PROM version)
ABSOLUTE MAXIMUM RATINGS (EPROM or One Time PROM version)
Table 30 Absolute maximum ratings (EPROM or One Time PROM version)
RECOMMENDED OPERATING CONDITIONS (EPROM or One Time PROM version)
Table 31 Recommended operating conditions (1) (EPROM or One Time PROM version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Power source voltage
A-D, D-A conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
5.5
5.5
5.5
VCC
VCC
VCC
VSS
VREF
AVSS
VIA
Symbol Parameter Limits
Min.
V
V
V
V
V
Unit
4.0
2.5
2.5
2.0
AVSS
5.0
5.0
5.0
0
0
Typ. Max.
Power source voltage
VO
VO
VO
Pd
Topr
Tstg
–0.3 to 7.0 V
Power source voltage
Input voltage P00–P07, P10–P17, P20–P27,
P40–P47, P50–P57, P60–P67
Input voltage P70–P77
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage C1, C2
Input voltage RESET, XIN
Output voltage C1, C2
VCC
VI
Symbol Parameter Conditions Ratings Unit
All voltages are based on VSS.
Output transistors are cut off.
VI
VI
VI
VI
VI
VI
VO
VO
VO
Output voltage P00–P07, P10–P15, P30–P37
Output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77
Output voltage VL3
Output voltage VL2, SEG0–SEG17
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
At output port
At segment output
Ta = 25°C
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
VL2 to 7.0
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to VCC
–0.3 to VL3
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to VL3
–0.3 to VCC +0.3
300
–20 to 85
–40 to 125
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mW
°C
°C
High-speed mode f(XIN) = 8 MHz
Middle-speed mode f(XIN) = 8 MHz
Low-speed mode
71
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P40, P71–P77 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P40, P71–P77 (Note 1)
P00–P07, P10–P15, P30–P37 (Note 2)
“H” peak output current P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 2)
P00–P07, P10–P15, P30–P37 (Note 2)
“L” peak output current P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 2)
P40, P71–P77 (Note 2)
P00–P07, P10–P15, P30–P37 (Note 3)
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 3)
P00–P07, P10–P15, P30–P37 (Note 3)
“L” average output current P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 3)
P40, P71–P77 (Note 3)
–20
–20
20
20
80
–10
–10
10
10
40
–1.0
Table 32 Recommended operating conditions (2) (EPROM or One Time PROM version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Notes1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“L” total average output current
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
Symbol Parameter Limits
Min. mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Unit
Typ. Max.
“H” peak output current
“L” peak output current
“L” peak output current
“H” average output current
“H” average output current
“L” average output current
“L” average output current
IOH(peak)
IOL(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
–5.0
5.0
10
20
–0.5
–2.5
2.5
5.0
mA
mA
mA
mA
mA
mA
mA
mA
Table 33 Recommended operating conditions (3) (EPROM or One Time PROM version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Notes1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
Input frequency for timers X and Y
(duty cycle 50%)
f(CNTR0)
f(CNTR1)
Symbol Parameter Limits
Min. MHz
Unit
Typ. Max.
(4.0 V ≤ VCC ≤ 5.5 V)
32.768
4.0
Main clock input oscillation frequency
(Note 1)
Sub-clock input oscillation frequency (Notes 1, 2)
f(XIN)
f(XCIN)
(VCC ≤ 4.0 V)
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
High-speed mode
(2.5 V ≤ VCC ≤ 4.0 V)
Middle-speed mode
(2✕VCC)
–4
8.0
(4✕VCC)
–8
8.0
50
MHz
MHz
MHz
MHz
kHz
Test conditions
IOL(avg) 10 mA
72
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7560 Group
MITSUBISHI MICROCOMPUTERS
VCC = 5.0 V, VO = VCC, Pullup ON
Output transistors “off”
VCC = 2.5 V,VO = VCC, Pullup ON
Output transistors “off”
IOL = 10 mA
IOL = 3.0 mA
IOL = 2.5 mA
VCC = 2.5 V
IOL = 5 mA
IOL = 1.5 mA
IOL = 1.25 mA
VCC = 2.5 V
VOL
IOH = –1 mA
IOH = –0.25 mA
VCC = 2.5 V
IOH = –5 mA
IOH = –1.5 mA
IOH = –1.25 mA
VCC = 2.5 V
VVCC–2.0
“H” output voltage
P00–P07, P10–P15, P30–P37
Symbol Parameter Limits
Min. Unit
0.5
Typ. Max.
Test conditions
VOH
2.0
0.5
ELECTRICAL CHARACTERISTICS (EPROM or One Time PROM version)
Table 34 Electrical characteristics (1) (EPROM or One Time PROM version)
(VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
IOL = 10 mA
IOL = 5 mA
VCC = 2.5 V
VI = VCC
VI = VCC
VI = VCC
VI = VSS
Pull-ups “off”
VCC = 5 V, VI = VSS
Pull-ups “on”
VCC = 2.5 V, VI = VSS
Pull-ups “on”
VI = VSS
VI = VSS
“H” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67 (Note 1)
“L” output voltage
P00–P07, P10–P15, P30–P37
“L” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67
“L” output voltage
P40, P71–P77
Hysteresis
INT0–INT2, ADT, CNTR0, CNTR1, P20–P27
Hysteresis SCLK, RXD, SIN2
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20–P27, P40–P47,
P50–P57, P60–P67, P70–P77
“H” input current RESET
“H” input current XIN
“L” input current
P00–P07,P10–P17, P20–P27,P41–P47,
P50–P57, P60–P67
“L” input current P40, P70–P77
“L” input current RESET
“L” input current XIN
Output load current
P30–P37
VOH
VOL
VOL
VT+ – VT–
VT+ – VT–
VT+ – VT–
IIH
IIH
IIH
IIL
IIL
IIL
ILOAD
VCC–2.0
VCC–0.5
–60.0
–6.0
0.5
0.5
4.0
–120.0
–25.0
–4.0
2.0
0.5
0.5
5.0
5.0
–5.0
–240.0
–45.0
–5.0
–5.0
–240.0
–45.0
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
IIL
VCC–0.8
VCC–0.8
V
V
V0.8
V0.8
0.3 V
µA
µA
µA
VO = VCC, Pullup OFF
Output transistors “off”
VO = VSS, Pullup OFF
Output transistors “off”
Output leak current
P30–P37
ILEAK 5.0
–5.0 µA
µA
–120.0
–25.0
–60.0
–6.0
73
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
Table 35 Electrical characteristics (2) (EPROM or One Time PROM version)
(VCC =2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
V
5.5
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter stop
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Symbol Parameter Limits
Min. Unit
Typ. Max.
Ta = 25 °C
Ta = 85 °C
Test conditions
ICC Power source current
6.4
VRAM RAM retention voltage At clock stop mode 2.0
When using voltage multiplier
VL1 = 1.8 V
VL1
IL1
Power source voltage
Power source current
(VL1) (Note)
Note: When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.
1.3
1.6
35
20
15
4.5
0.1
1.8
4.0
3.2
70
40
22
9.0
1.0
10
2.3
mA
µA
µA
µA
µA
µA
V
mA
13
µA
74
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7560 Group
MITSUBISHI MICROCOMPUTERS
A-D CONVERTER CHARACTERISTICS (EPROM or One Time PROM version)
Table 36 A-D converter characteristics (EPROM or One Time PROM version)
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, f(XIN) = 500 kHz to 8 MHz, in middle/high-speed mode unless otherwise noted)
8-bit A-D mode (when conversion mode selection bit (bit 0 of address 0014 16) is “1”)
Symbol Parameter Limits
Min. Unit
Typ. Max.
Test conditions
–Resolution
Absolute accuracy
(excluding quantization error) VCC = VREF = 2.7 to 5.5 V Bits
LSB
35
150
8
±2
tc(ADCLK)
(Note)
Conversion time
Ladder resistor
Reference power source input current
–
tCONV
RLADDER
IVREF
kΩ
µA
D-A CONVERTER CHARACTERISTICS (EPROM or One Time PROM version)
Table 38 D-A converter characteristics (EPROM or One Time PROM version)
(VCC = 2.7 to 5.5 V, VCC = VREF, VSS = AVSS = 0 V, Ta = –20 to 85°C, in middle/high-speed mode unless otherwise noted)
Symbol Parameter Limits
Min. Unit
Typ. Max.
Test conditions
–Resolution VCC = VREF = 5 V
VCC = VREF = 2.7 V
1
Bits
%
%
µs
kΩ
mA
3
2.5
8
1.0
2.0
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding currents flowing through
the A-D resistance ladder.
(Note)
Setting time
Output resistor
–
tsu
RO4
3.2
12
50
Absolute accuracy
Analog port input currentIIA
IVREF Reference power source input current
µA
100
200
5.0
VREF = 5 V
Table 37 A-D converter characteristics (EPROM or One Time PROM version)
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, f(XIN) = 500 kHz to 8 MHz, in middle/high-speed mode unless otherwise noted)
10-bit A-D mode (when conversion mode selection bit (bit 0 of address 0014 16) is “0”)
49 50
Symbol Parameter Limits
Min. Unit
Typ. Max.
Test conditions
–Resolution
Absolute accuracy
(excluding quantization error) VCC = VREF = 2.7 to 5.5 V Bits
LSB
35
150
10
±4
tc(ADCLK)
(Note)
Conversion time
Ladder resistor
Reference power source input current
–
tCONV
RLADDER
IVREF
kΩ
µA
12
50
Analog port input currentIIA µA
100
200
5.0
VREF = 5 V
61 62
Note: ADCLK is the control clock of the A-D converter. System clock
φ
is used.
Note: ADCLK is the control clock of the A-D converter. System clock
φ
is used.
75
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
TIMING REQUIREMENTS (EPROM or One Time PROM version)
Table 39 Timing requirements 1 (EPROM or One Time PROM version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
2
125
45
40
250
105
105
80
80
800
370
370
220
100
1000
400
400
200
200
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT2 input “H” pulse width
INT0 to INT2 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
Serial I/O2 input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
t
su(R
X
D–S
CLK1
)
th(SCLK1–RXD)
tc(SCLK2)
twH(SCLK2)
twL(SCLK2)
t
su(S
IN2
–S
CLK2
)
th(SCLK2–SIN2)
Symbol Parameter Limits
Min. µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
Table 40 Timing requirements 2 (EPROM or One Time PROM version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
2
125
45
40
500/(VCC-2)
250/(VCC-2)–20
250/(VCC-2)–20
230
230
2000
950
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT2 input “H” pulse width
INT0 to INT2 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK1)
twH(SCLK1)
Symbol Parameter Limits
Min. µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
t
su(S
IN2
–S
CLK2
)
th(SCLK2–SIN2)
twL(SCLK1)
t
su(R
X
D–S
CLK1
)
th(SCLK1–RXD)
tc(SCLK2)
twH(SCLK2)
twL(SCLK2)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
Serial I/O2 input hold time
950
400
200
2000
950
950
400
300
ns
ns
ns
ns
ns
ns
ns
ns
76
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7560 Group
MITSUBISHI MICROCOMPUTERS
SWITCHING CHARACTERISTICS (EPROM or One Time PROM version)
Table 41 Switching characteristics 1 (EPROM or One Time PROM version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
140
30
30
0.2 ✕ tC (SCLK2)
40
30
30
Symbol Parameter Limits
Min. ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
tC (SCLK1)/2–30
tC (SCLK1)/2–30
–30
10
10
Typ. Max.
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK2
–S
OUT2
)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Table 42 Switching characteristics 2 (EPROM or One Time PROM version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
350
50
50
0.2 ✕ tC (SCLK2)
50
50
50
Symbol Parameter Limits
Min.
tC (SCLK1)/2–50
tC (SCLK1)/2–50
–30
20
20
Max.
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK2
–S
OUT2
)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Typ.
tC (SCLK2)/2–160
tC (SCLK2)/2–160
0
t
C
(S
CLK2
)/2–240
t
C
(S
CLK2
)/2–240
0
77
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
ELECTRICAL CHARACTERISTICS (Extended operating temperature version)
ABSOLUTE MAXIMUM RATINGS (Extended operating temperature version)
Table 43 Absolute maximum ratings (Extended operating temperature version)
RECOMMENDED OPERATING CONDITIONS (Extended operating temperature version)
Table 44 Recommended operating conditions (1) (Extended operating temperature version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20 °C unless otherwise noted)
Power source voltage
A-D, D-A conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
5.5
5.5
5.5
5.5
5.5
VCC
VCC
VCC
VSS
VREF
AVSS
VIA
Symbol Parameter Limits
Min.
V
V
V
V
V
Unit
4.0
2.5
3.0
2.5
3.0
2.0
AVSS
5.0
5.0
5.0
5.0
5.0
0
0
Typ. Max.
Power source voltage
VO
VO
VO
Pd
Topr
Tstg
–0.3 to 6.5 V
Power source voltage (Note 1)
Input voltage P00–P07, P10–P17, P20–P27,
P40–P47, P50–P57, P60–P67
Input voltage P70–P77
Input voltage VL1
Input voltage VL2
Input voltage VL3 (Note 2)
Input voltage C1, C2 (Note 1)
Input voltage RESET, XIN
Output voltage C1, C2 (Note 1)
VCC
VI
Symbol Parameter Conditions Ratings Unit
All voltages are based on VSS.
Output transistors are cut off.
VI
VI
VI
VI
VI
VI
VO
VO
VO
Output voltage P00–P07, P10–P15, P30–P37
Output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77
Output voltage VL3 (Note 1)
Output voltage VL2, SEG0–SEG17
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
At output port
At segment output
Ta = 25°C
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
VL2 to 6.5
–0.3 to 6.5
–0.3 to VCC +0.3
–0.3 to 6.5
–0.3 to VCC
–0.3 to VL3
–0.3 to VCC +0.3
–0.3 to 6.5
–0.3 to VL3
–0.3 to VCC +0.3
300
–40 to 85
–65 to 150
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mW
°C
°C
High-speed mode f(XIN) = 8 MHz
Middle-speed mode Ta = –20 to 85 °C
f(XIN) = 8 MHz Ta = –40 to –20 °C
Low-speed mode Ta = –20 to 85 °C
Ta = –40 to –20 °C
Notes 1: –0.3 V to 7.0 V for M37560EFD.
2: VL2 to 7.0 V for M37560EFD
V
V
“H” input voltage P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
“H” input voltage P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
RESET
XIN
“L” input voltage P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
“L” input voltage P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
RESET
XIN
“H” input voltage
“H” input voltage
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
“L” input voltage
“L” input voltage
0.7 VCC
0.8 VCC
0.8 VCC
0.8 VCC
0
0
0
0
VCC
VCC
VCC
VCC
0.3 VCC
0.2 VCC
0.2 VCC
0.2 VCC
V
V
V
V
V
V
78
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7560 Group
MITSUBISHI MICROCOMPUTERS
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P40, P71–P77 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P40, P71–P77 (Note 1)
P00–P07, P10–P15, P30–P37 (Note 2)
“H” peak output current P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 2)
P00–P07, P10–P15, P30–P37 (Note 2)
“L” peak output current P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 2)
P40, P71–P77 (Note 2)
P00–P07, P10–P15, P30–P37 (Note 3)
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 3)
P00–P07, P10–P15, P30–P37 (Note 3)
“L” average output current P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 3)
P40, P71–P77 (Note 3)
–20
–20
20
20
80
–10
–10
10
10
40
–1.0
Table 45 Recommended operating conditions (2) (Extended operating temperature version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20 °C, unless otherwise noted)
Notes1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“L” total average output current
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
Symbol Parameter Limits
Min. mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Unit
Typ. Max.
“H” peak output current
“L” peak output current
“L” peak output current
“H” average output current
“H” average output current
“L” average output current
“L” average output current
IOH(peak)
IOL(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
–5.0
5.0
10
20
–0.5
–2.5
2.5
5.0
mA
mA
mA
mA
mA
mA
mA
mA
Table 46 Recommended operating conditions (3) (Extended operating temperature version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20 °C, unless otherwise noted)
Notes1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
Input frequency for timers X and Y
(duty cycle 50%)
f(CNTR0)
f(CNTR1)
Symbol Parameter Limits
Min. MHz
Unit
Typ. Max.
(4.0 V ≤ VCC ≤ 5.5 V)
32.768
4.0
Main clock input oscillation frequency
(Note 1)
Sub-clock input oscillation frequency (Notes 1, 2)
f(XIN)
f(XCIN)
(VCC ≤ 4.0 V)
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
High-speed mode
(VCC ≤ 4.0 V)
Middle-speed mode
(2✕VCC)
–4
8.0
(4✕VCC)
–8
8.0
50
MHz
MHz
MHz
MHz
kHz
Test conditions
IOL(avg) 10 mA
79
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
VCC = 5.0 V, VO = VCC, Pullup ON
Output transistors “off”
VCC = 3.0 V,VO = VCC, Pullup ON
Output transistors “off”
IOL = 10 mA
IOL = 3.0 mA
IOL = 3.0 mA
VCC = 3.0 V
IOL = 5 mA
IOL = 1.5 mA
IOL = 1.25 mA
VCC = 3.0 V
VOL
IOH = –1 mA
IOH = –0.25 mA
VCC = 3.0 V
IOH = –5 mA
IOH = –1.5 mA
IOH = –1.25 mA
VCC = 3.0 V
VVCC–2.0
“H” output voltage
P00–P07, P10–P15, P30–P37
Symbol Parameter Limits
Min. Unit
0.5
Typ. Max.
Test conditions
VOH
2.0
0.5
ELECTRICAL CHARACTERISTICS (Extended operating temperature version)
Table 47 Electrical characteristics (1) (VCC =4.0 to 5.5 V, Ta = –40 to 85°C, unless otherwise noted)
IOL = 10 mA
IOL = 5 mA
VCC = 3.0 V
VI = VCC
VI = VCC
VI = VCC
VI = VSS
Pull-ups “off”
VCC = 5 V, VI = VSS
Pull-ups “on”
VCC = 3.0 V, VI = VSS
Pull-ups “on”
VI = VSS
VI = VSS
“H” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67 (Note 1)
“L” output voltage
P00–P07, P10–P15, P30–P37
“L” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67
“L” output voltage
P40, P71–P77
Hysteresis
INT0–INT2, ADT, CNTR0, CNTR1, P20–P27
Hysteresis SCLK, RXD, SIN2
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20–P27, P40–P47,
P50–P57, P60–P67, P70–P77
“H” input current RESET
“H” input current XIN
“L” input current
P00–P07,P10–P17, P20–P27,P41–P47,
P50–P57, P60–P67
“L” input current P40, P70–P77
“L” input current RESET
“L” input current XIN
Output load current
P30–P37
VOH
VOL
VOL
VT+ – VT–
VT+ – VT–
VT+ – VT–
IIH
IIH
IIH
IIL
IIL
IIL
ILOAD
VCC–2.0
VCC–0.5
–60.0
–7.0
0.5
0.5
4.0
–120.0
–30.0
–4.0
2.0
0.5
0.5
5.0
5.0
–5.0
–240.0
–55.0
–5.0
–5.0
–240.0
–55.0
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
IIL
VCC–1.0
VCC–1.0
V
V
V1.0
V1.0
0.4 V
µA
µA
µA
VO = VCC, Pullup OFF
Output transistors “off”
VO = VSS, Pullup OFF
Output transistors “off”
Output leak current
P30–P37
ILEAK 5.0
–5.0 µA
µA
–120.0
–30.0
–60.0
–7.0
80
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7560 Group
MITSUBISHI MICROCOMPUTERS
Table 48 Electrical characteristics (2) (Extended operating temperature version)
(VCC =2.5 to 5.5 V, Ta = –20 to 85°C, and VCC =3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted)
V
5.5
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter stop
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Symbol Parameter Limits
Min. Unit
Typ. Max.
Test conditions
ICC Power source current
6.4
VRAM RAM retention voltage At clock stop mode 2.0
When using voltage multiplier
VL1 = 1.8 V
VL1
IL1
Power source voltage
Power source current
(VL1) (Note)
Note: When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.
1.3
1.3
1.6
35
20
15
4.5
0.1
1.8
1.8
4.0
3.2
70
40
22
9.0
1.0
10
2.1
2.3
mA
µA
µA
µA
µA
µA
V
mA13
µA
Ta = 25 °C
Ta = 85 °C
M37560MFD
M37560EFD
81
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
A-D CONVERTER CHARACTERISTICS (Extended operating temperature version)
Table 49 A-D converter characteristics (Extended operating temperature version)
(VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –40 to 85°C, f(XIN) = 500 kHz to 8 MHz, in middle/high-speed mode unless otherwise noted)
8-bit A-D mode (when conversion mode selection bit (bit 0 of address 0014 16) is “1”)
Symbol Parameter Limits
Min. Unit
Typ. Max.
Test conditions
–Resolution
Absolute accuracy
(excluding quantization error) VCC = VREF = 3.0 to 5.5 V Bits
LSB
35
150
8
±2
tc(ADCLK)
(Note)
Conversion time
Ladder resistor
Reference power source input current
–
tCONV
RLADDER
IVREF
kΩ
µA
D-A CONVERTER CHARACTERISTICS (Extended operating temperature version)
Table 51 D-A converter characteristics (Extended operating temperature version)
(VCC = 3.0 to 5.5 V, VCC = VREF, VSS = AVSS = 0 V, Ta = –40 to 85°C, in middle/high-speed mode unless otherwise noted)
Symbol Parameter Limits
Min. Unit
Typ. Max.
Test conditions
–Resolution VCC = VREF = 5 V
VCC = VREF = 3.0 V
1
Bits
%
%
µs
kΩ
mA
3
2.5
8
1.0
2.0
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding currents flowing through
the A-D resistance ladder.
(Note)
Setting time
Output resistor
–
tsu
RO4
3.2
12
50
Absolute accuracy
Analog port input currentIIA
IVREF Reference power source input current
µA
100
200
5.0
VREF = 5 V
Table 50 A-D converter characteristics (Extended operating temperature version)
(VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –40 to 85°C, f(XIN) = 500 kHz to 8 MHz, in middle/high-speed mode unless otherwise noted)
10-bit A-D mode (when conversion mode selection bit (bit 0 of address 0014 16) is “0”)
49 50
Symbol Parameter Limits
Min. Unit
Typ. Max.
Test conditions
–Resolution
Absolute accuracy
(excluding quantization error) VCC = VREF = 3.0 to 5.5 V Bits
LSB
35
150
10
±4
tc(ADCLK)
(Note)
Conversion time
Ladder resistor
Reference power source input current
–
tCONV
RLADDER
IVREF
kΩ
µA
12
50
Analog port input currentIIA µA
100
200
5.0
VREF = 5 V
61 62
Note: ADCLK is the control clock of the A-D converter. System clock
φ
is used.
Note: ADCLK is the control clock of the A-D converter. System clock
φ
is used.
82
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7560 Group
MITSUBISHI MICROCOMPUTERS
TIMING REQUIREMENTS (Extended operating temperature version)
Table 52 Timing requirements 1 (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, unless otherwise noted)
2
125
45
40
250
105
105
80
80
800
370
370
220
100
1000
400
400
200
200
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT2 input “H” pulse width
INT0 to INT2 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
Serial I/O2 input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
t
su(R
X
D–S
CLK1
)
th(SCLK1–RXD)
tc(SCLK2)
twH(SCLK2)
twL(SCLK2)
t
su(S
IN2
–S
CLK2
)
th(SCLK2–SIN2)
Symbol Parameter Limits
Min. µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
Table 53 Timing requirements 2 (Extended operating temperature version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted)
2
125
45
40
500/(VCC-2)
250/(VCC-2)–20
250/(VCC-2)–20
230
230
2000
950
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT2 input “H” pulse width
INT0 to INT2 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK1)
twH(SCLK1)
Symbol Parameter Limits
Min. µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
t
su(S
IN2
–S
CLK2
)
th(SCLK2–SIN2)
twL(SCLK1)
t
su(R
X
D–S
CLK1
)
th(SCLK1–RXD)
tc(SCLK2)
twH(SCLK2)
twL(SCLK2)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
Serial I/O2 input hold time
950
400
200
2000
950
950
400
300
ns
ns
ns
ns
ns
ns
ns
ns
83
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
SWITCHING CHARACTERISTICS (Extended operating temperature version)
Table 54 Switching characteristics 1 (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, unless otherwise noted)
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
140
30
30
0.2 ✕ tC (SCLK2)
40
30
30
Symbol Parameter Limits
Min. ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
tC (SCLK1)/2–30
tC (SCLK1)/2–30
–30
10
10
Typ. Max.
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK2
–S
OUT2
)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Table 55 Switching characteristics 2 (Extended operating temperature version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
350
50
50
0.2 ✕ tC (SCLK2)
50
50
50
Symbol Parameter Limits
Min.
tC (SCLK1)/2–50
tC (SCLK1)/2–50
–30
20
20
Max.
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK2
–S
OUT2
)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Typ.
tC (SCLK2)/2–160
tC (SCLK2)/2–160
0
t
C
(S
CLK2
)/2–240
t
C
(S
CLK2
)/2–240
0
Fig. 69 Circuit for measuring output switching characteristics
M
easurement output p
i
n
1
0
0
p
F
C
M
O
S
o
u
t
p
u
t
N
o
t
e
:
W
h
e
n
P
7
1
–
P
7
7
,
P
4
0
a
n
d
b
i
t
4
o
f
t
h
e
U
A
R
T
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
0
0
1
B
1
6
)
i
s
“
1
”
(
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
m
o
d
e
)
.
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
(
N
o
t
e
)
1
k
Ω
1
0
0
p
F
M
easurement output p
i
n
84
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7560 Group
MITSUBISHI MICROCOMPUTERS
Fig. 70 Timing diagram
I
N
T
0
–
I
N
T
2
C
N
T
R
0
,
C
N
T
R
1
0.2V
CC
t
W
L
(
I
N
T
)
0.8V
CC
t
WH(INT)
0.2V
CC
0.2V
CC
0.8V
CC
0.8V
CC
0.2V
CC
t
W
L
(
XI
N)
0.8V
CC
t
WH(XIN)
t
C(XIN)
X
I
N
0.2V
CC
0
.
8
V
C
C
t
W(RESET)
RESET
t
f
t
r
0
.
2
V
C
C
t
WL(CNTR)
0
.
8
V
C
C
t
WH(CNTR)
t
C(CNTR)
t
d
(
SC
L
K
1-
TXD
)
,
t
d
(
SC
L
K
2
-SO
U
T
2)
t
v(SCLK1-TXD),
t
v(SCLK2-SOUT2)
t
C(SCLK1),
t
C(SCLK2)
t
WL(SCLK1),
t
WL(SCLK2)
t
WH(SCLK1),
t
WH(SCLK2)
th
(SCLK1-RXD),
th
(SCLK2-SIN2)
t
su(RXD-SCLK1),
t
su(SIN2-SCLK2)
T
X
D
S
OUT2
R
X
D
S
IN2
S
CLK1
S
CLK2
85
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
PACKAGE OUTLINE
LQFP100-P-1414-0.50 Weight(g)
–0.63
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
100P6Q-A
Plastic 100pin 14✕14mm body LQFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.225 ––
I
2
0.9 ––
M
D
14.4 ––
M
E
14.4
10°0°0.1
1.0 0.70.50.3 16.216.015.8 16.216.015.8 0.5 14.114.013.9 14.114.013.9 0.1750.1250.105 0.280.180.13 1.4
01.7
e
e
E
H
E
1
76
75
51
5026
25
H
D
D
A
F
y
100
Lp
0.45
–
–
0.6
0.25
–
0.75
–
0.08
x
A3
b
x
M
A
1
A
2
L
1
L
Detail F
Lp
A3
c
M
D
l
2
b
2
M
E
e
Recommended Mount Pad
MMP
QFP100-P-1420-0.65 1.58
Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Alloy 42
100P6S-A Plastic 100pin 14✕20mm body QFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A2
b
c
D
E
HE
L
L1
y
b2
Dimension in Millimeters
HD
A1
0.35 ––
I21.3 ––
MD14.6 ––
ME20.6
10°0°0.1
1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.65 20.220.019.8 14.214.013.8 0.20.150.13 0.40.30.25 2.8
03.05
e
e
e
E
c
HE
1
30
31
81
50
80
51
HD
D
MD
ME
A
F
A1A2
L1
L
y
b2
I2
Recommended Mount Pad
Detail F
100
x––0.13
bxM
MMP
© 2003 MITSUBISHI ELECTRIC CORP.
Specifications subject to change without notice.
Notes regarding these materials
• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, origina ting in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
• All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by
Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
• When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision
on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved
destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7560 Group
MITSUBISHI MICROCOMPUTERS
REVISION HISTORY 7560 GROUP DATA SHEET
Rev. Date Description
Page Summary
(1/3)
1.0 03/28/01
1.1 06/08/01
1.2 12/05/01
First Edition
Table 13 VREF Min. VCC+0.3 → VCC
• A-D converter; 8 bits → 10 bits
• Power source voltage; value at EPROM and One Time PROM version and at
extended operating temperature version added.
• Power dissipation;
In high-speed mode: 40 → 32 mW, In low-speed mode: 60 → 45 µW
• Operating temperature range; value at extended temperature version added.
Table 1; VCC, VSS: voltage valued at EPROM and One Time PROM version and at
extended operating temperature version added.
Fig. 4; Description about EPROM and One Time PROM version and extended
operating temperature version added.
Fig. 5; Under development → Mass product
GROUP EXPANSION for EPROM and One Time PROM version added.
GROUP EXPANSION for extended operating temperature version added.
Fig. 12; Reserved area: Note added.
Address 001416: Reserved area → A-D conversion register (ADL).
Address 003516: A-D conversion register (AD) → A-D conversion register (ADH)
Fig. 21; P52, P53, P43 revised.
[A-D Conversion Register (ADH, ADL)] 003516, 001416 revised.
Comparison Voltage Generator revised.
Fig. 38 revised.
Voltage Multiplier; 2.1 V → 2.1 V (2.3 V for EPROM and One Time PROM version)
Fig. 53; (9) AD conversion register (low-order) added.
Oscillation Control; (1) Stop mode revised.
DATA REQUIRED FOR MASK ORDERS; URL: mesc → maec
ROM PROGRAMMING METHOD added.
IOH (avg); (Note 3) added.
Table 22; ICC value revised.
Table 23; Note added. Conversion time revised.
Table 24; A-D converter characteristics at 10-bit A-D mode added.
Table 27; tc (CNTR) revised.
ELECTRICAL CHARACTERISTICS (EPROM and One Time PROM version) and
ELECTRICAL CHARACTERISTICS (Extended operating temperature version) added.
52
1
4
6
7
8
9
15
26
38
42
49
50
54
57
60
61
62
64 to 77
2.0 01/28/03 1
4
5
14
“●Interrupts” of “FEATURES” is partly added.
Table 1 is partly revised.
Table 2 is partly revised.
Figure 11 is partly revised.
REVISION HISTORY 7560 GROUP DATA SHEET
Rev. Date Description
Page Summary
(2/3)
2.0 01/28/03 15
16
16
16
16
20
21
22
23
24
25
26
26
27
27
28
29
30
30
31
31
32
32
34
36
36
37
40
40
41
42
43
46
50
51
52
52
54
55
Figure 12 is partly revised.
Explanations of “Direcion Registers” of “I/O PORTS” are partly revised.
Explanations of “Pull-up Control” of “I/O PORTS” are partly revised.
Figure 13 is added.
Figure 14 is added.
Figure 16 is partly revised.
Figure 17 is partly revised.
Figure 18 is partly revised.
Figure 19 is partly revised.
Explanations of “INTERRUPTS” are partly added.
Explanations of “■Notes on interrupts” are partly revised.
Explanations of “Key Input Interrupt (Key-on Wake Up)” are partly revised.
Figure 22 is partly revised.
Explanations of “Key Input Interrupt (Key-on Wake Up)” are added.
Figure 23 is added.
Figure 24 is partly revised.
Explanations of “Timer X” are partly added.
Explanations of “Timer Y” are partly added.
Explanations of “(2) Period measurement mode” of “Timer Y” are partly revised.
Explanations of “Timer 1, Timer 2, Timer 3” are partly added.
Explanations of “●Timer 2 Write Control” are partly added,
Explanations of “(1) Clock Synchronous Serial I/O Mode” are partly added.
Note of Figure 29 is partly added.
Explanations of “[UART Control Register (UARTON)] are partly revised.
Explanations of “Serial I/O2” are partly added.
Explanations of “[Serial I/O2 Control Register (SIO2CON)]” are partly added.
“●Serial I/O2 Operating” is added.
Explanations of “[A-D Control Register (ADCON)]” are partly added.
Figure 40 is partly added.
Figure 42 is partly added.
Figure 44 is partly added.
Figure 45 is added.
Explanations of “Voltage Multiplier (3 Times)” are partly revised.
Explanation of “Watchdog Timer” are partly revised.
Figure 55 is partly revised.
Explanations of “RESET CIRCUIT” are partly revised.
Figure 56 is partly revised.
Explanations of “(2) Wait mode” are partly revised.
Figure 61 is partly revised.
REVISION HISTORY 7560 GROUP DATA SHEET
Rev. Date Description
Page Summary
(3/3)
2.0 01/28/03 56
57
57
58, 59
67
67
74
74
81
81
All pages
Figure 62 is partly revised.
Explanations of “Interrupt” of “NOTES ON PROGRAMMING” are partly revised.
“Timers” of “NOTES ON PROGRAMMING”of Rev. 1.2 is eliminated.
“Countermeasures Against Noise” is added.
Table 23 is partly revised.
Table 24 is partly revised.
Table 36 is partly revised.
Table 37 is partly revised.
Table 49 is partly revised.
Table 50 is partly revised.
Text expressions are improved.