SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E - JULY 1995 - REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages OEA LE1B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 LE2B SEL description This 12-bit to 24-bit multiplexed D-type latch is designed for 1.65-V to 3.6-VCC operation. The SN74ALVCH16260 is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory-interleaving applications. Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank control in the A-to-B direction. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 OE2B LEA2B 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 LEA1B OE1B Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16260 is characterized for operation from -40C to 85C. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3-35 SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E - JULY 1995 - REVISED FEBRUARY 1999 Function Tables B TO A (OEB = H) INPUTS 1B 2B SEL LE1B LE2B OEA OUTPUT A H X H H X L H L X H H X L L X X H L X L X H L X H L A0 H X L L X H L L X X L X L L X X X X X H A0 Z A TO B (OEA = H) INPUTS 3-36 LEA2B OUTPUTS A LEA1B OE1B OE2B 1B 2B H H H L H H L L H H L L L H H L L L L H 2B0 2B0 L H L L L L H L H L L 1B0 1B0 H 2B0 Z L L H L L X L L L L X X X H H 1B0 Z X X X L H Active Z X X X H L Z Active X X X L L Active Active POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 L SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E - JULY 1995 - REVISED FEBRUARY 1999 logic diagram (positive logic) LE1B LE2B LEA1B LEA2B OE2B OE1B OEA SEL A1 2 27 30 55 56 29 1 28 G1 C1 1 1D 8 23 1B1 1 C1 1D 6 2B1 C1 1D C1 1D To 11 Other Channels POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3-37 SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E - JULY 1995 - REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL VI VO IOH Low-level input voltage MIN MAX 1.65 3.6 2 0.35 x VCC 0.7 0 0 IOL Low-level output current t/v Input transition rise or fall rate VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V V 0.8 Output voltage VCC = 2.7 V VCC = 3 V V 1.7 Input voltage High-level output current V 0.65 x VCC VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V VCC = 2.3 V UNIT VCC VCC V V -4 -12 -12 mA -24 4 12 12 mA 24 10 ns/V TA Operating free-air temperature -40 85 C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3-38 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E - JULY 1995 - REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = -100 A IOH = -4 mA 1.65 V IOH = -6 mA VOH IOH = -12 mA IOH = -24 mA IOL = 100 A UNIT VCC-0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.6 V 5 IOL = 24 mA VI = VCC or GND II(hold) MAX 1.65 V IOL = 12 mA II TYP 1.65 V to 3.6 V IOL = 4 mA IOL = 6 mA VOL MIN VI = 0.58 V VI = 1.07 V 1.65 V 25 1.65 V -25 VI = 0.7 V VI = 1.7 V 2.3 V 45 2.3 V -45 VI = 0.8 V VI = 2 V 3V 75 3V -75 V A A VI = 0 to 3.6 V 3.6 V 500 IOZ ICC VO = VCC or GND VI = VCC or GND, 3.6 V 10 A 40 A ICC Ci One input at VCC - 0.6 V, 750 A Control inputs IO = 0 Other inputs at VCC or GND 3.6 V 3 V to 3.6 V VI = VCC or GND VO = VCC or GND 3.3 V 3.5 pF Cio A or B ports 3.3 V 9 pF All typical values are at VCC = 3.3 V, TA = 25C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. For I/O ports, the parameter IOZ includes the input leakage current. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V tw Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high tsu Setup time, data before LE1B, LE2B, LEA1B, or LEA2B th Hold time, data after LE1B, LE2B, LEA1B, or LEA2B This information was not available at the time of publication. MIN MAX VCC = 2.5 V 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V 0.3 V MIN UNIT MAX 3.3 3.3 3.3 ns 1.4 1.1 1.1 ns 1.6 1.9 1.5 ns POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3-39 SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E - JULY 1995 - REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER FROM (INPUT) TO (OUTPUT) A or B tpd ten VCC = 1.8 V VCC = 2.5 V 0.2 V MIN MAX B or A TYP 1 VCC = 2.7 V MIN VCC = 3.3 V 0.3 V MAX MIN MAX 5.4 5.1 1.2 4.3 UNIT LE A or B 1 5.6 5.2 1 4.4 SEL A 1 6.9 6.6 1.1 5.6 OE A or B 1 6.7 6.4 1 5.4 ns 1 5.7 5 1.3 4.6 ns tdis A or B OE This information was not available at the time of publication. ns operating characteristics, TA = 25C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS All outputs enabled All outputs disabled CL = 50 pF, VCC = 1.8 V TYP f = 10 MHz This information was not available at the time of publication. 3-40 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 VCC = 2.5 V TYP VCC = 3.3 V TYP 37 41 4 7 UNIT pF SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E - JULY 1995 - REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 2 x VCC S1 1 k From Output Under Test Open GND CL = 30 pF (see Note A) 1 k TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 x VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3-41 SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E - JULY 1995 - REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V 2 x VCC S1 500 From Output Under Test Open GND CL = 30 pF (see Note A) 500 TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 x VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 3-42 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E - JULY 1995 - REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V 0.3 V 6V S1 500 From Output Under Test Open GND CL = 50 pF (see Note A) 500 TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) 2.7 V 1.5 V 0V tPZL 2.7 V Input 1.5 V 1.5 V 0V tPLH VOH Output 1.5 V Output Waveform 1 S1 at 6 V (see Note B) tPLZ 3V 1.5 V tPZH tPHL 1.5 V VOL 1.5 V Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3-43