1
Data sheet acquired from Harris Semiconductor
SCHS154A
Features
• ’HC161, ’HCT161 4-Bit Binary Counter,
Asynchronous Reset
• ’HC163, ’HCT163 4-Bit Binary Counter,
Synchronous Reset
• Synchronous Counting and Loading
• Two Count Enable Inputs for n-Bit Cascading
• Look-Ahead Carry for High-Speed Counting
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Description
The ’HC161, ’HCT161, ’HC163, and ’HCT163 are
presettable synchronous counters that feature look-ahead
carry logic for use in high-speed counting applications. The
’HC161 and ’HCT161 are asynchronous reset decade and
binary counters, respectively; the ’HC163 and ’HCT163
devices are decade and binary counters, respectively, that
are reset synchronously with the clock. Counting and
parallel presetting are both accomplished synchronously
with the negative-to-positive transition of the clock.
A low level on the synchronous parallel enable input, SPE,
disables counting operation and allows data at the P0 to P3
inputs to be loaded into the counter (provided that the
setup and hold requirements for SPE are met).
All counters are reset with a low level on the Master Reset
input, MR. In the ’HC163 and ’HCT163 counters
(synchronous reset types), the requirements for setup and
hold time with respect to the clock must be met.
Two count enables, PE and TE, in each counter are
provided for n-bit cascading. In all counters reset action
occurs regardless of the level of the SPE, PE and TE inputs
(and the clock input, CP, in the ’HC161 and ’HCT161
types).
If a decade counter is preset to an illegal state or assumes
an illegal state when power is applied, it will return to the
normal sequence in one count as shown in state diagram.
The look-ahead carry feature simplifies serial cascading of
the counters. Both count enable inputs (PE and TE) must
be high to count. The TE input is gated with the Q outputs
of all four stages so that at the maximum count the terminal
count (TC) output goes high for one clock period. This TC
pulse is used to enable the next cascaded stage.
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC161F -55 to 125 16 Ld CERDIP
CD54HC161F3A -55 to 125 16 Ld CERDIP
CD74HC161E -55 to 125 16 Ld PDIP
CD74HC161M -55 to 125 16 Ld SOIC
CD54HCT161F3A -55 to 125 16 Ld CERDIP
CD74HCT161E -55 to 125 16 Ld PDIP
CD74HCT161M -55 to 125 16 Ld SOIC
CD54HC163F3A -55 to 125 16 Ld CERDIP
CD74HC163E -55 to 125 16 Ld PDIP
CD74HC163M -55 to 125 16 Ld SOIC
CD54HCT163F -55 to 125 16 Ld CERDIP
CD54HCT163F3A -55 to 125 16 Ld CERDIP
CD74HCT163E -55 to 125 16 Ld PDIP
CD74HCT163M -55 to 125 16 Ld SOIC
NOTES:
1. Whenordering,usetheentirepartnumber.Addthesuffix96toob-
tain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local TI sales office or cus-
tomer service for ordering information.
February 1998 - Revised May 2000
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2000, Texas Instruments Incorporated
CD54/74HC161, CD54/74HCT161,
CD54/74HC163, CD54/74HCT163
High Speed CMOS Logic
Presettable Counters
[ /Title
(CD74
HC161
,
CD74
HCT16
1,
CD74
HC163
,
CD74
HCT16
3)
/Sub-
ject
(High
Speed
CMOS
Logic
Preset-
table
Counte
rs)
/Autho
r ()
/Key-
words
(High
Speed
CMOS
Logic
Preset-
table
Counte
rs,
High
Speed
2
Pinout
CD54HC161, CD54HCT161, CD54HC163, CD54HCT163
(CERDIP)
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
(PDIP, SOIC)
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
MR
CP
P0
P1
P2
P3
GND
PE
VCC
Q0
Q1
Q2
Q3
TE
SPE
TC
SPE
CP
MR
PE
TE
9
2
1
7
10
3456
14
13
12
11
15
Q0
Q1
Q2
Q3
TC
P0 P1 P2 P3
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
3
MODE SELECT - FUNCTION TABLE FOR ’HC161 AND ’HCT161
OPERATING MODE
INPUTS OUTPUTS
MR CP PE TE SPE PnQnTC
Reset (Clear) L XXXXXLL
Parallel Load H ↑XX l l LL
H↑X X l h H (Note 3)
Count H ↑h h h (Note 5) X Count (Note 3)
Inhibit H X I (Note 4) X h (Note 5) X qn(Note 3)
H X X I (Note 4) h (Note 5) X qnL
MODE SELECT - FUNCTION TABLE FOR ’HC163 AND ’HCT163
OPERATING MODE
INPUTS OUTPUTS
MR CP PE TE SPE PnQnTC
Reset (Clear) l ↑XXXXLL
Parallel Load h (Note 5) ↑XX l l LL
h (Note 5) ↑X X l h H (Note 3)
Count h (Note 5) ↑h h h (Note 5) X Count (Note 3)
Inhibit h (Note 5) X I (Note 4) X h (Note 5) X qn(Note 3)
h (Note 5) X X I (Note 4) h (Note 5) X qnL
NOTE: H = High voltage level steady state; L = Low voltage level steady state; h = High voltage level one setup time prior to the Low-to-High
clock transition; l = Low voltage level one setup time prior to the Low-to-High clock transition; X = Don’t Care; q = Lower case letters indicate
the state of the referenced output prior to the Low-to-High clock transition; ↑ = Low-to-High clock transition.
3. The TC output is High when TE is High and the counter is at Terminal Count (HHHH for HC/HCT161 and ’HC/HCT163).
4. The High-to-Low transition of PE or TE on the ’HC/HCT161 and the ’HC/HCT163 should only occur while CP is HIGH for conventional
operation.
5. The Low-to-High transition of SPE on the ’HC/HCT161 and SPE or MR on the ’HC/HCT163 should only occur while CP is HIGH for con-
ventional operation.
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
4
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 6) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
6. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
- - ---- - - -V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
- - ---- - - -V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
5
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2--2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC and
GND 0 5.5 - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC
(Note) VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
P0 - P3 0.25
PE 0.65
CP 1.05
MR 0.8
SPE 0.5
TE 1.05
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
Prerequisite For Switching Specifications
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Maximum CP Frequency
(Note7) fMAX - 2 6 - - 5 - 4 - MHz
4.5 30 - - 24 - 20 - MHz
6 35 - - 28 - 24 - MHz
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
6
CP Width (Low) tW(L) - 2 80 - - 100 - 120 - ns
4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns
MR Pulse Width (161) tW- 2 100 - - 125 - 150 - ns
4.5 20 - - 25 - 30 - ns
6 17 - - 21 - 26 - ns
Setup Time, Pn to CP tSU - 2 60 - - 75 - 90 - ns
4.5 12 - - 15 - 18 - ns
6 10 - - 13 - 15 - ns
Setup Time, PE or TE to CP tSU - 2 50 - - 65 - 75 - ns
4.5 10 - - 13 - 15 - ns
6 9 - - 11 - 13 - ns
Setup Time, SPE to CP tSU - 2 60 - - 75 - 90 - ns
4.5 12 - - 15 - 18 - ns
6 10 - - 13 - 15 - ns
Setup Time, MR to CP (163) tSU - 2 65 - - 80 - 100 - ns
4.5 13 - - 16 - 20 - ns
6 11 - - 14 - 17 - ns
Hold Time, PN to CP tH-23--3-3-ns
4.5 3 - - 3 - 3 - ns
63--3-3-ns
Hold Time, TE or PE to CP tH-20--0-0-ns
4.5 0 - - 0 - 0 - ns
60--0-0-ns
Hold Time, SPE to CP tH-20--0-0-ns
4.5 0 - - 0 - 0 - ns
60--0-0-ns
Recovery Time, MR to CP (161) tREC - 2 75 - - 95 - 110 - ns
4.5 15 - - 19 - 22 - ns
6 13 - - 16 - 19 - ns
HCT TYPES
Maximum CP Frequency fMAX - 4.5 30 - - 24 - 20 - MHz
CP Width (Low) (Note 7) tW(L) - 4.5 16 - - 20 - 24 - ns
MR Pulse Width (161) tW- 4.5 20 - - 25 - 30 - ns
Setup Time, Pn to CP tSU - 4.5 10 - - 13 - 15 - ns
Setup Time, PE or TE to CP tSU - 4.5 13 - - 16 - 20 - ns
Setup Time, SPE to CP tSU - 4.5 12 - - 15 - 18 - ns
Setup Time, MR to CP (163) tSU - 4.5 13 - - 16 - 20 - ns
Hold Time, PN to CP tH- 4.5 5 - - 5 - 5 - ns
Hold Time, TE or PE to CP tH- 4.5 3 - - 3 - 3 - ns
Prerequisite For Switching Specifications (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
7
Hold Time, SPE to CP tH- 4.5 3 - - 3 - 3 - ns
Recovery Time, MR to CP (161) tREC - 4.5 15 - - 19 - 22 - ns
NOTE:
7. Applies to non-cascaded operation only. With cascaded counters clock to terminal count propagation delays, count enables (PE or TE)-
to-clock setup times, and count enables (PE or TE)-to-clock hold times determine maximum clock frequency. For example with these HC
devices:
Prerequisite For Switching Specifications (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
fMAX (CP) 1
CP-to-TC prop. delay TE-to-CP setup TE-to-CP Hold++
----------------------------------------------------------------------------------------------------------------------------------------------------- 1
37 10 0++
-----------------------------21MHz min()≈==
Switching Specifications CL = 50pF, Input tr, tf= 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay tPHL, tPLH CL = 50pF
CP to TC 2 - - 185 - 230 - 280 ns
4.5 - - 37 - 46 - 56 ns
CL = 15pF 5 - 15 - - - - - ns
CL = 50pF 6 - - 31 - 39 - 48 ns
CP to Qn tPHL, tPLH CL = 50pF 2 - - 185 - 230 - 280 ns
4.5 - - 37 - 46 - 56 ns
CL = 15pF 5 - 15 - - - - - ns
CL = 50pF 6 - - 31 - 39 - 48 ns
TE to TC tPHL, tPLH CL = 50pF 2 - - 120 - 150 - 180 ns
4.5 - - 24 - 30 - 36 ns
CL = 15pF 5 - 9 - - - - - ns
CL = 50pF 6 - - 20 - 26 - 31 ns
MR to Qn (161) tPHL CL = 50pF 2 - - 210 - 265 - 315 ns
4.5 - - 42 - 53 - 63 ns
CL = 15pF 5 - 18 - - - - - ns
CL = 50pF 6 - - 36 - 45 - 54 ns
MR to TC (161) tPHL CL = 50pF 2 - - 210 - 265 - 315 ns
4.5 - - 42 - 53 - 63 ns
CL = 50pF 6 - - 36 - 45 - 54 ns
Output Transition Time tTHL, tTLH CL = 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Power Dissipation Capacitance
(Notes 8, 9) CPD -5-60-----pF
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
8
Input Capacitance CIN CL = 50pF - 10 - 10 - 10 - 10 pF
HCT TYPES
Propagation Delay
CP to TC tPHL, tPLH CL = 50pF 4.5 - - 42 - 53 - 63 ns
CL = 15pF 5 - 18 - - - - - ns
CP to Qn tPHL, tPLH CL = 50pF 4.5 - - 39 - 49 - 59 ns
CL = 15pF 5 - 16 - - - - - ns
TE to TC tPHL, tPLH CL = 50pF 4.5 - - 32 - 40 - 48 ns
CL = 15pF 5 - 13 - - - - - ns
MR to Qn (161) tPHL CL = 50pF 4.5 - - 50 - 63 - 75 ns
CL = 15pF 5 - 21 - - - - - ns
MR to TC (161) tPHL CL = 50pF 4.5 - - 50 - 63 - 75 ns
Output Transition Time tTHL, tTLH CL = 50pF 4.5 - - 15 - 19 - 22 ns
Power Dissipation Capacitance
(Notes 8, 9) CPD -5-63-----pF
Input Capacitance CIN CL = 50pF - 10 - 10 - 10 - 10 pF
NOTES:
8. CPD is used to determine the dynamic power consumption, per package.
9. PD=C
PD VCC2fi+∑(CLVCC2fO) where fi= Input Frequency, fO= Output Frequency, CL= Output Load Capacitance, VCC = Supply
Voltage.
Switching Specifications CL = 50pF, Input tr, tf= 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
9
Timing Diagram
Sequence illustrated on waveforms:
1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one, and two.
4. Inhibit.
MASTER RESET (161)
MASTER RESET (163)
SPE
P0
P1
P2
P3
PRESET
DATA
CP (161)
CP (163)
PE
TE
COUNT
ENABLES
Q0
Q1
Q2
Q3
OUTPUTS
TC
RESET PRESET COUNT INHIBIT
(ASYNCHRONOUS)
(SYNCHRONOUS)
12 13 14 15 0 1 2
INPUTS
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
10
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
CLOCK 90% 50%
10% GND
VCC
trCLtfCL
50% 50%
tWL tWH
10%
tWL + tWH =fCL
I
CLOCK 2.7V 1.3V
0.3V GND
3V
trCL= 6ns tfCL= 6ns
1.3V 1.3V
tWL tWH
0.3V
tWL + tWH =fCL
I
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
trCLtfCL
GND
VCC
GND
VCC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
VCC 50%
50%
90%
10%
50%
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
tH(H)
trCLtfCL
GND
3V
GND
3V
1.3V
2.7V
0.3V
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
3V 1.3V
1.3V
1.3V
90%
10%
1.3V
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
1.3V
tH(H)
1.3V
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
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Copyright 2000, Texas Instruments Incorporated
