SN54LS224A, SN74LS224A
16 ×4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Independent Synchronous Inputs and
Outputs
D
16 Words by 4 Bits Each
D
3-State Outputs Drive Bus Lines Directly
D
Data Rates up to 10 MHz
D
Fall-Through Time 50 ns Typical
D
Data Terminals Arranged for Printed Circuit
Board Layout
D
Expandable, Using External Gating
D
Packaged in Standard Plastic (N) and
Ceramic (J) 300-mil DIPs, and Ceramic Chip
Carriers (FK)
description
The SN54LS224A and SN74LS224A 64-bit,
low-power Schottky memories are organized as
16 words by 4 bits each. They can be expanded
in multiples of 15m + 1 words or 4n bits, or both
(where n is the number of packages in the vertical
array and m is the number of packages in the
horizontal array); however, some external gating
is required. For longer words, the input-ready (IR)
signals of the first-rank packages and
output-ready (OR) signals of the last-rank
packages must be ANDed for proper
synchronization.
A first-in, first-out (FIFO) memory is a storage
device that allows data to be written to and read
from its array at independent data rates. These
FIFOs are designed to process data at rates up to
10 MHz in a bit-parallel format, word by word.
The load clock (LDCK) normally is held low, and data is written into memory on the high-to-low transition of
LDCK. The unload clock (UNCK) normally is held high, and data is read out on the low-to-high transition of
UNCK. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked
out. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory
is empty, UNCK signals have no effect.
Status of the FIFO memory is monitored by the IR and OR flags that indicate not-full and not-empty conditions.
IR is high only when the memory is not full and LDCK is low. OR is high only when the memory is not empty
and UNCK is high.
A low level on the clear (CLR) input resets the internal stack-control pointers and also sets IR high and OR low
to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting, with respect to
the data inputs, and are at high impedance when the output-enable (OE) input is low. OE does not affect the
IR and OR outputs.
The SN74LS224A is characterized for operation from 0°C to 70°C. The SN54LS224A is characterized over the
full military temperature range of –55°C to 125°C.
18
17
14
OR
Q0
NC
Q1
Q2
LDCK
D0
NC
D1
D2
OE
IR
LDCK
D0
D1
D2
D3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
UNCK
OR
Q0
Q1
Q2
Q3
CLR
SN54LS224A ...J PACKAGE
SN74LS224A ...N PACKAGE
(TOP VIEW)
1920132
16
15
131211910
5
4
6
7
8
IR
OE
NC
V
UNCK
GND
NC
CLR
Q3
D3
SN54LS224A . . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LS224A, SN74LS224A
16 ×4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol†
CLR
EN5
1
OE
CT = 0
9
1D
4
D0 5
D1 6
D2 7
D3
Q0
13
Q1
12
Q2
11
Q3
10
IR
2
2
3
LDCK
CT < 16 &+ /C1
Z2
CT > 0 &–
Z3
OR
14
3
CT = 0 &
V4
2
4, 5
CTR
FIFO 16 × 4
15
UNCK
†This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. This symbol is functionally accurate, but does
not show the details of implementation; for these details, see the logic diagram. The symbol represents the memory as if it were controlled by
a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is 0.
Pin numbers shown are for the J and N packages.
SN54LS224A, SN74LS224A
16 ×4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
9
3
15
4
5
6
7
2
14
13
12
11
10
OE
CLR
LDCK
UNCK
D0
D1
D2
D3
IR
OR
Q0
Q1
Q2
Q3
16
16
16
16
Ring
Counter
CTR
DIV 16
Write
Address
Ring
Counter
CTR
DIV 16
Read
Address
COMP
RAM
16 × 4
+
CT = 1
+
CT = 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P
Q
1A
2A
C5
1
16
EN
≥1
1A,5D 2A
1
16
S
1D
C1
S
2D
C2
R
3D
C3
R
4D
C4
Q=P+1
P=Q+1
P=Q
EMPTY
Pin numbers shown are for the J and N packages.
SN54LS224A, SN74LS224A
16 ×4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
13 kΩ NOM
VCC
Input
19 kΩ NOM
VCC
Input
EQUIVALENT OF CLR INPUT EQUIVALENT OF OTHER INPUTS
100 Ω NOM
VCC
Output
120 Ω NOM
VCC
Output
TYPICAL OF IR AND OR OUTPUTS TYPICAL OF Q OUTPUTS
SN54LS224A, SN74LS224A
16 ×4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing diagram
ÎÎÎ
ÎÎÎ
Invalid
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
W1 W2 W1 W2 W15 W16
ÎÎÎÎ
ÎÎÎÎ
Invalid Word 1 Word 2 Word 1
Word 2
CLR
LDCK
IR
UNCK
D0–D3
OR
Q0–Q3
Load
Two Words Unload
Two Words Load Until Full UnloadInitialize
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Off-state output voltage range, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA: N package (see Note 2) 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package (see Note 3) 88°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-3.
SN54LS224A, SN74LS224A
16 ×4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
SN54LS224A SN74LS224A
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH
High level out
p
ut current
Q outputs –1–2.6
mA
I
OH
High
-
level
output
current
IR, OR –0.4 –0.4
mA
IOL
Low level out
p
ut current
Q outputs 12 24
mA
I
OL
Low
-
level
output
current
IR, OR 4 8
mA
TAOperating free-air temperature –55 125 0 70 °C
NOTE 4: T o ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCK and UNCK clock inputs.
Any excessive noise or glitching on the clock inputs that violates the VIL, VIH, or minimum pulse-duration limits can cause a false clock
or improper operation of the internal read and write pointers.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS†
SN54LS224A SN74LS224A
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VIK VCC = MIN, II = –18 mA –1.5 –1.5 V
Q out
p
uts
VCC = MIN
IOH = –2.6 mA 2.4 3.4
VOH
Q
outputs
V
CC =
MIN
IOH = –1 µA 2.4 3.3 V
IR, OR VCC = MIN, IOH = –0.4 mA 2.5 3.4 2.7 3.4
Q out
p
uts
VCC = MIN
IOL = 12 mA 0.25 0.4 0.25 0.4
VOL
Q
outputs
V
CC =
MIN
IOL = 24 mA 0.35 0.5
V
V
OL
IR OR
VCC = MIN
IOL = 4 mA 0.25 0.4 0.25 0.4
V
IR
,
OR
V
CC =
MIN
IOL = 8 mA 0.35 0.5
IOZH Q outputs VCC = MAX, VO = 2.7 V 20 20 µA
IOZL Q outputs VCC = MAX, VO = 0.4 V –20 –20 µA
IIVCC = MAX, VI = 7 V 0.1 0.1 mA
IIH VCC = MAX, VI = 2.7 V 20 20 µA
IIL VCC = MAX, VI = 0.4 V –0.4 –0.4 mA
I§
Q outputs
VCC = MAX
–30 –130 –30 –130
mA
I
OS
§
IR, OR
V
CC =
MAX
–20 –100 –20 –100
mA
Outputs high 84 135 84 135
ICC VCC = MAX Outputs low 87 155 87 155 mA
Outputs disabled 89 155 89 155
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
SN54LS224A, SN74LS224A
16 ×4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating conditions (see Note 4 and Figure 1)
SN54LS224A SN74LS224A
UNIT
MIN MAX MIN MAX
UNIT
LDCK high 60 60
LDCK low 15 15
twPulse duration UNCK low 30 30 ns
UNCK high 30 30
CLR low 20 20
Data to LDCK↓50 50
tsu Setup time LDCK↓ before UNCK↓50 50 ns
UNCK↑ before LDCK↑50 50
thHold time Data from LDCK↓10 10 ns
NOTE 4: T o ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCK and UNCK clock inputs.
Any excessive noise or glitching on the clock inputs that violates the VIL, VIH, or minimum pulse-duration limits can cause a false clock
or improper operation of the internal read and write pointers.
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST
CONDITIONS MIN TYP MAX UNIT
tPLH LDCK↓
IR
RL=2kΩ
CL=15
p
F
25 40
ns
tPHL LDCK↑
IR
R
L =
2
kΩ
,
C
L =
15
pF
36 50
ns
tPLH LDCK↓OR RL = 2 kΩ, CL = 15 pF 48 70 ns
tPLH UNCK↑
OR
RL=2kΩ
CL=15
p
F
29 45
ns
tPHL UNCK↓
OR
R
L =
2
kΩ
,
C
L =
15
pF
28 45
ns
tPLH UNCK↑IR RL = 2 kΩ, CL = 15 pF 49 70 ns
tPLH
CLR↓
IR
RL=2kΩ
CL=15
p
F
36 55
ns
tPHL
CLR↓
OR
R
L =
2
kΩ
,
C
L =
15
pF
25 40
ns
tPHL LDCK↓Q RL = 667 Ω, CL = 45 pF 34 50 ns
tPLH
UNCK↑
Q
RL= 667 Ω
CL=45
p
F
54 80
ns
tPHL
UNCK↑
Q
R
L =
667
Ω
,
C
L =
45
pF
45 70
ns
tPZL
OE↑
Q
RL= 667 Ω
CL=45
p
F
22 35
ns
tPZH
OE↑
Q
R
L =
667
Ω
,
C
L =
45
pF
21 35
ns
tPLZ
OE↓
Q
RL= 667 Ω
CL=5
p
F
16 30
ns
tPHZ
OE↓
Q
R
L =
667
Ω
,
C
L =
5
pF
18 30
ns
SN54LS224A, SN74LS224A
16 ×4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
tPHZ
tPLZ
tPHL tPLH
0.5 V
tPZL
tPZH
tPLH tPHL
1.3 V
1.3 V1.3 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
Control
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3 V
3 V
0.3 V
0 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
W aveform 1
(see Note B)
W aveform 2
(see Note B)
[
1.5 V
VOH
VOL
[
1.5 V
In-Phase
Output
0.5 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
LOAD CIRCUIT
S1
(see Note B)
5 kΩ
S2
VCC
RL
From Output
Under Test CL
(see Note A)
tPZL
tPZH
tPLZ/tPHZ
tPLH/tPHL
Closed
Open
Closed
Closed
TEST S1 Open
Closed
Closed
Closed
S2
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr < 15 ns, tf < 6 ns, ZO ≈ 50 Ω.
D. All diodes are 1N916 or 1N3064.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN54LS224AJ OBSOLETE CDIP J 16 TBD Call TI Call TI
SN74LS224AN ACTIVE PDIP N 16 TBD Call TI Call TI
SN74LS224AN3 OBSOLETE PDIP N 16 TBD Call TI Call TI
SNJ54LS224AFK OBSOLETE LCCC FK 20 TBD Call TI Call TI
SNJ54LS224AJ OBSOLETE CDIP J 16 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 19-Sep-2005
Addendum-Page 1
MECHANICAL DATA
MLCC006B – OCTOBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
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