LTC4150
1
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TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Coulomb Counter/
Battery Gas Gauge
The LTC
®
4150 measures battery depletion and charging
in handheld PC and portable product applications. The
device monitors current through an external sense resistor
between the battery’s positive terminal and the battery’s
load or charger. A voltage-to-frequency converter trans-
forms the current sense voltage into a series of output
pulses at the interrupt pin. These pulses correspond to a
fi xed quantity of charge fl owing into or out of the battery.
The part also indicates charge polarity as the battery is
depleted or charged.
The LTC4150 is intended for 1-cell or 2-cell Li-Ion and
3-cell to 6-cell NiCd or NiMH applications.
Integral Nonlinearity, % of Full Scale
n Indicates Charge Quantity and Polarity
n ±50mV Sense Voltage Range
n Precision Timer Capacitor or Crystal Not Required
n 2.7V to 8.5V Operation
n High Side Sense
n 32.55Hz/V Charge Count Frequency
n 1.5μA Shutdown Current
n 10-Pin MSOP Package
n Battery Chargers
n Palmtop Computers and PDAs
n Cellular Telephones and Wireless Modems
CF–
CF+INT
4.7μF CLR CHG DISCHG
RL
RSENSE
POL
SHDN
4.7μF
CHARGER
LOAD
SENSE–SENSE+
GND
LTC4150 μP
4150 TA01a
VDD
+
RL
CURRENT SENSE VOLTAGE (mV)
–50 –25 0 25 50
ERROR (% FULL SCALE)
4150 TA01b
0.5
0.4
0.3
0.2
0.1
–0.5
–0.4
–0.3
–0.2
–0.1
0
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode are registered trademarks and
ThinSOT and PowerPath are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
LTC4150
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD) .................................. –0.3V to 9V
Input Voltage Range
Digital Inputs (CLR, SHDN) ........–0.3V to (VDD + 0.3)
SENSE–, SENSE+ , CF–, CF+ .........–0.3V to (VDD + 0.3)
Output Voltage Range
Digital Outputs (INT, POL) ....................... –0.3V to 9V
Operating Temperature Range
LTC4150CMS ........................................... 0°C to 70°C
LTC4150IMS .......................................–40°C TO 85°C
Storage Temperature Range ................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
(Note 1)
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VDD = 2.7V and 8.5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIL Digital Input Low Voltage, CLR, SHDN l0.7 V
VIH Digital Input High Voltage, CLR, SHDN l1.9 V
VOL Digital Output Low Voltage, INT, POL IOL = 1.6mA, VDD = 2.7V l0.5 V
ILEAK Digital Output Leakage Current, INT, POL VINT = VPOL = 8.5V l0.01 1 μA
VOS Differential Offset Voltage (Note 4) VDD = 4.0V
l
±100
±150
μV
μV
VDD = 8.0V
l
±100
±150
μV
μV
VDD = 2.7V to 8.5V
l
±150
±200
μV
μV
VSENSE(CM) Sense Voltage Common Mode Input Range lVDD – 0.06 VDD + 0.06 V
VSENSE Sense Voltage Differential Input Range SENSE+ – SENSE–l–0.05 0.05 V
RIDR Average Differential Input Resistance,
Across SENSE+ and SENSE–VDD = 4.1V (Note 3) 155 270 390 kΩ
VUVLO Undervoltage Lockout Threshold VDD Rising l2.5 2.7 V
PIN CONFIGURATION
1
2
3
4
5
SENSE+
SENSE–
CF+
CF–
SHDN
10
9
8
7
6
INT
CLR
VDD
GND
POL
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 160°C/W
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4150CMS#PBF LTC4150CMS#TRPBF LTQW 10-Lead Plastic MSOP 0°C to 70°C
LTC4150IMS#PBF LTC4150IMS#TRPBF LTQW 10-Lead Plastic MSOP –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
ORDER INFORMATION
LTC4150
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ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Guaranteed by design and not tested in production.
Note 3: Measured at least 20ms after power on.
Note 4: Tested in feedback loop to SENSE+ and SENSE–.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply Current
IDD Supply Current, Operating VDD = 8.5V
VDD = 2.7V
l
l
115
80
140
100
μA
μA
IDD(SD) Supply Current, Shutdown VDD = 8.5V
VDD = 5.5V
VDD = 2.7V
l
l
l
10 22
10
1.5
μA
μA
μA
AC Characteristics
GVF Voltage to Frequency Gain VSENSE = 50mV to –50mV,
2.7V ≤ VDD ≤ 8.5V l
32.0
31.8
32.55 33.1
33.3
Hz/V
Hz/V
ΔGVF(VDD) Gain Variation with Supply 2.7V ≤ VDD ≤ 8.5V 0 0.5 %/V
ΔGVF(TEMP) Gain Variation with Temperature (Note 2) l–0.03 0.03 %/ºC
INL Integral Nonlinearity
l
–0.4
–0.5
0.4
0.5
%
%
tCLR CLR Pulse Width to Reset INT,
INT and CLR Not Connected
Figure 2 20 μs
tINT INT Low Time, INT Connected to CLR Figure 3, CL = 15pF l1μs
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VDD = 2.7V and 8.5V unless otherwise noted.
LTC4150
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TYPICAL PERFORMANCE CHARACTERISTICS
Voltage to Frequency Gain
vs Supply Voltage
Voltage to Frequency Gain
vs Temperature
TA = 25°C, unless otherwise noted.
Shutdown IDD vs VDD Digital Output Low Voltage vs VDD
Undervoltage Lockout Threshold
vs Temperature
VDD (V)
234 6 8579
GVF ERROR (% OF TYPICAL)
4150 G01
+1.00
–1.00
–0.75
–0.50
–0.25
0
+0.25
+0.50
+0.75
VSENSE = 25mV
VSENSE = 50mV
TEMPERATURE (°C)
-50 -25 0 50 10025 75 125
GVF ERROR (% OF TYPICAL)
4150 G02
+1.00
–1.00
–0.75
–0.50
–0.25
0
+0.25
+0.50
+0.75
VSENSE = 50mV
VDD = 2.7V
VDD = 8.5V
VDD (V)
234 6857910
IDD (μA)
4150 G03
140
120
100
80
60
VDD (V)
234 6857910
IDD (μA)
4150 G04
6
5
4
3
2
1
0
VDD (V)
234 6 8579
VOL (mV)
4150 G05
400
0
50
100
150
200
250
300
350
POL PIN
IOL = 1.6mA
INT PIN
UVLO (V)
4150 G06
2.60
2.52
2.53
2.54
2.55
2.56
2.57
2.58
2.59
RISING EDGE
TEMPERATURE (°C)
-50 -25 0 50 10025 75 125
Operating IDD vs VDD
LTC4150
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PIN FUNCTIONS
SENSE+ (Pin 1): Positive Sense Input. This is the nonin-
verting current sense input. Connect SENSE+ to the load
and charger side of the sense resistor. Full-scale current
sense input is 50mV. SENSE+ must be within 60mV of
VDD for proper operation.
SENSE– (Pin 2): Negative Sense Input. This is the inverting
current sense input. Connect SENSE– to the positive bat-
tery terminal side of the sense resistor. Full-scale current
sense input is 50mV. SENSE– mus t be wi thin 60mV of V DD
for proper operation.
CF+ (Pin 3): Filter Capacitor Positive Input. A capacitor
connected between CF+ and CF– fi lters and averages
noise and fast battery current variations. A 4.7μF value
is recommended. If fi ltering is not desired, leave CF+ and
CF– unconnected.
CF– (Pin 4): Filter Capacitor Negative Input. A capacitor
connected between CF+ and CF– fi lters and averages
noise and fast battery current variations. A 4.7μF value
is recommended. If fi ltering is not desired, leave CF+ and
CF– unconnected.
SHDN (Pin 5): S h u t d o w n D i g i t a l I n p u t . W h e n a s s e r t e d l o w,
SHDN forces the LTC4150 into its low current consumption
power-down mode and resets the part. In applications
with logic supply VCC > VDD, a resistive divider must be
used between SHDN and the logic which drives it. See the
Applications Information section.
POL (Pin 6): Battery Current Polarity Open-Drain Output.
POL indicates the most recent battery current polarity when
INT is high. A low state indicates the current is fl owing out
of the battery while high impedance means the current
is going into the battery. POL latches its state when INT
is asserted low. POL is an open-drain output and can be
pulled up to any logic supply up to 9V. In shutdown, POL
is high impedance.
GND (Pin 7): Ground. Connect directly to the negative
battery terminal.
VDD (Pin 8): Positive Power Supply. Connect to the load
and charger side of the sense resistor. SENSE+ also con-
nects to VDD. VDD operating range is 2.7V to 8.5V. Bypass
VDD with 4.7μF capacitor.
CLR (Pin 9): Clear Interrupt Digital Input. When asserted
low for more than 20μs, CLR resets INT high. Charge
counting is unaffected. INT may be directly connected to
CLR. In this case the LTC4150 will capture each assertion
of INT and wait at least 1μs before resetting it. This ensures
that INT pulses low for at least 1μs but gives automatic
INT reset. In applications with a logic supply VCC > VDD,
a resistive divider must be used between INT and CLR.
See the Applications Information section.
INT (Pin 10): Charge Count Interrupt Open-Drain Output.
INT latches low every 1/(VSENSE • GVF) seconds and is
reset by a low pulse at CLR. INT is an open-drain output
and can be pulled up to any logic supply of up to 9V. In
shutdown INT is high impedance.
LTC4150
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BLOCK DIAGRAM
+
––
+
–
+
AMPLIFIER
CF+
CF
SENSE+
VDD
RSENSE
IBAT
CF–
SENSE–
2k
2k
200k
200k
100pF
200k
S2
S1
S3
SHDN
CONTROL
LOGIC
POLARITY
DETECTION
OFLOW/
UFLOW
REFHI
1.7V
REFLO
0.95V
CLR
POL
DISCHARGE
CHARGE
INT
GND
LOADCHARGER
COUNTER
UP/DN
R
SQ
4150 F01
8
1
3
4
2
7
10
9
6
5
Figure 1. Block Diagram
TIMING DIAGRAMS
tCLR
4150 F02
50%
CLR
INT
50%
tINT
4150 F03
50%
INT 50%
Figure 2. CLR Pulse Width to Reset INT,
CLR and INT Not Connected
Figure 3. INT Minimum Pulse Width, CLR and INT Connected
LTC4150
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OPERATION
Charge is the time integral of current. The LTC4150 mea-
sures battery current by monitoring the voltage developed
across a sense resistor and then integrates this information
in several stages to infer charge. The Block Diagram shows
the st ages described below. As each uni t of charge passes
into or out of the battery, the LTC4150 INT pin interrupts
an external microcontroller and the POL pin reports the
polarity of the charge unit. The external microcontroller
then resets INT with the CLR input in preparation for the
next interrupt issued by the LTC4150. The value of each
charge unit is determined by the sense resistor value and
the sense voltage to interrupt frequency gain GVF of the
LTC4150.
Power-On and Start-Up Initialization
When power is fi rst applied to the LTC4150, all internal
circuitry is reset. After an initialization interval, the LTC4150
begins counting charge. This inter val depends on V DD and
the voltage across the sense resistor but will be at least
5ms. It may take an additional 80ms for the LTC4150 to
accurately track the sense voltage. An internal undervoltage
lockout circuit monitors VDD and resets all circuitry when
VDD falls below 2.5V.
Asserting SHDN low also resets the LTC4150’s internal
circuitry and reduces the supply current to 1.5μA. In this
condition, POL and INT outputs are high impedance. The
LTC4150 resumes counting after another initialization
interval. Shutdown minimizes battery drain when both
the charger and load are off.
CHARGE COUNTING
First, the current measurement is fi ltered by capacitor CF
connected across pins CF+ and CF–. This averages fast
changes in current arising from ripple, noise and spikes
in the load or charging current.
Second, the fi lter’s output is applied to an integrator with
the amplifi er and 100pF capacitor at its core. When the
integrator output ramps to REFHI or REFLO levels, switches
S1 and S2 reverse the ramp direction. By observing the
condition of S1 and S2 and the ramp direction, polarity is
determined. The integrating interval is trimmed to 600μs
at 50mV full-scale sense voltage.
Third, a counter is incremented or decremented every
time the integrator changes ramp direction. The counter
effectively increases integration time by a factor of 1024,
greatly reducing microcontroller overhead required to
service interrupts from the LTC4150.
At each counter under or overfl ow, the INT output latches
low, fl agging a microcontroller. Simultaneously, the POL
output is latched to indicate the polarity of the observed
charge. With this information, the microcontroller can
total the charge over long periods of time, developing
an accurate estimate of the battery’s condition. Once the
interrupt is recognized, the microcontroller resets INT with
a low going pulse on CLR and awaits the next interrupt.
Alternatively, INT can drive CLR.
LTC4150
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APPLICATIONS INFORMATION
SENSE VOLTAGE INPUT AND FILTERS
Since the overall integration time is set by internally trim-
ming the LTC4150, no external timing capacitor or trimming
is necessary. The only external component that affects
the transfer function of interrupts per coulomb of charge
is the sense resistor, RSENSE. The common mode range
for the SENSE+ and SENSE– pins is VDD ±60mV, with a
maximum differential voltage range of ±50mV. SENSE+ is
normally tied to VDD, so there is no common mode issue
when SENSE– operates within the 50mV differential limit
relative to SENSE+.
Choose RSENSE t o provide 5 0mV drop at m a xi mum ch arg e
or discharge current, whichever is greater. Calculate
RSENSE from:
RmV
I
SENSE MAX
=50
(1)
The sense input range is small (±50mV) to minimize the
loss across RSENSE. To preserve accuracy, use Kelvin
connections at RSENSE.
The external fi lter capacitor, CF, operates against a total
on-chip resistance of 4k to form a lowpass fi lter that
averages battery current and improves accuracy in the
presence of noise, spikes and ripple. 4.7μF is recom-
mended for general applications but can be extended to
higher values as long as the capacitor’s leakage is low.
A 10nA leakage is roughly equivalent to the input offset
error of the integrator. Ceramic capacitors are suitable
for this use.
Switching regulators are a particular concern because
they generate high levels of current ripple which may fl ow
through the battery. The VDD and SENSE+ connection to
the charger and load should be bypassed by at least 4.7μF
at the LTC4150 if a switching regulator is present.
The LTC4150 maintains high accuracy even when Burst
Mode
®
switching regulators are used. Burst pulse “on”
levels must be within the specifi ed differential input volt-
age range of 50mV as measured at CF+ and CF–. To retain
accurate charge information, the LTC4150 must remain
enabled during Burst Mode operation. If the LTC4150
shuts down or VDD drops below 2.5V, the part resets and
charge information is lost.
Coulomb Counting
The LTC4150’s transfer function is quantifi ed as a volt-
age to frequency gain GVF, where output frequency is the
number of interrupts per second and input voltage is the
differential drive VSENSE across SENSE+ and SENSE–. The
number of interrupts per second will be:
f = GVF • ⏐VSENSE
⏐ (2)
where
V
SENSE = IBATTERY • RSENSE (3)
Therefore,
f = GVF • ⏐IBATTERY • RSENSE
⏐ (4)
Since I • t = Q, coulombs of battery charge per INT pulse
can be derived from Equation 4:
One INT GR Coulombs
VF SENSE
=1
•
(5)
Battery capacity is most often expressed in ampere-
hours.
1Ah = 3600 Coulombs (6)
Combining Equations 5 and 6:
One INT GR
VF SENSE
=1
3600 • •
[Ah] (7)
or
1Ah = 3600 • GVF • RSENSE Interrupts (8)
The charge measurement may be further scaled within
the microcontroller. However, the number of interrupts,
coulombs or Ah all represent battery charge.
The LTC4150’s transfer function is set only by the value
of the sense resistor and the gain GVF. Once RSENSE is
selected using Equation 1, the charge per interrupt can
be determined from Equation 5 or 7.
Note that RSENSE is not chosen to set the relationship
between ampere-hours of battery charge and number of
interrupts issued by the LTC4150. Rather, RSENSE is chosen
to keep the maximum sense voltage equal to or less than
the LTC4150’s 50mV full-scale sense input.
LTC4150
9
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APPLICATIONS INFORMATION
INT, POL and CLR
INT asserts low each time the LTC4150 measures a unit
of charge. At the same time, POL is latched to indicate
the polarity of the charge unit. The integrator and counter
continue running, so the microcontroller must service and
clear the interrupt before another unit of charge accumu-
lates. Otherwise, one measurement will be lost. The time
available between interrupts is the reciprocal of
Equation 2:
Time per INT Assertion =1
GVF •⏐VSENSE⏐
(9)
At 50mV full scale, the minimum time available is 596ms.
To be conservative and accommodate for small, unex-
pected excursions above the 50mV sense voltage limit, the
microcontroller should process the interrupt and polarity
information and clear INT within 500ms.
Toggling CLR low for at least 20μs resets INT high and
unlatches POL. Since the LTC4150’s integrator and counter
operate independently of the INT and POL latches, no
charge information is lost during the latched period or
while CLR is low. Charge/discharge information contin-
ues to accumulate during those intervals and accuracy
is unaffected.
Once cleared, INT idles in a high state and POL indicates
real-time polarity of the battery current. POL high indicates
charge fl owing into the battery and low indicates charge
fl owing out. Indication of a polarity change requires at
least:
tGV
POL
VF SENSE
=2
1024••⏐⏐
(10)
where VSENSE is the smallest sense voltage magnitude
before and after the polarity change.
Open-drain outputs POL and INT can sink IOL = 1.6mA
at VOL = 0.5V. The minimum pull-up resistance for these
pins should be:
R
L > (VCC – 0.5)/1.6mA (11)
where VCC is the logic supply voltage. Because speed isn’t
an issue, pull-up resistors of 10k or higher are adequate.
Interfacing to INT, POL, CLR and SHDN
The LTC4150 operates directly from the battery, while in
most cases the microcontroller supply comes from some
separate, regulated source. This poses no problem for INT
and POL because they are open-drain outputs and can
be pulled up to any voltage 9V or less, regardless of the
voltage applied to the LTC4150’s VDD.
CLR and SHDN inputs require special attention. To drive
them, the microcontroller or external logic must generate
a minimum logic high level of 1.9V. The maximum input
level for these pins is VDD + 0.3V. If the microcontroller’s
supply is more than this, resistive dividers must be used
on CLR and SHDN. The schematic in Figure 6 shows an
application with INT driving CLR and microcontroller VCC
> VDD. The resistive dividers on CLR and SHDN keep the
voltages at these pins within the LTC4150’s VDD range.
Choose R2 and R1 so that:
(R1 + R2) ≥ 50RL (12)
19 1
12
.()VR
RR
V V Minimum
CC DD
≤+≤
(13)
Equation 13 also applies to the selection of R3 and R4.
The minimum VDD is the lowest supply to the LTC4150
when the battery powering it is at its lowest discharged
voltage.
When the battery is removed in any application, the CLR
and SHDN inputs are unpredictable. INT and POL outputs
may be erratic and should be ignored until after the bat-
tery is replaced.
If desired, the simple logic of Figure 4 may be used to
derive separate charge and discharge pulse trains from
INT and POL.
INT CHARGE
DISCHARGE
CLR
POL
LTC4150
4150 F04
Figure 4. Unravelling Polarity—
Separate Charge and Discharge Outputs
LTC4150
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APPLICATIONS INFORMATION
AUTOMATIC CHARGE COUNT INTERRUPT AND CLEAR
In applications where a CLR p u l s e i s u n a v a i l a b l e , i t ’ s e a s y t o
make the LTC4150 run autonomously, as shown in Figures
5 and 6. If the microcontroller VCC is less than or equal to
the battery VDD, INT may be directly connected to CLR, as
in Figure 5. The only requirement is that the microcontroller
s h o u l d b e a b l e t o p r o v i d e a h i g h l o g i c l e v e l o f 1. 9 V t o SHDN.
If the microcontroller VCC is greater than the battery VDD,
use Figure 6. The resistor dividers on CLR and SHDN keep
the voltages at these pins within the LTC4150’s VDD range.
Choose an RL value using Equation 11 and R1-R4 values
using Equation 13. In either application, the LTC4150 will
capture the fi rst assertion of INT and wait at least 1μs
before resetting it. This insures that INT pulses low for at
least 1μs but gives automatic INT reset.
INTSENSE+
SENSE–
SHDN
CLR
POL
LTC4150
μP
C2
4.7μF
RL
10
9
8
7
6
1
2
5
4150 F05
VDD
GND
RL
PROCESSOR
VCC
POWER-DOWN
SWITCH
CL
47μF
LOAD
+CF+
CF–
3
4
CF
4.7μF
2.7V TO 8.5V
BATTERY
RSENSE
INTSENSE+
SENSE–
SHDN
SHUTDOWN
R4
R3
CLR
POL
LTC4150
μP
C2
4.7μF
RL
10
9
8
7
6
1
2
5
4150 F06
VDD
GND
RL
PROCESSOR
VCC
POWER-DOWN
SWITCH
CL
47μF
LOAD
+CF+
CF–
3
4
CF
4.7μF
BATTERY
VBATTERY < VCC
RSENSE R2
R1
Figure 5. Application with INT Direct Drive or CLR and Separate Microprocessor Supply VCC ≤ VDD
Figure 6. Application with INT Driving CLR and Separate Microprocessor Supply VCC > VDD
LTC4150
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APPLICATIONS INFORMATION
PC BOARD LAYOUT SUGGESTIONS
Keep all traces as short as possible to minimize noise
and inaccuracy. The supply bypass capacitor C2 should
be placed close to the LTC4150. The 4.7μF fi lter capacitor
CF should be placed close the CF+ and CF– pins and should
be a low leakage, unpolarized type. Use a 4-wire Kelvin
sense connection for the sense resistor, locating it close
to the LTC4150 with short sense traces to the SENSE+ and
SENSE– pins and longer force lines to the battery pack
and powered load, see Figure 7.
4150 F07
PIN 1
TO BATTERY
TO CHARGER
LTC4150
RSENSE
Figure 7. Kelvin Connection on SENSE Resistor
TYPICAL APPLICATIONS
Figure 8 shows a typical application designed for a single
cell lithium-ion battery and 500mA maximum load current.
Use Equation 1 to calculate RSENSE = 0.05V/0.5A = 0.1Ω.
With RSENSE = 0.1Ω, Equation 7 shows that each interrupt
corresponds to 0.085mAh. Equation 14, derived from
Equation 2, gives the number of INT assertions for average
battery current, IBATT, over a time, t, in seconds:
INT Assertions = GVF • IBATT • RSENSE • t (14)
Loading the battery so that 51.5mA is drawn from it over
600 seconds results in 100 INT assertions. For an 800mAh
battery, this is (51.5mA • 1/6h) / 800mAh = 11% of the
battery’s capacity.
With a microcontroller supply = 5V, Equation 11 gives
RL > 2.875k. The nearest standard value is 3k.
From Equation 12, RL = 3k gives R1 + R2 equal to 150.5k.
A single cell lithium-ion battery can discharge as low as
2.7V.
From Equation 13, select R1 = 75k; the nearest standard
value for R2 is 76.8k.
Also from Equation 13, we choose R3 = 75k and R4 =
76.8k.
INTSENSE+
SENSE–
SHDN
SHUTDOWN
R4
76.8k
R3
75k
CLR
POL
LTC4150
μP
C2
4.7μF
RL
3k
10
9
8
7
6
1
2
5
4150 F08
VDD
GND
RL
3k
5.0V
POWER-DOWN
SWITCH
CL
47μF
LOAD
CF+
CF–
3
4
CF
4.7μF
SINGLE-CELL
Li-Ion
3.0V ~ 4.2V
RSENSE
0.1Ω
R2
76.8k
R1
75k
+
Figure 8. Typical Application, Single Cell Lithium-Ion Battery
LTC4150
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PACKAGE DESCRIPTION
MSOP (MS) 0307 REV E
0.53 p 0.152
(.021 p .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
12345
4.90 p 0.152
(.193 p .006)
0.497 p 0.076
(.0196 p .003)
REF
8910 76
3.00 p 0.102
(.118 p .004)
(NOTE 3)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0o – 6o TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 p 0.127
(.035 p .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 p 0.038
(.0120 p .0015)
TYP
0.50
(.0197)
BSC
0.1016 p 0.0508
(.004 p .002)
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
LTC4150
13
4150fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
t i o n t h a t t h e i n t e r c o n n e c t i o n o f i t s c i r c u i t s a s d e s c r i b e d h e r e i n w i l l n o t i n f r i n g e o n e x i s t i n g p a t e n t r i g h t s .
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
C 2/10 Added Conditions to Power Supply Current in Electrical Characteristics 3
(Revision history begins at Rev C)
LTC4150
14
4150fc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2003
LT 0210 REV C • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
1.1Ω1.2Ω 100mΩ
SENSE RESISTANCE = 0.0852Ω
IMAX = 588mA
10,000 PULSES = 1Ah
+
INTSENSE+
SENSE–
CLR
4150 F09
LTC4150
CD40110B
CD40110B
CD40110B
CD40110B
CD40110B
LOADCHARGER
Figure 9. Ampere-Hour Gauge
PART NUMBER DESCRIPTION COMMENTS
LTC1732 Lithium-Ion Linear Battery Charger Controller Simple Charger uses External FET, Features Preset Voltages, C/10 Charger
Detection and Programmable Timer, Input Power Good Indication
LTC1733 Monolithic Lithium-Ion Linear Battery Charger Standalone Charger with Programmable Timer, Up to 1.5A Charge Current
LTC1734 Lithium-Ion Linear Battery Charger in ThinSOT™Simple ThinSOT Charger, No Blocking Diode, No Sense Resistor Needed
LTC1734L Lithium-Ion Linear Battery Charger in ThinSOT Low Current Version of LTC1734
LTC1998 Lithium-Ion Low Battery Detector 1% Accurate 2.5μA Quiescent Current, SOT-23
LTC4006 Small, High Effi ciency, Fixed Voltage,
Lithium-Ion Battery Charger
Constant-Current/Constant Voltage Switching Regulator with Termination
Timer, AC Adapter Current Limit and Thermistor Sensor in a Small 16-Pin
Package
LTC4050 Lithium-Ion Linear Battery Charger Controller Simple Charger uses External FET, Features Preset Voltages, C/10 Charger
Detection and Programmable Timer, Input Power Good Indication,
Thermistor Interface
LTC4052 Monolithic Lithium-Ion Battery Pulse Charger No Blocking Diode or External Power FET Required, Safety Current Limit
LTC4053 USB Compatible Monolithic Lithium-Ion Battery Charger Standalone Charger with Programmable Timer, Up to 1.25A Charge Current
LTC4054 800mA Standalone Linear Lithium-Ion Battery Charger
with Thermal Regulation in ThinSOT
No External MOSFET, Sense Resistor or Blocking Diode Required, Charge
Current Monitor for Gas Gauging, C/10 Charge Termination
LTC4410 USB Power Manager For Simultaneous Operation of USB Peripheral and Battery Charging from
USB Port, Keeps Current Drawn from USB Port Constant, Keeps Battery
Fresh, Use with the LTC4053, LTC1733, LTC4054
LTC4412 PowerPath™ Controller in ThinSOT More Effi cient Diode OR’ing, Automatic Switching Between DC Sources,
Simplifi ed Load Sharing, 3V ≤ VIN ≤ 28V
