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PRELIMINARY DATA
July 2004
This is preliminary information on a new product now in devel opment or unde rgoing ev aluation. Details are subject to change witho ut no tic e.
NAND128-A, NAND256-A
NAND512-A, NAND01G-A
128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16)
528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
FEATURES SUMMARY
■HIGH DENSITY NAND FLASH MEMORIES
– Up to 1 Gbit memory array
– Up to 32 Mbit spare area
– Cost effective solutions for mass storage
applications
■NAND INTERFACE
– x8 or x16 bus width
– Multiplexed Address/ Data
– Pinout compatibility for all densities
■SUPPLY VOLTAGE
– 1.8V device: VDD = 1.7 to 1.95V
– 3.0V device: VDD = 2.7 to 3.6V
■PAGE SIZE
– x8 device: (512 + 16 spare) Bytes
– x16 device: (256 + 8 spare) Words
■BLOCK SIZE
– x8 device: (16K + 512 spare) Bytes
– x16 device: (8K + 256 spare) Words
■PAGE READ / PROGRAM
– Random access: 12µs (max)
– Sequential access: 50ns (min)
– Page program time: 200µs (typ)
■COPY BACK PROGRAM MODE
– Fast page copy without external buffering
■FAST BLOCK ERASE
– Block erase time: 2ms (Typ)
■STATUS REGISTER
■ELECTRONIC SIGNATURE
■CHIP ENABLE ‘DON’T CARE’ OPTION
– Simple interface with microcontroller
■AUTOMATIC PAGE 0 READ AT POWER-UP
OPTION
– Boot from NAND support
– Automatic Memory Download
■SERIAL NUMBER OPTION
Figure 1. Packages
■HARDWARE DATA PROTECTION
– Program/Erase locked during Power
transitions
■DATA INTEGRITY
– 100,000 Program/Erase cycles
– 10 years Data Retention
■DEVELOPMENT TOOLS
– Error Correction Code software and
hardware models
– Bad Blocks Management and Wear
Leveling algorithms
– PC Demo board with simulation software
– File System OS Native reference software
– Hardware simulation models
TSOP48 12 x 20mm
VFBGA55 8 x 10 x 1mm
TFBGA55 8 x 10 x 1.2mm
VFBGA63 8.5 x 15 x 1mm
TFBGA63 8.5 x 15 x 1.2mm
FBGA
WSOP48 12 x 17 x 0.65mm
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
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Table 1. Product List
Reference Part Number
NAND128-A
NAND128R3A
NAND128W3A
NAND1282R4A
NAND128W4A
NAND256-A
NAND256R3A
NAND256W3A
NAND256R4A
NAND256W4A
NAND512-A
NAND512R3A
NAND512W3A
NAND512R4A
NAND512W4A
NAND01G-A
NAND01GR3A
NAND01GW3A
NAND01GR4A
NAND01GW4A
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NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. TSOP48 and WSOP48 Connections, x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. TSOP48 and WSOP48 Connections, x16 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. FBGA55 Connections, x8 devices (Top view through package) . . . . . . . . . . . . . . . . . . . 11
Figure 7. FBGA55 Connections, x16 devices (Top view through package) . . . . . . . . . . . . . . . . . . 12
Figure 8. FBGA63 Connections, x8 devices (Top view through package) . . . . . . . . . . . . . . . . . . . 13
Figure 9. FBGA63 Connections, x16 devices (Top view through package) . . . . . . . . . . . . . . . . . . 14
MEMORY ARRAY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bad Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Valid Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10.Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Inputs/Outputs (I/O0-I/O7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Inputs/Outputs (I/O8-I/O15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Read Enable (R).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write En abl e (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Ready/Busy (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VDD Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Address Insertion, x8 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
4/56
Table 7. Address Insertion, x16 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Address Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DEVICE OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11.Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12.Pointer Operations for Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read Memory Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Sequential Row Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13.Read (A,B,C) Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 14.Read Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15.Sequential Row Read Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16.Sequential Row Read Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17.Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. Copy Back Program Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18.Copy Back Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19.Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
P/E/R Controller Bit (SR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Error Bit (SR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SR5, SR4, SR3, SR2 and SR1 are Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 11. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Automatic Page 0 Read at Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Automatic Page 0 Read Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Chip Enable Don’t Care Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Chip Enable Don’t Care Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 20.Chip Enable Don’t Care Enabled and Automatic Page 0 Read at Power-Up . . . . . . . . . 28
Figure 21.Automatic Page 0 Read at Power-Up (Chip Enable Don’t Care Disabled) . . . . . . . . . . . 29
SOFTWARE ALGORITHMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 22.Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Figure 23.Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Wear-leveling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Error Correction Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 24.Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Hardware Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 14. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 32
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 15. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 17. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 18. DC Characteristics, 1.8V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 19. DC Characteristics, 3V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 20. AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 21. AC Characteristics for Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 25.Command Latch AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 26.Address Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 27.Data Input Latch AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 28.Sequential Data Output after Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 29.Read Status Register AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 30.Read Electronic Signature AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 31.Page Read A/ Read B Operation AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 32.Read C Operation, One Page AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 33.Page Program AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 34.Block Erase AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 35.Reset AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Ready/Busy Signal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 36.Ready/Busy AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 37.Ready/Busy Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 38.Resistor Value Versus Waveform Timings For Ready/Busy Signal . . . . . . . . . . . . . . . . 45
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 39.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . 46
Table 22. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 46
Figure 40.WSOP48 – 48 lead Plastic Very Very Thin Small Outline, 12 x 17mm, Package Outline47
Table 23. WSOP48 lead Plastic Very Very Thin Small Outline, 12 x 17mm, Mechanical Data. . . . 47
Figure 41.VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . 48
Table 24. VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data. 48
Figure 42.TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Outline . . . . . . . . 49
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
6/56
Table 25. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data 49
Figure 43.VFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . 50
Table 26. VFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data50
Figure 44.TFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . 51
Table 27. TFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data51
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 28. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
APPENDIX A.HARDWARE INTERFACE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 45.Connection to Microcontroller, Without Glue Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 46.Connection to Microcontroller, With Glue Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 47.Building Storage Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
RELATED DOCUMENTATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
SUMMARY D ESCRIPTION
The NAND Flash 528 Byte/ 264 Word Page is a
family of non-volatile Flash memories that uses
NAND cell technology. The devices range from
128Mbits to 1Gbit and operate with either a 1.8V
or 3V v oltage suppl y. The s ize of a P age is eithe r
528 Bytes (512 + 16 spare) or 264 Words (256 + 8
spare) depending on whether the de vi c e has a x8
or x16 bus width.
The address lines are multiplexed with the Data In-
put/Output signals on a multiplexed x8 or x16 In-
put/Output bus. This interface reduces the pin
count and makes it possible to migrate to other
densities without changing the footprint.
Each block can be programmed and erased over
100,000 cycles. To extend the lifetime of NAND
Flash devices it is strongly recommended to imple-
ment an Error Correction Code (ECC). A Write
Protect p in is av ail ab le t o gi ve a ha rd war e pro t ec-
tion against program and erase operations.
The devices feature an open-drain Ready/Busy
output that ca n be used to iden tify if the Prog ram/
Erase/Re ad (P/E/R) Contr oller is curre ntly active.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor.
A Copy Back command is available to optimize the
management of defective blocks. When a Page
Program operation fails, the data can be pro-
grammed in another page without having to re-
send the data to be programmed.
The devices are available in the following packag-
es:
■TSOP48 12 x 20mm for all products
■WSOP48 12 x 17 x 0.65mm for 128Mb,
256Mb and 512Mb products
■VFBGA55 (8 x 10 x 1mm, 6 x 8 ball array,
0.8mm pitch) for 128Mb and 256Mb products
■TFBGA55 (8 x 10 x 1.2mm, 6 x 8 ball array,
0.8mm pitch) for 512Mb Dual Die product
■VFBGA63 (8.5 x 15 x 1mm, 6 x 8 ball array,
0.8mm pitch) for the 512Mb product
■TFBGA63 (8.5 x 15 x 1.2mm, 6 x 8 ball array,
0.8mm pitch) for the 1Gb Dual Die product
Three options are available for the NAND Flash
family:
■Automatic Page 0 Read after Power-up, which
allows the microcontroller to directly download
the boot code from page 0.
■Chip Enable Don’t Care, which allows code to
be directly downloaded by a microcontroller,
as Chip Enable transitions during the latency
time do not stop the read operation.
■A Serial Number, which allows each device to
be uniquely identified. The Serial Number
options is subjec t to an NDA (Non Disc losure
Agreement) and so not described in the
datasheet. For more details of this option
contact your nearest ST Sales office.
For information on how to order these options refer
to Table 28., Ordering Information Scheme. De-
vices are shipped from the factory with Block 0 al-
ways valid and the memory content bits, in valid
blocks, erased to ’1’.
See Table 2., Product Description, for all the de-
vices available in the family.
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
8/56
Table 2. Product Description
Figure 2. Logic Diagram Table 3. Signal Names
Referen c e Part Numbe r Density Bus
Width Page
Size Block
Size Memory
Array Operating
Voltage
Timings
Package
Random
Access
Max
Sequential
Access
Min
Page
Program
Typical
Block
Erase
Typical
NAND128-A
NAND128R3A
128Mbit
x8 512+16
Bytes 16K+512
Bytes 32 Pages x
1024 Blocks
1.7 to 1.95V 10µs 60ns 200µs
2ms TSOP48
WSOP48
VFBGA55
NAND128W3A 2.7 to 3.6V 10µs 50ns 200µs
NAND128R4A x16 256+8
Words 8K+256
Words 1.7 to 1.95V 10µs 60ns 200 µs
NAND128W4A 2.7 to 3.6V 10µs 50ns 200µs
NAND256-A
NAND256R3A
256Mbit
x8 512+16
Bytes 16K+512
Bytes 32 Pages x
2048 Blocks
1.7 to 1.95V 10µs 60ns 200µs
2ms TSOP48
WSOP48
VFBGA55
NAND256W3A 2.7 to 3.6V 10µs 50ns 200µs
NAND256R4A x16 256+8
Words 8K+256
Words 1.7to 1.95V 10µs 60ns 200µs
NAND256W4A 2.7 to 3.6V 10µs 50ns 200µs
NAND512-A
NAND512R3A
512Mbit
x8 512+16
Bytes 16K+512
Bytes 32 Pages x
4096 Blocks
1.7to 1.95V 10µs 60ns 200µs
2ms TFBGA55
NAND512W3A 2.7 to 3.6V 10µs 50ns 200µs
NAND512R4A x16 256+8
Words 8K+256
Words 1.7 to 1.95V 10µs 60ns 200 µs
NAND512W4A 2.7 to 3.6V 10µs 50ns 200µs
NAND512-A
NAND512R3A
512Mbit
x8 512+16
Bytes 16K+512
Bytes 32 Pages x
4096 Blocks
1.7to 1.95V 15µs 60ns 200µs
2ms TSOP48
WSOP48
VFBGA63
NAND512W3A 2.7 to 3.6V 12µs 50ns 200µs
NAND512R4A x16 256+8
Words 8K+256
Words 1.7 to 1.95V 15µs 60ns 200 µs
NAND512W4A 2.7 to 3.6V 12µs 50ns 200µs
NAND01G-A
NAND01GR3A
1Gbit
x8 512+16
Bytes 16K+512
Bytes 32 Pages x
8192 Blocks
1.7 to 1.95V 15µs 60ns 200µs
2ms TSOP48
TFBGA63
NAND01GW3A 2.7 to 3.6V 12µs 50ns 200µs
NAND01GR4A x16 256+8
Words 8K+256
Words 1.7 to 1.95V 15µs 60ns 200 µs
NAND01GW4A 2.7 to 3.6V 12µs 50ns 200µs
AI07557C
W
I/O8-I/O15, x16
VDD
NAND Flash
E
VSS
WP
AL
CL
RB
RI/O0-I/O7, x8/x16
I/O8-15 Data Input/O ut pu ts for x16 dev ice s
I/O0-7 Data Input/Outputs, Address Inputs,
or Command Inputs for x8 and x16
devices
AL Address Latch Enable
CL Command Latch Enable
EChip Enable
RRead Enable
RB Ready/Busy (open-drain output)
WWrite Enable
WP Write Protect
VDD Supply Voltage
VSS Ground
NC Not Conn ec ted Inter na lly
DU Do Not Use
9/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Figure 3. Logic Block Diagram
Address
Register/Counter
Command
Interface
Logic
P/E/R Controller,
High Voltage
Generator
WP
I/O Buffers & Latches
I/O8-I/O15, x16
E
W
AI07561b
R
Y Decoder
Page Buffer
NAND Flash
Memory Array
X Decoder
I/O0-I/O7, x8/x16
Command Register
CL
AL
Cache Register
RB
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
10/56
Figure 4. TSOP48 and WSOP48 Connections,
x8 devices Figure 5. TSOP48 and WSOP48 Connections,
x16 devices
I/O3
I/O2
I/O6
R
RB
NC
I/O4
I/O7
AI07585B
NAND Flash
(x8)
12
1
13
24 25
36
37
48
E
I/O1
NC
NC
NC
NC
NC
NC
NC
WP
W
NC
NC
NC
VSS
VDD
AL
NC
NC
CL
NC
I/O5
NC
NC
NC
I/O0
NC
NC
NC
NC
NC
VDD
NC
NC
NC
VSS
NC
NC
NC
NC
I/O3
I/O9
I/O2
I/O6
R
RB
NC
I/O14
I/O12
I/O10
I/O4
I/O7
AI07559B
NAND Flash
(x16)
12
1
13
24 25
36
37
48
I/O8
E
I/O1
I/O11
NC
NC
NC
NC
NC
NC
NC
WP
W
NC
NC
NC
VSS
VDD
AL
NC
NC
CL
NC
I/O13
I/O15
I/O5
VSS
NC
VSS
I/O0
NC
NC
NC
NC
NC
VDD
11/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Figure 6. FBGA55 Connections, x8 devices (Top view through package)
AI09366b
I/O7
WP
I/O4I/O3
NC VDD
I/O5VDD
NC
H
VSS
I/O6
D
E
CL
C
NC
NC
BDU
NC
W
NC
A
87654321
NCNC
NC NC
G
F
E
I/O0
AL
NC NC
NC
NCNC NC NCNC
NCNC
VSS
NCNC
NC NC
RB
I/O2
NC
DU
I/O1
R
NC
NC
NC
VSS
DU
DU
DUDU
DU
M
L
K
J
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
12/56
Figure 7. FBGA55 Connections, x16 devices (Top view through package)
AI09365b
I/O15
WP
I/O4I/O11
I/O10 VDD
I/O6VDD
I/O3
H
VSS
I/O13
D
E
CL
C
NC
NC
BDU
NC
W
NC
A
87654321
NCNC
NC NC
G
F
E
I/O1
AL
NC NC
NC
NCNC NC I/O7I/O5
I/O14I/O12
VSS
NCNC
NC NC
RB
I/O2
I/O0
DU
I/O9
R
NC
NC
I/O8
VSS
DU
DU
DUDU
DU
M
L
K
J
13/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Figure 8. FBGA63 Connections, x8 devices (Top view through package)
AI07586B
I/O7
WP
I/O4I/O3
NC VDD
I/O5VDD
NC
H
VSS
I/O6
D
E
CL
C
NC
NC
BDU
NC
W
NC
A
87654321
NCNC
NC NC
G
F
E
I/O0
AL
DU
NC NC
NC
NCNC NC NCNC
NCNC
VSS
NCNC
NC NC
RB
I/O2
DU
NC
DU
I/O1
109
R
NC
NC
NC
VSS
DU
DU DU
DU
DU DU
DU
DU
DU DU
DU
M
L
K
J
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
14/56
Figure 9. FBGA63 Connections, x16 devices (Top view through package)
AI07560B
I/O15
WP
I/O4I/O11
I/O10 VDD
I/O6
VDD
I/O3
H
VSS
I/O13
D
E
CL
C
NC
NC
BDU
NC
W
NC
A
87654321
NCNC
NC NC
G
F
E
I/O1
AL
DU
NC NC
NC
NCNC NC I/O7I/O5
I/O14I/O12
VSS
NCNC
NC NC
RB
I/O2
DU
I/O0
DU
I/O9
109
R
NC
NC
I/O8
VSS
DU
DU DU
DU
DU DU
DU
DU
DU DU
DU
M
L
K
J
15/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
MEMORY ARRAY ORGANIZATION
The memory array is made up of NAND structures
where 16 cells are connected in series.
The memory array is organized in blocks where
each block contains 32 pages. The array is split
into two areas, th e m ain ar e a a nd the sp ar e ar ea.
The main area of the array is used to store data
whereas the spare area is typically used to store
Error correction Codes, software flags or Bad
Block identification.
In x8 dev ices the pa ges are spli t into a main area
with two half pages of 256 Bytes each and a spare
area of 16 Bytes. In the x16 devices the pages are
split into a 256 Word main area and an 8 Word
spare area. Refer to Figure 10., Memory Array Or-
ganization.
Bad Blocks
The NAND Flash 528 Byte/ 264 Word Page devic-
es may contain Bad Blocks, that is blocks that con-
tain one or more invalid bits whose reliability is not
guaranteed. Additional Bad Blocks may develop
during the lifetime of the device.
The Bad Blo ck Inform ation is wr itten prior to ship -
ping (refer to Bad Block Management section for
more details).
Table 4. shows the minimum number of valid
blocks in each device. The values shown include
both the Bad Blocks that are present when the de-
vice is shipp ed and th e Ba d Block s that c ould de -
velop later on.
These blocks need to be managed using Bad
Blocks M ana gem ent, B lo ck Replaceme nt or E rro r
Correction Codes (refer to SOFTWARE ALGO-
RITHMS section).
Table 4. Valid Blocks
Figure 10. Memory Array Organization
Density of Device Min Max
1Gbit 8032 8192
512Mbits 4016 4096
256Mbits 2008 2048
128Mbits 1004 1024
AI07587
Block = 32 Pages
Page = 528 Bytes (512+16)
512 Bytes
512 Bytes
Spare Area
2nd half Page
(256 bytes)
16
Bytes
Block
8 bits
16
Bytes 8 bits
Page
Page Buffer, 512 Bytes
1st half Page
(256 bytes)
Block = 32 Pages
Page = 264 Words (256+8)
256 Words
256 Words
Spare Area
Main Area
8
Words
16 bits
8
Words 16 bits
Page Buffer, 264 Words
Block
Page
x8 DEVICES x16 DEVICES
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
16/56
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table
3., Signal Names, for a brief overview of the sig-
nals connected to this device.
Inputs/Outputs (I/O0-I/O7). Input/Outputs 0 to 7
are used to input the selected address, output the
data during a Read operation or input a command
or data during a Write operation. The inputs are
latched on the r i sing e dge of Write E na ble . I/O 0-I/
O7 are left floatin g when t he dev ice is deselec ted
or the outputs are disabled.
Inputs/Outputs (I/O8-I/O15). Input/Outputs 8 to
15 are only available in x16 devices. They are
used to output the data during a Read operation or
input data during a Write operation. Command and
Address Inputs only require I/O0 to I/O7.
The inp uts ar e la tch ed on the rising edge of W rite
Enable. I/O8-I/O15 are left floating when the de-
vice is deselected or the outputs are disabled.
Address Latch Enable (A L). The Ad dress Latc h
Enable activates the latching of the Address inputs
in the Command Interface. When AL is high, the
inputs ar e latched on th e rising edg e of Write En -
able.
Command Latch Enable (CL). The Command
Latch Enable activates the latching of the Com-
mand inputs in the Command Interface. When CL
is high, the inputs are latched on the rising edge of
Write Enable.
Chip Enable (E). The Chip Enable input acti-
vates th e memory c ontrol lo gic, input buffers, de -
coders and sense amplifiers. When Chip Enable is
low, VIL, the device is selected. If Chip Enable
goes high, vIH, while the device is busy, the device
remains selected and does not go into standby
mode.
When the device is executing a Sequential Row
Read operation, Chip Enable must be held low
(from the second page read onwards) during the
time that the device is busy (tBLBH1). If Chip En-
able goes high during tBLBH1 the operation is
aborted.
Read Enable (R). The Read Enable, R, controls
the sequential data output during Read opera-
tions. Data is valid tRLQV after the falling edge of R.
The falling e dge of R also increme nts the internal
column address counter by one.
Write Enable (W). The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data are latched on the rising edge of Write En-
able.
During power-up and power-down a recovery time
of 1µs (min) is required before the Command Inter-
face is ready to accept a command. It is recom-
mended to keep Write Enable high during the
recovery time.
Write Protect (WP). The Write Protect pin is an
input that g iv es a h ar dware pr otec tion a gai ns t un -
wanted pro gram or era se ope ra tio ns . W hen W rite
Protect is Low, VIL, the device does not accept any
program or erase operations.
It is recommended to keep the Write Protect pin
Low, VIL, during power-up and power-down.
Ready/Busy (RB). The Ready/Busy output, RB,
is an open-drain output that can be used to identify
if the P/E/R Controller is currently active.
When Ready/Busy is Low, VOL, a read, program or
erase operation is in progress. When the operation
completes Ready/Busy goes High, VOH.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Refer to the Ready/Busy Signal Electrical Charac-
teristics section for details on how to calculate the
value of the pull-up resistor.
VDD Supply Voltage. VDD provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations (read,
program and erase).
An inter nal voltage de tector disab les all funct ions
whenever VDD is below 2.5V (for 3V devices) or
1.5V (for 1.8V devices) to protect the device from
any invol unt ary pr og ra m/e rase dur in g powe r-tr an -
sitions.
Each devi ce in a s yste m shoul d have V DD decou-
pled with a 0.1µF capacitor. The PCB track widths
should be sufficient to carry the required program
and erase currents
VSS Ground. Ground, VSS, is the reference for
the power supply. It must be connected to the sys-
tem ground.
17/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
BUS OPERATIONS
There are six standard bus operations that control
the memory. Each of these is described in this
section, see Tab le 5., Bus O perations, for a sum-
mary.
Command Input
Command Input bus operations are used to give
commands to the memory. Command are accept-
ed when Chip Enable is Low, Command Latch En-
able is High, Address Latch Enable is Low and
Read Enable is High. They are latc hed on the ris -
ing edge of the Write Enable signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 25. and Table 20. for details of the tim-
in gs requirements.
Address Input
Address Input bus operations are used to input the
memory address. Three bus cycles are required to
input the addresses for the 128Mb and 256Mb de-
vices and four bus cycles are required to input the
addresses for the 512Mb and 1Gb devices (refer
to Tables 6 and 7, Address Insertion).
The addresses are accepted when Chip Enable is
Low, Address Latch Enable is High, Command
Latch Enable is Low and Read Enable is High.
They are latched on the rising edge of the Write
Enable signal. O nly I/O0 to I/ O7 are us ed to in put
addresses.
See Figure 26. and Table 20. for details of the tim-
in gs requirements.
Data Input
Data Input bus operations are used to input the
data to be programmed.
Data is accepted only when Chip Enable is Low,
Address Latch Enable is Low, Command Latch
Enable is Low and Read Enable is High. The data
is latched on the rising edge of the Write Enable
signal. The data is input sequentially using the
Write Enable signal.
See Figure 27. and Table 20. and Table 21. for de-
tails of the timings requirements.
Data Output
Data Output bu s operations are used to read : the
data in the memory array, the Status Register, the
Electronic Signature and the Serial Number.
Data is output when Chip Enable is Low, Write En-
able is High, Address Latch Enable is Low, and
Command Latch Enable is Low.
The data is output sequentially using the Read En-
able signal.
See Figure 28. and Table 21. for details of the tim-
in gs requirements.
Write Protect
Write Protect bus operations are used to protect
the memory against program or erase operations.
When the Write Protect signal is Low the device
will not accept program or erase operations and so
the contents of the memory array cannot be al-
tered. The Write Protect signal is not latched by
Write Enable to ensure protection even during
power-up.
Standby
When Chip Enable is High the memory enters
Standby mode, the device is deselected, outputs
are disabled and power consumption is reduced.
Table 5. Bus Operations
Note: 1. Only for x16 devices.
2. WP must be VIH when issuing a program or erase command.
Bus Op er ati on E AL CL R WWP I/O0 - I/O7 I/O8 - I/O15(1)
Command Input VIL VIL VIH VIH Rising X(2) Command X
Address Input VIL VIH VIL VIH Rising X Address X
Data Input VIL VIL VIL VIH Rising X Data Input Data Input
Data Output VIL VIL VIL Falling VIH X Data Output Data Output
Write Protect XXXXX
VIL XX
Standby VIH XXXXX X X
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
18/56
Table 6. Address Insertion, x8 Devices
Note: 1. A8 is set Low or High by the 00h or 01h Command, see Pointer Operations section.
2. Any additional address input cycles will be ignored.
3. The 4th cycle is only required for 512Mb and 1Gb devices.
Table 7. Address Insertion, x16 Devices
Note: 1. A8 is Don’t Care in x16 dev ices.
2. Any additional address input cycles will be ignored.
3. The 01h Command is not used in x16 devices.
4. The 4th cycle is only required for 512Mb and 1Gb devices.
Table 8. Address Definitions
Bus Cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1st A7 A6 A5 A4 A3 A2 A1 A0
2nd A16 A15 A14 A13 A12 A11 A10 A9
3rd A24 A23 A22 A21 A20 A19 A18 A17
4th(4) VIL VIL VIL VIL VIL VIL A26 A25
Bus
Cycle I/O8-
I/O15 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1st XA7 A6 A5 A4 A3 A2 A1 A0
2nd XA16 A15 A14 A13 A12 A11 A10 A9
3rd XA24 A23 A22 A21 A20 A19 A18 A17
4th(4) XVIL VIL VIL VIL VIL VIL A26 A25
Address Definition
A0 - A7 Column Address
A9 - A26 Page Address
A9 - A13 Address in Block
A14 - A26 Block Address
A8 A8 is set Low or High by the 00h or 01h Command, and is
Don’t Care in x16 devices
19/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
COMMAND SET
All bus write operations to the device are interpret-
ed by the Command Interface. The Commands
are input on I/O0-I/O7 and are latched on the rising
edge of Write Enable when the Command Latch
Enable signal is high. Device operations are se-
lected by writing specific commands to the Com-
mand Register. The two-step command
sequen ces for pro gram and eras e operatio ns are
imposed to maximize data security.
The Commands are summarized in Table
9., Commands.
Table 9. Commands
Note: 1. The bus cycles are on ly shown for issuing the c odes. The cycles requ ired to input th e addresses or input/output data are not shown.
2. Any undefined command sequence will be ignored by the device.
Command Bus Write Operations(1) Comman d acc ep te d
during bu sy
1st CYCL E 2nd CYCLE 3rd CYCLE
Read A 00h - -
Read B 01h(2) - -
Read C 50h - -
Read Electronic Signature 90h - -
Read Status Register 70h - - Yes
Page Program 80h 10h -
Copy Back Program 00h 8Ah 10h
Block Erase 60h D0h -
Reset FFh - - Yes
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
20/56
DEVICE OPERAT IONS
Pointer Operations
As the NAND Flash memories contain two differ-
ent areas for x16 devices and three different areas
for x8 devices (see Figure 11.) the re ad c ommand
codes (0 0h, 01h, 5 0h) are u sed to act a s poin ters
to the different areas of the memory array (they se-
lect the most significant column address).
The Read A and Read B comm ands ac t as point -
ers to the m ain memory a rea. Their use dep ends
on the bus width of the device.
■In x16 devices the Read A command (00h)
sets the pointer to Area A (the whole of the
main area) that is Words 0 to 255.
■In x8 devices the Read A command (00h) sets
the pointer to Area A (the first half of the main
area) that is Bytes 0 to 255, and the Read B
command (01h) sets the pointer to Area B (the
second half of the main area) that is Bytes 256
to 511.
In both the x8 and x16 devices the Read C com-
mand (50h), acts as a pointer to Area C (the spare
memory area) that is Bytes 512 to 527 or Words
256 to 263.
Once the Read A and Read C commands have
been issue d the pointer remai ns in the respectiv e
areas until another pointer code is issued. Howev-
er, the R ead B c ommand i s effect ive for o nly one
operation, once an operation has been executed
in Area B the pointer returns automatically to Area
A.
The poin ter op erations can als o be us ed bef ore a
program operation, that is the appropriate code
(00h, 01h or 50h) can be issued before the pro-
gram command 80h is issued (see Figure 12.).
Figure 11. Pointer Operations
Figure 12. Pointer Operations for Programming
AI07592
Area A
(00h)
A
Area B
(01h) Area C
(50h)
Bytes 0- 255 Bytes 256-511 Bytes 512
-527
CB
Pointer
(00h,01h,50h)
Page Buffer
Area A
(00h)
A
Area C
(50h)
Words 0- 255 Words 256
-263
C
Pointer
(00h,50h)
Page Buffer
x8 Devices x16 Devices
ai07591
I/O Address
Inputs Data Input 10h
80h
Areas A, B, C can be programmed depending on how much data is input. Subsequent 00h commands can be omitted.
AREA A
00h Address
Inputs Data Input 10h
80h
00h
I/O Address
Inputs Data Input 10h
80h
Areas B, C can be programmed depending on how much data is input. The 01h command must be re-issued before each program.
AREA B
01h Address
Inputs Data Input 10h
80h
01h
I/O Address
Inputs Data Input 10h
80h
Only Areas C can be programmed. Subsequent 50h commands can be omitted.
AREA C
50h Address
Inputs Data Input 10h
80h
50h
21/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Read Memory Array
Each operation to read the memory area starts
with a pointer operation as shown in the Pointer
Operations section. Once the area (main or spare)
has been selected using the Read A, Read B or
Read C commands four bus cycles (for 512Mb
and 1Gb dev ices) or three b us cycles (for 128 Mb
and 256Mb dev ices) are requ ired to input th e ad-
dress (refer to Table 6.) of the data to be read.
The devi ce defaul ts to Read A m ode aft er pow er-
up or a Reset operation. D ev ices , whe re pag e0 i s
read automatically at power-up, are available on
request.
When reading the spare area addresses:
■A0 to A3 (x8 devices)
■A0 to A2 (x16 devices)
are used to set the start address of the spare area
while addresses:
■A4 to A7 (x8 devices)
■A3 to A7 (x16 devices)
are ignored.
Once the Read A or Read C commands have
been issued they do not need to be reissued for
subsequent read operations as the pointer re-
mains i n the respec tive area. Howe ver, the Re ad
B command is effective for only one operation,
once an operation has been executed in Area B
the pointer retur ns autom ati ca ll y to Ar ea A and so
another Read B co mmand is required to start an-
other read operation in Area B.
Once a read command is issued three types of op-
erations are available: Random Read, Page Read
and Sequential Row Read.
Random Read. Each time the command is is-
sued the first read is Random Read.
Page Read. After the Random Read access the
page data is transferred to the Page Buffer in a
time of tWHBH (refer to Table 21. for value). Once
the transfer is complete the Ready/Busy signal
goes High. The data can then be read out sequen-
tially (from selected column address to last column
address) by pulsing the Read Enable signal.
Sequential Row Read. A fter the data in last col-
umn of the page is output, if the Read Enable sig-
nal is pulsed and Chip Enable remains Low then
the next page is automatically loaded into the
Page Buffer and the read operation continues. A
Sequential Row Read operati on ca n onl y be used
to read within a bl ock. If the block c hanges a new
read command must be issued.
Refer to Figure 15. and Figure 16. for details of Se-
quential Row Read operations.
To terminate a Sequential Row Read operation set
the Chip Enable signal to High for more than tEHEL.
Sequential Row Read is not available when the
Chip Enable Don't Care option is enabled.
Figure 13. Read (A,B,C) Operations
CL
E
W
AL
R
I/O
RB
00h/
01h/ 50h
ai07595
Busy
Command
Code
Address Input Data Output (sequentially)
tBLBH1
(read)
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
22/56
Figure 14. Read Block Diagrams
Note: 1. Highest address depends on device density.
Figure 15. Sequential Row Read Operations
Figure 16. Sequential Row Read Block Diagrams
AI07596
A0-A7
A9-A26(1)
Area A
(1st half Page)
Read A Command, X8 Devices
Area B
(2nd half Page) Area C
(Spare) Area A
(main area) Area C
(Spare)
A0-A7
Read A Command, X16 Devices
A0-A7
Read B Command, X8 Devices
Area A
(1st half Page) Area B
(2nd half Page) Area C
(Spare)
A0-A3 (x8)
A0-A2 (x16)
Read C Command, X8/x16 Devices
Area A Area A/ B Area C
(Spare)
A9-A26(1)
A9-A26(1)
A9-A26(1)
A4-A7 (x8), A3-A7 (x16) are don't care
I/O
RB
Address Inputs
ai07597
1st
Page Output
Busy
tBLBH1
(Read Busy time)
00h/
01h/ 50h
Command
Code
2nd
Page Output Nth
Page Output
BusyBusy
tBLBH1 tBLBH1
AI07598
Block
Area A
(1st half Page)
Read A Command, x8 Devices
Area B
(2nd half Page) Area C
(Spare) Area A
(main area) Area C
(Spare)
Read A Command, x16 Devices
Read B Command, x8 Devices Read C Command, x8/x16 Devices
Area A Area A/ B Area C
(Spare)
Area A
(1st half Page) Area B
(2nd half Page) Area C
(Spare)
1st page
2nd page
Nth page
1st page
2nd page
Nth page
1st page
2nd page
Nth page
1st page
2nd page
Nth page
Block
Block
Block
23/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Page Program
The Page Program operation is the standard oper-
ation to program data to the memory array.
The main area of the memory array is pro-
grammed by page, however partial page program-
ming is allowed where any number of bytes (1 to
528) or words (1 to 264) can be programmed.
The maximum number of consecutive partial page
program operations allowed in the same page is
three. After exceeding this a Block Erase com-
mand must be issue d before any furthe r program
operations can take place in that page.
Before starting a Page Program operation a Point-
er operation can be performed to point to the area
to be programmed. Refer to the Pointer Opera-
tions se cti on and Figure 12. for details.
Each Page Program operation consists of five
steps (see Figure 17.):
1. one bus cycle is required to setup the Page
Program command
2. four bus cycles are then required to input the
program address (refer to Table 6.)
3. the data is then input (up to 528 Bytes/ 264
Words) and loaded into the Page Buffer
4. one bus cycle is required to issue the confirm
command to start the P/E/R Controller.
5. The P/E/R Controller then programs the data
into the array.
Once the program operation has started the Sta-
tus Register can be read using the Read Status
Register command. During program operations
the Status Regi ste r will onl y flag erro rs for bits set
to '1' that have not been successfully programmed
to '0'.
During the prog ra m op er ation, onl y the Read Sta -
tus Register and Reset commands will be accept-
ed, all other commands will be ignored.
Once the program operation has completed the P/
E/R Control ler bi t SR 6 is se t to ‘1 ’ and the Read y/
Busy signal goes High.
The device remains in Read Status Register mode
until another valid command is written to the Com-
mand Interface.
Figure 17. Page Program Operation
Note: Before starting a Page Program operation a Poin ter operation can be performed. Refer t o Pointer Operations section for details.
I/O
RB
Address Inputs SR0
ai07566
Data Input 10h 70h
80h
Page Program
Setup Code Confirm
Code Read Status Register
Busy
tBLBH2
(Program Busy time)
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
24/56
Copy Back Program
The Copy Back Program operation is used to copy
the data stored in one page and reprogram it in an-
other page.
The Copy Back Program operation does not re-
quire external memory and so the operation is
faster and more efficient because the reading and
loading cycles are not required. The operation is
particul arl y us ef ul wh en a po rtio n of a block is up -
dated and the rest of the block needs to be copied
to the newly assigned block.
If the Copy Bac k Program oper ation fails an error
is signalled in the Status Register. However as the
standard external ECC cannot be used with the
Copy Back operation bit error due to charge loss
cannot be detected. For this reason it is recom-
mended to limit the number of Copy Back opera-
tions on the same data and or to improve the
performance of the ECC.
The Copy Back Pr ogram o perati on requi res three
steps:
1. The source page must be read using the Read
A command (one bus write cycle to setup the
command and then 4 bus write cycles to input
the source page address). This operation
copies all 264 Words/ 528 Bytes from the page
into the Page Buffe r.
2. When the device returns to the ready state
(Ready/Busy High), the second bus write
cycle of the command is given with the 4 bus
cycles to input the target page address. Refer
to Table 10. for the addresses that must be the
same for the Source and Target pages.
3. Then the confirm command is issued to start
the P/E/R Controller.
After a Copy Back Program operation, a partial-
page program is not allowed in the target page un-
til the block has been erased.
See Figure 18. for an example of the Copy Back
operation.
Table 10. Copy Back Program Addresses
Figure 18. Copy Back Operation
Density Same Address for Source and
Target Pages
128Mbit A23
256Mbit A24
512Mbit A25
1Gbit A25,A26
I/O
RB
Source
Address Inputs SR0
ai07590b
8Ah 70h00h
Copy Back
Code
Read
Code Read Status Register
Target
Address Inputs
tBLBH1
(Read Busy time)
10h
Busy
tBLBH2
(Program Busy time)
25/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Block Erase
Erase operations are done one block at a time. An
erase operation sets all of the bits in the ad-
dressed b lock to ‘1’. Al l prev io us da ta in the bl oc k
is lost.
An erase operation consists of three steps (refer to
Figure 19.):
1. One bus cycle is required to setup the Block
Erase command.
2. Only three bus cycles for 512Mb and 1Gb
devices, or two for 128Mb and 256Mb devices
are required to input the block address. The
first cycle (A0 to A7) is not required as only
addresses A14 to A26 (highest address
depends on device density) are valid, A9 to
A13 are ignored. In the last address cycle I/O0
to I/O7 must be set to VIL.
3. One bus cycle is required to issue the confirm
command to start the P/E/R Controller.
Once the er ase op eration ha s comp leted th e Sta-
tus Register can be checked for errors.
Figure 19. Block Erase Operation
Reset
The Reset command is used to reset the Com-
mand Interface and Status Register. If the Reset
comma nd is issued during any operation, the op-
eration will be aborted. If it was a program or erase
operation that was aborted, the contents of the
memory locations being modified will no longer be
valid as the data will be partially programmed or
erased.
If the dev ic e has a lr ead y bee n r eset the n t he new
Reset command will not be accepted.
The Ready/B usy signal goe s Low for tBLBH4 after
the Reset command is issued. The value of tBLBH4
depends on the operation that the device was per-
forming when the command was issued, refer to
Table 21. for the values.
I/O
RB
Block Address
Inputs SR0
ai07593
D0h 70h
60h
Block Erase
Setup Code Confirm
Code Read Status Register
Busy
tBLBH3
(Erase Busy time)
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
26/56
Read Status Register
The device contains a Status Register which pro-
vides information on the current or previous Pro-
gram or Erase operation. The various bits in the
Status Regi ster convey inform ation and errors on
the operation.
The Status Register is read by issuing the Read
Status Register command. The Status Register in-
formation is presen t on the output da ta bus (I/O0 -
I/O7) on the falling edge of Chip Enable or Read
Enable, whichever occurs last. When several
memories are connected in a system, the use of
Chip Enable and Read Enable signals allows the
system to poll each device separately, even when
the Ready/Busy pins are common-wired. It is not
necessa ry to toggle the Ch ip Enable or Rea d En-
able signals to update the contents of the Status
Register.
After the Read Status Register command has
been issued, the device remains in Read Status
Register mode until another command is issued.
Therefore if a Read Status Register command is
issued during a Random Read cycle a new read
command must be issued to continue with a Page
Read or Sequential Row Read operation.
The Status Regis te r bits ar e su mma r ized in Table
11., Status Register Bits. Refer to Table 11. in
conjunction with the following text descriptions.
Write Protection Bit (SR7). The Write Protection
bit can be used to identify if the device is protected
or not. If the Write Protection bit is set to ‘1’ the de-
vice is not prote cte d and pr og ram or eras e ope ra -
tions are al lowed. If the Write Prote ction bit is set
to ‘0’ the device is protected and program or erase
operations are not allowed.
P/E/R Controller Bit (SR6). The P rogram/ Erase/
Read Controller bit indicates whether the P/E/R
Controller is active or inactive. When the P/E/R
Controller bit is set to ‘0’, the P/E/R Controller is
active (device is busy); when the bit is set to ‘1’, the
P/E/R Controller is in active (device is ready).
Erro r Bit ( SR0 ). The Error bit is used to identify if
any errors h av e bee n de tected by the P /E /R Con -
tr oller. The Err or Bit is set to ’1’ w hen a progra m or
erase operation has failed to write the correct data
to the memory. If the Error Bit is set to ‘0’ the oper-
ation has completed successfully.
SR5, SR4, SR3, SR2 and SR1 are Reserved.
27/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Table 11. Status Register Bits
Read Electronic Signature
Th e d e v i ce c o n tai n s a Manufacturer Code and De-
vice Cod e . To r ea d t hes e co des two step s are re -
quired:
1. first use one Bus Write cycle to issue the Read
Electronic Signature command (90h)
2. then perform two Bus Read operations – the
first will read the Manufacturer Code and the
second, the Device Code. Further Bus Read
operations will be ignored.
Refer to Table 1 2., Electro nic Signatu re, for inf or-
mation on the addresses.
Table 12. Electronic Signature
Bit Name Logic Level Definition
SR7 Write Protection '1' Not Protected
'0' Protected
SR6 Program/ Erase/ Read
Controller '1' P/E/R C inactive, device ready
'0' P/E/R C active, device busy
SR5, SR4,
SR3, SR2, SR1 Reserved Don’t Care
SR0 Generic Error ‘1’ Error – operation failed
‘0’ No Error – operation successful
Part Number Manufacturer
Code Devic e cod e
NAND128R3A 20h 33h
NAND128W3A 73h
NAND128R4A 0020h 0043h
NAND128W4A 0053h
NAND256R3A 20h 35h
NAND256W3A 75h
NAND256R4A 0020h 0045h
NAND256W4A 0055h
NAND512R3A 20h 36h
NAND512W3A 76h
NAND512R4A 0020h 0046h
NAND512W4A 0056h
NAND01GR3A 20h 39h
NAND01GW3A 79h
NAND01GR4A 0020h 0049h
NAND01GW4A 0059h
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
28/56
Automatic Page 0 Read at Power-Up
Automatic Page 0 Read a t Power- Up is an o ption
available on all devices belonging to the NAND
Flash 528 Byte/264 Word Page family. It allows
the microcontroller to directly download boot code
from page 0, without requiring any command or
address input sequence. The Automatic Page 0
Read option is particularly suited for applications
that boot from the NAND.
Devices del iv ered wi th A utom ati c Pag e 0 Read at
Power-Up can have the Chip Enable Don’t Care
option either enabled or disabled. For details on
how to order the different options, refer to Table
28., Ordering Information Scheme.
Automatic Page 0 Read Description. A t power-
up, once the supply voltage has reached the
threshold level, VDDth, all digital outputs revert to
their reset state and the internal NAND device
functions (reading, writing, erasing) are enabled.
The device then automatically switches to read
mode whe re, as in any read operation , the devic e
is busy for a time tBLBH1 during which data is trans-
ferred to the Page Buffer. Once the data transfer is
complete the Ready/Busy signal goes High. The
data can then be r ead out sequenti ally on the I/O
bus by pulsing the Read Ena bl e, R, signal. Figure
20. and Figure 21. s how the power- up wavefo rm s
for devices featuring the Automatic Page 0 Read
option.
Chip Enable Don’t Care Enabled. If the device
is deli vered with Chip Enab le Don’t Care and Au-
tomatic Page 0 Read at Power-up, only the first
page (Page 0) will be automa tically read af ter the
power-up sequence. Refer to Figure 20..
Chip Enable Don’t Care Disabled. If the device
is delivered with the Automatic Page 0 Read op-
tion only (Chip Enable Don’t Care disabled), the
device will automatically enter Sequential Row
Read mode (Automatic Memory Download) after
the power-up sequence, and start reading Page 0,
Page 1, etc., until the last memory location is
reached, each new page being accessed after a
time tBLBH1.
The Sequential Row Read operation can be inhib-
ited or interrupted by de-asserting E (set to VIH) or
by issuing a command.
Figure 20. Chip Enable Don’t Care Enabled and Automatic Page 0 Read at Power-Up
Note: 1. VDDth is equal to 2.5V for 3V Power Supply devi ces and to 1.5V for 1.8V Power Supply devices.
VDD
W
E
AL
CL
RB
R
I/O
tBLBH1
Data
NData
N+1 Data
N+2 Last
Data
Busy Data Output
from Address N to Last Byte or Word in Page
VDDth (1)
ai08443b
29/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Figure 21. Automatic Page 0 Read at Power-Up (Chip Enable Don’t Care Disabled)
SOFTWARE ALGORITHMS
This se ction gives info rmation on the soft ware al-
gorithms that ST recommends to implement to
manage the Bad Blocks and extend the lifetime of
the NAND device.
NAND Flash memories are programmed and
erased by Fowler-Nordheim tunneling using a high
voltage. E xpos ing th e devi ce to a high vo ltag e for
extend ed period s ca n caus e the o xide lay er to be
damaged. For this reason, the number of program
and erase cycles is l imited (see T able 14. for v al-
ue) and it is recommended to implement Garbage
Collecti on, a Wear-L eveling Algor ithm and a n Er-
ror Correction Code, to extend the number of pro-
gram and erase cycles and increase the data
retention.
To help integrate a NAND memory into an applica-
tion ST Microelectronics can provide:
■A Demo board with NAND simulation software
for PCs
■File System OS Native reference software,
which supports the basic commands of file
management.
Contact the neares t ST Mi croe lectron ics sales of-
fice for more details.
Bad Block Management
Devices with Bad Blocks have the same quality
level and th e same AC and DC charact eristics as
devices where all the blocks are valid. A Bad Block
does not affect the performance of valid blocks be-
cause it is isolated from the bit line and common
source line by a select transistor.
The device s are suppli ed with all the loc ations in-
side vali d blocks erase d (FFh). T he Bad Bl ock In-
formation is written prior to shipping. Any block
where the 6th B yte/ 1st Wo rd in the spare area of
the 1st or 2nd page (if the 1st page is Bad) does
not contain FFh is a Bad Block.
The Bad Block Information must be read before
any erase i s a ttem pted as the B ad Bloc k In for ma -
tion may be erased. For the syst em to be ab le to
recognize the Bad Blocks based on the original in-
formation it is recommended to create a Bad Block
table following the flowchart shown in Figure 22.
Block Replacement
Over the lifetime of the device additional Bad
Blocks may de velop . In this case the b lock has to
be replaced by copying the data to a valid block.
These additional Bad Blocks can be identified as
attempts to program or erase them will give errors
in the Status Register.
As the failure of a page program operation does
not affect the data in other pages in the same
block, the block can be replaced by re-program-
ming the current data and copying the rest of the
replaced block to an available valid block. The
Copy Back Program command can be used to
copy the data to a valid block.
See the “Copy Back Program” section for more de-
tails.
Refer to Table 13. for the recommended proce-
dure to follow if an error occurs during an opera-
tion.
Table 13. Block Failure
I/O
RB
Page 0
Data Out
ai08444
Page 1
Data Out
Busy
tBLBH1
Page 2
Data Out Page Nth
Data Out
BusyBusy
tBLBH1 tBLBH1
tBLBH1
(Read Busy time)
Busy
Operation Recommended Procedure
Erase Block Replacement
Program Block Replacement or ECC
Read ECC
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
30/56
Figure 22. Bad Block Management Flowchart
Figure 23. Garbage Collection
Garbage Collection
When a data page needs to be modified, it is faster
to write to the first available page, and the previous
page is marked as invalid. After several updates it
is necessary to remove invalid pages to free some
memory space.
To free this memory space a nd allow fu rther pro-
gram ope rations it is recomme nded to impl ement
a Garbage Collection algorithm. In a Garbage Col-
lection s oftware the valid pages are co pied into a
free area and the block containing the invalid pag-
es is erased (see Figure 23.).
Wear-leveling Algorithm
For write-intensive applications, it is recommend-
ed to implement a Wear-leveling Algorithm to
monitor and spread the number of write cycles per
block.
In memories that do not use a Wear-Leveling Al-
gorithm not all blocks get used at the same rate.
Blocks with long-lived data do not endure as many
write cycles as the blocks with frequently-changed
data.
The Wear-leveling Algorithm ensures that equal
use is made of all the available write cycles for
each block. There are two wear-leveling levels:
AI07588C
START
END
NO
YES
YES
NO
Block Address =
Block 0
Data
= FFh?
Last
block?
Increment
Block Address
Update
Bad Block table
Valid
Page
Invalid
Page Free
Page
(Erased)
Old Area
AI07599B
New Area (After GC)
31/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
■First Level Wear-leveling, new data is
programmed to the free blocks that have had
the fewest write cycles
■Second Level Wear-leveling, long-lived data is
copied to another block so that the original
block can be used for more frequently-
changed data.
The Second Level Wear-leveling is triggered when
the difference between the maximum and the min-
imum n umber of wr ite cycl es per blo ck reach es a
specific threshold.
Error Correction Code
An Error Correction Code (ECC) can be imple-
mented in the Nand Flash memories to identify
and correct errors in the data.
For every 2048 bits in the device it is recommend-
ed to implement 22 bits of ECC (16 bits for line par-
ity plus 6 bits for column parity).
An ECC model is available in VHDL or Verilog.
Contact the neares t ST Mi croe lectron ics sales of-
fice for more details.
Figure 24. Error Detection
Hardware Simulation Models
Behavioral simulation models. Denali Software
Corporation models are platform independent
functional models designed to assist customers in
performing entire system simulations (typical
VHDL/Verilog). These models describe the logic
behavior and timings of NAND Flash devices, and
so allow software to be developed before hard-
ware.
IBIS simulations models. IBIS (I/O Buffer Infor-
mation S pecific ation) m ode ls des cribe t he beh av-
ior of the I/O buffers and elect rical characte ristics
of Flash devices.
These models provide information such as AC
characteristics, rise/fall times and package me-
chanica l data, all of wh ich are meas ured or simu -
lated at voltage and temperature ranges wider
than those allowed by target specifications.
IBIS models are used to simulate PCB connec-
tions and can be used to resolve compatibi lity is-
sues when upgrading devices. They can be
imported into SPICETOOLS.
New ECC generated
during read
XOR previous ECC
with new ECC
All results
= zero?
22 bit data = 0
YES
11 bit data = 1
NO
1 bit data = 1
Correctable
Error ECC Error
No Error
ai0833
2
>1 bit
= zero?
YES
NO
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
32/56
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES
The Progra m and Erase tim es and the num ber of
Program/ Erase cycles per block are shown in Ta-
ble 14.
Table 14. Program, Erase Times and Program Erase Endurance Cycles
MAXIMUM RATING
Stressing the device above the ratings listed in Ta-
ble 15., Absolute Maximum Ratings, may cause
permanent damage to the device. These are
stress ratings only and operation of th e device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicro ele ctr o nic s S URE P ro gram an d other rel -
evant quality documents.
Table 15. Absolute Maximum Ratings
Note: 1. Minimum Voltage may undershoot to –2V for less than 20ns during transitions on input and I/O pins. Maximum voltage may over-
shoot to VDD + 2V for les s than 20ns dur ing transitions on I/O pins.
Parameters NAND Flash Unit
Min Typ Max
Page Program Time 200 500 µs
Block Erase Time 23ms
Program/Erase Cycles (per block) 100,000 cycles
Data Retention 10 years
Symbol Parameter Value Unit
Min Max
TBIAS Temperature Under Bias – 50 125 °C
TSTG Storage Temperature – 65 150 °C
VIO (1) Input or Output Voltage 1.8V device s – 0.6 2.7 V
3 V devices – 0.6 4.6 V
VDD Supply Voltage 1.8V device s – 0.6 2.7 V
3 V devices – 0.6 4.6 V
33/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
DC AND AC PARA METERS
This section summarizes th e operating and mea-
suremen t cond itions, and the D C and A C ch arac -
teristics of the device. The parameters in the DC
and AC charac terist ics Tables that follow , are de-
rived from tests performed under the Measure-
ment Conditions summarized in Table
16., Operating and AC Measurement Conditions.
Designers should check that the operating condi-
tions in their circuit match the measurement condi-
tions when relying on the quoted parameters.
Table 16. Operating and AC Measurement Conditions
Table 17. Capacitance
Note: TA = 25°C, f = 1 MHz. CIN and CI/O are not 100 % tested.
Parameter NAND Flash Units
Min Max
Supply Voltage (V DD)1.8V devices 1.7 1.95 V
3V device s 2.7 3.6 V
Ambient Temperature (TA)Grade 1 0 70 °C
Grade 6 –40 85 °C
Load Capacitance (CL) (1 TTL GATE and CL)
1.8V devices 30 pF
3V devices (2.7 - 3.6V) 50 pF
3V devices (3.0 - 3.6V) 100 pF
Input Pulses Voltages 1.8V devices 0 VDD V
3V device s 0.4 2.4 V
Input and Output Timing Ref. Voltages 1.8V devices 0.9 V
3V device s 1.5 V
Input Rise and Fall Times 5 ns
Symbol Parameter Test Condition Typ Max Unit
CIN Input Capacitance VIN = 0V 10 pF
CI/O Input/Outp ut Ca pacitanc e VIL = 0V 10 pF
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
34/56
Table 18. DC Characteristics, 1.8V Devices
Symbol Parameter Test Conditions Min Typ Max Unit
IDD1 Operating
Current
Sequential
Read tRLRL minimum
E=VIL, IOUT = 0 mA - 8 15 mA
IDD2 Program - - 8 15 mA
IDD3 Erase - - 8 15 mA
IDD5
Stand-By Current (CMOS)
128Mb, 256Mb, 512Mb devices E=VDD-0.2,
WP=0/VDD
-10 50 µA
Stand-By Current (CMOS)
512Mb and 1Gb Dual Die devices -20 100 µA
ILI Input Leakage Current VIN= 0 to VDDmax - - ±10 µA
ILO Output Leakage Current VOUT= 0 to VDDmax - - ±10 µA
VIH Input High Voltage -VDD-0.4 -VDD+0.3 V
VIL Input Low Voltage --0.3 -0.4 V
VOH Output Hig h Voltage Level IOH = -100µA VDD-0.1 - - V
VOL Output Low Voltage Level IOL = 100µA - - 0.1 V
IOL (RB)Output Low Current (RB)VOL = 0.1V 3 4 mA
VLKO VDD Supply Voltage (Erase and
Program lockout) - - - 1.5 V
35/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Table 19. DC Characteristics, 3V Devices
Symbol Parameter Test Conditions Min Typ Max Unit
IDD1 Operating
Current
Sequential
Read tRLRL minimum
E=VIL, IOUT = 0 mA -10 20 mA
IDD2 Program - - 10 20 mA
IDD3 Erase - - 10 20 mA
IDD4
Stand-by Current (TTL),
128Mb, 256Mb, 512Mb devices E=VIH, WP=0V/VDD
- - 1 mA
Stand-by Current (TTL)
512Mb and 1Gb Dual Die devices - - 2 mA
IDD5
Stand-By Current (CMOS)
128Mb, 256Mb, 512Mb devices E=VDD-0.2,
WP=0/VDD
-10 50 µA
Stand-By Current (CMOS)
512Mb and 1Gb Dual Die devices -20 100 µA
ILI Input Leakage Current VIN= 0 to VDDmax - - ±10 µA
ILO Output Leakage Current VOUT= 0 to VDDmax - - ±10 µA
VIH Input High Voltage -2.0 -VDD+0.3 V
VIL Input Low Voltage -−0.3 -0.8 V
VOH Output Hig h Voltage Level IOH = −400µA 2.4 - - V
VOL Output Low Voltage Level IOL = 2.1mA - - 0.4 V
IOL (RB)Output Low Current (RB)VOL = 0.4V 810 mA
VLKO VDD Supply Voltage (Erase and
Program lockout) - - - 2.5 V
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
36/56
Table 20. AC Characteristics for Command, Address, Data Input
Note: 1. If tELWL is less than 10ns , tWLWH must be minimum 35ns, otherwise, tWLWH may be minimum 25ns.
Symbol Alt.
Symbol Parameter 1.8V
Devices 3V
Devices Unit
tALLWL tALS Address Latch Low to Write Enable Low AL Setup time Min 0 0 ns
tALHWL Address Latch High to Write Enable Low
tCLHWL tCLS Command Latch High to Write Enable Low CL Setup time Min 0 0 ns
tCLLWL Command Latch Low to Write Enable Low
tDVWH tDS Data Valid to Write Enable High Data Setup time Min 20 20 ns
tELWL tCS Chip Enable Low to Write Enable Low E Setup time Min 0 0 ns
tWHALH tALH Write Enable High to Address Latch High AL Hold time Min 10 10 ns
tWHALL Write Enable High to Address Latch Low
tWHCLH tCLH Write Enable High to Command Latch High CL hold time Min 10 10 ns
tWHCLL Wr it e E na b le H ig h to C om man d La t ch Lo w
tWHDX tDH Write Enable High to Data Transition Data Hold time Min 10 10 ns
tWHEH tCH Write Enable High to Chip Enable High E Hold tim e Min 10 10 ns
tWHWL tWH Write Enable High to Write Enable Low W High Hold
time Min 20 15 ns
tWLWH tWP Write Enable Low to Write Enable High W Pulse Width Min 40 25(1) ns
tWLWL tWC Write Enable Low to Write Enable Low Write Cycle time Min 60 50 ns
37/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Table 21. AC Characteristics for Operations
Note: 1. The time to Read y depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figures 36, 37 and 38.
2. To break the sequential read cycle, E must be held High for longer than tEHEL.
3. ES = Electronic Signatu r e.
Symbol Alt.
Symbol Parameter 1.8V
Devices 3V
Devices Unit
tALLRL1 tAR Address Latch Low to
Read Enable Low Read Electronic Signature Min 10 10 ns
tALLRL2 Read cycle Min 10 10 ns
tBHRL tRR Ready/Busy High to Read Enable Low Min 20 20 ns
tBLBH1
Ready/Busy Low to
Ready/Busy High
Read Busy time, 128Mb, 256Mb,
512Mb Dual Die Max 10 10 µs
Read Busy time, 512Mb, 1Gb Max 15 12 µs
tBLBH2 tPROG Program Busy time Max 500 500 µs
tBLBH3 tBERS Erase Busy time Max 3 3 ms
tBLBH4 Reset Bus y tim e, dur ing read y Max 5 5 µs
tWHBH1 tRST Write Enable High to
Ready/Busy High
Reset Bus y tim e, dur ing read Max 5 5 µs
Reset Bus y tim e, during prog ram Max 10 10 µs
Reset Bus y tim e, during eras e Max 500 500 µs
tCLLRL tCLR Command Latch Low to Read Enable Low Min 10 10 ns
tDZRL tIR Data Hi-Z to Read Enable Low Min 0 0 ns
tEHBH tCRY Chip Enable High to Ready/Busy High (E intercepted read) Max 60 + tr(1) 60 + tr(1) ns
tEHEL tCEH Chip Enable High to Chip Enable Low(2) Min 100 100 ns
tEHQZ tCHZ Chip Enable High to Output Hi-Z Max 20 20 ns
tELQV tCEA Chip Enable Low to Output Valid Max 45 45 ns
tRHBL tRB Read E nable High to Ready/Busy Low Max 100 100 ns
tRHRL tREH Read Ena b le High to
Read Enable Low Read Enable High Hold t ime Min 15 15 ns
tRHQZ tRHZ Read Enable High to Output Hi-Z Min 15 15 ns
Max 30 30
tRLRH tRP Read Enable Low to
Read Enable High Read Enable Pulse Width Min 30 30 ns
tRLRL tRC Read Enable Low to
Read Enable Low Read Cycle time Min 60 50 ns
tRLQV tREA Read Enable Low to
Output Valid Read Enable Access time Max 35 35 ns
Read ES Ac ces s time(3)
tWHBH tRWrite Enable High to
Ready/Busy High
Read Busy time, 128Mb, 256Mb,
512Mb Dual Die Max 10 10 µs
Read Busy time, 512Mb, 1Gb Max 15 12 µs
tWHBL tWB Write Enable High to Ready/Busy Low Max 100 100 ns
tWHRL tWHR Write Enable High to Read Enable Low Min 80 60 ns
tWLWL tWC Write Enable Low to
Write Enable Low Write Cycle time Min 60 50 ns
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
38/56
Figure 25. Command Latch AC Waveforms
Figure 26. Address Latch AC Waveforms
Note: Address cycle 4 is only required for 512Mb and 1G b devices.
ai08028
CL
E
W
AL
I/O
tCLHWL
tELWL
tWHCLL
tWHEH
tWLWH
tALLWL tWHALH
Command
tDVWH tWHDX
(CL Setup time) (CL Hold time)
(Data Setup time) (Data Hold time)
(ALSetup time) (AL Hold time)
(E Setup time) (E Hold time)
ai08029
CL
E
W
AL
I/O
tWLWH
tELWL tWLWL
tCLLWL
tWHWL
tALHWL
tDVWH
tWLWL tWLWL
tWLWHtWLWH tWLWH
tWHWL tWHWL
tWHDX
tWHALL
tDVWH
tWHDX
tDVWH
tWHDX
tDVWH
tWHDX
tWHALL
Adrress
cycle 1
tWHALL
(AL Setup time)
(AL Hold time)
Adrress
cycle 4
Adrress
cycle 3
Adrress
cycle 2
(CL Setup time)
(Data Setup time)
(Data Hold time)
(E Setup time)
39/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Figure 27. Data Input Latch AC Waveforms
Figure 28. Sequential Data Output after Read AC Waveforms
Note: 1. CL = Low, AL = Low, W = High.
tWHCLH
CL
E
AL
W
I/O
tALLWL tWLWL
tWLWH
tWHEH
tWLWH
tWLWH
Data In 0 Data In 1 Data In
Last
tDVWH
tWHDX
tDVWH
tWHDX
tDVWH
tWHDX
ai08030
(Data Setup time)
(Data Hold time)
(ALSetup time)
(CL Hold time)
(E Hold time)
E
ai08031
R
I/O
RB
tRLRL
tRLQV
tRHRL
tRLQV
Data Out Data Out Data Out
tRHQZ
tBHRL
tRLQV
tRHQZ
tEHQZ
(Read Cycle time)
(R Accesstime)
(R High Holdtime)
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
40/56
Figure 29. Read Stat us Register AC Waveform
Figure 30. Read Electronic Signature AC Waveform
Note: Refer to Table 12. for the values of the Manufa ct urer and Device Codes.
tELWL
tDVWH
Status Register
Output
70h
CL
E
W
R
I/O
tCLHWL
tWHDX
tWLWH
tWHCLL
tCLLRL
tDZRL
tRLQV
tEHQZ
tRHQZ
tWHRL
tELQV
tWHEH
ai08032
(Data Setup time) (Data Hold time)
90h 00h Man.
code Device
code
CL
E
W
AL
R
I/O
tRLQV
Read Electronic
Signature
Command
1st Cycle
Address Manufacturer and
Device Codes
ai08039b
(Read ES Access time)
tALLRL1
41/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Figure 31. Page Read A/ Read B Operation AC Waveform
Note: Address cycl e 4 is only required for 512Mb and 1Gb devices.
tEHEL
CL
E
W
AL
R
I/O
RB
tWLWL
tWHBL
tALLRL2
00h or
01h
Data
NData
N+1 Data
N+2 Data
Last
tRHBL
tEHBH
tWHBH tRLRL
tEHQZ
tRHQZ
ai08033b
Busy
Command
Code Address N Input Data Output
from Address N to Last Byte or Word in Page
Add.N
cycle 1 Add.N
cycle 4
Add.N
cycle 3
Add.N
cycle 2
(Read Cycle time)
tRLRH
tBLBH1
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
42/56
Figure 32. Read C Operation, One Page AC Waveform
Note: 1. A0-A7 is the address in the Spare Memory area, where A0-A3 are valid and A4-A7 are ‘don’t care’.
CL
E
W
AL
R
I/O
RB
tWHALL
Data M Data
Last
tALLRL2
ai08035
tWHBH
tBHRL
50h Add. M
cycle 1 Add. M
cycle 4
Add. M
cycle 3
Add. M
cycle 2
Busy
Command
Code Address M Input Data Output from M to
Last Byte or Word in Area C
43/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Figure 33. Page Program AC Waveform
Note: Address cycl e 4 is only required for 512Mb and 1Gb devices.
CL
E
W
AL
R
I/O
RB
SR0
ai08037
N
Last 10h
70h
80h
Page Program
Setup Code Confirm
Code Read Status Register
tWLWL tWLWL tWLWL
tWHBL
tBLBH2
Page
Program
Address Input Data Input
Add.N
cycle 1 Add.N
cycle 4
Add.N
cycle 3
Add.N
cycle 2
(Write Cycle time)
(Program Busy time)
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
44/56
Figure 34. Block Erase AC Waveform
Note: Address cycl e 3 is required for 512Mb and 1G b devices only.
Figure 35. Reset AC Waveform
D0h60h SR0
70h
ai08038b
tWHBL
tWLWL
tBLBH3
Block Erase
Setup Command Block Erase
CL
E
W
AL
R
I/O
RB
Confirm
Code Read Status Register
Block Address Input
(Erase Busy time)
(Write Cycle time)
Add.
cycle 1 Add.
cycle 3
Add.
cycle 2
W
R
I/O
RB
tBLBH4
AL
CL
FFh
ai08043
(Reset Busy time)
45/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Ready/Busy Signal Electrical Characteristics
Figures 37, 36 and 38 show th e electrica l ch ar ac-
teristics for the Ready/Busy signal. The value re-
quired for th e resistor RP can be calculated using
the following equation:
So,
where IL is the su m of the i nput c urrents of a ll the
devices ti ed to the Rea dy/Busy sig nal. RP max is
determined by the maximum value of tr.
Figure 36. Ready/Busy AC Waveform
Figure 37. Ready/Busy Load Circuit
Figure 38. Resistor Value Versus Waveform Timings For Ready/Busy Signal
Note: T = 25°C.
RPmin VDDmax VOLmax
–()
IOL IL
+
------------------------------------------------------------=
RPmin 1,8V()1,85V
3mA IL
+
---------------------------=
RPmin 3V() 3,2V
8mA IL
+
---------------------------=
AI07564B
busy
VOH
ready VDD
VOL
tftr
AI07563B
RP
VDD
VSS
RB
DEVICE
Open Drain Output
ibusy
ai07565B
RP (KΩ)
1234
100
300
200
tr, tf (ns)
1
2
3
1.7
0.85
30
1.7 1.7 1.7 1.7
tr
tfibusy
0
400 4
RP (KΩ)
1234
100
300
200
1
2
3
ibusy (mA)
2.4
1.2 0.8
0.6
100
200
300
400
3.6 3.6 3.6 3.6
0
400 4
VDD = 1.8V, CL = 30pF VDD = 3.3V, CL = 100pF
tr, tf (ns)
ibusy (mA)
60 90
120
0.57 0.43
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
46/56
PACKAGE MECHANICAL
Figure 39. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
Note: Drawing is not to scale.
Table 22. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.100 0.050 0.150 0.0039 0.0020 0.0059
A2 1.000 0.950 1.050 0.0394 0.0374 0.0413
B 0.220 0.170 0.270 0.0087 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.080 0.0031
D1 12.000 11.900 12.100 0.4724 0.4685 0.4764
E 20.000 19.800 20.200 0.7874 0.7795 0.7953
E1 18.400 18.300 18.500 0.7244 0.7205 0.7283
e 0.500 – – 0.0197 – –
L 0.600 0.500 0.700 0.0236 0.0197 0.0276
L1 0.800 0.0315
α3° 0° 5° 3° 0° 5°
TSOP-G
B
e
DIE
C
LA1 α
E1
E
A
A2
1
24
48
25
D1
L1
CP
47/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Figure 40. WSOP48 – 48 lead Plastic Very Very Thin Small Outline, 12 x 17mm, Package Outline
Note: Drawing not to scale.
Table 23. WSOP48 lead Plastic Very Very Thin Small Outline, 12 x 17mm, Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 0.65 0.026
A1 0.10 0.004
A2 0.52 0.47 0.57 0.020 0.019 0.022
b 0.16 0.13 0.23 0.006 0.005 0.009
c 0.10 0.08 0.17 0.004 0.003 0.007
D1 12.00 11.90 12.10 0.472 0.469 0.476
ddd 0.06 0.002
E 17.00 16.80 17.20 0.669 0.661 0.677
E1 15.40 15.30 15.50 0.606 0.602 0.610
e 0.50 – – 0.020 – –
L 0.55 0.45 0.65 0.022 0.018 0.026
L1 0.25 – – 0.010 – –
θ0° 5° 0° 5°
WSOP-A
b
e
DIE
c
A1 θ
E1
E
A
A2
1
24
48
25
D1
ddd
L1
L
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
48/56
Figure 41. VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Outline
Note: Drawing is not to scale
Table 24. VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.05 0.041
A1 0.25 0.010
A2 0.70 0.028
b 0.45 0.40 0.50 0.018 0.016 0.020
D 8.00 7.90 8.10 0.315 0.311 0.319
D1 4.00 0.157
D2 5.60 0.220
ddd 0.10 0.004
E 10.00 9.90 10.10 0.394 0.390 0.398
E1 5.60 0.220
E2 8.80 0.346
e 0.80 – – 0.031 – –
FD 2.00 0.079
FD1 1.20 0.047
FE 2.20 0.087
FE1 0.60 0.024
SD 0.40 0.016
SE 0.40 0.016
D1
D
e
b
SD
BGA-Z61
ddd
A2
A1
A
SE E2
FE1
E1 E
D2
FE
FD1
FD
49/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Figure 42. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Outline
Note: Drawing is not to scale
Table 25. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.20 0.047
A1 0.25 0.010
A2 0.80 0.031
b 0.45 0.40 0.50 0.018 0.016 0.020
D 8.00 7.90 8.10 0.315 0.311 0.319
D1 4.00 0.157
D2 5.60 0.220
ddd 0.10 0.004
E 10.00 9.90 10.10 0.394 0.390 0.398
E1 5.60 0.220
E2 8.80 0.346
e 0.80 – – 0.031 – –
FD 2.00 0.079
FD1 1.20 0.047
FE 2.20 0.087
FE1 0.60 0.024
SD 0.40 0.016
SE 0.40 0.016
D1
D
e
b
SD
BGA-Z61
ddd
A2
A1
A
SE E2
FE1
E1 E
D2
FE
FD1
FD
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
50/56
Figure 43. VFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Outline
Note: Drawing is not to scale.
Table 26. VFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.050 0.0413
A1 0.250 0.0098
A2 0.700 0.0276
b 0.450 0.400 0.500 0.0177 0.0157 0.0197
D 8.500 8.400 8.600 0.3346 0.3307 0.3386
D1 4.000 0.1575
D2 7.200 0.2835
ddd 0.100 0.0039
E 15.000 14.900 15.100 0.5906 0.5866 0.5945
E1 5.600 0.2205
E2 8.800 0.3465
e 0.800 0.0315
FD 2.250 0.0886
FD1 0.650 0.0256
FE 4.700 0.1850
FE1 3.100 0.1220
SD 0.400 0.0157
SE 0.400 0.0157
E
D
eb
SD
SE
A2
A1
A
BGA-Z53
ddd
FD1
D2
E2
e
FE
BALL "A1" FE1
e
E1
D1
FD
51/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
Figure 44. TFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Outline
Note: Drawing is not to scale
Table 27. TFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.250 0.0098
A2 0.600 0.0236
b 0.450 0.400 0.500 0.0177 0.0157 0.0197
D 8.500 8.400 8.600 0.3346 0.3307 0.3386
D1 4.000 0.1575
D2 7.200 0.2835
ddd 0.100 0.0039
E 15.000 14.900 15.100 0.5906 0.5866 0.5945
E1 5.600 0.2205
E2 8.800 0.3465
e 0.800 – – 0.0315 – –
FD 2.250 0.0886
FD1 0.650 0.0256
FE 4.700 0.1850
FE1 3.100 0.1220
SD 0.400 0.0157
SE 0.400 0.0157
E
D
eb
SD
SE
A2
A1
A
BGA-Z53
ddd
FD1
D2
E2
e
FE
BALL "A1"
FE1
e
E1
D1
FD
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
52/56
PART NUMBERING
Table 28. Ordering Information Scheme
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to ’1’.
For further information on any aspect of this device, please contact your nearest ST Sales Office.
Example: NAND512R3A 0 A ZA 1 T
Device Type
NAND = NAND Flash Memory
Density
128 = 128Mb
256 = 256Mb
512 = 512Mb
01G = 1Gb
Operatin g Voltage
R = VDD = 1.7 to 1.95V
W = VDD = 2.7 to 3.6V
Bus Width
3 = x8
4 = x16
Family Identifier
A = 528 Bytes/ 264 Word Page
Device Options
0 = No Options
1 = Automatic Page 0 Read at Power-up
2 = Chip Enable Don’t Care Enabled
3 = Chip Enable Don’t Care Enabled and Automatic Page 0 Read at Power-up
Product Version
A = 120nm process technology
(Single Die 128Mb, 256Mb, 512Mb) (Dual Die 512Mb, 1Gb)
Package
N = TSOP48 12 x 20mm (all devices)
V = WSOP48 12 x 17 x 0.65mm (128Mbit, 256Mbit and 512Mbit devices)
ZA = VFBGA55 8 x 10 x 1mm, 6x8 ball array, 0.8mm pitch (128Mbit and 256Mbit devices)
ZB = TFBGA55 8 x 10 x 1.2mm, 6x8 ball array, 0.8mm pitch (512Mbit Dual Die devices)
ZA = VFBGA63 8.5 x 15 x 1mm, 6x8 ball array, 0.8mm pitch (512Mbit devices)
ZB = TFBGA63 8.5 x 15 x 1.2mm, 6x8 ball array, 0.8mm pitch (1Gbit Dual Die devices)
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
blank = Standard Pa ck ing
T = Tape & Reel Packing
E = Lead Free Package, Standard Packing
F = Lead Free Package, Tape & Reel Packing
53/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
APPENDIX A. HARDWARE INTERFACE EXAMPLES
Nand Flash devices can be connected to a micro-
controller system bus for code and data storage.
For microcontrollers that have an embedded
NAND controller the NAND Flash can be connect-
ed without the addition of glue logic (see
Figure 45.). However a minimum of glue logic is
required for g ene ra l pur po se m ic roco ntr ol lers t hat
do not have an embedded NAND controller. The
glue lo gic usually cons i sts of a flip-f lo p to h old the
Chip Enable, Address Latch Enable and Com-
mand Latch Enable signals stable during com-
mand and address latch operations, and some
logic gates to simplify the firmware or make the de-
sign more robust.
Figure 46 . gives a n example of how to co nnect a
NAND Flash to a general purpose microcontroller.
The additional OR gates allow the microcontrol-
ler’s Output Enable and Write Enable signals to be
used for other perip herals. T he OR gate between
A3 and CSn maps the flip-flop and NAND I/O in
different address spaces inside the same chip se-
lect unit, which improves the setup and hold times
and simplifies the firmware. The structure uses the
microcont roller DM A (Direct M emory Acce ss) en-
gines to opti mize the transfe r betwee n the NAND
Flash and the system RAM.
For any interface with glue logic, the extra delay
caused by the gates and flip-flop must be taken
into accoun t. This dela y must be add ed to the mi-
crocontroller’s AC characteristics and register set-
tings to get the NAND Flash setup and hold times.
For mass storage applications (hard disk emula-
tions o r sy st ems whe re a hu ge a mou nt of stora ge
is required) NAND Flash memories can be con-
nected together to build storage modules (see Fig-
ure 47.).
Figure 45. Connection to Microcontroller, Without Glue Logic
AI08045b
R
W
I/O
E
AL
CL
W
G
CSn
AD(24:16)
Microcontroller
NAND
Flash
DQ
WP
RBPWAITEN
AD17
AD16
VDD
VDD or VSS
or General Purpose I/O
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
54/56
Figure 46. Connection to Microcontroller, With Glue Logic
Figure 47. Building Storage Modules
AI07589
R
W
I/O
E
AL
CL
CLK
D2
D1
D0 Q0
Q1
Q2
W
G
CSn
A3
A0
A1
A2
Microcontroller NAND Flash
DQ
D flip-flop
AI08331
WNAND Flash
Device 1
G
E1
CL
AL NAND Flash
Device 3
NAND Flash
Device 2 NAND Flash
Device n+1
NAND Flash
Device n
E2E3EnEn+1
I/O0-I/O7 or
I/O0-I/O15
RB
55/56
NAND128-A, NAND256-A, NA ND512-A, NAND 01G-A
RELATED DOCUMENTATION
STMicro electron ics has pub li sh ed a s et o f app li ca tio n not es to suppo rt the NA ND F lash mem o ries . The y
are available from the ST Website
www.st.com
. or from your local ST Distributor.
REVISION HISTORY
Table 29. Document Revision History
Date Version Revision Details
06-Jun-2003 1.0 First Issue
07-Aug- 20 03 2.0 Desig n Ph ase
27-Oct-2003 3.0 Engineering Phase
03-Dec-2003 4.0
Document promoted from Target Specification to Preliminary Data status.
VCC changed to VDD and ICC to IDD.
Title of Table 2.. change d to “Product De scription” and Page Progra m Typic al Timing
for NANDXXXR3A devices corrected. Table 1., Product List, inserted on page 2.
13-Apr-2004 5.0
WSOP48 and VFBGA55 packages added, VFBGA63 (9 x 11 x 1mm) removed.
Figure 19., Cache Program Operation, modified and note 2 modified. Note removed
for tWLWH timing in T able 20., AC Ch aracteri stics for Co mmand , Address , Data Inp ut.
Meaning of tBLBH4 modified, partly replaced by tWHBH1 an d tWHRL min fo r 3V de vices
modified in Table 21., AC Characteristics for Operations.
References removed from RELATED DOCUMENTATION section and reference
made to ST Website instead.
Figure 6., Figure 7., Figure 31. and Figure 34. modified. Read Electronic Signature
paragraph clarified and Figure 30., Read Electronic Signature AC Waveform,
modified. Note 2 to Figur e 3 2. , Read C Op er at i o n, On e Pa g e AC Wa ve fo r m, removed.
Note 3 to Table 7., Address Insertion, x16 Devices removed. Only 00h Pointer
operations are valid before a Cache Program operation. IDD4 removed from Table
18., DC Characteristics, 1.8V Devices. Note added to Figure 34., Block Erase AC
Waveform. Small text changes.
28-May-2004 6.0
TFBGA55 package added (mechanical data to be announced). 512Mb Dual Die
devices added. Figure 19., Cache Program Operation modified.
Packag e code changed for TFBGA63 8.5 x 15 x 1.2mm, 6x8 ball array, 0.8mm pitch
(1Gbit Dual Die devices) in Table 28., Ordering Information Scheme.
02-Jul-2004 7.0
Cache Program removed from document. TFBGA55 package specifications added
(Figure 42., TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package
Outline and Table 25., TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch,
Package Mechanical Data).
Test conditions modified for VOL and VOH parameters in Table 19., DC
Charact eri stic s, 3V Devic es .
NAND128-A , NAND256-A, NAND512-A, NAND01G-A
56/56
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