CGS74C2525MX - National Semiconductor

CGS74C2525,CGS74C2526,CGS74CT2525,

CGS74CT2526

CGS74CT2525 1-to-8 Minimum Skew Clock Driver

Literature Number: SNOS559

TL/F/10684

CGS74C2525 #CGS74CT2525 #CGS74C2526 #CGS74CT2526

1-to-8 Minimum Skew Clock Driver

September 1995

CGS74C2525 #CGS74CT2525

CGS74C2526 #CGS74CT2526

1-to-8 Minimum Skew Clock Driver

The CGS ’C/CT2525 is a minimum skew clock driver with

one input driving eight outputs specifically designed for sig-

nal generation and clock distribution applications. The ’2525

is designed to distribute a single clock to eight separate

receivers with low skew across all outputs during both the

tPLH and tPHL transitions. The ’2526 is similar to the ’2525

but contains a multiplexed clock input to allow for systems

with dual clock speeds or systems where a separate test

clock has been implemented.

Features

YThese CGS devices implement National’s FACTTM

family

YIdeal for signal generation and clock distribution

YGuaranteed pin to pin and part to part skew

YMultiplexed clock input (’2526)

YGuaranteed 2 kV minimum ESD protection

YSymmetric output current drive of 24 mA for IOL/IOH

Y’CT has TTL-compatible inputs

YThese products are identical to 74AC/ACT2525 and

2526

YAvailable as Mil/Aero versions

54AC/ACT2525

54AC/ACT2526

Logic Symbols

’2525

TL/F/10684–1

’2526

TL/F/10684–2

Connection Diagrams

Pin Assignment

for DIP and SOIC

’2525

TL/F/10684–3

’2526

TL/F/10684–4

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

FACTTM is a trademark of National Semiconductor Corporation.

C1996 National Semiconductor Corporation RRD-B30M106/Printed in U. S. A. http://www.national.com

Functional Description

On the multiplexed clock device, the SEL pin is used to

determine which CLKn input will have an active effect on

the outputs of the circuit. When SEL e1, the CLK1 input is

selected and when SEL e0, the CLK0 input is selected.

The non-selected CLKn input will not have any effect on the

logical output level of the circuit. The output pins act as a

single entity and will follow the state of the CLK or

CLK1/CLK0 pins when either the multiplexed (’2526) or the

straight (’2525) clock distribution chip is selected.

Pin Description

Pin Names Description

CLK Clock Input (’2525)

CLK0, CLK1 Clock Inputs (’2526)

O0–O7Outputs

SEL Clock Select (’2526)

Truth Tables

’2525

Inputs Outputs

CLK O0–O7

’2526

Inputs Outputs

CLK0 CLK1 SEL O0–O7

LXL L

HXL H

XLH L

XHH H

Low Voltage Level

HeHigh Voltage Level

XeImmaterial

’2525

TL/F/10684–7

’2526

TL/F/10684–8

http://www.national.com 2

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage (VCC)b0.5V to a7.0V

DC Input Diode Current (IIK)

VIeb

0.5V b20 mA

VIeVCC a0.5V a0.2 mA

DC Input Voltage (VI)b0.5V to (VCC a0.5V)

DC Output Diode Current (IOK)

VOe0.5V b20 mA

VOeVCC a0.5V a20 mA

DC Output Voltage (VO)b0.5V to (VCC a0.5V)

DC Output Source

or Sink Current (IO)g50 mA

DC VCC or Ground Current

per Output Pin (ICC or IGND)g50 MA

Storage Temperature (TSTG)b65§Ctoa

150§C

Junction Temperature (iJA)

Plastic (N) 14-Lead 102§C/W

Plastic (M) 14-Lead 128§C/W

Plastic (N) 16-Lead 97§C/W

Plastic (M) 16-Lead 124§C/W

Recommended Operating

Conditions

Supply Voltage (VCC)

‘C’ 2.0V to 6.0V

‘CT’ 4.5V to 5.5V

Input Voltage (VI) 0VtoV

Output Voltage (VO) 0VtoV

Operating Temperature (TA)

CGS74C/CT b40§Ctoa

85§C

54AC/ACT b55§Ctoa

125§C

Input Rise and Fall Times Devices

(30% to 70% of VCC)

VCC e3.3V 10.5 ns max

4.5V 14.4 ns max

5.5V 17.6 ns max

Input Rise and Fall Times Devices

(0.8V to 2.0V) 9.6 ns max

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, without

exception, to ensure that the system design is reliable over its power supply,

temperature, and output/input loading variables. National does not recom-

mend operation of CGS circuits outside databook specifications.

DC Electrical Characteristics for CGS74C and 54AC Family Devices

Over recommended operating conditions unless specified otherwise.

CGS74C 54AC CGS74C

Symbol Parameter VCC TAea

25§CTAeTAeUnits Conditions

(V) b55§Ctoa

125§Cb40§Ctoa

85§C

Typ Guaranteed Limits

VIH Minimum High Level 3.0 1.5 2.1 2.1 2.1 VOUT e0.1V

Input Voltage 4.5 2.25 3.15 3.15 3.15 V or VCC b0.1V

5.5 2.75 3.85 3.85 3.85

VIL Maximum Low Level 3.0 1.5 0.9 0.9 0.9 VOUT e0.1V

Input Voltage 4.5 2.25 1.35 1.35 1.35 V or VCC b0.1V

5.5 2.75 1.65 1.65 1.65

VOH Minimum High Level 3.0 2.99 2.9 2.9 2.9 IOUT eb

50 mA

Output Voltage 4.5 4.49 4.4 4.4 4.4 V

(Note 2) 5.5 5.49 5.4 5.4 5.4

VIN eVIL or VIH

3.0 2.56 2.4 2.46 b12 mA

4.5 3.86 3.7 3.76 V IOH b24 mA

5.5 4.86 4.7 4.76 b24 mA

VOL Maximum Low Level 3.0 0.002 0.1 0.1 0.1 IOUT e50 mA

Output Voltage 4.5 0.001 0.1 0.1 0.1 V

(Note 2) 5.5 0.001 0.1 0.1 0.1

VIN eVIL or VIH

3.0 0.36 0.40 0.44 12 mA

4.5 0.36 0.50 0.44 V IOL

24 mA

5.5 0.36 0.50 0.44 24 mA

http://www.national.com3

DC Electrical Characteristics for CGS74C and 54AC Family Devices (Continued)

Over recommended operating conditions unless specified otherwise.

CGS74C 54AC CGS74C

Symbol Parameter VCC TAea

25§CTAeTAeUnits Conditions

(V) b55§Ctoa

125§Cb40§Ctoa

85§C

Typ Guaranteed Limits

IIN Maximum Input

5.5 g0.1 g1.0 g1.0 mA

Leakage Current VIeVCC, GND

(Note 3)

IOLD Minimum Dynamic 5.5 50 75 mA VOLD e1.65V Max

IOHD Output Current

5.5 b50 b75 mA VOHD e3.85V Min

(Note 4)

ICC Maximum Quiescent

5.5 8.0 80.0 80.0 mAVIN eVCC

Supply Current or GND

(Note 3)

DC Electrical Characteristics for CGS74CT and 54ACT Family Devices

Over recommended operating conditions unless specified otherwise.

CGS74CT 54ACT CGS74CT

Symbol Parameter VCC TAea

25§CTAeTAeUnits Conditions

(V) b55§Ctoa

125§Cb40§Ctoa

85§C

Typ Guaranteed Limits

VIH Minimum High Level 4.5 1.5 2.0 2.0 2.0 VVOUT e0.1V

Input Voltage 5.5 1.5 2.0 2.0 2.0 or VCC b0.1V

VIL Maximum Low Level 4.5 1.5 0.8 0.8 0.8 VVOUT e0.1V

Input Voltage 5.5 1.5 0.8 0.8 0.8 or VCC b0.1V

VOH Minimum High Level 4.5 4.49 4.4 4.4 4.4 VI

OUT eb

50 mA

Output Voltage 5.5 5.49 5.4 5.4 5.4

(Note 2) VIN eVIL or VIH

4.5 3.86 3.70 3.76 V IOH

b24 mA

5.5 4.86 4.70 4.76 b24 mA

VOL Maximum Low Level 4.5 0.001 0.1 0.1 0.1 VI

OUT e50 mA

Output Voltage 5.5 0.001 0.1 0.1 0.1

(Note 2) VIN eVIL or VIH

4.5 0.36 0.50 0.44 V IOL

24 mA

5.5 0.36 0.50 0.44 24 mA

IIN Maximum Input 5.5 g0.1 g1.0 g1.0 mAV

CC, GND

Leakage Current

ICCT Maximum ICC/Input 5.5 0.6 1.6 1.5 mA VIeVCC b2.1V

IOLD Minimum Dynamic 5.5 50 75 mA VOLD e1.65V Max

IOHD Output Current

5.5 b50 b75 mA VOHD e3.85V Min

(Note 4)

ICC Maximum Quiescent

5.5 8.0 160.0 80.0 mAVIN eVCC

Supply Current or GND

(Note 5)

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AC Electrical Characteristics Over recommended operating conditions unless specified otherwise.

(Note 6)

Range

VCC

(V)

CGS74C 54AC CGS74C

TAea

25§CTAeb

55§CT

40§C

Symbol Parameter CLe50 pF to a125§Cto

85§C Units

CLe50 pF CLe50 pF

Min Typ Max Min Max Min Typ Max

tPLH, Propagation Delay 3.3 3.0 6.5 11.0 3.0 11.0 3.0 12.5 ns

tPHL CLK to On(’2525) 5.0 3.2 5.0 7.8 2.5 8.2 2.9 8.1

tPLH, Propagation Delay 3.3 3.0 7.0 13.0 3.0 14.0 ns

tPHL CLKn to On(’2526) 5.0 3.6 5.5 7.8 3.3 8.6

tPLH, Propagation Delay 3.3 3.0 8.0 14.0 3.0 15.0 ns

tPHL SEL to On(’2526) 5.0 4.0 6.5 8.5 3.5 9.5

tOSHL Maximum Skew 3.3 0.3 1.5 600

Common Edge ps

Output-to-Output (Note 7) 5.0 0.2 1.0 500

Variation

tOSLH Maximum Skew 3.3 0.3 1.5 600

Common Edge ps

Output-to-Output (Note 7) 5.0 0.2 1.0 500

Variation

tOST Maximum Skew 1.5

Opposite Edge 5.0 0.4 1.0 1.0 ns

Output-to-Output (Note 7) 1.0

Variation

tPV Maximum Skew ’C2525

Part-to-Part ’CT2525 5.0 3.5 4.0 ns

Variation (Note 8) ’C2526

’CT2526 5.0 5.0 ns

trise, Maximum

tfall Rise/Fall Time 5.0 3.0 4.0 3.75 ns

(20% to 80% VCC)

trise, Maximum

tfall Rise/Fall Time 0.9 1.1 ns

(0.8V/2.0V and 2.0V/0.8V)

AC Electrical Characteristics Over recommended operating conditions unless specified otherwise.

(Note 6)

Range

VCC

(V)

CGS74CT 54ACT CGS74CT

TAea

25§CTAeb

55§CT

40§C

Symbol Parameter CLe50 pF to a125§Cto

85§C Units

CLe50 pF CLe50 pF

Min Typ Max Min Max Min Max

tPLH, Propagation Delay 5.0 4.6 6.5 9.0 4.0 10.1 ns

tPHL CLK to On(’2525)

tPLH, Propagation Delay 5.0 5.8 8.5 11.1 5.1 12.4 ns

tPHL CLKn to On(’2526)

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AC Electrical Characteristics

Over recommended operating conditions unless specified otherwise. (Continued)

(Note 6)

Range

VCC

(V)

CGS74CT 54ACT CGS74CT

TAea

25§CTAeb

55§CT

40§C

Symbol Parameter CLe50 pF to a125§Cto

85§C Units

CLe50 pF CLe50 pF

Min Typ Max Min Max Min Typ Max

tPLH, Propagation Delay 5.0 5.1 8.5 12.4 4.4 14.1 ns

tPHL SEL to On(’2526)

tOSHL Maximum Skew

Common Edge 5.0 0.2 550 ps

Output-to-Output (Note 7)

Variation

tOSLH Maximum Skew

Common Edge 5.0 0.2 550 ps

Output-to-Output (Note 7)

Variation

tOST Maximum Skew

Opposite Edge 5.0 0.4 1.0 ns

Output-to-Output (Note 7)

Variation

tPV Maximum Skew AC2525

Part-to-Part ACT2525

Variation (Note 8) AC2526 5.0 3.5 ns

ACT2526 5.0 5.0 ns

trise, Maximum

tfall Rise/Fall Time 5.0 3.0 3.75 ns

(20% to 80% VCC)

trise, Maximum

tfall Rise/Fall Time 0.9 1.1 ns

(0.8V/2.0V and 2.0V/0.8V)

Note 2: All outputs loaded; thresholds on input associated with output under test.

Note 3: IIN and ICC @3.0V are guaranteed to be less than or equal to the respective limit @5.5V VCC.

ICC for 54AC @25§C is identical to CGS74C @25§C.

Note 4: Maximum test duration 2.0 ms, one output loaded at a time.

Note 5: ICC for 54ACT @25§C is identical to CGS74CT @25§C.

Note 6: Voltage Range 5.0 is 5.0V g0.5V, voltage range 3.3 is 3.3V g0.3V.

Note 7: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged

device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH) or in opposite directions both

HL and LH (tOST). tOSHL and tOSLH are characterized and guaranteed by design @1 MHz.

Note 8: Part-to-part skew is defined as the absolute value of the difference between the propagation delay for any outputs from device to device. The parameter is

specified for a given set of conditions (i.e., capacitive load, VCC, temperature, Ýof outputs switching, etc.). Parameter guaranteed by design.

Note 9: Load capacitance includes the test jig.

http://www.national.com 6

Capacitance

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC e5.0V

CPD Power Dissipation Capacitance (’2525) 820 pF– 1.2 x 10b18 (f)*pF VCC e5.0V

CPD Power Dissipation Capacitance (’2526) 820 pF– 1.2 x 10b18 (f)*pF VCC e5.0V

*fefrequency

Recommended Maximum Power Dissipation (W)

LFPM TAe25§CT

85§C

PDIP SOIC PDIP SOIC

0 1.105 0.858 0.528 0.41

225 1.493 1.055 0.714 0.504

500 1.71 1.210 0.820 0.578

Timing Diagrams

TL/F/10684–27

TL/F/10684–28

Test Circuit

TL/F/10684–29

RLis 500X

CLis 50 pF for all prop delays and skew measurements.

http://www.national.com7

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are

defined as follows:

TL/F/10684–26

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (M)

NS Package Number M14A

http://www.national.com 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Integrated Circuit (M)

NS Package Number M16A

14-Lead Plastic Dual-In-Line Package (N)

NS Package Number N14A

http://www.national.com9

CGS74C2525 #CGS74CT2525 #CGS74C2526 #CGS74CT2526

1-to-8 Minimum Skew Clock Driver

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (N)

NS Package Number N16E

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