Single-Phase Energy Measurement IC with
8052 MCU, RTC, and LCD Driver
Data Sheet ADE5169/ADE5569
Rev. E Document Feedback
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GENERAL FEATURES
Wide supply voltage operation: 2.4 V to 3.7 V
Internal bipolar switch between regulated and battery inputs
Ultralow power operation with power saving modes (PSM)
Full operation: 4.4 mA to 1.6 mA (PLL clock dependent)
Battery mode: 3.3 mA to 400 μA (PLL clock dependent)
Sleep mode
Real-time clock (RTC) mode: 1.7 μA
RTC and LCD mode: 38 μA (LCD charge pump enabled)
Reference: 1.2 V ± 0.1% (10 ppm/°C drift)
64-lead, low profile quad flat, RoHS-compliant package (LQFP)
Operating temperature range: −40°C to +85°C
ENERGY MEASUREMENT FEATURES
Proprietary analog-to-digital converters (ADCs) and digital
signal processing (DSP) provide high accuracy active
(watt), reactive (var), and apparent energy (volt-ampere
(VA)) measurement
<0.1% error on active energy over a dynamic range of
1000 to 1 at 25°C
<0.5% error on reactive energy over a dynamic range of
1000 to 1 at 25°C (ADE5169 and ADE5569 only)
<0.5% error on root mean square (rms) measurements
over a dynamic range of 500 to 1 for current (Irms) and
100 to 1 for voltage (Vrms) at 25°C
Supports IEC 62053-21; IEC 62053-22; IEC 62053-23;
EN 50470-3 Class A, Class B, and Class C; and ANSI C12-16
Differential input with programmable gain amplifiers (PGAs)
supports shunts, current transformers, and di/dt current
sensors (ADE5169 and ADE5569 only)
2 current inputs for antitamper detection in the ADE5169
High frequency outputs proportional to Irms, active, reactive,
or apparent power (AP)
Table 1. Features Available on Each Device
Part No. Antitamper
Watt,
VA,
Irms, Vrms Var
di/dt
Sensor
Memory
Size
ADE5169 Yes Yes Yes Yes 62 kB
ADE5569 No Yes Yes Yes 62 kB
MICROPROCESSOR FEATURES
8052-based core
Single-cycle 4 MIPS 8052 core
8052-compatible instruction set
32.768 kHz external crystal with on-chip PLL
2 external interrupt sources
External reset pin
Low power battery mode
Wake-up from input/output (I/O), temperature change,
alarm, and universal asynchronous receiver/transmitter
(UART)
LCD driver operation with automatic scrolling
Temperature measurement
Real-time clock (RTC)
Counter for seconds, minutes, hours, days, months,
and years
Date counter, including leap year compensation
Automatic battery switchover for RTC backup
Operation down to 2.4 V
Ultralow battery supply current: 1.7 μA
Selectable output frequency: 1 Hz to 16 kHz
Embedded digital crystal frequency compensation for
calibration and temperature variation of 2 ppm resolution
Integrated LCD driver
108-segment driver for the and ADE5569
104-segment driver for the and ADE5169
2×, 3×, or 4× multiplexing
4 LCD memory banks for screen scrolling
LCD voltages generated internally or with external resistors
Internal adjustable drive voltages up to 5 V independent
of power supply level
On-chip peripherals
2 independent UART interfaces
SPI or I2C
Watchdog timer
Power supply management with user selectable levels
Memory: 62 kB flash memory, 2.256 kB RAM
Development tools
Single-pin emulation
IDE-based assembly and C source debugging
ADE5169/ADE5569 Data Sheet
Rev. E | Page 2 of 155
TABLE OF CONTENTS
General Features ............................................................................... 1
Energy Measurement Features ........................................................ 1
Microprocessor Features .................................................................. 1
Revision History ............................................................................... 4
General Description ......................................................................... 5
Functional Block Diagrams ............................................................. 5
Specifications ..................................................................................... 7
Energy Metering ........................................................................... 7
Analog Peripherals ....................................................................... 8
Digital Interface ............................................................................ 9
Timing Specifications ................................................................ 11
Absolute Maximum Ratings .......................................................... 16
Thermal Resistance .................................................................... 16
ESD Caution ................................................................................ 16
Pin Configurations and Function Descriptions ......................... 17
Typical Performance Characteristics ........................................... 21
Terminology .................................................................................... 25
Special Function Register (SFR) Mapping .................................. 26
Power Management ........................................................................ 28
Power Management Register Details ....................................... 28
Power Supply Architecture ........................................................ 31
Battery Switchover ...................................................................... 31
Power Supply Management (PSM) Interrupt ......................... 31
Using the Power Supply Features ............................................. 33
Operating Modes ............................................................................ 36
PSM0 (Normal Mode) ............................................................... 36
PSM1 (Battery Mode) ................................................................ 36
PSM2 (Sleep Mode) .................................................................... 36
3.3 V Peripherals and Wake-Up Events ................................... 37
Transitioning Between Operating Modes ............................... 38
Using the Power Management Features .................................. 38
Energy Measurement ..................................................................... 39
Access to Energy Measurement SFRs ...................................... 39
Access to Internal Energy Measurement Registers ................ 39
Energy Measurement Registers ................................................ 42
Energy Measurement Internal Registers Details .................... 43
Interrupt Status/Enable SFRs .................................................... 46
Analog Inputs .............................................................................. 47
Analog-to-Digital Conversion .................................................. 48
Fault Detection (ADE5169 Only) ............................................ 52
di/dt Current Sensor and Digital Integrator ............................... 53
Power Quality Measurements ................................................... 54
Phase Compensation ................................................................. 56
RMS Calculation ........................................................................ 57
Active Power Calculation .......................................................... 59
Active Energy Calculation ........................................................ 62
Reactive Power Calculation ...................................................... 65
Reactive Energy Calculation ..................................................... 67
Apparent Power Calculation ..................................................... 70
Apparent Energy Calculation ................................................... 70
Ampere-Hour Accumulation ................................................... 72
Energy to Frequency Conversion ............................................. 73
Energy Register Scaling ............................................................. 73
Energy Measurement Interrupts .............................................. 74
Temperature, Battery, and Supply Voltage Measurements........ 75
Temperature Measurement ....................................................... 77
Battery Measurement ................................................................. 77
External Voltage Measurement ................................................ 78
8052 MCU Core Architecture....................................................... 80
MCU Registers ............................................................................ 80
Basic 8052 Registers ................................................................... 82
Standard 8052 SFRs .................................................................... 84
Memory Overview ..................................................................... 85
Addressing Modes ...................................................................... 86
Instruction Set ............................................................................ 87
Read-Modify-Write Instructions ............................................. 89
Instructions That Affect Flags .................................................. 90
Dual Data Pointers ......................................................................... 92
Interrupt System ............................................................................. 93
Standard 8052 Interrupt Architecture ..................................... 93
Interrupt Architecture ............................................................... 93
Interrupt Registers...................................................................... 93
Interrupt Priority ........................................................................ 94
Interrupt Flags ............................................................................ 95
Interrupt Vectors ........................................................................ 97
Interrupt Latency ........................................................................ 97
Context Saving ............................................................................ 97
Watchdog Timer ............................................................................. 98
Writing to the Watchdog Timer SFR (WDCON,
Address 0xC0) ............................................................................. 99
Data Sheet ADE5169/ADE5569
Rev. E | Page 3 of 155
Watchdog Timer Interrupt......................................................... 99
LCD Driver ................................................................................... 100
LCD Registers ........................................................................... 100
LCD Setup ................................................................................. 103
LCD Timing and Waveforms ................................................. 103
Scrolling Mode ......................................................................... 104
Display Element Control ......................................................... 104
Voltage Generation .................................................................. 105
LCD External Circuitry ........................................................... 105
LCD Function in PSM2 Mode ............................................... 106
Flash Memory ............................................................................... 107
Flash Memory Overview ......................................................... 107
Flash Memory Organization ................................................... 107
Using the Flash Memory ......................................................... 108
Protecting the Flash Memory ................................................. 111
In-Circuit Programming ......................................................... 113
Timers ............................................................................................ 114
Timer Registers ......................................................................... 114
Timer 0 and Timer 1 ................................................................ 116
Timer 2 ...................................................................................... 117
Phase-Locked Loop (PLL) .......................................................... 119
PLL Registers ............................................................................ 119
Real-Time Clock (RTC) .............................................................. 120
Access to RTC SFRs ................................................................. 120
Access to Internal RTC Registers ........................................... 120
RTC SFRs .................................................................................. 121
RTC Registers ........................................................................... 124
RTC Calendar ........................................................................... 125
RTC Interrupts ......................................................................... 126
RTC Crystal Compensation .................................................... 127
UART Serial Interface .................................................................. 128
UART SFRs ................................................................................ 128
UART Operation Modes .......................................................... 131
UART Baud Rate Generation .................................................. 132
UART Additional Features ...................................................... 134
UART2 Serial Interface................................................................. 135
UART2 SFRs .............................................................................. 135
UART2 Operation Modes ........................................................ 137
UART2 Baud Rate Generation ................................................ 137
UART2 Additional Features .................................................... 138
Serial Peripheral Interface (SPI) .................................................. 139
SPI Registers .............................................................................. 139
SPI Pins ....................................................................................... 142
SPI Master Operating Modes .................................................. 143
SPI Interrupt and Status Flags ................................................. 144
I2C-Compatible Interface ............................................................. 145
Serial Clock Generation ........................................................... 145
Slave Addresses .......................................................................... 145
I2C Registers ............................................................................... 145
Read and Write Operations ..................................................... 146
I2C Receive and Transmit FIFOs ............................................. 147
I/O Ports ......................................................................................... 148
Parallel I/O ................................................................................. 148
I/O Registers .............................................................................. 149
Port 0 ........................................................................................... 152
Port 1 ........................................................................................... 152
Port 2 ........................................................................................... 152
Determining the Version of the ADE5169/ADE5569 .............. 153
Outline Dimensions ...................................................................... 154
Ordering Guide ......................................................................... 154
ADE5169/ADE5569 Data Sheet
Rev. E | Page 4 of 155
REVISION HISTORY
10/15—Rev. D to Rev. E
Deleted the ADE5166, ADE5566, and the 32 kB Flash
Memory Model ................................................................... Universal
Changes to Ordering Guide ........................................................ 154
4/12—Rev. C to Rev. D
Changes to Table 1 ............................................................................ 1
Moved Revision History .................................................................. 4
Added 32 kB Flash Option Section ................................................ 5
Changes to Vrms Measurement Bandwidth Parameter, Table 2 .. 7
Changes to Table 17 ........................................................................ 28
Changes to Figure 39 ...................................................................... 40
Changes to Figure 40 ...................................................................... 41
Changes to RMS Calculation Section, Current Channel RMS
Calculation Section, and Figure 60 .............................................. 57
Changes to Current Channel RMS Offset Compensation
Section, Figure 61, and Figure 62 ................................................. 58
Changes to Figure 63 and Voltage Channel RMS Calculation
Section .............................................................................................. 59
Changes to Figure 74 ...................................................................... 68
Added Flash Memory Organization for the 32 kB Model
Section and Figure 97, Renumbered Sequentially ................... 114
Change to Table 127 ..................................................................... 122
Changes to UART Timer Generated Baud Rates Section ....... 135
Changes to Table 149.................................................................... 137
Removed UART2 TxD2 Signal Modulation Section ............... 137
Changes to Table 155.................................................................... 143
Changes to Table 161.................................................................... 150
Changes to Table 167.................................................................... 151
Changes to Ordering Guide ........................................................ 155
6/10—Rev. B to Rev. C
Changes to Bit 5, Table 161 ......................................................... 148
Changes to Ordering Guide ........................................................ 153
11/09—Rev. A to Rev. B
Deleted RTCCAL Function.......................................... Throughout
Changes to Fault Detection (ADE5166/ADE5169
Only) Section .................................................................................. 51
2/09—Rev. 0 to Rev. A
Added ADE5566/ADE5569 ............................................... Universal
Changes to General Features and Microprocessor Features ........ 1
Change to Figure 29, Figure 30, and Figure 31 ........................... 23
Changes to Figure 46 ...................................................................... 49
Changes to Figure 59 ...................................................................... 56
Changes to Figure 61 ...................................................................... 57
Change to Figure 73 ....................................................................... 67
Changes to Figure 89 ...................................................................... 95
Changes to Figure 103 ................................................................. 120
Changes to Determining the Version of the
ADE5166/ADE5169/ADE5566/ADE5569 Section .................. 152
Changes to Ordering Guide ........................................................ 153
10/08—Revision 0: Initial Version
Data Sheet ADE5169/ADE5569
Rev. E | Page 5 of 155
GENERAL DESCRIPTION
The ADE5169/ADE55691 integrate the Analog Devices, Inc.,
energy (ADE) metering IC analog front end and fixed function
DSP solution with an enhanced 8052 MCU core, a full RTC, an
LCD driver, and all the peripherals to make an electronic energy
meter with an LCD display in a single device.
The ADE measurement core includes active, reactive, and apparent
energy calculations, as well as voltage and current rms measure-
ments. This information is accessible for energy billing by using the
built-in energy scalars. Many power line supervisory features such
as SAG, peak, and zero crossing are included in the energy
measurement DSP to simplify energy meter design.
The microprocessor functionality includes a single cycle 8052 core,
a full RTC with a power supply backup pin, an SPI or I2C interface,
and two independent UART interfaces. The ready to use infor-
mation from the ADE core reduces the requirement for program
memory size, making it easy to integrate complicated design into
62 kB of flash memory.
The ADE5169 includes a 104-segment LCD driver and the
ADE5569 includes a 108-segment LCD driver, each with the
capability to store up to four LCD screens in memory. This driver
generates voltages capable of driving LCDs up to 5 V.
1 Patents pending.
FUNCTIONAL BLOCK DIAGRAMS
I
PA
I
N
V
P
V
N
REF
IN/OUT
ENERGY
MEASUREMENT
DSP
OSC
COM0
...
...
COM3
...
CF1
CF2
3V/ 5V LCD
CHARGE P UM P
SINGLE
CYCLE
8052
MCU
ADE5169
V
DCIN
V
BAT
V
DD
V
SWOUT
DGND
A
GND
LCDVA
LCDVB
LCDVC
...
FP0
FP15
RTC
SS
SCLK
MISO
MOSI/SDATA
T2
T2EX
T0
T1
LCDVP1
LCDVP2
XTAL2
XTAL1
INT0
INT1
FP16
FP17
FP23
FP22
FP21
FP20
FP19
FP18
FP25
FP24
1.20V
REF
52
53
49
50
I
PB 55
63
54
58
64 61
60 4647 48 45
5
6
FP28
FP27
2
1
7
8
9
10
11
12
13
14
20
35
1
4
15
17
18
16
19
44
14
13
12
57 43 42 39 38 7 6 45 11 43 42 41 40 39 38 37 36 567891038 39 40 41
PGA2
–
+
PGA1
–
+
PGA1
–
+
ADC
ADC
ADC
TEMP
ADC
VSW
ADC
PROGRAM MEMORY
62kB FLASH
POWER SUPPLY
CONT ROL AND
MONITORING
USER RAM
256 BYT E S
USER XRAM
2kB
TEMP
SENSOR
BATTERY
ADC
SPI/I
2
C
SERIAL
INTERFACE
3 × 16-BIT
COUNTER
TIMERS
104-SEGMENT
LCD DRIV E R
WATCHDOG
TIMER
PLL
07411-201
LDO
V
INTD
V
INTA
RESET
TxD
UART
SERIAL
PORT
UART2
SERIAL
PORT
UART2
TIMER
RxD
62 56 51
TxD2
44
36
RxD2
38
37
59
DOWNLOADER
DEBUGGER
1-PIN
EMULATOR
LDO
EA
UART
TIMER
POR
P0.7/SS/T1/RxD2
P0.6/SCLK/T0
P0.5/MISO/ZX
P0.4/MOSI/SDATA
P0.0 (BCTRL/INT1/P0.0)
P1.0/RxD
P1.1/TxD
P1.2/FP25/ZX
P1.3/T2EX/FP24
P1.6/FP21
P1.7/FP20
P1.4/T2/FP23
P1.5/FP22
P0.1/FP19
P0.2/CF1
P0.3/CF2
P2.0/FP18
P2.1/FP17
P2.2/FP16
P2.3 (SDEN/P2.3/TxD2)
Figure 1. ADE5169 Functional Block Diagram
ADE5169/ADE5569 Data Sheet
Rev. E | Page 6 of 155
I
P
I
N
V
P
V
N
REF
IN/OUT
ENERGY
MEASUREMENT
DSP
OSC
COM0
...
...
COM3
...
CF1
CF2
LDO
3V/ 5V LCD
CHARGE PUMP
SINGLE
CYCLE
8052
MCU
ADE5569
FP26
V
DCIN
V
BAT
V
DD
V
SWOUT
V
INTD
V
INTA
RESET
DGND
AGND
TxD
UART
SERIAL
PORT
UART2
SERIAL
PORT
UART2
TIMER
LCDVA
LCDVB
LCDVC
...
FP0
FP15
RTC
SS
SCLK
MISO
MOSI/SDATA
RxD
T2
T2EX
T0
T1
LCDVP1
LCDVP2
XTAL2
XTAL1
INT0
INT1
FP16
FP17
FP23
FP22
FP21
FP20
FP19
FP18
FP25
FP24
P0.7/SS/T1/RxD2
P0.6/SCLK/T0
P0.5/MISO/ZX
P0.4/MOSI/SDATA
P0.0 ( BCTRL /I NT1/P 0.0)
P1.0/RxD
P1.1/TxD
P1.2/FP25/ZX
P1.3/T2EX/FP24
P1.6/FP21
P1.7/FP20
P1.4/T2/FP23
P1.5/FP22
P2.0/FP18
P2.1/FP17
P2.2/FP16
P2. 3 ( S DEN/P2.3/ TxD2)
P0.1/FP19
P0.2/CF1
P0.3/CF2
1.20V
REF
53
52
55
49
50
63
54
58
64 61
60 62 56 51
TxD2
44
36
RxD2
38
37 4647 48 45
5
FP28
FP27
2
1
6
7
8
9
10
11
12
13
14
20
35
1
4
15
17
18
16
19
44
14
13
12
57 43 42 39 38 7645 11 43 42 41 40 39 38 37 36 567891038 39 40 41
59
PGA2
–
+
PGA1
–
+ADC
ADC
TEMP
ADC
VSW
ADC
PROGRAM MEMORY
62kB FLASH
POWER SUPPLY
CONTROL AND
MONITORING
USER RAM
256 BYT E S
USER XRAM
2kB
TEMP
SENSOR
BATTERY
ADC
SPI/I
2
C
SERIAL
INTERFACE
3 × 16-BIT
COUNTER
TIMERS
108-SEGMENT
LCD DRIVER
WATCHDOG
TIMER
DOWNLOADER
DEBUGGER
PLL
1-PIN
EMULATOR
LDO
EA
UART
TIMER
POR
07411-001
Figure 2. ADE5569 Functional Block Diagram
Data Sheet ADE5169/ADE5569
Rev. E | Page 7 of 155
SPECIFICATIONS
VDD = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTALx = 32.768 kHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.
ENERGY METERING
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
MEASUREMENT ACCURACY1
Phase Error Between Channels
PF = 0.8 Capacitive ±0.05 Degrees Phase lead: 37°
PF = 0.5 Inductive ±0.05 Degrees Phase lag: 60°
Active Energy Measurement Error
2
0.1 % of reading Over a dynamic range of 1000 to 1 at 25°C
AC Power Supply Rejection
2
V
DD
= 3.3 V + 100 mV rms/120 Hz
Output Frequency Variation 0.01 % I
Px
= V
P
= ±100 mV rms
DC Power Supply Rejection2 V
DD
= 3.3 V ± 117 mV dc
Output Frequency Variation
0.01
%
Active Energy Measurement Bandwidth
1
8 kHz
Reactive Energy Measurement Error
2
0.5 % of reading Over a dynamic range of 1000 to 1 at 25°C
V
rms
Measurement Error2 0.5 % of reading Over a dynamic range of 100 to 1 at 25°C
Vrms Measurement Bandwidth1 63.7 Hz Fundamental only, mean absolute
measurement
I
rms
Measurement Error
2
0.5 % of reading Over a dynamic range of 500 to 1 at 25°C
I
rms
Measurement Bandwidth
1
3.9 kHz
ANALOG INPUTS
Maximum Signal Levels
±500
mV peak
VP − VN differential input
ADE5169 ±500 mV peak I
PA
− I
N
and I
PB
− I
N
differential inputs
ADE5569 ±500 mV peak I
P
− I
N
Input Impedance (DC) 770 kΩ
ADC Offset Error2 ±10 mV PGA1 = PGA2 = 1
±1
mV
PGA1 = 16
Gain Error
2
Current Channel ±3 % I
PA
= I
PB
= 0.5 V dc or I
P
= 0.5 V dc
Voltage Channel ±3 % V
P
− V
N
= 0.5 V dc
Gain Error Match ±0.2 %
CF1 AND CF2 PULSE OUTPUT
Maximum Output Frequency 21.6 kHz VP − VN = 500 mV peak; IPA − IN = 500 mV for
the ADE5169; IP − IN = 500 mV for the
ADE5569
Duty Cycle 50 % If the CF1 or CF2 frequency > 5.55 Hz
Active High Pulse Width 90 ms If the CF1 or CF2 frequency < 5.55 Hz
FAULT DETECTION3
Fault Detection Threshold
Inactive Input ≠ Active Input 6.25 % of active I
PA
or I
PB
active
Input Swap Threshold
Inactive Input > Active Input 6.25 % of active I
PA
or I
PB
active
Accuracy Fault Mode Operation
IPA Active, IPB = AGND
0.1
% of reading
Over a dynamic range of 500 to 1
I
PB
Active, I
PA
= AGND 0.1 % of reading Over a dynamic range of 500 to 1
Fault Detection Delay 3 Seconds
Swap Delay 3 Seconds
1 These specifications are not production tested but are guaranteed by design and/or characterization data on production release.
2 See Terminologysection for definition.
3 Available only in the ADE5169.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 8 of 155
ANALOG PERIPHERALS
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
Power Supply Operating Range 2.4 3.7 V Measured on V
SWOUT
No Missing Codes
8 Bits
Conversion Delay2 38 µs
ADC Gain
V
Measurement 15.3 mV/LSB
V
Measurement 14.6 mV/LSB
Temperature Measurement 0.83 °C/LSB
ADC Offset
V
Measurement at 3 V 200 LSB
V
Measurement at 3.7 V 246 LSB
Temperature Measurement at 25°C 123 LSB
V
Analog Input
Maximum Signal Levels 0 3.3 V
Input Impedance (DC) 1 MΩ
Low V
Detection Threshold 1.09 1.2 1.27 V
POWER-ON RESET (POR)
V
POR
Detection Threshold 2.5 2.95 V
POR Active Timeout Period 33 ms
V
POR
Detection Threshold 1.8 2.2 V
POR Active Timeout Period 20 ms
V
POR
Detection Threshold 2.0 2.25 V
POR Active Timeout Period 16 ms
V
POR
Detection Threshold 2.0 2.25 V
POR Active Timeout Period 120 ms
BATTERY SWITCHOVER
Voltage Operating Range (V
) 2.4 3.7 V
V
to V
Switching
Switching Threshold (V
) 2.5 2.95 V
Switching Delay 10 ns When V
DD
to V
BAT
switch is activated by V
DD
30 ms When V
DD
to V
BAT
switch is activated by V
DCIN
V
to V
Switching
Switching Threshold (V
) 2.5 2.95 V
Switching Delay 30 ms Based on V
DD
> 2.75 V
V
to V
Leakage Current 10 nA V
BAT
= 0 V, V
SWOUT
= 3.43 V, T
A
= 25°C
LCD, CHARGE PUMP ACTIVE
Charge Pump Capacitance Between
LCDVP1 and LCDVP2
100 nF
470
nF
LCDVA 0 1.9 V
LCDVB 0 3.8 V 1/3 bias mode
LCDVC 0 5.8 V 1/3 bias mode
V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 µA
V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 µA
V3 Segment Line Voltage LCDVC − 0.1 LCDVC V Current on segment line = −2 µA
DC Voltage Across Segment and COMx Pin 50 mV LCDVC − LCDVB, LCDVC − LCDVA, or
LCDVB − LCDVA
Data Sheet ADE5169/ADE5569
Rev. E | Page 9 of 155
Parameter Min Typ Max Unit Test Conditions/Comments
LCD, RESISTOR LADDER ACTIVE
Leakage Current ±20 nA 1/2 and 1/3 bias modes, no load
V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 µA
V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 µA
LCDVC − 0.1
LCDVC
V
Current on segment line = −2 µA
ON-CHIP REFERENCE Nominal 1.2035 V
Reference Error −2.2 +2.2 mV T
A
= 25°C, f
CORE
= 1.024 MHz
Power Supply Rejection 80 dB
Temperature Coefficient
10 50 ppm/°C f
CORE
= 1.024 MHz
1 These specifications are not production tested but are guaranteed by design and/or characterization data on production release.
2 Delay between ADC conversion request and interrupt set.
DIGITAL INTERFACE
Table 4.
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS1
All Inputs Except XTAL1, XTAL2, BCTRL,
INT0, INT1, RESET
Input High Voltage, V
2.0 V
Input Low Voltage, V
0.8 V
BCTRL, INT0, INT1, RESET
Input High Voltage, V
1.3 V
Input Low Voltage, V
0.8 V
Input Currents
RESET 100 nA RESET = VSWOUT = 3.3 V
Port 0, Port 1, Port 2 ±100 nA Internal pull-up disabled, input = 0 V or
V
SWOUT
−3.75
−8.5
µA
Internal pull-up enabled, input = 0 V,
V
SWOUT
= 3.3 V
Input Capacitance 10 pF All digital inputs
FLASH MEMORY
Endurance
20,000 Cycles At 25°C
Data Retention
20 Years T
J
= 85°C
CRYSTAL OSCILLATOR
Crystal Equivalent Series Resistance 30 50 kΩ
Crystal Frequency 32 32.768 33.5 kHz
XTAL1 Input Capacitance 12 pF
XTAL2 Output Capacitance 12 pF
MCU CLOCK RATE (f
) 4.096 MHz Crystal = 32.768 kHz and CD bits = 0b000
32 kHz Crystal = 32.768 kHz and CD bits = 0b111
LOGIC OUTPUTS
Output High Voltage, V
2.4 V V
DD
= 3.3 V ± 5%
I
80 µA
Output Low Voltage, V
5 0.4 V V
DD
= 3.3 V ± 5%
2
mA
START-UP TIME6
PSM0 Power-On Time 880 ms V
DD
at 2.75 V to PSM0 code execution
From Power Saving Mode 1 (PSM1)
PSM1 to PSM0 130 ms V
DD
at 2.75 V to PSM0 code execution
From Power Saving Mode 2 (PSM2)
PSM2 to PSM1 48 ms Wake-up event to PSM1 code execution
PSM2 to PSM0 186 ms V
DD
at 2.75 V to PSM0 code execution
ADE5169/ADE5569 Data Sheet
Rev. E | Page 10 of 155
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY INPUTS
V
3.13 3.3 3.46 V
V
2.4 3.3 3.7 V
INTERNAL POWER SUPPLY SWITCH (V
)
V
to V
On Resistance 12 Ω V
BAT
= 2.4 V
V
to V
On Resistance 9 Ω V
DD
= 3.13 V
V
to/from V
Switching Open Time 40 ns
BCTRL State Change and Switch Delay 18 µs
V
Output Current Drive 6 mA
POWER SUPPLY OUTPUTS
2.3
2.70
V
V
2.3 2.70 V
V
Power Supply Rejection 60 dB
V
Power Supply Rejection 50 dB
POWER SUPPLY CURRENTS
Current in Normal Mode (PSM0) 4.4 5.3 mA f
CORE
= 4.096 MHz, LCD and meter active
2.2 mA f
CORE
= 1.024 MHz, LCD and meter active
1.6 mA f
CORE
= 32.768 kHz, LCD and meter active
3 3.9 mA fCORE = 4.096 MHz; metering ADC and DSP,
powered down
Current in Battery Mode (PSM1) 3.3 5.05 mA f
CORE
= 4.096 MHz, LCD active, V
BAT
= 3.7 V
1 mA f
CORE
= 1.024 MHz, LCD active
Current in Sleep Mode (PSM2) 38 µA LCD active with charge pump at 3.3 V + RTC,
V
BAT
= 3.3 V
1.7 µA RTC only, T
A
= 25°C, V
BAT
= 3.3 V
1 Specifications guaranteed by design.
2 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
3 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.
4 Recommended crystal specifications.
5 Test carried out with all the I/Os set to a low output level.
6 Delay between power supply valid and execution of first instruction by 8052 core.
Data Sheet ADE5169/ADE5569
Rev. E | Page 11 of 155
TIMING SPECIFICATIONS
AC inputs during testing were driven at VSWOUT − 0.5 V for Logic 1
and at 0.45 V for Logic 0. Timing measurements were made at VIH
minimum for Logic 1 and at VIL maximum for Logic 0, as shown in
Figure 3.
For timing purposes, a port pin is no longer floating when
a 100 mV change from load voltage occurs. A port pin begins
to float when a 100 mV change from the loaded VOH/VOL level
occurs, as shown in Figure 3.
CLOAD = 80 pF for all outputs, unless otherwise noted. VDD = 2.7 V
to 3.6 V; all specifications TMIN to TMAX, unless otherwise noted.
V
SWOUT
–
0.5
V
0.45V
0.2V
SWOUT
+ 0.9V
TEST POINTS
0.2V
SWOUT
– 0.1V
V
LOAD
– 0.1V
V
LOAD
V
LOAD
+ 0.1V
TIMING
REFERENCE
POINTS
V
LOAD
– 0.1VV
LOAD
V
LOAD
– 0.1V
07411-002
Figure 3. Timing Waveform Characteristics
Table 5. Clock Input (External Clock Driven XTAL1) Parameters
32.768 kHz External Crystal
Parameter Description Min Typ Max Unit
tCK XTAL1 period 30.52 μs
tCKL XTAL1 width low 6.26 μs
tCKH XTAL1 width high 6.26 μs
tCKR XTAL1 rise time 9 ns
tCKF XTAL1 fall time 9 ns
1/tCORE Core clock frequency1 1.024 MHz
1 The ADE5169/ADE5569 internal PLL locks onto a multiple (512×) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the system.
The core can operate at this frequency or at a binary submultiple defined by the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26).
Table 6. I2C-Compatible Interface Timing Parameters (400 kHz)
Parameter Description Typ Unit
tBUF Bus free time between stop condition and start condition 1.3 μs
tL SCLK low pulse width 1.36 μs
tH SCLK high pulse width 1.14 μs
tSHD Start condition hold time 251.35 μs
tDSU Data setup time 740 ns
tDHD Data hold time 400 ns
tRSU Setup time for repeated start 12.5 ns
tPSU Stop condition setup time 400 ns
tR Rise time of both SCLK and SDATA 200 ns
tF Fall time of both SCLK and SDATA 300 ns
tSUP1 Pulse width of spike suppressed 50 ns
1 Input filtering on both the SCLK and SDATA suppresses noise spikes of <50 ns.
MSB
tBUF
SDATA (I/O)
SCLK (I)
STOP
CONDITION START
CONDITION REPEATED
START
LSB ACK MSB
12TO 7 89 1
S(R)
PS
tPSU
tDSU
tSHD
tDHD tDSU tDHD
tSUP
tH
tSUP
tL
tRSU tR
tR
tF
tF
07411-003
Figure 4. I2C-Compatible Interface Timing
ADE5169/ADE5569 Data Sheet
Rev. E | Page 12 of 155
Table 7. SPI Master Mode Timing Parameters (SPICPHA = 1)
Parameter Description Min Typ Max Unit
t
SL
SCLK low pulse width 2
SPIR
× t
CORE1
ns
t
SH
SCLK high pulse width 2SPIR × t
CORE
1 ns
t
DAV
Data output valid after SCLK edge 3 × t
CORE
1 ns
t
DSU
Data input setup time before SCLK edge 0 ns
t
DHD
Data input hold time after SCLK edge t
CORE1
ns
t
DF
Data output fall time 19 ns
t
DR
Data output rise time 19 ns
t
SR
SCLK rise time 19 ns
tSF
SCLK fall time
19
ns
1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz.
SCLK
(SPICPOL = 0)
t
DSU
SCLK
(SPICPOL = 1)
MOSI
MISO
MSB LSB
LSB IN
BITS[6:1]
BITS[6:1]
t
DHD
t
DR
t
DAV
t
DF
t
SH
t
SL
t
SR
t
SF
MSB IN
07411-004
Figure 5. SPI Master Mode Timing (SPICPHA = 1)
Data Sheet ADE5169/ADE5569
Rev. E | Page 13 of 155
Table 8. SPI Master Mode Timing Parameters (SPICPHA = 0)
Parameter Description Min Typ Max Unit
t
SL
SCLK low pulse width 2
SPIR
× t
CORE1
(SPIR + 1) × t
CORE1
ns
t
SH
SCLK high pulse width 2SPIR × t
CORE
1 (SPIR + 1) × t
CORE
1 ns
t
DAV
Data output valid after SCLK edge 3 × t
CORE
1 ns
t
DOSU
Data output setup before SCLK edge 75 ns
t
DSU
Data input setup time before SCLK edge 0 ns
t
DHD
Data input hold time after SCLK edge t
CORE1
ns
t
DF
Data output fall time 19 ns
t
DR
Data output rise time 19 ns
t
SR
SCLK rise time 19 ns
tSF
SCLK fall time
19
ns
1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz.
SCLK
(SPICPOL = 0)
tDSU
SCLK
(SPICPOL = 1)
MOSI
MISO
MSB LSB
LSB IN
BITS[6:1]
BITS[6:1]
tDHD
tDR
tDAV
tDF
tDOSU
tSH tSLtSR tSF
MSB IN
07411-005
Figure 6. SPI Master Mode Timing (SPICPHA = 0)
ADE5169/ADE5569 Data Sheet
Rev. E | Page 14 of 155
Table 9. SPI Slave Mode Timing Parameters (SPICPHA = 1)
Parameter Description Min Typ Max Unit
tSS SS to SCLK edge 145 ns
t
SL
SCLK low pulse width 6 × t
CORE1
ns
t
SH
SCLK high pulse width 6 × t
CORE1
ns
t
DAV
Data output valid after SCLK edge 25 ns
t
DSU
Data input setup time before SCLK edge 0 ns
t
DHD
Data input hold time after SCLK edge 2 × t
CORE
1 + 0.5 µs
t
DF
Data output fall time 19 ns
t
DR
Data output rise time 19 ns
t
SR
SCLK rise time 19 ns
t
SF
SCLK fall time 19 ns
tSFS SS high after SCLK edge 0 ns
1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz.
MSB
MOSI BITS[6:1]
t
DHD
t
DSU
MSB IN LSB IN
BITS[6:1] LSB
t
DR
t
DF
t
DAV
MISO
t
SL
t
SH
t
SR
t
SF
t
SFS
t
SS
SCLK
(SPICPOL = 1)
SCLK
(SPICPOL = 0)
SS
07411-006
Figure 7. SPI Slave Mode Timing (SPICPHA = 1)
Data Sheet ADE5169/ADE5569
Rev. E | Page 15 of 155
Table 10. SPI Slave Mode Timing Parameters (SPICPHA = 0)
Parameter Description Min Typ Max Unit
tSS SS to SCLK edge 145 ns
t
SL
SCLK low pulse width 6 × t
CORE1
ns
t
SH
SCLK high pulse width 6 × t
CORE1
ns
t
DAV
Data output valid after SCLK edge 25 ns
t
DSU
Data input setup time before SCLK edge 0 ns
t
DHD
Data input hold time after SCLK edge 2 × t
CORE
1+ 0.5 µs
t
DF
Data output fall time 19 ns
t
DR
Data output rise time 19 ns
t
SR
SCLK rise time 19 ns
t
SF
SCLK fall time 19 ns
tDOSS Data output valid after SS edge 0 ns
tSFS SS high after SCLK edge 0 ns
1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz.
MSB
MOSI BITS[6:1]
tDHD
tDSU
LSB IN
BITS[6:1] LSB
tDR
tDF
tDAV
MISO
tSR tSF
tSFS
tSS
SCLK
(SPICPOL = 1)
SCLK
(SPICPOL = 0)
SS
tSH tSL
tDOSS
MSB IN
07411-007
Figure 8. SPI Slave Mode Timing (SPICPHA = 0)
ADE5169/ADE5569 Data Sheet
Rev. E | Page 16 of 155
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 11.
Parameter Rating
V
DD
to DGND −0.3 V to +3.7 V
V
BAT
to DGND −0.3 V to +3.7 V
V
DCIN
to DGND −0.3 V to V
SWOUT
+ 0.3 V
Input LCD Voltage to AGND, LCDVA,
LCDVB, LCDVC1
−0.3 V to VSWOUT + 0.3 V
Analog Input Voltage to AGND, VP, VN,
I
P
/I
PA
, I
PB
, and I
N
−2 V to +2 V
Digital Input Voltage to DGND −0.3 V to V
SWOUT
+ 0.3 V
Digital Output Voltage to DGND −0.3 V to V
SWOUT
+ 0.3 V
Operating Temperature Range (Industrial) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
64-Lead LQFP, Power Dissipation
Lead Temperature (Soldering, 30 sec)
300°C
1 When used with external resistor divider.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst case condition, that is, a device
soldered in a circuit board for surface-mount packages.
Table 12. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
64-Lead LQFP 60 20.5 °C/W
ESD CAUTION
Data Sheet ADE5169/ADE5569
Rev. E | Page 17 of 155
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
64
V
DCIN
63
DGND
62
V
INTD
61
V
SWOUT
60
V
DD
59
V
INTA
58
V
BAT
57
REF
IN/OUT
56
I
PB
55
RESET
54
AGND
53
I
N
52
I
PA
51
EA
50
V
N
49
V
P
47
XTAL1
46
XTAL2
45
BCTRL/INT1/P0.0
42
P0.3/CF2
43
P0.2/CF1
44
SDEN/P2.3/TxD2
48
INT0
41
P0.4/MOSI/SDATA
40
P0.5/MISO/ZX
39
P0.6/SCLK/T0
37
P1.0/RxD
36
P1.1/TxD
35
FP0
34
FP1
33
FP2
38
P0.7/SS/T1/RxD2
2
COM2/FP28
3
COM1
4
COM0
7
P1.4/T2/FP23
6
P1.3/T2EX/FP24
5
P1.2/FP25/ZX
1
COM3/FP27
8
P1.5/FP22
9
P1.6/FP21
10
P1.7/FP20
12
P2.0/FP18
13
P2.1/FP17
14
P2.2/FP16
15
LCDVC
16
LCDVP2
11
P0.1/FP19
17
LCDVB
18
LCDVA
19
LCDVP1
20
FP15
21
FP14
22
FP13
23
FP12
24
FP11
25
FP10
26
FP9
27
FP8
28
FP7
29
FP6
30
FP5
31
FP4
32
FP3
PIN 1
ADE5169
TOP VIEW
(No t t o Scal e)
07411-010
Figure 9. ADE5169 Pin Configuration
Table 13. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane.
2 COM2/FP28 Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane.
3 COM1 Common Output 1. COM1 is used for the LCD backplane.
4 COM0 Common Output 0. COM0 is used for the LCD backplane.
5 P1.2/FP25/ZX General-Purpose Digital I/O Port 1.2/LCD Segment Output 25/ZX Output.
6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24.
7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23.
8 P1.5/FP22 General-Purpose Digital I/O Port 1.5/LCD Segment Output 22.
9 P1.6/FP21 General-Purpose Digital I/O Port 1.6/LCD Segment Output 21.
10 P1.7/FP20 General-Purpose Digital I/O Port 1.7/LCD Segment Output 20.
11 P0.1/FP19 General-Purpose Digital I/O Port 0.1/LCD Segment Output 19.
12 P2.0/FP18 General-Purpose Digital I/O Port 2.0/LCD Segment Output 18.
13
P2.1/FP17
General-Purpose Digital I/O Port 2.1/LCD Segment Output 17.
14 P2.2/FP16 General-Purpose Digital I/O Port 2.2/LCD Segment Output 16.
15 LCDVC Output Port for LCD Levels. This pin should be decoupled with a 470 nF capacitor.
16 LCDVP2 Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP1 for the internal LCD
charge pump device.
17, 18 LCDVB, LCDVA Output Ports for LCD Levels. These pins should be decoupled with a 470 nF capacitor.
19 LCDVP1 Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP2 for the internal LCD
charge pump device.
20 to 35 FP15 to FP0 LCD Segment Output 15 to LCD Segment Output 0.
36 P1.1/TxD General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous).
37
P1.0/RxD
General-Purpose Digital I/O Port 1.0/Receive Data Input (Asynchronous).
38 P0.7/SS/T1/RxD2 General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input/Receive Data
Input 2 (Asynchronous).
39 P0.6/SCLK/T0 General-Purpose Digital I/O Port 0.6/Clock Output for I
2
C or SPI Port/Timer 0 Input.
40 P0.5/MISO/ZX General-Purpose Digital I/O Port 0.5/Data Input for SPI Port/ZX Output.
41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 18 of 155
Pin No. Mnemonic Description
42 P0.3/CF2 General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives
instantaneous active, reactive, or apparent power or I
rms
information.
43 P0.2/CF1 General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1. The CF1 logic output gives
instantaneous active, reactive, or apparent power or I
rms
information.
44
SDEN
/P2.3/TxD2
Serial Download Mode Enable/General-Purpose Digital Output Port 2.3/Transmitter Data Output 2
(Asynchronous). This pin is used to enable serial download mode through a resistor when pulled low on
power-up or reset. On reset, this pin momentarily becomes an input, and the status of the pin is sampled.
If there is no pull-down resistor in place, the pin momentarily goes high, and then user code is executed.
If the pin is pulled down on reset, the embedded serial download/debug kernel executes, and this pin remains
low during the internal program execution. After reset, this pin can be used as a digital output port pin (P2.3)
or as Transmitter Data Output 2 (asynchronous).
45 BCTRL/INT1/P0.0 Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic
input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left
open, the connection between V
DD
or V
BAT
and V
SWOUT
is selected internally.
46 XTAL2 A crystal can be connected across this pin and XTAL1 (see the XTAL1 pin description) to provide a clock
source. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate
oscillator circuit. An internal 6 pF capacitor is connected to this pin.
47 XTAL1 An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected
across XTAL1 and XTAL2 to provide a clock source. The clock frequency for specified operation is 32.768 kHz.
An internal 6 pF capacitor is connected to this pin.
48 INT0 External Interrupt Input 0.
49, 50
V
P
, V
N
Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±500 mV for specified operation. This channel also has an internal PGA.
51 EA Input for Emulation. When held high, this input enables the device to fetch code from internal program
memory locations. The ADE5169 do not support external code memory. This pin should not be left floating.
52, 53 IPA , IN Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±500 mV for specified operation. This channel also has an internal PGA.
54 AGND Ground Reference for Analog Circuitry.
55 IPB Analog Input for Second Current Channel. This input is fully differential with a maximum differential level of
±500 mV, referred to I
N
for specified operation. This channel also has an internal PGA.
56 RESET Reset Input, Active Low.
57 REFIN/OUT Access to On-Chip Voltage Reference. The on-chip reference has a nominal value of 1.2 V ± 0.1% and a typical
temperature coefficient of 50 ppm/°C maximum. This pin should be decoupled with a 1 µF capacitor in
parallel with a ceramic 100 nF capacitor.
58 VBAT Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to VDD when
the battery is selected as the power supply.
59 VINTA Access to On-Chip 2.5 V Analog LDO. No external active circuitry should be connected to this pin. This pin
should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
60 VDD 3.3 V Power Supply Input from the Regulator. This pin is connected internally to VSWOUT when the regulator is
selected as the power supply. This pin should be decoupled with a 10 µF capacitor in parallel with a ceramic
100 nF capacitor.
61 VSWOUT 3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and the internal circuitry. This
pin should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
62 VINTD Access to On-Chip 2.5 V Digital LDO. No external active circuitry should be connected to this pin. This pin
should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
63 DGND Ground Reference for Digital Circuitry.
64 VDCIN Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to
AGND. This pin is used to monitor the preregulated dc voltage.
Data Sheet ADE5169/ADE5569
Rev. E | Page 19 of 155
64
V
DCIN
63
DGND
62
V
INTD
61
V
SWOUT
60
V
DD
59
V
INTA
58
V
BAT
57
REF
IN/OUT
56 55
RESET
54
AGND
53
I
N
52 51
EA
50
V
N
49
V
P
47
XTAL1
46
XTAL2
45
BCTRL/INT1/P0.0
42
P0.3/CF2
43
P0.2/CF1
44
SDEN/P2.3/TxD2
48
INT0
41
P0.4/MOSI/SDATA
40
P0.5/MISO/ZX
39
P0.6/SCLK/T0
37
P1.0/RxD
36
P1.1/TxD
35
FP0
34
FP1
33
FP2
38
P0.7/SS/T1/RxD2
2
COM2/FP28
3
COM1
4
COM0
7
P1.4/T2/FP23
6
P1.3/T2EX/FP24
5
P1.2/FP25/ZX
1
COM3/FP27
8
P1.5/FP22
9
P1.6/FP21
10
P1.7/FP20
12
P2.0/FP18
13
P2.1/FP17
14
P2.2/FP16
15
LCDVC
16
LCDVP2
11
P0.1/FP19
17
LCDVB
18
LCDVA
19
LCDVP1
20
FP15
21
FP14
22
FP13
23
FP12
24
FP11
25
FP10
26
FP9
27
FP8
28
FP7
29
FP6
30
FP5
31
FP4
32
FP3
PIN 1
ADE5569
TOP VIEW
(No t t o Scal e)
07411-028
I
P
FP26
Figure 10. ADE5569 Pin Configuration
Table 14. Pin Function Descriptions
Pin No. Mnemonic Description
1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane.
2 COM2/FP28 Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane.
3 COM1 Common Output 1. COM1 is used for the LCD backplane.
4 COM0 Common Output 0. COM0 is used for the LCD backplane.
5 P1.2/FP25/ZX General-Purpose Digital I/O Port 1.2/LCD Segment Output 25/ZX Output.
6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24.
7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23.
8 P1.5/FP22 General-Purpose Digital I/O Port 1.5/LCD Segment Output 22.
9 P1.6/FP21 General-Purpose Digital I/O Port 1.6/LCD Segment Output 21.
10 P1.7/FP20 General-Purpose Digital I/O Port 1.7/LCD Segment Output 20.
11 P0.1/FP19 General-Purpose Digital I/O Port 0.1/LCD Segment Output 19.
12 P2.0/FP18 General-Purpose Digital I/O Port 2.0/LCD Segment Output 18.
13 P2.1/FP17 General-Purpose Digital I/O Port 2.1/LCD Segment Output 17.
14
P2.2/FP16
General-Purpose Digital I/O Port 2.2/LCD Segment Output 16.
15
LCDVC
Output Port for LCD Levels. This pin should be decoupled with a 470 nF capacitor.
16 LCDVP2 Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP1 for the internal LCD
charge pump device.
17, 18 LCDVB, LCDVA Output Ports for LCD Levels. These pins should be decoupled with a 470 nF capacitor.
19 LCDVP1 Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP2 for the internal LCD
charge pump device.
20 to 35 FP15 to FP0 LCD Segment Output 15 to LCD Segment Output 0.
36 P1.1/TxD General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous).
37 P1.0/RxD General-Purpose Digital I/O Port 1.0/Receive Data Input (Asynchronous).
38 P0.7/SS/T1/RxD2 General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input/Receive Data
Input 2 (Asynchronous).
39 P0.6/SCLK/T0 General-Purpose Digital I/O Port 0.6/Clock Output for I2C or SPI Port/Timer 0 Input.
40 P0.5/MISO/ZX General-Purpose Digital I/O Port 0.5/Data Input for SPI Port/ZX Output.
41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I
2
C-Compatible Data Line.
42 P0.3/CF2 General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives
instantaneous active, reactive, or apparent power or I
rms
information.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 20 of 155
Pin No. Mnemonic Description
43 P0.2/CF1 General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1. The CF1 logic output gives
instantaneous active, reactive, or apparent power or I
rms
information.
44 SDEN/P2.3/TxD2 Serial Download Mode Enable/General-Purpose Digital Output Port 2.3/Transmitter Data Output 2
(Asynchronous). This pin is used to enable serial download mode through a resistor when pulled low on
power-up or reset. On reset, this pin momentarily becomes an input, and the status of the pin is sampled.
If there is no pull-down resistor in place, the pin momentarily goes high, and then user code is executed.
If the pin is pulled down on reset, the embedded serial download/debug kernel executes, and this pin remains low
during the internal program execution. After reset, this pin can be used as a digital output port pin (P2.3) or
as Transmitter Data Output 2 (asynchronous).
45 BCTRL/INT1/P0.0 Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic
input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left
open, the connection between V
DD
or V
BAT
and V
SWOUT
is selected internally.
46 XTAL2 A crystal can be connected across this pin and XTAL1 (see the XTAL1 pin description) to provide a clock
source. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate
oscillator circuit. An internal 6 pF capacitor is connected to this pin.
47 XTAL1 An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected
across XTAL1 and XTAL2 to provide a clock source. The clock frequency for specified operation is 32.768 kHz.
An internal 6 pF capacitor is connected to this pin.
48 INT0 External Interrupt Input 0.
49, 50 VP, VN Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±500 mV for specified operation. This channel also has an internal PGA.
51
EA
Input for Emulation. When held high, this input enables the device to fetch code from internal program
memory locations. The ADE5569 do not support external code memory. This pin should not be left floating.
52, 53 IP, IN Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±500 mV for specified operation. This channel also has an internal PGA.
54 AGND Ground Reference for Analog Circuitry.
55 FP26 LCD Segment Output 26.
56 RESET Reset Input, Active Low.
57 REFIN/OUT Access to On-Chip Voltage Reference. The on-chip reference has a nominal value of 1.2 V ± 0.1% and a typical
temperature coefficient of 50 ppm/°C maximum. This pin should be decoupled with a 1 µF capacitor in
parallel with a ceramic 100 nF capacitor.
58 VBAT Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to VDD when
the battery is selected as the power supply.
59 VINTA Access to On-Chip 2.5 V Analog LDO. No external active circuitry should be connected to this pin. This pin
should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
60 VDD 3.3 V Power Supply Input from the Regulator. This pin is connected internally to VSWOUT when the regulator is
selected as the power supply. This pin should be decoupled with a 10 µF capacitor in parallel with a ceramic
100 nF capacitor.
61 VSWOUT 3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and the internal circuitry. This
pin should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
62 VINTD Access to On-Chip 2.5 V Digital LDO. No external active circuitry should be connected to this pin. This pin
should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
63 DGND Ground Reference for Digital Circuitry.
64 VDCIN Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to
AGND. This pin is used to monitor the preregulated dc voltage.
Data Sheet ADE5169/ADE5569
Rev. E | Page 21 of 155
TYPICAL PERFORMANCE CHARACTERISTICS
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 1 10 100
MID CLAS S C
MI D C LASS C
–40°C; PF = 1
07411-126
CURRENT CHANNE L (% of Full S cale)
ERROR ( % o f Read i ng )
+85°C ; P F = 1
+25°C; P F = 1
GAIN = 1
INTEGRATOR OFF
INTERN AL REFERE N CE
Figure 11. Active Energy Error as a Percentage of Reading (Gain = 1)
over Temperature with Internal Reference, Integrator Off
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0.1 1 10 100
MI D CLASS C
MI D CLASS C
–40°C; PF = 1
07411-127
CURRENT CHANNEL ( % o f F ull Scale)
ERROR (% of Reading)
+85°C; PF = 0.5
+25°C; PF = 1
–40°C; PF = 0. 5
+85°C; PF = 1
+25°C; PF = 0.5
GAIN = 1
INTEGRATOR OFF
INTERN AL REFERENCE
Figure 12. Active Energy Error as a Percentage of Reading (Gain = 1)
over Power Factor with Internal Reference, Integrator Off
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 1 10 100
–40°C; PF = 0
07411-128
CURRENT CHANNEL ( % o f F ull Scale)
ERROR ( % o f Read i ng )
+85°C; PF = 0
+25°C; PF = 0
GAIN = 1
INTEGRATOR OFF
INTERNA L REFERE N CE
Figure 13. Reactive Energy Error as a Percentage of Reading (Gain = 1)
over Temperature with Internal Reference, Integrator Off
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 1 10 100
07411-129
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Read ing)
GAIN = 1
INTEGRATOR OFF
INTERNA L REFERE N CE
–40°C; P F = 0. 866 +85°C; PF = 0
+25°C; PF = 0.866 –40°C; P F = 0
+25°C; PF = 0
Figure 14. Reactive Energy Error as a Percentage of Reading (Gain = 1)
over Power Factor with Internal Reference, Integrator Off
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 1 10 100
MI D CLASS C
MI D C LASS C
–40°C; PF = 1
07411-130
CURRENT CHANNEL (% of Full Scale)
ERROR (% o f Read ing)
+85°C; PF = 1
+25°C; PF = 1
GAIN = 1
INTEGRATOR OFF
INTERNA L REFERE N CE
Figure 15. Current RMS Error as a Percentage of Reading (Gain = 1)
over Temperature with Internal Reference, Integrator Off
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 1 10 100
MI D CLASS C
MI D C LASS C
07411-131
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 1
INTEGRATOR OFF
INTERNA L REFERE N CE
–40°C; PF = 1
+85°C; PF = 0.5
+25°C; PF = 1
–40°C; P F = 0.5
+85°C; PF = 1
+25°C; PF = 0.5
Figure 16. Current RMS Error as a Percentage of Reading (Gain = 1)
over Power Factor with Internal Reference, Integrator Off
ADE5169/ADE5569 Data Sheet
Rev. E | Page 22 of 155
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.1 1 10 100
07411-132
CURRENT CHANNEL ( % o f F ull Scale)
ERRO R ( % o f Read in g )
GAIN = 1
INTEGRATOR OFF
INTERNA L REFERE N CE
V
RMS
; 3.43V
V
RMS
; 3.13V
I
RMS
; 3.13V
I
RMS
; 3.43V
V
RMS
; 3.3V
I
RMS
; 3.3V
Figure 17. Voltage and Current RMS Error as a Percentage of Reading
(Gain = 1) over Power Supply with Internal Reference
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
40 45 50 55 60 65 70
PF = 1
PF = 0.5
GAIN = 1
INTEGRATOR OFF
INTERNAL RE FERE NCE
07411-133
LINE FREQUENCY (Hz)
ERROR (% of Read ing)
MI D C LASS B
MI D C LASS B
Figure 18. Active Energy Error as a Percentage of Reading (Gain = 1)
over Frequency with Internal Reference, Integrator Off
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.1 1 10 100
07411-134
CURRENT CHANNEL (% of F ul l Scal e)
ERROR (% of Read ing)
GAIN = 1
INTEGRATOR OFF
INT E RN AL RE FERE NCE
VAR; 3. 43V
W; 3.43V VAR; 3.3V
VAR; 3.13V
W; 3.13V
W; 3.3V
Figure 19. Active and Reactive Energy Error as a Percentage of Reading (Gain = 1)
over Power Supply with Internal Reference, Integrator Off
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0.1 1 10 100
MID CLASS C
MID CLASS C
07411-135
CURRENT CHANNE L (% o f Fu l l Scale)
ERRO R ( % o f Reading)
PF = +0.5
PF = +1
PF = –0.5
GAIN = 8
INT E GRAT OR O F F
INTERNAL REFERENCE
Figure 20. Active Energy Error as a Percentage of Reading (Gain = 8)
over Power Factor with Internal Reference, Integrator Off
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0.1 1 10 100
07411-136
CURRENT CHANNE L (% o f Fu l l Scale)
ERROR (% o f Readi ng)
GAIN = 8
INT E GRAT OR O F F
INTERNAL REFERENCE
PF = +0.866
PF = 0
PF = –0.866
Figure 21. Reactive Energy Error as a Percentage of Reading (Gain = 8)
over Power Factor with Internal Reference, Integrator Off
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0.1 1 10 100
MID CLASS C
MID CLASS C
07411-137
CURRENT CHANNE L (% o f Fu l l Scale)
ERROR ( % of Readin g)
PF = +0.5
PF = +1
PF = –0.5
GAIN = 8
INT E GRAT OR O F F
INTERNAL REFERENCE
Figure 22. Current RMS Error as a Percentage of Reading (Gain = 8)
over Power Factor with Internal Reference, Integrator Off
Data Sheet ADE5169/ADE5569
Rev. E | Page 23 of 155
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
2.0
1.5
0.1 1 10 100
MID CLASS C
MID CLASS C
07411-138
CURRENT CHANNE L (% o f Full S cale)
ERROR (% of Reading)
GAIN = 16
INT E GRAT OR O F F
INTERNAL REFEREN CE
+25°C
;
PF = 1
–40°C
;
PF = 1
+85°C
;
PF = 1
Figure 23. Active Energy Error as a Percentage of Reading (Gain = 16)
over Temperature with Internal Reference, Integrator Off
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
2.0
1.5
0.1 1 10 100
MID CLASS C
MID CLASS C
07411-139
CURRENT CHANNE L (% o f Full S cale)
ERRO R ( % o f Reading)
+25°C
;
PF = 1
+25°C
;
PF = 0.5
–40°C
;
PF = 0.5
–40°C
;
PF = 1
+85°C
;
PF = 0.5
GAIN = 16
INTEGRATOR OFF
INT E RN AL RE FERE NCE
+85°C
;
PF = 1
Figure 24. Active Energy Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator Off
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0.1 1 10 100
07411-140
CURRENT CHANNE L ( % o f Fu ll S cal e)
ERROR (% of Read ing)
GAIN = 16
INTEGRATOR OFF
INTERNAL REFERENC E
+85°C; P F = 0 –40°C; PF = 0
+25°C; PF = 0
Figure 25. Reactive Energy Error as a Percentage of Reading (Gain = 16)
over Temperature with Internal Reference, Integrator Off
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0.1 1 10 100
07411-141
CURRENT CHANNE L ( % o f Fu ll S cal e)
ERROR ( % of Read i ng)
GAIN = 16
INTEGRATOR OFF
INTERNAL REFERENC E
+85°C; PF = 0 –40° C ; P F = 0
–40° C ; P F = 0.866
+25°C; PF = 0 +25°C; PF = 0.866
+85°C; PF = 0.866
Figure 26. Reactive Energy Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator Off
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
2.0
1.5
0.1 1 10 100
MI D C LASS C
MI D C LASS C
07411-142
CURRENT CHANNEL (% of Fu ll Scale)
ERROR (% o f Read ing)
GAIN = 16
INTEGRATOR OFF
INTERNA L REFERE N CE
+25°C
;
PF = 1
+85°C
;
PF = 1
–40°C
;
PF = 1
Figure 27. Current RMS Error as a Percentage of Reading (Gain = 16)
over Temperature with Internal Reference, Integrator Off
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
2.0
1.5
0.1 1 10 100
MI D C LASS C
MI D C LASS C
07411-143
CURRENT CHANNEL (% of Fu ll Scale)
ERROR (% of Read ing)
GAIN = 16
INTEGRATOR OFF
INTERNA L REFERE N CE
+25°C
;
PF = 1
+85°C
;
PF = 1
+85°C
;
PF = 0.5
+25°C
;
PF = 0.5
–40°C
;
PF = 1
–40°C
;
PF = 0.5
Figure 28. Current RMS Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator Off
ADE5169/ADE5569 Data Sheet
Rev. E | Page 24 of 155
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
2.0
1.5
0.1 1 10 100
MI D C LASS C
MI D C LASS C
07411-144
CURRENT CHANNEL (% of Fu ll Scale)
ERROR ( % of Read i ng )
GAIN = 16
INTEGRATOR ON
INTERNA L REFERE N CE
+25°C; PF = 1
+25°C; PF = 0.5
+85°C
;
PF = 1 +85°C
;
PF = 0.5
–40°C
;
PF = 1
–40°C
;
PF = 0.5
Figure 29. Active Energy Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator On
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0.1 1 10 100
07411-145
CURRENT CHANNE L (% o f Fu l l Scale)
ERROR (% of Read ing)
GAIN = 16
INTEGRATOR ON
INTERNAL RE FERE NCE
+85°C; PF = 0 –40°C; P F = 0
–40°C; PF = 0.866
+25°C; PF = 0 +25°C; PF = 0.866
+85°C; P F = 0.86 6
Figure 30. Reactive Energy Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator On
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
2.0
1.5
0.1 1 10 100
MI D C LASS C
MI D C LASS C
07411-146
CURRENT CHANNEL (% of Fu ll Scale)
ERROR ( % o f Read i ng)
GAIN = 16
INTEGRATOR ON
INTERNA L REFERE N CE
+25°C; PF = 0.5
+25°C; PF = 1
+85°C
;
PF = 1
+85°C
;
PF = 0.5
–40°C; P F = 0.5
–40°C; P F = 1
Figure 31. Current RMS Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator On
ADE5169/ADE5569
Rev. E | Page 25 of 155
TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the
ADE5169/ADE5569 is defined by the following formula:
Measurement Error =
%
100
×
−
EnergyTrue
EnergyTrueRegisterEnergy
Phase Error Between Channels
The digital integrator and the high-pass filter (HPF) in the current
channel have a nonideal phase response. To offset this phase
response and equalize the phase response between channels,
two phase correction networks are placed in the current channel:
one for the digital integrator and the other for the HPF. The phase
correction networks correct the phase response of the corre-
sponding component and ensure a phase match between the
current channel and the voltage channel to within ±0.1° over a
range of 45 Hz to 65 Hz with the digital integrator off. With the
digital integrator on, the phase is corrected to within ±0.4° over
a range of 45 Hz to 65 Hz.
Power Supply Rejection (PSR)
PSR quantifies the ADE5169/ADE5569 measurement error as a
percentage of reading when the power supplies are varied. For
the ac PSR measurement, a reading at nominal supplies (3.3 V)
is taken. A second reading is obtained with the same input signal
levels when an ac signal (100 mV rms/ 120 Hz) is introduced onto
the supplies. Any error introduced by this ac signal is expressed
as a percentage of the reading (see the Measurement Error
definition).
For the dc PSR measurement, a reading at nominal supplies
(3.3 V) is taken. A second reading is obtained with the same
input signal levels when the supplies are varied ±5%. Any error
introduced is expressed as a percentage of the reading.
ADC Offset Error
ADC offset error is the dc offset associated with the analog
inputs to the ADCs. It means that, with the analog inputs
connected to AGND, the ADCs still see a dc analog input
signal. The magnitude of the offset depends on the gain and
input range selection. However, when HPF1 is switched on,
the offset is removed from the current channel, and the power
calculation is not affected by this offset. The offsets can be
removed by performing an offset calibration (see the Analog
Inputs section).
Gain Error
Gain error is the difference between the measured ADC output
code (minus the offset) and the ideal output code (see the Current
Channel ADC section and the Voltage Channel ADC section).
It is measured for each of the gain settings on the current channel
(1, 2, 4, 8, and 16). The difference is expressed as a percentage
of the ideal code.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 26 of 155
SPECIAL FUNCTION REGISTER (SFR) MAPPING
Table 15. SFR Mapping
Mnemonic Address Description
INTPR 0xFF Interrupt pins configuration SFR
(see Table 17).
SCRATCH4 0xFE Scratch Pad 4 (see Table 25).
SCRATCH3 0xFD Scratch Pad 3 (see Table 24).
SCRATCH2 0xFC Scratch Pad 2 (see Table 23).
SCRATCH1 0xFB Scratch Pad 1 (see Table 22).
BAT VTH 0xFA Battery detection threshold
(see Table 53).
STRBPER 0xF9 Peripheral ADC strobe period
(see Table 50).
IPSMF 0xF8 Power management interrupt flag
(see Table 18).
TEMPCAL
0xF7
RTC temperature compensation
(see Table 133).
RTCCOMP 0xF6 RTC nominal compensation
(see Table 132).
BATPR 0xF5 Battery switchover configuration
(see Table 19).
PERIPH 0xF4 Peripheral configuration (see Table 20).
DIFFPROG 0xF3 Temperature and supply delta
(see Table 51).
B 0xF0 Auxiliary math (see Table 57).
VDCINADC 0xEF V
DCIN
ADC value (see Table 54).
SBAUD2 0xEE Enhanced Serial Baud Rate Control 2
(see Table 148).
LCDSEGE2 0xED LCD Segment Enable 2 (see Table 101).
IPSME 0xEC Power management interrupt enable
(see Table 21).
SBUF2 0xEB Serial Port 2 buffer (see Table 147).
SPISTAT 0xEA SPI interrupt status (see Table 155).
SPI2CSTAT 0xEA I
2
C interrupt status (see Table 159).
SPIMOD2 0xE9 SPI Configuration SFR 2 (see Table 154).
I2CADR 0xE9 I2C slave address (see Table 158).
SPIMOD1 0xE8 SPI Configuration SFR 1 (see Table 153).
I2CMOD 0xE8 I2C mode (see Table 157).
WAV2H 0xE7 Selection 2 sample MSB (see Table 31).
WAV2M 0xE6 Selection 2 sample middle byte
(see Table 31).
WAV2L 0xE5 Selection 2 sample LSB (see Table 31).
WAV1H 0xE4 Selection 1 sample MSB (see Table 31).
WAV1M
0xE3
Selection 1 sample middle byte
(see Table 31).
WAV1L 0xE2 Selection 1 sample LSB (see Table 31).
SCON2 0xE1 Serial Communications Control 2
(see Table 146).
ACC 0xE0 Accumulator (see Table 57).
BATADC
0xDF
Battery ADC value (see Table 55).
MIRQSTH 0xDE Interrupt Status 3 (see Table 43).
MIRQSTM 0xDD Interrupt Status 2 (see Table 42).
MIRQSTL 0xDC Interrupt Status 1 (see Table 41).
MIRQENH 0xDB Interrupt Enable 3 (see Table 46).
MIRQENM 0xDA Interrupt Enable 2 (see Table 45).
Mnemonic Address Description
MIRQENL 0xD9 Interrupt Enable 1 (see Table 44).
ADCGO
0xD8
Start ADC measurement (see Table 52).
TEMPADC 0xD7 Temperature ADC value (see Table 56).
IRMSH 0xD6 I
rms
measurement MSB (see Table 31).
IRMSM 0xD5 Irms measurement middle byte
(see Table 31).
IRMSL 0xD4 I
rms
measurement LSB (see Table 31).
VRMSH
0xD3
Vrms measurement MSB (see Table 31).
VRMSM 0xD2 Vrms measurement middle byte
(see Table 31).
VRMSL 0xD1 V
rms
measurement LSB (see Table 31).
PSW 0xD0 Program status word (see Table 58).
TH2 0xCD Timer 2 high byte (see Table 120).
TL2 0xCC Timer 2 low byte (see Table 121).
RCAP2H 0xCB Timer 2 reload/capture high byte
(see Table 122).
RCAP2L 0xCA Timer 2 reload/capture low byte
(see Table 123).
T2CON 0xC8 Timer/Counter 2 control (see Table 115).
EADRH 0xC7 Flash high byte address (see Table 110).
EADRL 0xC6 Flash low byte address (see Table 109).
POWCON 0xC5 Power control (see Table 26).
KYREG 0xC1 Key (see Table 126).
WDCON 0xC0 Watchdog timer (see Table 88).
STCON
0xBF
Stack boundary (see Table 65).
EDATA 0xBC Flash data (see Table 108).
PROTKY 0xBB Flash protection key (see Table 107).
FLSHKY 0xBA Flash key (see Table 106).
ECON 0xB9 Flash control (see Table 105).
IP
0xB8
Interrupt priority (see Table 82).
SPH 0xB7 Stack pointer high (see Table 64).
PINMAP2 0xB4 Port 2 weak pull-up enable
(see Table 164).
PINMAP1 0xB3 Port 1 weak pull-up enable
(see Table 163).
PINMAP0 0xB2 Port 0 weak pull-up enable
(see Table 162).
LCDCONY 0xB1 LCD Configuration Y (see Table 94).
CFG 0xAF Configuration (see Table 66).
LCDDAT 0xAE LCD data (see Table 100).
LCDPTR 0xAC LCD pointer (see Table 99).
IEIP2 0xA9 Interrupt Enable and Priority 2
(see Table 83).
IE 0xA8 Interrupt enable (see Table 81).
DPCON 0xA7 Data pointer control (see Table 79).
RTCDAT 0xA4 RTC pointer data (see Table 131).
RTCPTR 0xA3 RTC pointer address (see Table 130).
TIMECON2 0xA2 RTC Configuration 2 (see Table 129).
TIMECON 0xA1 RTC configuration (see Table 128).
P2 0xA0 Port 2 (see Table 167).
EPCFG 0x9F Extended port configuration
(see Table 161).
Data Sheet ADE5169/ADE5569
Rev. E | Page 27 of 155
Mnemonic Address Description
SBAUDT 0x9E Enhanced serial baud rate control
(see Table 142).
SBAUDF 0x9D UART timer fractional divider
(see Table 143).
LCDCONX
0x9C
LCD Configuration X (see Table 92).
SPI2CRx 0x9B SPI/I
2
C receive buffer (see Table 152).
SPI2CTx 0x9A SPI/I
2
C transmit buffer (see Table 151).
SBUF 0x99 Serial port buffer (see Table 141).
SCON 0x98 Serial communications control
(see Table 140).
LCDSEGE 0x97 LCD segment enable (see Table 98).
LCDCLK 0x96 LCD clock (see Table 95).
LCDCON 0x95 LCD configuration (see Table 91).
MDATH 0x94 Energy measurement pointer data MSB
(see Table 31).
MDATM
0x93
Energy measurement pointer data
middle byte (see Table 31).
MDATL 0x92 Energy measurement pointer data LSB
(see Table 31).
Mnemonic Address Description
MADDPT 0x91 Energy measurement pointer address
(see Table 30).
P1 0x90 Port 1 (see Table 166).
TH1 0x8D Timer 1 high byte (see Table 118).
TH0 0x8C Timer 0 high byte (see Table 116).
TL1 0x8B Timer 1 low byte (see Table 119).
TL0 0x8A Timer 0 low byte (see Table 117).
TMOD 0x89 Timer/Counter 0 and Timer/Counter 1
mode (see Table 113).
TCON 0x88 Timer/Counter 0 and Timer/Counter 1
control (see Table 114).
PCON 0x87 Program control (see Table 59).
DPH 0x83 Data pointer high (see Table 61).
DPL 0x82 Data pointer low (see Table 60).
SP 0x81 Stack pointer (see Table 63).
P0 0x80 Port 0 (see Table 165).
ADE5169/ADE5569 Data Sheet
Rev. E | Page 28 of 155
POWER MANAGEMENT
The ADE5169/ADE5569 have elaborate power management
circuitry that manages the regular power supply to battery
switchover and power supply failures.
The power management functionalities can be accessed directly
through the 8052 power management SFRs (see Table 16).
Table 16. Power Management SFRs
SFR Address R/W Mnemonic Description
0xEC R/W IPSME Power management interrupt enable (see Table 21).
0xF5 R/W BATPR Battery switchover configuration (see Table 19).
0xF8 R/W IPSMF Power management interrupt flag (see Table 18).
0xFF R/W INTPR Interrupt pins configuration (see Table 17).
0xF4 R/W PERIPH Peripheral configuration (see Table 20).
0xC5 R/W POWCON Power control (see Table 26).
0xFB R/W SCRATCH1 Scratch Pad 1 (see Table 22).
0xFC R/W SCRATCH2 Scratch Pad 2 (see Table 23).
0xFD R/W SCRATCH3 Scratch Pad 3 (see Table 24).
0xFE R/W SCRATCH4 Scratch Pad 4 (see Table 25).
POWER MANAGEMENT REGISTER DETAILS
Table 17. Interrupt Pins Configuration SFR (INTPR, Address 0xFF)
Bit Mnemonic Default Description
[7:4] Reserved Not applicable Reserved.
[3:1] INT1PRG 000 Controls the function of INT1.
INT1PRG Result
X001 GPIO enabled
X011 BCTRL enabled
01X1 INT1 input disabled
11X1 INT1 input enabled
0 INT0PRG 0 Controls the function of INT0.
INT0PRG Result
0 INT0 input disabled
1 INT0 input enabled
1 X means don’t care
Writing to the Interrupt Pins Configuration SFR (INTPR, Address 0xFF)
To protect the RTC from runaway code, a key must be written to the key SFR (KYREG, Address 0xC1) to obtain write access to the
INTPR SFR. The KYREG SFR (see Table 126) should be set to 0xEA to unlock the INTPR SFR and reset to 0 after a timekeeping register is
written to. The RTC registers can be written using the following 8052 assembly code:
MOV KYREG, #0EAh
MOV INTPR, #080h
Data Sheet ADE5169/ADE5569
Rev. E | Page 29 of 155
Table 18. Power Management Interrupt Flag SFR (IPSMF, Address 0xF8)
Bit Bit Address Mnemonic Default Description
7 0xFF FPSR 0 Power supply restored interrupt flag. Set when the VDD power supply has been restored.
This occurs when the source of V
SWOUT
changes from V
BAT
to V
DD
.
6 0xFE FPSM 0 PSM interrupt flag. Set when an enabled PSM interrupt condition occurs.
5 0xFD FSAG 0 Voltage SAG interrupt flag. Set when an ADE energy measurement SAG condition occurs.
4 0xFC Reserved 0 This bit must be kept at 0 for proper operation.
3 0xFB FVADC 0 VDCINADC monitor interrupt flag. Set when VDCIN changes by VDCIN_DIFF or when the VDCIN
measurement is ready.
2 0xFA FBAT 0 VBAT monitor interrupt flag. Set when VB AT falls below BATVTH or when VBAT measurement is
ready.
1
0xF9
FBSO
0
Battery switchover interrupt flag. Set when VSWOUT switches from VDD to VBAT.
0 0xF8 FVDCIN 0 V
DCIN
monitor interrupt flag. Set when V
DCIN
falls below 1.2 V.
Table 19. Battery Switchover Configuration SFR (BATPR, Address 0xF5)
Bit Mnemonic Default Description
[7:2] Reserved 0 These bits must be kept at 0 for proper operation.
[1:0] BATPRG 0 Control bits for battery switchover.
BATPRG Result
00 Battery switchover enabled on low V
DD
01 Battery switchover enabled on low V
DD
and low V
DCIN
1X1 Battery switchover disabled
1 X means don’t care.
Table 20. Peripheral Configuration SFR (PERIPH, Address 0xF4)
Bit Mnemonic Default Description
7 RX2FLAG 0 If set, indicates that an RxD2 edge event has triggered wake-up from PSM2.
6 VSWSOURCE 1 Indicates the power supply that is internally connected to V
SWOUT
.
0 = V
SWOUT
is connected to V
BAT
.
1 = VSWOUT is connected VDD.
5 VDD_OK 1 If set, indicates that the V
DD
power supply is ready for operation.
4 PLL_FLT 0 If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLLACK bit (Bit 7) in the start
ADC measurement SFR (ADCGO, Address 0xD8) to acknowledge the fault and clear the PLL_FLT bit
(see Table 52).
3 REF_BAT_EN 0 Set this bit to enable the internal voltage reference in PSM2 mode. This bit should be set if LCD is on
in the PSM1 and PSM2 modes.
2 Reserved 0 This bit must be kept at 0 for proper operation.
[1:0] RXPROG 0 Controls the function of the P0.7/SS/T1/RxD2 pin.
RXPROG Result
00 GPIO
01 RxD2 with wake-up disabled
11 RxD2 with wake-up enabled
Table 21. Power Management Interrupt Enable SFR (IPSME, Address 0xEC)
Bit Mnemonic Default Description
7 EPSR 0 Enables a PSM interrupt when the power supply restored interrupt flag (FPSR) is set.
6 Reserved 0 Reserved.
5 ESAG 0 Enables a PSM interrupt when the voltage SAG interrupt flag (FSAG) is set.
4 Reserved 0 This bit must be kept at 0 for proper operation.
3 EVADC 0 Enables a PSM interrupt when the V
DCIN
ADC monitor interrupt flag (FVADC) is set.
2 EBAT 0 Enables a PSM interrupt when the V
BAT
monitor interrupt flag (FBAT) is set.
1
EBSO
0
Enables a PSM interrupt when the battery switchover interrupt flag (FBSO) is set.
0 EVDCIN 0 Enables a PSM interrupt when the V
DCIN
monitor interrupt flag (FVDCIN) is set.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 30 of 155
Table 22. Scratch Pad 1 SFR (SCRATCH1, Address 0xFB)
Bit Mnemonic Default Description
[7:0] SCRATCH1 0 Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 23. Scratch Pad 2 SFR (SCRATCH2, Address 0xFC)
Bit Mnemonic Default Description
[7:0] SCRATCH2 0 Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 24. Scratch Pad 3 SFR (SCRATCH3, Address 0xFD)
Bit Mnemonic Default Description
[7:0] SCRATCH3 0 Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 25. Scratch Pad 4 SFR (SCRATCH4, Address 0xFE)
Bit Mnemonic Default Description
[7:0] SCRATCH4 0 Value can be written/read in this register. This value is maintained in all the power saving modes.
Clearing the Scratch Pad Registers (SCRATCH1, Address 0xFB to SCRATCH4, Address 0xFE)
Note that these scratch pad registers are cleared only when the device loses VDD and VBAT.
Table 26. Power Control SFR (POWCON, Address 0xC5)
Bit Mnemonic Default Description
7 Reserved 1 Reserved.
6 METER_OFF 0 Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if metering
functions are not needed in PSM0 mode.
5 Reserved 0 This bit should be kept at 0 for proper operation.
4 COREOFF 0 Set this bit to shut down the core and enter PSM2 mode if in the PSM1 operating mode.
3 Reserved 0 Reserved.
[2:0] CD 010 Controls the core clock frequency, f
CORE
. f
CORE
= 4.096 MHz/2CD.
CD Result (f
CORE
in MHz)
000 4.096
001 2.048
010 1.024
011
0.512
100 0.256
101 0.128
110
0.064
111 0.032
Writing to the Power Control SFR (POWCON, Address 0xC5)
Writing data to the power control SFR (POWCON, Address 0xC5) involves writing 0xA7 into the key SFR (KYREG, Address 0xC1),
which is described in Table 126, followed by a write to the POWCON SFR. For example,
MOV KYREG,#0A7h ;Write KYREG to 0xA7 to get write access to the POWCON SFR
MOV POWCON,#10h ;Shut down the core
Data Sheet ADE5169/ADE5569
Rev. E | Page 31 of 155
POWER SUPPLY ARCHITECTURE
The ADE5169/ADE5569 have two power supply inputs, VDD and
VBAT. They require only a single 3.3 V power supply at VDD for full
operation. A battery backup, or secondary power supply, with a
maximum of 3.7 V can be connected to the VBAT input. Internally,
the ADE5169/ADE5569 connect VDD or VBAT to VSWOUT, which is
used to derive power for the ADE5169/ADE5569 circuitry. The
VSWOUT output pin reflects the voltage at the internal power supply
(VSWOUT) and has a maximum output current of 6 mA. This pin can
also be used to power a limited number of peripheral components.
The 2.5 V analog supply (VINTA) and the 2.5 V supply for the core
logic (VINTD) are derived by on-chip linear regulators from VSWOUT.
Figure 32 shows the ADE5169/ADE5569 power supply
architecture.
POWER SUPPLY
MANAGEMENT
LDO V
INTD
LDO V
INTA
ADC
V
SW
ADC
SCRATCH PAD LCD RTC
TEMPERATURE ADC 3.3V
MCU
ADE
SPI/I
2
C
UART
2.5V
V
DCIN
V
DD
V
BAT
V
SWOUT
BCTRL
07411-011
Figure 32. Power Supply Architecture
The ADE5169/ADE5569 provide automatic battery switchover
between VDD and VBAT based on the voltage level detected at VDD
or VDCIN. In addition, the BCTRL input can be used to trigger a
battery switchover. The conditions for switching VSWOUT from VDD
to VBAT and back to VDD are described in the Battery Switchover
section. VDCIN is an input pin that can be connected to a dc signal of
0 V to 3.3 V. This input is intended for power supply supervisory
purposes and does not provide power to the ADE5169/ADE5569
circuitry (see the Battery Switchover section).
BATTERY SWITCHOVER
The ADE5169/ADE5569 monitor VDD, VBAT, and VDCIN.
Automatic battery switchover from VDD to VBAT can be
configured based on the status of the VDD, VDCIN, or BCTRL pin.
Battery switchover is enabled by default. Setting Bit 1 in the
battery switchover configuration SFR (BATPR, Address 0xF5)
disables battery switchover so that VDD is always connected to
VSWOUT (see Table 19). The source of VSWOUT is indicated by Bit 6
in the peripheral configuration SFR (PERIPH, Address 0xF4),
which is described in Table 20. Bit 6 is set when VSWOUT is con-
nected to VDD and cleared when VSWOUT is connected to VBAT.
The battery switchover functionality provided by the ADE5169/
ADE5569 allows a seamless transition from VDD to VBAT. An
automatic battery switchover option ensures a stable power
supply to the ADE5169/ADE5569, as long as the external
battery voltage is above 2.75 V.
It allows continuous code execution even while the internal power
supply is switching from VDD to VBAT and back. Note that the energy
metering ADCs are not available when VBAT is used for VSWOUT.
Power supply management (PSM) interrupts can be enabled to
indicate when battery switchover occurs and when the VDD power
supply is restored (see the Power Supply Management (PSM)
Interrupt section).
Switching from VDD to VBAT
The following three events switch the internal power supply
(VSWOUT) from VDD to VBAT:
• VDCIN < 1.2 V. When VDCIN falls below 1.2 V, V SWOUT switches
from VDD to VBAT. This event is enabled when the BATPRG
bits (Bits[1:0]) in the battery switchover configuration SFR
(BATPR, Address 0xF5) are set to 0b01.
• VDD < 2.75 V. When VDD falls below 2.75 V, VSWOUT switches
from VDD to VBAT. This event is enabled when the BATPRG
bits in the BATPR SFR are cleared.
• Falling edge on BCTRL. When the battery control pin,
BCTRL, goes low, VSWOUT switches from VDD to VBAT. This
external switchover signal can trigger a switchover to VBAT
at any time. Setting the INT1PRG bits (Bits[3:1]) to 0bX01 in
the interrupt pins configuration SFR (INTPR, Address 0xFF)
enables the BCTRL pin (see Table 17).
Switching from VBAT to VDD
To switch VSWOUT from VBAT to VDD, all of the following events
must be true:
• VDD > 2.75 V. VSWOUT switches back to VDD after VDD remains
above 2.75 V.
• VDCIN > 1.2 V and VDD > 2.75 V. If the low VDCIN condition
is enabled, VSWOUT switches to VDD after VDCIN remains
above 1.2 V and VDD remains above 2.75 V.
• Rising edge on BCTRL. If the battery control pin is enabled,
VSWOUT switches back to VDD after BCTRL is high, and the
first or second bullet point is satisfied.
POWER SUPPLY MANAGEMENT (PSM) INTERRUPT
The power supply management (PSM) interrupt alerts the 8052
core of power supply events. The PSM interrupt is disabled by
default. Setting Bit 1 (EPSM) in the Interrupt Enable and Priority 2
SFR (IEIP2, Address 0xA9) enables the PSM interrupt (see
Table 83).
The power management interrupt enable SFR (IPSME,
Address 0xEC) controls the events that result in a PSM interrupt
(see Table 21).
Figure 33 illustrates how the PSM interrupt vector is shared among
the PSM interrupt sources. The PSM interrupt flags are latched
and must be cleared by writing to the power management interrupt
flag SFR (IPSMF, Address 0xF8), as described in Table 18.
ADE5169/ADE5569
Rev. E | Page 32 of 155
EPSR
FPSR
ESAG
FSAG
EVADC
FVADC
EBAT
FBAT
EBSO
FBSO
EVDCIN
FVDCIN
FPSM
EPSM TRUE? PE NDING P S M
INTERRUPT
EPSR RESERVED ESAG RESERVED EVADC EBAT EBSO EVDCIN
FPSR FPSM FSAG RESERVED FVADC FBAT FBSO FVDCIN
PS2 PTI ES2 PSI EADE ETI EPSM ESI
IP SME ADDR. 0xEC
IPSMF ADDR. 0xF8
IE IP2 ADDR. 0xA9
NOT I NV OLVED IN P S M INTERRUP T SIG NAL CHAI N
07411-012
Figure 33. Power Supply Management Interrupt Sources
Battery Switchover and Power Supply Restored
PSM Interrupt
The ADE5169/ADE5569 can be configured to generate a PSM
interrupt when the source of VSWOUT changes from VDD to VBAT,
indicating battery switchover. Setting the EBSO bit (Bit 1) in the
power management interrupt enable SFR (IPSME, Address 0xEC)
enables this event to generate a PSM interrupt (see Table 21).
The ADE5169/ADE5569 can also be configured to generate an
interrupt when the source of VSWOUT changes from VBAT to VDD,
indicating that the VDD power supply has been restored. Setting
the EPSR bit (Bit 7) in the power management interrupt enable
SFR (IPSME, Address 0xEC) enables this event to generate a PSM
interrupt.
The flags in the IPSMF SFR for these interrupts, FBSO (Bit 1)
and FPSR (Bit 7), are set regardless of whether the respective
enable bits are set. The battery switchover and power supply restore
event flags (FBSO and FPSR) are latched. These events must be
cleared by writing 0 to these bits. The VSWSOURCE bit (Bit 6) in
the peripheral configuration SFR (PERIPH, Address 0xF4) tracks
the source of VSWOUT. The bit is set when VSWOUT is connected
to VDD and cleared when VSWOUT is connected to VBAT.
VDCINADC PSM Interrupt
The ADE5169/ADE5569 can be configured to generate a PSM
interrupt when VDCIN changes magnitude by more than a config-
urable threshold. This threshold is set in the temperature and
supply delta SFR (DIFFPROG, Address 0xF3), as described in
Table 51. See the External Voltage Measurement section for more
information. Setting the EVADC bit (Bit 3) in the power manage-
ment interrupt enable SFR (IPSME, Address 0xEC) enables this
event to generate a PSM interrupt.
The VDCIN voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to check
the change in VDCIN. Conversions can also be initiated by writing to
the start ADC measurement SFR (ADCGO, Address 0xD8), as
described in Table 52. The FVADC flag indicates when a VDCIN
measurement is ready. See the External Voltage Measurement
section for details on how VDCIN is measured.
VBAT Monitor PSM Interrupt
The VBAT voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to check
the change in VBAT. The FBAT bit (Bit 2 in the IPSMF SFR) is
set when the battery level is lower than the threshold set in the
battery detection threshold SFR (BATVTH, Address 0xFA),
described in Table 53; or when a new measurement is ready in
the battery ADC value SFR (BATADC, Address 0xDF), described
in Table 55. See the Battery Measurement section for more infor-
mation. Setting the EBAT bit (Bit 2) in the power management
interrupt enable SFR (IPSME, Address 0xEC) enables this event
to generate a PSM interrupt.
VDCIN Monitor PSM Interrupt
The VDCIN voltage is monitored by a comparator. The FVDCIN
bit (Bit 0) in the power management interrupt flag SFR (IPSMF,
Address 0xF8) is set when the VDCIN input level is lower than 1.2 V.
Setting the EVDCIN bit (Bit 0) in the IPSME SFR enables this
event to generate a PSM interrupt. This event, which is associated
with the SAG monitoring, can be used to detect that a power
supply (VDD) is compromised and to trigger further actions prior to
initiating a switch from VDD to VBAT.
Data Sheet ADE5169/ADE5569
Rev. E | Page 33 of 155
SAG Monitor PSM Interrupt
The ADE5169/ADE5569 energy measurement DSP monitors
the ac voltage input at the VP and VN input pins. The SAGLVL
register (Address 0x14) is used to set the threshold for a line
voltage SAG event. The FSAG bit (Bit 5) in the power management
interrupt flag SFR (IPSMF, Address 0xF8) is set if the line voltage
stays below the level set in the SAGLVL register for the number
of line cycles set in the SAGCYC register (Address 0x13). See the
Line Voltage SAG Detection section for more information. Setting
the ESAG bit (Bit 5) in the power management interrupt enable
SFR (IPSME, Address 0xEC) enables this event to generate a
PSM interrupt.
USING THE POWER SUPPLY FEATURES
In an energy meter application, the 3.3 V power supply (VDD) is
typically generated from the ac line voltage and regulated to 3.3 V
by a voltage regulator IC. The preregulated dc voltage, typically
5 V to 12 V, can be connected to VDCIN through a resistor divider.
A 3.6 V battery can be connected to VBAT. Figure 34 shows how
the ADE5169/ADE5569 power supply inputs are set up in this
application.
Figure 35 shows the sequence of events that occurs if the main
power supply generated by the PSU starts to fail in the power
meter application shown in Figure 34. The SAG detection can
provide the earliest warning of a potential problem on VDD. When a
SAG event occurs, user code can be configured to back up data
and prepare for battery switchover, if desired. The relative spacing
of these interrupts depends on the design of the power supply.
Figure 36 shows the sequence of events that occurs if the main
power supply starts to fail in the power meter application shown
in Figure 34, with battery switchover on low VDCIN or low VDD
enabled.
Finally, the transition between VDD and VBAT and the different
power supply modes (see the Operating Modes section) are
represented in Figure 37 and Figure 38.
VOLTAGE
SUPERVISORY
POWER SUPPLY
MANAGEMENT
IPSMF SFR
(ADDR. 0xF8)
V
SW
V
BAT
V
SWOUT
V
DD
58
61
60
VOLTAGE
SUPERVISORY
64
V
DCIN
3.3V
REGULATOR
5V TO 12V DC
PSU
50
SAG
DETECTION
49
45
BCTRL
V
P
V
N
(240V, 220V, 110V TYPICAL)
AC INPUT
07411-013
Figure 34. Power Supply Management for Energy Meter Application
Table 27. Power Supply Event Timing Operating Modes
Parameter Time Description
t1 10 ns min Time between when VDCIN goes below 1.2 V and when FVDCIN is raised.
t2 10 ns min Time between when VDD falls below 2.75 V and when battery switchover occurs.
t3 30 ms typ Time between when VDCIN falls below 1.2 V and when battery switchover occurs if VDCIN is enabled to cause
battery switchover.
t4 130 ms typ Time between when power supply restore conditions are met (VDCIN > 1.2 V and VDD > 2.75 V if the BATPRG
bits = 0b01, or VDD > 2.75 V if the BATPRG bits = 0b00) and when VSWOUT switches to VDD.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 34 of 155
t
1
t
2
VDD
VDCIN
V
P –
V
N
2.75V
1.2V
SAG LEVEL TRIP POINT
SAGCYC = 1
SAG EVENT
(FSAG = 1)
VDCIN EVENT
(FVDCIN = 1)
IF SWITCHOVER ON LOW V
DD IS ENABLED,
AUTOMATIC BATTERY SWITCHOVER OCCURS.
VSWOUT IS CONNECTED TO VBAT.
BSO EVENT
(FBSO = 1)
07411-014
Figure 35. Power Supply Management Interrupts and Battery Switchover with Only VDD Enabled for Battery Switchover
t
1
t
3
V
DD
V
DCIN
V
P
–
V
N
2.75V
1.2V
SAG LEVEL TRIP POINT
SAGCYC = 1
SAG EVENT
(FSAG = 1)
V
DCIN
EVENT
(FVDCIN = 1)
IF SWITCHOVER ON LOW V
DCIN
IS
ENABLED, AUTOMATIC BATTERY
SWITCHOVER OCCURS. V
SWOUT
IS CONNECTED TO V
BAT
.
BSO EVENT
(FBSO = 1)
07411-015
Figure 36. Power Supply Management Interrupts and Battery Switchover with VDD or VDCIN Enabled for Battery Switchover
Data Sheet ADE5169/ADE5569
Rev. E | Page 35 of 155
V
P
− V
N
SAG LEVEL
TRIP POINT
SAG EVENT
V
DCIN
1.2V
30ms 130ms
V
DCIN
EVENT
V
DCIN
EVENT
V
BAT
V
DD
2.75V
V
SWOUT
BATTERY SWITCH
ENABLED ON
LOW V
DCIN
V
SWOUT
BATTERY SWITCH
ENABLED ON
LOW V
DD
PSM0 PSM0
PSM0 PSM0
PSM1 OR PSM2
PSM1 OR PSM2
07411-016
Figure 37. Power Supply Management Transitions Between Modes
ADE5169/ADE5569 Data Sheet
Rev. E | Page 36 of 155
OPERATING MODES
PSM0 (NORMAL MODE)
In PSM0 mode, or normal operating mode, VSWOUT is connected to
VDD. All of the analog circuitry and digital circuitry powered by
VINTD and VINTA are enabled by default. In normal mode, the default
clock frequency, fCORE, which is established during a power-on
reset or software reset, is 1.024 MHz.
PSM1 (BATTERY MODE)
In PSM1 mode, or battery mode, VSWOUT is connected to VBAT.
In this operating mode, the 8052 core and all of the digital circuitry
are enabled by default. The analog circuitry for the ADE energy
metering DSP powered by VINTA is disabled. This analog circuitry
automatically restarts, and the switch to the VDD power supply
occurs when the VDD supply is greater than 2.75 V and the
PWRDN bit in the MODE1 register (Address 0x0B) is cleared
(see Table 33). The default fCORE for PSM1, established during
a power-on reset or software reset, is 1.024 MHz.
PSM2 (SLEEP MODE)
PSM2 mode is a low power consumption sleep mode for use in
battery operation. In this mode, VSWOUT is connected to VBAT. All
of the 2.5 V digital and analog circuitry powered through VINTA and
VINTD is disabled, including the MCU core, resulting in the
following:
The RAM in the MCU is no longer valid.
The program counter for the 8052, also held in volatile
memory, becomes invalid when the 2.5 V supply is shut
down. Therefore, the program does not resume from where
it left off but always starts from the power-on reset vector
when the ADE5169/ADE5569 exit PSM2 mode.
The 3.3 V peripherals (temperature ADC, VDCINADC, RTC, and
LCD) are active in PSM2 mode. They can be enabled or disabled
to reduce power consumption and are configured for PSM2
operation when the MCU core is active (see Table 29 for more
information about the individual peripherals and their PSM2
configuration). The ADE5169/ADE5569 remain in PSM2 mode
until an event occurs to wake them up.
In PSM2 mode, the ADE5169/ADE5569 provide four scratch pad
RAM SFRs that are maintained during this mode. These SFRs can
be used to save data from the PSM0 or PSM1 mode when entering
PSM2 mode (see Table 22 to Table 25).
In PSM2 mode, the ADE5169/ADE5569 maintain some SFRs
(see Table 28). The SFRs that are not listed in this table should
be restored when the device enters PSM0 or PSM1 mode from
PSM2 mode.
Table 28. SFRs Maintained in PSM2 Mode
I/O Configuration Power Supply Management RTC Peripherals LCD Peripherals
Interrupt pins configuration SFR
(INTPR, Address 0xFF);
see Table 17.
Battery detection threshold SFR
(BATVTH, Address 0xFA);
see Table 53.
RTC nominal compensation SFR
(RTCCOMP, Address 0xF6); see Table 132.
LCD Segment Enable 2 SFR
(LCDSEGE2, Address 0xED);
see Table 101.
Peripheral configuration SFR
(PERIPH, Address 0xF4);
see Table 20.
Battery switchover configuration
SFR (BATPR, Address 0xF5);
see Table 19.
RTC temperature compensation SFR
(TEMPCAL, Address 0xF7); see Table 133.
LCD Configuration Y SFR
(LCDCONY, Address 0xB1);
see Table 94.
Port 0 weak pull-up enable SFR
(PINMAP0, Address 0xB2);
see Table 162.
Battery ADC value SFR (BATADC,
Address 0xDF); see Table 55.
RTC configuration SFR (TIMECON,
Address 0xA1); see Table 128.
LCD Configuration X SFR
(LCDCONX, Address 0x9C);
see Table 92.
Port 1 weak pull-up enable SFR
(PINMAP1, Address 0xB3);
see Table 163.
Peripheral ADC strobe period SFR
(STRBPER, Address 0xF9);
see Table 50.
RTC Configuration 2 SFR (TIMECON2,
Address 0xA2); see Table 129.
LCD configuration SFR
(LCDCON, Address 0x95);
see Table 91.
Port 2 weak pull-up enable SFR
(PINMAP2, Address 0xB4);
see Table 164.
Temperature and supply delta
SFR (DIFFPROG, Address 0xF3);
see Table 51.
All indirectly accessible registers defined
in the RTC register list; see Table 134.
LCD clock SFR (LCDCLK,
Address 0x96); see Table 95.
Scratch Pad 1 SFR (SCRATCH1,
Address 0xFB); see Table 22.
VDCINADC value SFR (VDCINADC,
Address 0xEF); see Table 54.
Not applicable LCD segment enable SFR
(LCDSEGE, Address 0x97);
see Table 98.
Scratch Pad 2 SFR (SCRATCH2,
Address 0xFC); see Table 23.
Temperature ADC value SFR
(TEMPADC, Address 0xD7);
see Table 56.
Not applicable LCD pointer SFR (LCDPTR,
Address 0xAC); see Table 99.
Scratch Pad 3 SFR (SCRATCH3,
Address 0xFD); see Table 24.
Not applicable Not applicable LCD data SFR (LCDDAT,
Address 0xAE); see Table 100.
Scratch Pad 4 SFR (SCRATCH4,
Address 0xFE); see Table 25)
Not applicable Not applicable Not applicable
ADE5169/ADE5569 Data Sheet
Rev. E | Page 37 of 155
3.3 V PERIPHERALS AND WAKE-UP EVENTS
Some of the 3.3 V peripherals are capable of waking the ADE5169/
ADE5569 from PSM2 mode. The events that can cause the
ADE5169/ADE5569 to wake up from PSM2 mode are listed in
the wake-up event column in Table 29.
The interrupt flag associated with these events must be cleared
prior to executing instructions that put the ADE5169/ADE5569 in
PSM2 mode after wake-up.
Table 29. 3.3 V Peripherals and Wake-Up Events1
3.3 V
Peripheral
Wake-Up
Event
Wake-Up
Enable Bits Flag
Interrupt
Vector Comments
Temperature
ADC
∆T Maskable N/A N/A
The temperature ADC can wake up the ADE5169/ADE5569.
A pending interrupt is generated according to the description in
the Temperature Measurement section. This wake-up event can be
disabled by disabling temperature measurements in the
temperature and supply delta SFR (DIFFPROG, Address 0xF3) in
PSM2 mode. The temperature interrupt needs to be serviced and
acknowledged prior to entering PSM2 mode.
VDCINADC ΔV Maskable FVADC
(IPSMF[3])
IPSM The VDCIN measurement can wake up the ADE5169/ADE5569. The
FVADC flag, Bit 3 of the power manage-ment interrupt flag SFR
(IPSMF, Address 0xF8), is set according to the description in the
External Voltage Measurement section. This wake-up event can
be disabled by clearing the EVADC bit, Bit 3 in the power
management interrupt enable SFR (IPSME, Address 0xEC); see
Table 21. The FVADC flag needs to be cleared prior to entering
PSM2 mode.
Power Supply
Management
PSR Nonmaskable
FPSR
(IPSMF[7])
IPSM The ADE5169/ADE5569 wake up if the power supply is restored (if
VSWOUT switches to be connected to VDD). The VSWSOURCE flag,
Bit 6 of the peripheral configuration SFR (PERIPH, Address 0xF4), is
set to indicate that VSWOUT is connected to VDD.
RTC Interval Maskable
ITFLAG
(TIMECON[2])
IRTC The ADE5169/ADE5569 wake up after the programmable time
interval has elapsed. The RTC interrupt needs to be serviced and
acknowledged prior to entering PSM2 mode.
Alarm Maskable ALFLAG
(TIMECON[6])
IRTC An alarm can be set to wake the ADE5169/ADE5569 after the
desired amount of time. The RTC alarm is enabled by setting the
ALxxx_EN bits in the RTC Configuration 2 SFR (TIMECON2,
Address 0xA2). The RTC interrupt needs to be serviced and
acknowledged prior to entering PSM2 mode.
I/O Ports2 INT0 INT0PRG = 1
(INTPR[0])
N/A IE0
The edge of the interrupt is selected by the IT0 bit, Bit 0 in the
TCON SFR (TCON, Address 0x88). The IE0 flag, Bit 1 in the TCON
SFR, is not affected. The Interrupt 0 interrupt needs to be serviced
and acknowledged prior to entering PSM2 mode.
INT1 INT1PRG = 11x
(INTPR[3:1])
N/A IE1
The edge of the interrupt is selected by the IT1 bit, Bit 2 in the
TCON SFR (TCON, Address 0x88). The IE1 flag, Bit 3 in the TCON
SFR, is not affected. The Interrupt 1 interrupt needs to be
serviced and acknowledged prior to entering PSM2 mode.
Rx2 edge
RXPROG = 11
(PERIPH[1:0])
RX2FLAG
(PERIPH[7])
N/A An Rx edge event occurs if a rising or falling edge is detected
on the RxD2 line. The UART2 RxD flag needs to be cleared prior
to entering PSM2 mode.
External
Reset
Reset Nonmaskable N/A N/A If the RESET pin is brought low while the ADE5169/ADE5569 are
in PSM2 mode, they wake up to PSM1 mode.
LCD N/A N/A N/A N/A
The LCD can be enabled/disabled in PSM2 mode. The LCD data
memory remains intact.
Scratch Pad N/A N/A N/A N/A The four SCRATCHx registers remain intact in PSM2 mode.
1 N/A means not applicable.
2 All I/O pins are treated as inputs. The weak pull-up on each I/O pin can be disabled individually in the Port 0 weak pull-up enable SFR (PINMAP0, Address 0xB2), Port 1
weak pull-up enable SFR (PINMAP1, Address 0xB3), and Port 2 weak pull-up enable SFR (PINMAP2, Address 0xB4) to decrease current consumption. The interrupts can
be enabled or disabled.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 38 of 155
TRANSITIONING BETWEEN OPERATING MODES
The operating mode of the ADE5169/ADE5569 is determined
by the power supply connected to VSWOUT. Therefore, changes in
the power supply, such as when VSWOUT switches from VDD to
VBAT or when VSWOUT switches to VDD, alter the operating mode.
This section describes events that change the operating mode.
Automatic Battery Switchover (PSM0 to PSM1)
If any of the enabled battery switchover events occurs (see the
Battery Switchover section), VSWOUT switches to VBAT. This switch-
over results in a transition from PSM0 to PSM1 operating mode.
When battery switchover occurs, the analog circuitry used in
the ADE energy measurement DSP is disabled. To reduce power
consumption, user code can initiate a transition to PSM2 mode.
Entering Sleep Mode (PSM1 to PSM2)
To reduce power consumption when VSWOUT is connected to VBAT,
user code can initiate sleep mode, PSM2, by setting Bit 4 in the
power control SFR (POWCON, Address 0xC5) to shut down the
MCU core. Events capable of waking the MCU can be enabled
(see the 3.3 V Peripherals and Wake-Up Events section).
Servicing Wake-Up Events (PSM2 to PSM1)
The ADE5169/ADE5569 may need to wake up from PSM2
mode to service wake-up events (see the 3.3 V Peripherals and
Wake-Up Events section). PSM1 code execution begins at the
power-on reset vector. After servicing the wake-up event, the
ADE5169/ADE5569 can return to PSM2 mode by setting Bit 4 in
the power control SFR (POWCON, Address 0xC5) to shut down
the MCU core.
Automatic Switch to VDD (PSM2 to PSM0)
If the conditions to switch VSWOUT from VBAT to VDD occur (see the
Battery Switchover section), the operating mode switches to PSM0
mode. When this switch occurs, the MCU core and the analog
circuitry used in the ADE energy measurement DSP automatically
restart. PSM0 code execution begins at the power-on reset vector.
Automatic Switch to VDD (PSM1 to PSM0)
If the conditions to switch VSWOUT from VBAT to VDD occur (see
the Battery Switchover section), the operating mode switches
to PSM0 mode. When this switch occurs, the analog circuitry
used in the ADE energy measurement DSP automatically restarts.
Note that code execution continues normally. A software reset
can be performed to start PSM0 code execution at the power-on
reset vector.
USING THE POWER MANAGEMENT FEATURES
Because program flow is different for each operating mode, the
status of VSWOUT must be known at all times. The VSWSOURCE bit
in the peripheral configuration SFR (PERIPH, Address 0xF4)
indicates the power supply to which VSWOUT is connected (see
Table 20). This bit can be used to control program flow on wake-
up. Because code execution always starts at the power-on reset
vector, Bit 6 of the PERIPH SRF can be tested to determine which
power supply is being used and to branch to normal code execution
or to wake up event code execution. Power supply events can also
occur when the MCU core is active. To be aware of the events that
change what VSWOUT is connected to, use the following guidelines:
• Enable the battery switchover interrupt (EBSO)
if VSWOUT = VDD at power-up.
• Enable the power supply restored interrupt (EPSR)
if VSWOUT = VBAT at power-up.
An early warning that battery switchover is about to occur is
provided by SAG detection and, possibly, by low VDCIN detection
(see the Battery Switchover section).
For a user controlled battery switchover, enable automatic battery
switchover on low VDD only. Next, enable the low VDCIN event to
generate the PSM interrupt. When a low VDCIN event occurs, start
data backup. Upon completion of the data backup, enable battery
switchover on low VDCIN. Battery switchover occurs 30 ms later.
PSM1
BATTERY MODE
V
SWOUT
IS CONNECTED TO V
BAT
PSM0
NORMAL MO DE
V
SWOUT
IS CONNECTED TO V
DD
PSM2
SLEEP MODE
V
SWOUT
IS CONNECTED TO V
BAT
POWER SUPPLY
RESTORED
AUTOMATIC BATTERY
SWITCHOVER
WAKE-UP
EVENT
USER CO DE DIRECTS MCU
TO SHUT DOW N CORE AFTER
SERVICING A WAKE-UP EVENT
POWER SUPPLY
RESTORED
07411-017
Figure 38. Transitioning Between Operating Modes
Data Sheet ADE5169/ADE5569
Rev. E | Page 39 of 155
ENERGY MEASUREMENT
The ADE5169/ADE5569 offer a fixed function, energy
measurement, digital processing core that provides all the
information needed to measure energy in single-phase energy
meters. The device provides two ways to access the energy
measurements: direct access through SFRs for time sensitive
information and indirect access through address and data SFRs
for the majority of energy measurements. The Irms, Vrms, interrupt,
and waveform registers are readily available through the SFRs, as
shown in Table 31. Other energy measurement information is
mapped to a page of memory that is accessed indirectly through
the MADDPT, MDATL, MDATM, and MDATH SFRs. The
address and data SFRs act as pointers to the energy measurement
internal registers.
ACCESS TO ENERGY MEASUREMENT SFRs
Access to the energy measurement SFRs is achieved by reading
or writing to the SFR addresses detailed in Table 31. The internal
data for the MIRQx SFRs is latched byte by byte into the SFR
when the SFR is read.
The WAV1x, WAV2x, VRMSx, and IRMSx registers are all 3-byte
SFRs. The 24-bit data is latched into these SFRs when the high
byte is read. Reading the low or medium byte before the high
byte results in reading the data from the previous latched sample.
Sample code to read the VRMSx register is as follows:
MOV R1, VRMSH //latches data in VRMSH,
VRMSM, and VRMSL SFRs
MOV R2, VRMSM
MOV R3, VRMSL
ACCESS TO INTERNAL ENERGY MEASUREMENT
REGISTERS
Access to the internal energy measurement registers is achieved
by writing to the energy measurement pointer address SFR
(MADDPT, Address 0x91). This SFR selects the energy measure-
ment register to be accessed and determines if a read or a write
is performed (see Table 30).
Table 30. Energy Measurement Pointer Address SFR
(MADDPT, Address 0x91)
Bit Description
7 1 = write
0 = read
[6:0]
Energy measurement internal register address
Writing to the Internal Energy Measurement Registers
When Bit 7 of the energy measurement pointer address SFR
(MADDPT, Address 0x91) is set, the contents of the MDATx SFRs
(MDATL, MDATM, and MDATH) are transferred to the internal
energy measurement register designated by the address in the
MADDPT SFR. If the internal register is one byte long, only the
MDATL SFR contents are copied to the internal register. The
MDATM SFR and MDATH SFR contents are ignored.
The energy measurement core functions with an internal clock of
4.096 MHz∕5 or 819.2 kHz. Because the 8052 core functions with
another clock, 4.096 MHz∕2CD, synchronization between the two
clock environments when CD = 0 or 1 is an issue. When data is
written to the internal energy measurement registers, a small wait
period needs to be implemented before another read or write to
these registers can take place.
Sample code to write 0x0155 to the 2-byte SAGLVL register,
located at Address 0x14 in the energy measurement memory
space, is as follows:
MOV MDATM,#01h
MOV MDATL,#55h
MOV MADDPT,#SAGLVL_W (Address 0x94)
MOV A,#05h
DJNZ ACC,$
;Next write or read to energy
measurement SFR can be done after this.
Reading the Internal Energy Measurement Registers
When Bit 7 of energy measurement pointer address SFR
(MADDPT, Address 0x91) is cleared, the contents of the inter-
nal energy measurement register designated by the address in
MADDPT are transferred to the MDATx SFRs. If the internal
register is one byte long, only the MDATL SFR contents are
updated with a new value. The MDATM SFR and MDATH SFR
contents are reset to 0x00.
The energy measurement core functions with an internal clock
of 4.096 MHz∕5 or 819.2 kHz. Because the 8052 core functions
with another clock, 4.096 MHz∕2CD, synchronization between
the two clock environments is an issue when CD = 0 or CD = 1.
When data is read from the internal energy measurement registers,
a small wait period needs to be implemented before the MDATx
SFRs are transferred to another SFR.
Sample code to read the peak voltage in the 2-byte VPKLVL
register, located at Address 0x16, into the data pointer is as
follows:
MOV MADDPT,#VPKLVL_R (Address 0x16)
MOV A,#05h
DJNZ ACC,$
MOV DPH,MDATM
MOV DPL,MDATL
ADE5169/ADE5569 Data Sheet
Rev. E | Page 40 of 155
Table 31. Energy Measurement SFRs
Address R/W Mnemonic Description
0x91 R/W MADDPT Energy measurement pointer address.
0x92 R/W MDATL Energy measurement pointer data LSB.
0x93 R/W MDATM Energy measurement pointer data middle byte.
0x94 R/W MDATH Energy measurement pointer data MSB.
0xD1 R VRMSL Vrms measurement LSB.
0xD2 R VRMSM Vrms measurement middle byte.
0xD3 R VRMSH Vrms measurement MSB.
0xD4 R IRMSL Irms measurement LSB.
0xD5 R IRMSM Irms measurement middle byte.
0xD6 R IRMSH Irms measurement MSB.
0xD9 R/W MIRQENL Energy measurement interrupt enable LSB.
0xDA R/W MIRQENM Energy measurement interrupt enable middle byte.
0xDB R/W MIRQENH Energy measurement interrupt enable MSB.
0xDC R/W MIRQSTL Energy measurement interrupt status LSB.
0xDD R/W MIRQSTM Energy measurement interrupt status middle byte.
0xDE R/W MIRQSTH Energy measurement interrupt status MSB.
0xE2 R WAV1L Selection 1 sample LSB.
0xE3 R WAV1M Selection 1 sample middle byte.
0xE4 R WAV1H Selection 1 sample MSB.
0xE5 R WAV2L Selection 2 sample LSB.
0xE6 R WAV2M Selection 2 sample middle byte.
0xE7 R WAV2H Selection 2 sample MSB.
07411-117
×1, ×2, ×4,
×8, ×16
ADC
IPA
IN
PGA1
I
{GAIN[2:0]}
HPF
ADC
IPB
PGA1
HPF
IBGAIN[11:0]
ADC
DFC
MULTIPLIER
INTEGRATOR
WATTOS[15:0]
VAGAIN[11:0]
VADIV[7:0]
IRMSOS[11:0]
VRMSOS[11:0]
WGAIN[11:0]
dt
METERING SFRs
VN
VP
PGA2
CF1
WDIV[7:0]
%%
Ф
π
2
VARDIV[7: 0]
%
VAROS[15:0]
VARG AI N[ 11 :0 ]
DFC
CF2NUM[15:0]
CF2DEN[15:0]
CF1DEN[15:0]
CF1NUM[15:0]
CF2
HPF
HPF
LPF1
LPF3
LPF3
LPF2
LPF2
LPF2
x
2
|X|
PHCAL[7:0]
Figure 39. ADE5169 Energy Metering Block Diagram
Data Sheet ADE5169/ADE5569
Rev. E | Page 41 of 155
07411-100
×1, ×2, ×4,
×8, ×16
ADC
IPA
IN
PGA1
I
{GAIN[2:0]}
HPF
ADC
DFC
MULTIPLIER
INTEGRATOR
WATTOS[15:0]
VAGAIN[11:0]
VADIV[7:0]
IRMSOS[11:0]
VRMSOS[11:0]
dt
MET ERING S FRs
VN
VPPGA2
CF1
WDIV[7:0]
%%
Ф
π
2
VARDIV[7:0]
%
VAROS[15:0]
VARGAIN[11:0]
DFC
CF2NUM[15:0]
CF2DEN[15:0]
CF1DEN[15:0]
CF1NUM[15:0]
CF2
HPF
HPF
LPF1
LPF3
LPF3
LPF2
LPF2
LPF2
x2
PHCAL[7:0]
|X|
WGAIN[11:0]
Figure 40. ADE5569 Energy Metering Block Diagram
ADE5169/ADE5569 Data Sheet
Rev. E | Page 42 of 155
ENERGY MEASUREMENT REGISTERS
Table 32. Energy Measurement Register List
Address
MADDPT[6:0] Mnemonic R/W
Length
(Bits)
Signed/
Unsigned Default Description
0x01 WATTHR R 24 S 0 Reads the Wh accumulator without reset.
0x02 RWAT THR R 24 S 0 Reads the Wh accumulator with reset.
0x03 LWATTHR R 24 S 0 Reads the Wh accumulator synchronous to line cycle.
0x04 VARHR R 24 S 0 Reads the varh accumulator without reset.
0x05 RVARHR R 24 S 0 Reads the varh accumulator with reset.
0x06 LVARHR R 24 S 0 Reads the varh accumulator synchronous to line cycle.
0x07 VAHR R 24 S 0 Reads VAh accumulator without reset. If the VARMSCFCON bit in the
MODE2 register (Address 0x0C) is set, this register accumulates I
rms
.
0x08 RVAHR R 24 S 0 Reads VAh accumulator with reset. If the VARMSCFCON bit in the
MODE2 register (Address 0x0C) is set, this register accumulates I
rms
.
0x09 LVAHR R 24 S 0 Reads VAh accumulator synchronous to line cycle. If the VARMSCFCON
bit in the MODE2 register (Address 0x0C) is set, this register accumulates
I
rms
.
0x0A PER_FREQ R 16 U 0 Reads line period or frequency register, depending on MODE2 register.
0x0B MODE1 R/W 8 U 0x06 Sets basic configuration of energy measurement (see Table 33).
0x0C MODE2 R/W 8 U 0x40 Sets basic configuration of energy measurement (see Table 34).
0x0D WAVMODE R/W 8 U 0 Sets configuration of Waveform Sample 1 and Waveform Sample 2
(see Table 35).
0x0E NLMODE R/W 8 U 0 Sets level of energy no load thresholds (see Table 36).
0x0F ACCMODE R/W 8 U 0 Sets configuration of watt and var accumulation and various tamper
alarms (see Table 37).
0x10 PHCAL R/W 8 S 0x40 Sets phase calibration register (see the Phase Compensation section).
0x11 ZXTOUT R/W 12 U 0xFFF Sets timeout for zero-crossing timeout detection (see the Zero-
Crossing Timeout section).
0x12 LINCYC R/W 16 U 0xFFFF Sets number of half-line cycles for LWATTHR, LVARHR, and LVAHR
accumulators.
0x13 SAGCYC R/W 8 U 0xFF Sets number of half-line cycles for SAG detection (see the Line Voltage
SAG Detection section).
0x14 SAGLVL R/W 16 U 0 Sets detection level for SAG detection (see the Line Voltage SAG
Detection section).
0x15 IPKLVL R/W 16 U 0xFFFF Sets peak detection level for current peak detection (see the Peak
Detection section).
0x16
VPKLVL
R/W
16
U
0xFFFF
Sets peak detection level for voltage peak detection (see the Peak
Detection section).
0x17 IPEAK R 24 U 0 Reads current peak level without reset (see the Peak Detection section).
0x18 RSTIPEAK R 24 U 0 Reads current peak level with reset (see the Peak Detection section).
0x19 VPEAK R 24 U 0 Reads voltage peak level without reset (see the Peak Detection section).
0x1A RSTVPEAK R 24 U 0 Reads voltage peak level with reset (see the Peak Detection section).
0x1B GAIN R/W 8 U 0 Sets PGA gain of analog inputs (see Table 38).
0x1C IBGAIN
1
R/W 12 S 0 Sets matching gain for I
PB
current input.
0x1D WGAIN R/W 12 S 0 Sets watt gain register.
0x1E VARGAIN R/W 12 S 0 Sets var gain register.
0x1F VAGAIN R/W 12 S 0 Sets VA gain register.
0x20
WAT TOS
R/W
16
S
0
Sets watt offset register.
0x21 VAROS R/W 16 S 0 Sets var offset register.
0x22 IRMSOS R/W 12 S 0 Sets current rms offset register.
0x23 VRMSOS R/W 12 S 0 Sets voltage rms offset register.
0x24 WDIV R/W 8 U 0 Sets watt energy scaling register.
0x25 VARDIV R/W 8 U 0 Sets var energy scaling register.
0x26 VADIV R/W 8 U 0 Sets VA energy scaling register.
0x27 CF1NUM R/W 16 U 0 Sets CF1 numerator register.
0x28 CF1DEN R/W 16 U 0x003F Sets CF1 denominator register.
Data Sheet ADE5169/ADE5569
Rev. E | Page 43 of 155
Address
MADDPT[6:0] Mnemonic R/W
Length
(Bits)
Signed/
Unsigned Default Description
0x29 CF2NUM R/W 16 U 0 Sets CF2 numerator register.
0x2A CF2DEN R/W 16 U 0x003F Sets CF2 denominator register.
0x2B MODE3 R/W 8 U 0 Enables zero-crossing outputs (see Table 39).
0x3B Reserved 0 This register must be set to its default value for proper operation.
0x3C Reserved 0x0300 This register must be set to its default value for proper operation.
0x3D CALMODE
1
R/W 8 U 0 Sets calibration mode (see Table 40).
0x3E Reserved 0 This register must be set to its default value for proper operation.
0x3F Reserved 0 This register must be set to its default value for proper operation.
1 This function is not available in the ADE5569.
ENERGY MEASUREMENT INTERNAL REGISTERS DETAILS
Table 33. Mode 1 Register (MODE1, Address 0x0B)
Bit Mnemonic Default Description
7
SWRST
0
Setting this bit resets all of the energy measurement registers to their default values.
6 DISZXLPF 0 Setting this bit disables the zero-crossing low-pass filter.
5 INTE 0 Setting this bit enables the digital integrator for use with a di/dt sensor.
4 SWAPBITS 0 Setting this bit swaps CH1 ADC and CH2 ADC.
3 PWRDN 0 Setting this bit powers down voltage and current ADCs.
2 DISCF2 1 Setting this bit disables Frequency Output CF2.
1 DISCF1 1 Setting this bit disables Frequency Output CF1.
0 DISHPF 0 Setting this bit disables the HPFs in voltage and current channels.
Table 34. Mode 2 Register (MODE2, Address 0x0C)
Bit Mnemonic Default Description
[7:6] CF2SEL 01 Configuration bits for CF2 output.
CF2SEL Result
00 CF2 frequency is proportional to active power
01 CF2 frequency is proportional to reactive power
1X
1
CF2 frequency is proportional to apparent power or I
rms
[5:4]
CF1SEL
00
Configuration bits for CF1 output.
CF1SEL Result
00 CF1 frequency is proportional to active power
01 CF1 frequency is proportional to reactive power
1X1 CF1 frequency is proportional to apparent power or I
rms
3 VARMSCFCON 0 Configuration bit for apparent power or Irms for CF1 and CF2 outputs and VA accumulation registers (VAHR,
RVAHR, and LVAHR). Note that CF1 cannot be proportional to VA if CF2 is proportional to I
rms
, and vice versa.
VARMSCFCON Result
0 If CF1SEL = 1X, CF1 is proportional to VA
If CF2SEL = 1X, CF2 is proportional to VA
1 If CF1SEL = 1X, CF1 is proportional to I
rms
If CF2SEL = 1X, CF2 is proportional to I
rms
2 ZXRMS 0 Logic 1 enables update of rms values synchronously to Voltage ZX.
1 FREQSEL 0 Configuration bit to select period or frequency measurement for the PER_FREQ register (Address 0x0A).
FREQSEL Result
0 The PER_FREQ register holds a period measurement
1 The PER_FREQ register holds a frequency measurement
0 WAVEN 0 When this bit is set, waveform sampling mode is enabled.
1 X means don’t care.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 44 of 155
Table 35. Waveform Mode Register (WAVMODE, Address 0x0D)
Bit Mnemonic Default Description
[7:5] WAV2SEL 000 Waveform Sample 2 selection for samples mode.
WAV2SEL Source
000 Current
001 Voltage
010 Active power multiplier output
011 Reactive power multiplier output
100 VA multiplier output
101 I
rms
LPF output (low 24-bit)
110, 111 Reserved
[4:2] WAV1SEL 000 Waveform Sample 1 selection for samples mode.
WAV1SEL Source
000 Current
001 Voltage
010 Active power multiplier output
011 Reactive power multiplier output
100 VA multiplier output
101
Irms LPF output (low 24-bit)
110, 111 Reserved
[1:0] DTRT 00 Waveform samples output data rate.
DTRT Update Rate (Clock = f
CORE
/5 = 819.2 kHz)
00 25.6 kSPS (clock/32)
01 12.8 kSPS (clock/64)
10 6.4 kSPS (clock/128)
11 3.2 kSPS (clock/256)
Table 36. No Load Configuration Register (NLMODE, Address 0x0E)
Bit Mnemonic Default Description
7
DISVARCMP
0
Setting this bit disables fundamental var gain compensation over line frequency.
6 IRMSNOLOAD 0 Logic 1 enables Irms no load threshold detection. The level is defined by the setting of the
VANOLOAD bits.
[5:4] VANOLOAD 00 Apparent power no load threshold.
VANOLOAD Result
00 No load detection disabled
01 No load detection enabled with threshold = 0.030% of full scale
10 No load detection enabled with threshold = 0.015% of full scale
11 No load detection enabled with threshold = 0.0075% of full scale
[3:2] VARNOLOAD 00 Reactive power no load threshold.
VARNOLOAD
Result
00
No load detection disabled
01 No load detection enabled with threshold = 0.015% of full scale
10 No load detection enabled with threshold = 0.0075% of full scale
11 No load detection enabled with threshold = 0.0037% of full scale
[1:0] APNOLOAD 00 Active power no load threshold.
APNOLOAD Result
00 No load detection disabled
01 No load detection enabled with threshold = 0.015% of full scale
10 No load detection enabled with threshold = 0.0075% of full scale
11 No load detection enabled with threshold = 0.0037% of full scale
Data Sheet ADE5169/ADE5569
Rev. E | Page 45 of 155
Table 37. Accumulation Mode Register (ACCMODE, Address 0x0F)
Bit Mnemonic Default Description
7 ICHANNEL
1
0 This bit indicates the current channel used to measure energy in antitampering mode.
0 = Channel A (I
PA
).
1 = Channel B (I
PB
).
6 FAULTSIGN
1
0 Configuration bit to select the event that triggers a fault interrupt.
0 = FAULTSIGN interrupt occurs when the device enters fault mode.
1 = FAULTSIGN interrupt occurs when the device enters normal mode.
5 VARSIGN 0 Configuration bit to select the event that triggers a reactive power sign interrupt.
If cleared to 0, a VARSIGN interrupt occurs when reactive power changes from positive to negative.
If set to 1, a VARSIGN interrupt occurs when reactive power changes from negative to positive.
4 APSIGN 0 Configuration bit to select the event that triggers an active power sign interrupt.
If cleared to 0, an APSIGN interrupt occurs when active power changes from positive to negative.
If set to 1, an APSIGN interrupt occurs when active power changes from negative to positive.
3 ABSVARM 0 Logic 1 enables absolute value accumulation of reactive power in energy register and pulse output.
2 SAVARM 0 Logic 1 enables reactive power accumulation depending on the sign of the active power.
If active power is positive, var is accumulated as it is.
If active power is negative, the sign of the var is reversed for the accumulation.
This accumulation mode affects both the var registers (VARHR, RVARHR, LVARHR) and the pulse
output when connected to the reactive measurement.
1 POAM 0 Logic 1 enables positive only accumulation of active power in energy register and pulse output.
0 ABSAM 0 Logic 1 enables absolute value accumulation of active power in energy register and pulse output.
1 This function is not available in the ADE5569.
Table 38. Gain Register (GAIN, Address 0x1B)
Bit Mnemonic Default Description
[7:5] PGA2 000 These bits define the voltage channel input gain.
PGA2
Result
000 Gain = 1
001 Gain = 2
010 Gain = 4
011 Gain = 8
100 Gain = 16
4 Reserved 0 Reserved.
3 CFSIGN_OPT 0 This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is implemented.
CFSIGN_OPT Result
0 Filtered power signal
1 On a per CF pulse basis
[2:0] PGA1 000 These bits define the current channel input gain.
PGA1
Result
000
Gain = 1
001 Gain = 2
010 Gain = 4
011 Gain = 8
100 Gain = 16
Table 39. Mode 3 Register (MODE3, Address 0x2B)
Bit Mnemonic Default Description
[7:2] Reserved 0 Reserved.
1 ZX1 0 Setting this bit enables the zero-crossing output signal on P1.2.
0
ZX2
0
Setting this bit enables the zero-crossing output signal on P0.5.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 46 of 155
Table 40. Calibration Mode Register (CALMODE, Address 0x3D)1
Bit Mnemonic Default Description
[7:6] Reserved 00 These bits must be kept at 0 for proper operation.
[5:4] SEL_I_CH 00 These bits define the current channel used for energy measurements.
SEL_I_CH Result
00 Current channel automatically selected by the tampering condition
01 Current channel connected to IPA
10 Current channel connected to IPB
11 Current channel automatically selected by the tampering condition
3 V_CH_SHORT 0 Logic 1 shorts the voltage channel to ground.
2 I_CH_SHORT 0 Logic 1 shorts the current channel to ground.
[1:0] Reserved 00 These bits must be kept at 0 for proper operation.
1 This register is not available in the ADE5569.
INTERRUPT STATUS/ENABLE SFRS
Table 41. Interrupt Status 1 SFR (MIRQSTL, Address 0xDC)
Bit Interrupt Flag Description
7 ADEIRQFLAG
This bit is set if any of the ADE status flags that are enabled to generate an ADE interrupt is set. This bit is
automatically cleared when all of the enabled ADE status flags are cleared.
6 Reserved Reserved.
5 FAULTSIGN1 Logic 1 indicates that the fault mode has changed according to the configuration of the ACCMODE register.
4 VARSIGN Logic 1 indicates that the reactive power sign has changed according to the configuration of the ACCMODE register.
3 APSIGN Logic 1 indicates that the active power sign has changed according to the configuration of the ACCMODE register.
2 VANOLOAD
Logic 1 indicates that an interrupt has been caused by apparent power no load detection. This interrupt is also
used to reflect that the device is entering the Irms no load mode.
1 RNOLOAD Logic 1 indicates that an interrupt has been caused by reactive power no load detection.
0 APNOLOAD Logic 1 indicates that an interrupt has been caused by active power no load detection.
1 This function is not available in the and ADE5569.
Table 42. Interrupt Status 2 SFR (MIRQSTM, Address 0xDD)
Bit Interrupt Flag Description
7 CF2 Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if the CF2 pulse output is not
enabled by clearing Bit 2 of the MODE1 register.
6 CF1 Logic 1 indicates that a pulse on CF1 has been issued. The flag is set even if the CF1 pulse output is not
enabled by clearing Bit 1 of the MODE1 register.
5 VAEOF Logic 1 indicates that the VAHR register has overflowed.
4 REOF Logic 1 indicates that the VARHR register has overflowed.
3 AEOF Logic 1 indicates that the WATTHR register has overflowed.
2 VAEHF Logic 1 indicates that the VAHR register is half full.
1 REHF Logic 1 indicates that the VARHR register is half full.
0 AEHF Logic 1 indicates that the WATTHR register is half full.
Table 43. Interrupt Status 3 SFR (MIRQSTH, Address 0xDE)
Bit Interrupt Flag Description
7 RESET Indicates the end of a reset (for both software and hardware reset).
6 Reserved Reserved.
5 WFSM Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7).
4 PKI Logic 1 indicates that the current channel has exceeded the IPKLVL value.
3 PKV Logic 1 indicates that the voltage channel has exceeded the VPKLVL value.
2 CYCEND Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles.
1 ZXTO Logic 1 indicates that no zero crossing on the line voltage occurred for the last ZXTOUT half-line cycles.
0 ZX Logic 1 indicates detection of a zero crossing in the voltage channel.
Data Sheet ADE5169/ADE5569
Rev. E | Page 47 of 155
Table 44. Interrupt Enable 1 SFR (MIRQENL, Address 0xD9)
Bit Interrupt Enable Bit Description
[7:6] Reserved Reserved.
5 FAU LTSI GN1 When this bit is set to Logic 1, the FAULTSIGN flag set creates a pending ADE interrupt to the 8052 core.
4 VARSIGN When this bit is set to Logic 1, the VARSIGN flag set creates a pending ADE interrupt to the 8052 core.
3 APSIGN When this bit is set to Logic 1, the APSIGN flag set creates a pending ADE interrupt to the 8052 core.
2 VANOLOAD When this bit is set to Logic 1, the VANOLOAD flag set creates a pending ADE interrupt to the 8052 core.
1 RNOLOAD When this bit is set to Logic 1, the RNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
0 APNOLOAD When this bit is set to Logic 1, the APNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
1 This function is not available in the ADE5569.
Table 45. Interrupt Enable 2 SFR (MIRQENM, Address 0xDA)
Bit Interrupt Enable Bit Description
7 CF2 When this bit is set to Logic 1, a CF2 pulse creates a pending ADE interrupt to the 8052 core.
6 CF1 When this bit is set to Logic 1, a CF1 pulse creates a pending ADE interrupt to the 8052 core.
5 VAEOF When this bit is set to Logic 1, the VAEOF flag set creates a pending ADE interrupt to the 8052 core.
4 REOF When this bit is set to Logic 1, the REOF flag set creates a pending ADE interrupt to the 8052 core.
3 AEOF When this bit is set to Logic 1, the AEOF flag set creates a pending ADE interrupt to the 8052 core.
2 VAEHF When this bit is set to Logic 1, the VAEHF flag set creates a pending ADE interrupt to the 8052 core.
1 REHF When this bit is set to Logic 1, the REHF flag set creates a pending ADE interrupt to the 8052 core.
0 AEHF When this bit is set to Logic 1, the AEHF flag set creates a pending ADE interrupt to the 8052 core.
Table 46. Interrupt Enable 3 SFR (MIRQENH, Address 0xDB)
Bit Interrupt Enable Bit Description
[7:6] Reserved Reserved.
5 WFSM When this bit is set to Logic 1, the WFSM flag set creates a pending ADE interrupt to the 8052 core.
4 PKI When this bit is set to Logic 1, the PKI flag set creates a pending ADE interrupt to the 8052 core.
3 PKV When this bit is set to Logic 1, the PKV flag set creates a pending ADE interrupt to the 8052 core.
2 CYCEND When this bit is set to Logic 1, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.
1 ZXTO When this bit is set to Logic 1, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.
0
ZX
When this bit is set to Logic 1, the ZX flag set creates a pending ADE interrupt to the 8052 core.
ANALOG INPUTS
Each ADE5169/ADE5569 has two fully differential voltage input
channels. The maximum differential input voltage for the VP/VN,
IPA/IN, IPB/IN, and IP/IN input pairs is ±0.5 V.
Each analog input channel has a programmable gain amplifier
(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The gain
selections are made by writing to the gain register (see Table 38
and Figure 41).
00000000
76543210
GAIN REGISTER*
CURRENT AND VOLTAGE CHANNE LS PGA CONT RO L
PGA2 GAI N S E LECT
000 = ×1
001 = ×2
010 = ×4
011 = ×8
100 = ×16
PGA1 GAI N S E LECT
000 = ×1
001 = ×2
010 = ×4
011 = ×8
100 = ×16
RESERVED
*REGISTER CO NTENTS SHOW P OW E R- ON DEFAULTS.
ADDR:
0x1B
CFSIGN_OPT
07411-019
Figure 41. Analog Gain Register
Bit 2 to Bit 0 select the gain for the PGA in the current channel,
and Bit 7 to Bit 5 select the gain for the PGA in the voltage channel.
Figure 42 shows how a gain selection for the current channel is
made using the gain register.
K × V
IN
I
P
, I
Px
I
IN
00000000
76543210
GAIN[7:0]
GAI N ( K)
SELECTION
V
IN
07411-018
Figure 42. PGA in Current Channel
ADE5169/ADE5569 Data Sheet
Rev. E | Page 48 of 155
ANALOG-TO-DIGITAL CONVERSION
Each ADE5169/ADE5569 has two Σ-Δ analog-to-digital
converters (ADCs). The outputs of these ADCs are mapped
directly to waveform sampling SFRs (Address 0xE2 to Address
0xE7) and are used for energy measurement internal digital signal
processing. In PSM1 (battery) mode and PSM2 (sleep) mode,
the ADCs are powered down to minimize power consumption.
For simplicity, the block diagram in Figure 44 shows a first-order
Σ-∆ ADC. The converter is made up of the Σ-∆ modulator and
the digital low-pass filter (LPF).
A Σ-∆ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE5169/ADE5569, the sampling clock is equal to
4.096 MHz/5. The 1-bit DAC in the feedback loop is driven by the
serial data stream. The DAC output is subtracted from the input
signal. If the loop gain is high enough, the average value of the
DAC output (and, therefore, the bit stream) can approach that of
the input signal level.
For any given input value in a single sampling interval, the data
from the 1-bit ADC is virtually meaningless. Only when a large
number of samples is averaged is a meaningful result obtained.
This averaging is carried into the second part of the ADC, the
digital LPF. By averaging a large number of bits from the modu-
lator, the low-pass filter can produce 24-bit data-words that are
proportional to the input signal level.
The Σ-∆ converter uses two techniques to achieve high resolution
from what is essentially a 1-bit conversion technique. The first
is oversampling. Oversampling means that the signal is sampled
at a rate (frequency) that is many times higher than the bandwidth
of interest. For example, the sampling rate in the ADE5169/
ADE5569 is 4.096 MHz/5 (819.2 kHz); and the band of interest
is 40 Hz to 2 kHz.
Oversampling has the effect of spreading the quantization noise
(noise due to sampling) over a wider bandwidth. With the noise
spread more thinly over a wider bandwidth, the quantization noise
in the band of interest is lowered (see Figure 43).
409.60819.22
NOISE
SIGNAL
DIGITAL
FILTER
ANTIALIASING
FILTE R ( RC) SAMPLING
FREQUENCY
HIGH RESOLUTION
OUTPUT FROM DIGITAL
LPF
SHAPED
NOISE
409.60819.22
NOISE
SIGNAL
FREQUENCY (kHz)
FREQUENCY (kHz)
07411-021
Figure 43. Noise Reduction Due to Oversampling and
Noise Shaping in the Analog Modulator
However, oversampling alone is not efficient enough to improve
the signal-to-noise ratio (SNR) in the band of interest. For example,
an oversampling ratio of 4 is required to increase the SNR by only
6 dB (one bit). To keep the oversampling ratio at a reasonable level,
it is possible to shape the quantization noise so that the majority
of the noise lies at the higher frequencies. In the Σ-∆ modulator,
the noise is shaped by the integrator, which has a high-pass type of
response for the quantization noise. The result is that most of
the noise is at the higher frequencies where it can be removed
by the digital LPF. This noise shaping is shown in Figure 43.
+
–
INTEGRATOR
V
REF
1-BIT DAC
DIGITAL
LOW-PASS
FILTER
24
MCLK/5
C
R
ANALOG
LOW-PASS FILTER
.. . 10100101 . ..
LATCHED
COMPARATOR
07411-020
Figure 44. First-Order
Σ
-∆ ADC
Data Sheet ADE5169/ADE5569
Rev. E | Page 49 of 155
Antialiasing Filter
Figure 44 also shows an analog LPF (RC) on the input to the
modulator. This filter is present to prevent aliasing, an artifact
of all sampled systems. Aliasing means that frequency components
in the input signal to the ADC that are higher than half the
sampling rate of the ADC appear in the sampled signal at a fre-
quency below half the sampling rate. Figure 45 illustrates the effect.
Frequency components (the black arrows) above half the sampling
frequency (also known as the Nyquist frequency, that is, 409.6 kHz)
are imaged or folded back down below 409.6 kHz. This happens
with all ADCs, regardless of the architecture. In Figure 45, only
frequencies near the sampling frequency (819.2 kHz) move into
the band of interest for metering (40 Hz to 2 kHz). This allows
the use of a very simple LPF to attenuate high frequency (at
approximately 819.2 kHz) noise and prevents distortion in the
band of interest.
409.60 819.22FREQUE NCY (kHz )
SAMPLING
FREQUENCY
ALIASING E F FECTS
IMAGE
FREQUENCIES
07411-022
Figure 45. ADC and Signal Processing in Current Channel Outline Dimensions
For conventional current sensors, a simple RC filter (single-pole
LPF) with a corner frequency of 10 kHz produces an attenuation
of approximately 40 dB at 819.2 kHz (see Figure 45). The 20 dB
per decade attenuation is usually sufficient to eliminate the effects
of aliasing for conventional current sensors. However, for a di/dt
sensor such as a Rogowski coil, the sensor has a 20 dB per decade
gain. This neutralizes the −20 dB per decade attenuation produced
by one simple LPF. Therefore, when using a di/dt sensor, care
should be taken to offset the 20 dB per decade gain. One simple
approach is to cascade two RC filters to produce the −40 dB per
decade attenuation needed.
ADC Transfer Function
Both ADCs in the ADE5169/ADE5569 are designed to produce
the same output code for the same input signal level. With a
full-scale signal on the input of 0.5 V and an internal reference
of 1.2 V, the ADC output code is nominally 2,147,483 or 0x20C49B.
The maximum code from the ADC is ±4,194,304; this is equiva-
lent to an input signal level of ±0.794 V. However, for specified
performance, it is recommended that the full-scale input signal
level of 0.5 V not be exceeded.
Current Channel ADC
Figure 46 and Figure 47 show the ADC and signal processing
chain for the current channel. In waveform sampling mode, the
ADC outputs a signed, twos complement, 24-bit data-word at a
maximum of 25.6 kSPS (4.096 MHz/160).
ADE5169/ADE5569 Data Sheet
Rev. E | Page 50 of 155
PGA1 ADC
I
PA
I
PB
I
N
I
REFERENCE
IBGAIN
×1, ×2, ×4
×8, ×16
{GAIN[2:0]}
HPF
DIGITAL
INTEGRATOR*
dt
MODE1[5] CURRENT RMS (I
rms
)
CALCULATION
WAVEFO RM SAMP L E
REGISTER
ACTIV E AND REACT IVE
POW E R CALCULATI ON
0V
V1
ANALOG
INPUT
RANGE
0.25V , 0.125V,
62.5mV , 31.3m V
CURRENT CHANNEL
WAVEFORM
DATA RANGE
0x28F5C2
0x000000
0xD70A3E
CURRENT CHANNEL
WAVEFORM
DATA RANGE AFTER
INTEGRATOR (50Hz)
0x342CD0
0x000000
0xCBD330
CURRENT CHANNEL
WAVEFORM
DAT A RANGE AF TER
INTEGRATOR (60Hz)
0x2B7850
0x000000
0xD487B0
60Hz
50Hz
PGA1 ADC HPF
*WHEN THE DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED
DEPENDIN G ON THE SIGNAL FREQUENCY BECAUSE THE I NT E GRATO R HAS A –20d B/DECADE
FREQUENCY RES P O NSE . WHEN DI SABL ED, THE O UT P UT IS NOT F URT HER ATTENUAT ED.
07411-009
Figure 46. ADC and Signal Processing in Current Channel for the ADE5169
PGA1 ADC
I
P
I
N
I
REFERENCE
×1, ×2, ×4
×8, ×16
{GAIN[2:0]}
HPF
DIGITAL
INTEGRATOR*
dt
MODE1[5] CURRENT RM S ( I
rms
)
CALCULATION
WAVEFO RM SAMPLE
REGISTER
ACTIV E AND REACTIV E
POWER CALCULATION
0V
V1
ANALOG
INPUT
RANGE
0.25V, 0. 125V,
62.5mV, 31.3mV CURRENT CHANNEL
WAVEFORM
DATA RANGE
0x28F5C2
0x000000
0xD70A3E
CURRENT CHAN NEL
WAVEFORM
DAT A RANGE AFT E R
INTEGRATOR (50Hz)
0x342CD0
0x000000
0xCBD330
CURRENT CHANNEL
WAVEFORM
DATA RANGE AFTER
INTEGRATOR (60Hz)
0x2B7850
0x000000
0xD487B0
60Hz
50Hz
*
WHEN THE DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED
DEPENDING ON THE SI GNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A –20dB/DECADE
FR E QUEN CY RESPONSE . WHEN DISA BLED , THE OUTPUT I S NOT FURTHER ATTENUATED.
07411-008
Figure 47. ADC and Signal Processing in Current Channel for the ADE5569
Data Sheet ADE5169/ADE5569
Rev. E | Page 51 of 155
Voltage Channel ADC
Figure 48 shows the ADC and signal processing chain for the
voltage channel. In waveform sampling mode, the ADC outputs
a signed, twos complement, 24-bit data-word at a maximum
of 25.6 kSPS (MCLK/160). The ADC produces an output code
that is approximately between 0x28F5 (+10,485d) and 0xD70B
(−10,485d).
Channel Sampling
The waveform samples of the current ADC and voltage ADC
can also be routed to the waveform registers to be read by the
MCU core. The active, reactive, and apparent power and energy
calculation remain uninterrupted during waveform sampling.
When in waveform sampling mode, one of four output sample
rates can be chosen by using the two DTRT bits of the WAVMODE
register (Address 0x0D[1:0]), as shown in Table 35. The output
sample rate can be 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS.
If the WFSM enable bit is set in the Interrupt Enable 3 SFR
(MIRQENH, Address 0xDB), the 8052 core has a pending ADE
interrupt. The sampled signals selected in the WAVMODE register
are latched into the waveform SFRs when the waveform high byte
(WAV1H or WAV2H) is read.
The ADE interrupt stays active until the WFSM status bit is cleared
(see the Energy Measurement Interrupts section).
ANALOG
INPUT
RANGE
HPF
ADC
REFERENCE
V2
0V
0.5V, 0. 25V ,
0.125V, 62. 5mV ,
31.3mV
VOLTAGE RMS (Vrms)
CALCULATION
VP
VN
PGA2
V2
VOLT AGE CHANNEL
WAVEFORM
DATA RANG E
0xD70B
0x0000
0x28F5
ACTIVE AND REACTIVE
POWER CALCULATI ON
LPF1
f
–3dB = 63.7Hz
MODE1[6]
ZX SIGNAL
DATA RANG E FO R 60Hz S IGNAL
0xE230
0x0000
0x1DD0
ZX DETECTION
ZX SIGNAL
DATA RANG E FO R 50Hz S IGNAL
0xDFC9
0x0000
0x2037
VOLTAGE PEAK DETECT
×1, × 2, ×4,
×8, × 16
{GAIN[7:5]}
WAVEFORM SAMPLE
REGISTER
07411-024
Figure 48. ADC and Signal Processing in Voltage Channel
ADE5169/ADE5569 Data Sheet
Rev. E | Page 52 of 155
FAULT DETECTION (ADE5169 ONLY)
The ADE5169 incorporates a fault detection scheme that warns of
fault conditions and allows accurate measurement to continue
during a fault event. (This feature is not available in the ADE5569.)
The ADE5169 does this by continuously monitoring both current
inputs (IPA and IPB). For ease of understanding, these currents are
referred to as phase and neutral (return) currents. In the ADE5169,
a fault condition is defined when the difference between IPA and
IPB is greater than 6.25% of the active channel caused by amplitude
or phase. If a fault condition is detected and the inactive channel
is larger than the active channel, the ADE5169 automatically
switches current measurement to the inactive channel. During a
fault, the active, reactive, and apparent power and the Irms are
generated using the larger of the two currents. On power-up,
IPA is the current input selected for active, reactive, and apparent
power and Irms calculations.
To pre vent a false alarm, averaging is done for the fault detection,
and a fault condition is detected approximately one second after
the event. The fault detection is automatically disabled when the
voltage signal is less than 0.3% of the full-scale input range. This
eliminates false detection of a fault due to noise at light loads.
Because the ADE5169 looks for a difference between the voltage
signals on IPA and IPB, it is important that both current transducers
be closely matched.
Channel Selection Indication
The current channel selected for measurement is indicated by the
ICHANNEL bit (Bit 7) in the ACCMODE register (Address 0x0F).
When Bit 7 is cleared, IPA is selected; when Bit 7 is set, IPB is
selected. The ADE5169 automatically switch from one channel
to the other and report the channel configuration in the
ACCMODE register.
The current channel selected for measurement can also be forced.
Setting the SEL_I_CH bits (Bits[5:4]) in the CALMODE register
(Address 0x3D) to 01 or 10 selects IPA and IPB, respectively. When
both bits are cleared or set, the current channel used for measure-
ment is selected automatically, based on the fault detection.
Fault Indication
The ADE5169 provides an indication of the device going into or
out of a fault condition. The new fault condition is indicated by the
FAULTSIGN flag (Bit 5) in the Interrupt Status 1 SFR (MIRQSTL,
Address 0xDC).
When the FAULTSIGN bit (Bit 6) in the ACCMODE register
(Address 0x0F) is cleared, the FAULTSIGN flag in the Interrupt
Status 1 SFR (MIRQSTL, Address 0xDC) is set when the device
is entering a fault condition or a normal condition.
When the FAULTSIGN bit (Bit 5) is set in the Interrupt Enable 1
SFR (MIRQENL, Address 0xD9) and the FAULTSIGN flag (Bit 5)
in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set,
the 8052 core has a pending ADE interrupt.
Fault with Active Input Greater Than Inactive Input
If IPA is the active current input (that is, IPA is being used for
billing), and the voltage signal on IPB (inactive input) falls below
93.75% of IPA , and the FAULTSIGN bit (Bit 6) of the ACCMODE
register (Address 0x0F) is cleared, the FAULTSIGN flag (Bit 5)
in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set.
Both analog inputs are filtered and averaged to prevent false
triggering of this logic output. As a consequence of the filtering,
there is a time delay of approximately 3 sec on the logic output
after the fault event. The FAULTSIGN flag is independent of
any activity. Because IPA is the active input and it is still greater
than IPB, billing is maintained on IPA; that is, no swap to the IPB
input occurs. IPA remains the active input.
Fault with Inactive Input Greater Than Active Input
If the difference between IPB (the inactive input) and IPA (the active
input that is being used for billing) becomes greater than 6.25%
of IPB, and the FAULTSIGN bit (Bit 6) in the ACCMODE register
(Address 0x0F) is cleared, the FAULTSIGN flag (Bit 5) in the Inter-
rupt Status 1 SFR (MIRQSTL, Address 0xDC) is set. The IPB analog
input becomes the active input. Again, a time constant of about
3 sec is associated with this swap. IPA does not swap back to the
active channel until IPA is greater than IPB and the difference
between IPA and IPB, in this order, becomes greater than 6.25% of IPB.
However, if the FAULTSIGN bit (Bit 6) in the ACCMODE register
(Address 0x0F) is set, the FAULTSIGN flag (Bit 5) in the Interrupt
Status 1 SFR (MIRQSTL, Address 0xDC) is set as soon as IPA is
within 6.25% of IPB. This threshold eliminates concerns about
potential chatter between IPA and IPB calibration.
Calibration Concerns
Typically, when a meter is calibrated, the voltage and current cir-
cuits are separated (see Figure 49). Current passes through only
the phase circuit or the neutral circuit. Figure 49 shows current
being passed through the phase circuit. This is the preferred option
because the ADE5169 starts billing on the IPA input on power-up.
The phase circuit, CT, is connected to IPA in the diagram. Because
the current sensors are not perfectly matched, it is important to
match current inputs. The ADE5169 provides a gain calibration
register for IPB, IBGAIN (Address 0x1C). IBGAIN is a 12-bit,
signed, twos complement register that provides a gain resolution
of 0.0244%/LSB.
AGND
IB
IN
IPA
RF
RF
C
F
C
F
CT
CT
R
B
R
B
0V
V
A
0
I
PB
PHASE
NEUTRAL
R
F
R
A
V
P
R
F
V
N
C
T
C
F
V
TEST
CURRENT
240V rms
07411-025
+
–
+
–
+
–
Figure 49. Fault Conditions for Inactive Input Greater Than Active Input
Data Sheet ADE5169/ADE5569
Rev. E | Page 53 of 155
For calibration, a first measurement should be done on IPA by
setting the SEL_I_CH bits (Bits[5:4]) to 0b01 in the CALMODE
register (Address 0x3D). This measurement should be compared
to the measurement on IPB. Measuring IPB can be forced by setting
the SEL_I_CH bits (Bits[5:4]) to 0b10 in the CALMODE register
(Address 0x3D). The gain error between these two measurements
can be evaluated using the following equation:
Error (%) = )(
)()(
PA
PA
PB
ItMeasuremen
ItMeasuremenItMeasuremen
The two channels, IPA and IPB, can then be matched by writing–
Error(%)/(1 + Error(%)) × 212 to the IBGAIN register
(Address 0x1C). This matching adjustment is valid for all energy
measurements made by the ADE5169, including active power,
reactive power, apparent power, and Irms.
di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR
The di/dt sensor, a feature available for the ADE5169/ADE5569,
detects changes in the magnetic field caused by ac currents.
Figure 50 shows the principle of a di/dt current sensor.
MAGNET IC FIELD CREATED BY CURRENT
(DIRECTLY PROPORTIONAL TO CURRENT)
+ EMF (ELECTROMOTIVE FORCE)
– INDUCED B Y CHANGE S IN
MAGNETIC FLUX DENSITY (di/dt)
07411-026
Figure 50. Principle of a di/dt Current Sensor
The flux density of a magnetic field induced by a current is directly
proportional to the magnitude of the current. The changes in the
magnetic flux density passing through a conductor loop generate
an electromotive force (EMF) between the two ends of the loop.
The EMF is a voltage signal that is proportional to the di/dt of the
current. The voltage output from the di/dt current sensor is deter-
mined by the mutual inductance between the current carrying
conductor and the di/dt sensor. The current signal needs to be
recovered from the di/dt signal before it can be used. An integrator
is, therefore, necessary to restore the signal to its original form.
The ADE5169/ADE5569 has a built in digital integrator to recover
the current signal from the di/dt sensor. The digital integrator on
the current channel is switched off by default when the ADE5169/
ADE5569 is powered up. Setting the INTE bit (Bit 5) in the
MODE1 register (Address 0x0B) turns on the integrator. Figure 51
to Figure 54 show the gain and phase response of the
digital integrator.
FREQUENCY (Hz)
10
GAIN (dB)
0
–10
–20
–30
–40
–50 100 1000
07411-027
Figure 51. Combined Gain Response of the Digital Integrator and
Phase Compensator
FREQUENCY (Hz)
10
2
10
3
FREQ
–
88.0
PHAS E (Degree s)
–88.5
–89.0
–89.5
–90.0
–90.5
0
7411-106
Figure 52. Combined Phase Response of the Digital Integrator and
Phase Compensator
FREQUENCY (Hz)
–1.0
–6.040 7045
GAIN (dB)
50 55 60 65
–1.5
–2.0
–2.5
–3.5
–4.5
–5.5
–3.0
–4.0
–5.0
07411-029
Figure 53. Combined Gain Response of the Digital Integrator and
Phase Compensator (40 Hz to 70 Hz)
ADE5169/ADE5569 Data Sheet
Rev. E | Page 54 of 155
–89.75
–89.80
–89.85
–89.90
–89.95
–90.00
FREQUENCY (Hz)
PHASE ( Degrees)
40 45 70
50 55 60 65
–90.05
–89.70
07411-030
Figure 54. Combined Phase Response of the Digital Integrator and
Phase Compensator (40 Hz to 70 Hz)
Note that the integrator has a −20 dB/dec attenuation and an
approximately −90° phase shift. When combined with a di/dt
sensor, the resulting magnitude and phase response should be a
flat gain over the frequency band of interest. The di/dt sensor has a
20 dB/dec gain associated with it. It also generates significant high
frequency noise. Therefore, a more effective antialiasing filter is
needed to avoid noise due to aliasing (see the Antialiasing Filter
section).
When the digital integrator is switched off, the ADE5169/ADE5569
can be used directly with a conventional current sensor, such as a
current transformer (CT), or with a low resistance current shunt.
POWER QUALITY MEASUREMENTS
Zero-Crossing Detection
Each ADE5169/ADE5569 has a zero-crossing detection circuit
on the voltage channel. This external zero-crossing signal can be
output on P0.5 and P1.2 (see Table 39). It is also used in
calibration mode.
The zero crossing is generated by default from the output of LPF1.
This filter has a low cutoff frequency and is intended for 50 Hz
and 60 Hz systems. If needed, this filter can be disabled to allow
a higher frequency signal to be detected or to limit the group delay
of the detection. If the voltage input fundamental frequency is
below 60 Hz, and a time delay in ZX detection is acceptable, it
is recommended that LPF1 be enabled. Enabling LPF1 limits the
variability in the ZX detection by eliminating the high frequency
components. Figure 55 shows how the zero-crossing signal is
generated.
The zero-crossing signal, ZX, is generated from the output of
LPF1 (bypassed or not). LPF1 has a single pole at 63.7 Hz (at
MCLK = 4.096 MHz). As a result, there is a phase lag between
the analog input signal, V2, and the output of LPF1. The phase
lag response of LPF1 results in a time delay of approximately
2 ms (at 60 Hz) between the zero crossing on the analog inputs
of the voltage channel and ZX detection.
×1, × 2, ×4,
×8, × 16
ADC 2
REFERENCE
LPF1
f–3dB = 63.7Hz
PGA2
{GAIN[7:5]}
VP
VN
V2
ZERO
CROSSING
ZX
HPF
MODE1[6]
43.24° @ 60Hz
1.0
0.73 ZX
V2 LPF1
07411-031
Figure 55. Zero-Crossing Detection on the Voltage Channel
The zero-crossing detection also drives the ZX flag in the Inter-
rupt Status 3 SFR (MIRQSTH, Address 0xDE). If the ZX bit (Bit 0)
in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) is set,
the 8052 core has a pending ADE interrupt. The ADE interrupt
stays active until the ZX status bit is cleared (see the Energy
Measurement Interrupts section).
Zero-Crossing Timeout
The zero-crossing detection also has an associated timeout
register, ZXTOUT. This unsigned, 12-bit register is decremented
(1 LSB) every 160/MCLK sec. The register is reset to its user-
programmed, full-scale value every time a zero crossing is detected
on the voltage channel. The default power-on value in this register
is 0xFFF. If the internal register decrements to 0 before a zero
crossing is detected in the Interrupt Status 3 SFR (MIRQSTH,
Address 0xDE) and the ZXTO bit (Bit 1) in the Interrupt Enable 3
SFR (MIRQENH, Address 0xDB) is set, the 8052 core has a
pending ADE interrupt.
The ADE interrupt stays active until the ZXTO status bit is
cleared (see the Energy Measurement Interrupts section). The
ZXTOUT register (Address 0x11) can be written to or read by
the user (see the Energy Measurement Registers section). The
resolution of the register is 160/MCLK sec per LSB. Thus, the
maximum delay for an interrupt is 0.16 sec (1/MCLK × 212) when
MCLK = 4.096 MHz.
Data Sheet ADE5169/ADE5569
Rev. E | Page 55 of 155
Figure 56 shows the mechanism of the zero-crossing timeout
detection when the line voltage stays at a fixed dc level for more
than MCLK/160 × ZXTOUT seconds.
12-BIT INTERNAL
REGISTER VALUE
ZXTOUT
ZXTO
FLAG
BIT
VOLTAGE
CHANNEL
07411-032
Figure 56. Zero-Crossing Timeout Detection
Period or Frequency Measurements
The ADE5169/ADE5569 provide the period or frequency
measurement of the line. The period or frequency measurement
is selected by clearing or setting the FREQSEL bit (Bit 1) in the
MODE2 register (Address 0x0C). The period/frequency register,
PER_FREQ (Address 0x0A), is an unsigned 16-bit register that is
updated every period. If LPF1 is enabled, a settling time of 1.8 sec
is associated with this filter before the measurement is stable.
When the period measurement is selected, the measurement has a
2.44 μs/LSB (4.096 MHz/10) resolution, which represents 0.014%
when the line frequency is 60 Hz. When the line frequency is
60 Hz, the value of the period register is approximately 0d6827.
The length of the register enables the measurement of line fre-
quencies as low as 12.5 Hz. The period register is stable at ±1 LSB
when the line is established and the measurement does not change.
When the frequency measurement is selected, the measurement
has a 0.0625 Hz/LSB resolution when MCLK = 4.096 MHz, which
represents 0.104% when the line frequency is 60 Hz. When the line
frequency is 60 Hz, the value of the frequency register is 0d960. The
frequency register is stable at ±4 LSB when the line is established
and the measurement does not change.
Line Voltage SAG Detection
In addition to detection of the loss of the line voltage signal
(zero crossing), the ADE5169/ADE5569 can also be programmed
to detect when the absolute value of the line voltage drops below a
certain peak value for a number of line cycles. This condition is
illustrated in Figure 57.
SAG IS RESET LO W
WHEN VOLTAGE
CHANNEL E X CE E DS
SAGLVL[15:0] AND
SAG FLAG I S RESET
FULL SCALE
SAGLVL[15:0]
SAG FLAG SAGCYC[7:0] = 0x04
3 LINE CYCLE S
VO LT AG E CH ANNE L
07411-033
Figure 57. SAG Detection
Figure 57 shows the line voltage falling below a threshold that
is set in the SAG level register (SAGLVL, Address 0x14[15:0])
for three line cycles. The quantities 0 and 1 are not valid for the
SAGCYC register, and the contents represent one more than the
desired number of full line cycles. For example, when the SAG
cycle register (SAGCYC, Address 0x13[7:0]) contains 0x04, FSAG
(Bit 5) in the power management interrupt flag SFR (IPSMF,
Address 0xF8) is set at the end of the third line cycle after the line
voltage falls below the threshold. If the SAG enable bit (ESAG,
Bit 5) in the power management interrupt enable SFR (IPSME,
Address 0xEC) is set, the 8052 core has a pending power supply
management interrupt. The PSM interrupt stays active until the
FSAG bit is cleared (see the Power Supply Management (PSM)
Interrupt section).
In Figure 57, the SAG flag (FSAG) is set on the fifth line cycle
after the signal on the voltage channel first drops below the
threshold level.
SAG Level Set
The 2-byte contents of the SAG level register (SAGLVL,
Address 0x14) are compared to the absolute value of the output
from LPF1. Therefore, when LPF1 is enabled, writing 0x2038 to the
SAG level register puts the SAG detection level at full scale (see
Figure 57). Writing 0x00 or 0x01 puts the SAG detection level at 0.
The SAG level register is compared to the input of the ZX detec-
tion, and detection is made when the ZX input falls below the
contents of the SAG level register.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 56 of 155
Peak Detection
The ADE5169/ADE5569 can be programmed to detect when the
absolute value of the voltage or current channel exceeds a specified
peak value. Figure 58 illustrates the behavior of the peak detection
for the voltage channel. Both voltage and current channels are
monitored at the same time.
PKV RESET
LOW WHEN
MIRQSTH SF R
IS READ
VPKLVL[15:0]
V
2
RESET BIT PKV
IN MIRQSTH SF
R
PKV INTERRUPT
FLAG
07411-034
Figure 58. Peak Level Detection
Figure 58 shows a line voltage exceeding a threshold that is set in
the voltage peak register (VPKLVL, Address 0x16[15:0]). The
voltage peak event is recorded by setting the PKV flag (Bit 3)
in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE). If
the PKV enable bit (Bit 3) is set in the Interrupt Enable 3 SFR
(MIRQENH, Address 0xDB), the 8052 core has a pending ADE
interrupt. Similarly, the current peak event is recorded by setting
the PKI flag (Bit 4) in the Interrupt Status 3 SFR (MIRQSTH,
Address 0xDE). The ADE interrupt stays active until the PKV
or PKI status bit is cleared (see the Energy Measurement
Interrupts section).
Peak Level Set
The contents of the VPKLVL register (Address 0x16) and the
IPKLVL register (Address 0x15) are compared to the absolute value
of the voltage and two MSBs of the current channel, respectively.
Thus, for example, the nominal maximum code from the current
channel ADC with a full-scale signal is 0x28F5C2 (see the Current
Channel ADC section). Therefore, writing 0x28F5 to the IPKLVL
register puts the current channel peak detection level at full scale
and sets the current peak detection to its least sensitive value.
Writing 0x00 puts the current channel detection level at 0. The
detection is done by comparing the contents of the IPKLVL reg-
ister to the incoming current channel sample. The PKI flag (Bit 4)
in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) indicates
that the peak level is exceeded. If the PKI bit (Bit 4) or the PKV
bit (Bit 3) is set in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB), the 8052 core has a pending ADE interrupt.
Peak Level Record
Each ADE5169/ADE5569 records the maximum absolute value
reached by the current and voltage channels in two different
registers, IPEAK (Address 0x17) and VPEAK (Address 0x19),
respectively. Each register is a 24-bit, unsigned register that is
updated each time that the absolute value of the waveform
sample from the corresponding channel is above the value
stored in the IPEAK or VPEAK register. The contents of the
IPEAK and VPEAK registers represent the maximum absolute
value observed on the current and voltage channel input,
respectively. Reading the RSTIPEAK (Address 0x18) and
RSTVPEAK (Address 0x1A) registers clears their respective
contents after the read operation.
PHASE COMPENSATION
The ADE5169/ADE5569 must work with transducers that can
have inherent phase errors. For example, a phase error of 0.1° to
0.3° is not uncommon for a current transformer (CT). These phase
errors can vary from device to device, and they must be corrected
to perform accurate power calculations. The errors associated with
phase mismatch are particularly noticeable at low power factors.
The ADE5169/ADE5569 provide a means of digitally calibrating
these small phase errors. The device allows a small time delay or
time advance to be introduced into the signal processing chain
to compensate for small phase errors. Because the compensation is
in time, this technique should be used only for small phase errors
in the range of 0.1° to 0.5°. Correcting large phase errors using a
time shift technique may introduce significant phase errors at
higher harmonics.
The phase calibration register (PHCAL[7:0], Address 0x10) is
a twos complement, signed, single-byte register that has values
ranging from 0x82 (−126d) to 0x68 (+104d).
The PHCAL register is centered at 0x40, meaning that writing
0x40 to the register gives 0 delay. By changing this register, the
time delay in the voltage channel signal path can change from
−231.93 μs to +48.83 μs (MCLK = 4.096 MHz). One LSB is equiv-
alent to a 1.22 μs (4.096 MHz/5) time delay or advance. A line
frequency of 60 Hz gives a phase resolution of 0.026° at the
fundamental (that is, 360° × 1.22 μs × 60 Hz).
Data Sheet ADE5169/ADE5569
Rev. E | Page 57 of 155
Figure 59 illustrates how the phase compensation is used to
remove a 0.1° phase lead in the current channel due to the
external transducer. To cancel the lead (0.1°) in the current
channel, a phase lead must also be introduced into the voltage
channel. The resolution of the phase adjustment allows the intro-
duction of a phase lead in increments of 0.026°. The phase lead is
achieved by introducing a time advance into the voltage channel.
A time advance of 4.88 μs is made by writing −4 (0x3C) to the
time delay block, thus reducing the amount of time delay by
4.88 μs, or equivalently, a phase lead of approximately 0.1° at a
line frequency of 60 Hz (0x3C represents −4 because the register
is centered with 0 at 0x40).
110100
1
70
PGA1
I
P
/
I
PA
I
N
IADC 1
HPF 24
PGA2
V
P
V
N
V
ADC 2
24 LPF2
V
I
60Hz
0.1°
I
V
CHANNEL 2 DELAY
REDUCED BY 4.88µs
(0.1°LEAD AT 60Hz)
0x3C IN PHCAL[7:0]
PHCAL[7:0]
–231.93µs TO +48.83µs
60Hz
11
DELAY BLOCK
1.22µs/LSB
07411-035
Figure 59. Phase Calibration
RMS CALCULATION
Current Channel RMS Calculation
The root mean square (rms) value of a continuous signal, I(t), is
defined as
dttI
T
I
T
rms )(
12
0
(1)
For time sampling signals, rms calculation involves squaring the
signal, taking the average, and obtaining the square root. The
ADE5169/ADE5569 implement this method on the current
channel by serially squaring the input, averaging the results, and
then taking the square root of the average. The averaging part of
this signal processing is done by implementing a low-pass filter
(LPF3 in Figure 60, Figure 61, and Figure 62).
This LPF has a −3 dB cutoff frequency of 2 Hz when MCLK =
4.096 MHz.

)sin(2 tItI
(2)
where V is the rms voltage.

tIItI
2cos)( 222 (3)
When this signal goes through LPF3, the cos(2ωt) term is atte-
nuated and only the dc term, Irms2 (shown as I2 in Figure 60),
goes through.
IRMS
LPF3
INPUT
I
2
(t) = I
2
–I
2
cos (2ωt)
I
2
(t) = I
2
I(t) = √2 × I sin(ωt)
07411-036
Figure 60. IRMS Signal Processing
The Irms signal can be read from the waveform register by set-
ting the WAVMODE register (Address 0x0D) and setting the
WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB). Like the current and voltage channels waveform
sampling modes, the waveform data is available at sample rates of
25.6 kSPS, 12.8 kSPS, 6.4 kSPS, and 3.2 kSPS.
It is important to note that when the current input is larger than
40% of full scale, the Irms waveform sample register does not
represent the true processed rms value. The rms value processed
with this level of input is larger than the 24-bit read by the wave-
form register, making the value read truncated on the high end.
Figure 61 and Figure 62 show the detail of the signal processsing
chain for the rms calculation on the current channel. The current
channel rms value is processed from the samples used in the
current channel waveform sampling mode and is stored in the
unsigned, 24-bit IRMS SFRs (IRMSL, Address 0xD4; IRMSM,
Address 0xD5; and IRMSH, Address 0xD6). One LSB of the
current channel rms register (IRMSL, IRMSM, and IRMSH) is
equivalent to 1 LSB of a current channel waveform sample.
The update rate of the current channel rms measurement is
4.096 MHz/5. To minimize noise in the reading of the register, the
Irms register can also be configured to update only with the zero
crossing of the voltage input. This configuration is done by setting
the ZXRMS bit (Bit 2) in the MODE2 register (Address 0x0C).
With the different specified full-scale analog input values, the ADC
produces an output code that is approximately ±0d2,684,354
(see the Current Channel ADC section). Similarly, the equiva-
lent rms value of a full-scale ac signal is 0d1,898,124 (0x1CF68C).
The current rms measurement provided in the ADE5169/
ADE5569 is accurate to within ±0.5% for signal inputs between
full scale and full scale/500. The conversion from the register value
to amps must be done externally in the microprocessor using an
amps/LSB constant.
Current Channel RMS Offset Compensation
The ADE5169/ADE5569 incorporate a current channel rms offset
compensation register (IRMSOS). This is a 12-bit, signed register
that can be used to remove offset in the current channel rms
calculation. An offset can exist in the rms calculation due to
input noises that are integrated into the dc component of V2(t).
ADE5169/ADE5569 Data Sheet
Rev. E | Page 58 of 155
One LSB of the current channel rms offset is equivalent to
32,768 LSBs of the square of the current channel rms register.
Assuming that the maximum value from the current channel
rms calculation is 0d1,898,124 with full-scale ac inputs, then
1 LSB of the current channel rms offset represents 0.23% of
measurement error at −60 dB down from full scale.
768,32
2
0 IRMSOSII rmsrms (4)
where Irms0 is the rms measurement without offset correction.
I
rms
(t)
0x00
+
IRMSOS[11:0]
I
rms
[23:0]
2
26
2
25
sgn 2
27
2
17
2
16
2
18
24 24
dt
HPF
MODE1[5]
HPF
CURRENT CHANNEL
WAVEFORM
DATA RANGE W I TH
INTEGRATOR OFF
0xD70A3E
0x000000
0x28F5C2
60Hz
0xD487B0
I
PA
I
PB
0x2B7850
0x000000
CURRENT CHANNEL
WAVEFORM
DATA RANGE W IT H
INTEGRATOR ON (60Hz)
HPF1
DIGITAL
INTEGRATOR LPF3
0
7411-057
LPF2
IBGAIN
Figure 61. ADE5169 Current Channel RMS Signal Processing with PGA1 = 2, 4, 8, or 16
I
rms
(t)
0x00
+
IRMSOS[11:0]
I
rms
[23:0]
2
26
2
25
sgn 2
27
2
17
2
16
2
18
24 24
dt
MODE1[5]
CURRENT CHANNEL
WAVEFORM
DATA RANGE WITH
INTEGRATOR OFF
0xD70A3E
0x000000
0x28F5C2
60Hz
0xD487B0
0x2B7850
0x000000
CURRENT CHANNEL
WAVEFORM
DATA RANGE WITH
INTEGRATOR ON (60Hz)
DIGITAL
INTEGRATOR LPF3
07411-059
HPF
I
PA
HPF1 LPF2
Figure 62. ADE5569 Current Channel RMS Signal Processing with PGA1 = 2, 4, 8, or 16
Data Sheet ADE5169/ADE5569
Rev. E | Page 59 of 155
LPF3
VOLTAG E CHANNEL
0x28F5C2
++
VRMSOS[11:0]
V
OLTAGE SIGNAL (V(t))
0x28F5
0x0
0xD70B 2
16
sgn 2
15
2
7
2
6
2
8
07411-038
V
rms
(t)
0x00
V
rms
[23:0]
|X|
HPF LPF1
Figure 63. Voltage Channel RMS Signal Processing
Voltage Channel RMS Calculation
The voltage channel rms estimation is performed in the ADE5169/
ADE5569 using a mean absolute value calculation. This calculation
accurately estimates the rms of the voltage channel fundamental
signal. Figure 63 shows details of the signal processing chain for
the rms calculation on the voltage channel. The voltage channel
rms value is processed from the samples used in the voltage
channel waveform sampling mode and is stored in the unsigned
24-bit VRMS SFRs (VRMSL, Address 0xD1; VRMSM,
Address 0xD2; and VRMSH, Address 0xD3).
The update rate of the voltage channel rms measurement is
MCLK/5. To minimize noise in the reading of the register, the
VRMS SFRs can also be configured to update only with the zero
crossing of the voltage input. This configuration is done by setting
the ZXRMS bit (Bit 2) in the MODE2 register (Address 0x0C).
With the specified full-scale ac analog input signal of 0.5 V, the
output from the LPF1 in Figure 63 swings between 0x28F5 and
0xD70B at 60 Hz (see the Voltage Channel ADC section). The
equivalent rms value of this full-scale ac signal is approximately
0d1,898,124 (0x1CF68C) in the VRMS SFRs. The voltage rms
measurement provided in the ADE5169/ADE5569 is accurate to
within ±0.5% for signal input between full scale and full scale/20.
The conversion from the register value to volts must be done
externally in the microprocessor using a V/LSB constant.
Voltage Channel RMS Offset Compensation
The ADE5169/ADE5569 incorporate the voltage channel rms
offset compensation register (VRMSOS, Address 0x23). This
12-bit, signed register can be used to remove offset in the voltage
channel rms calculation. An offset can exist in the rms calculation
due to input noises and dc offset in the input samples.
One LSB of the voltage channel rms offset is equivalent to 64 LSBs
of the voltage channel rms register. Assuming that the maximum
value from the voltage channel rms calculation is 0d1,898,124 with
full-scale ac inputs, then 1 LSB of the voltage channel rms offset
represents 3.37% of measurement error at −60 dB down from
full scale.
Vrms = Vrms0 + 64 × VRMSOS (5)
where Vrms0 is the rms measurement without offset correction.
ACTIVE POWER CALCULATION
Active power is defined as the rate of energy flow from source
to load. It is the product of the voltage and current waveforms.
The resulting waveform is called the instantaneous power signal
and is equal to the rate of energy flow at every instant of time.
The unit of power is the watt or joules/second. Equation 8 gives an
expression for the instantaneous power signal in an ac system.
)sin(2)( tVtV (6)
)sin(2)( tItI (7)
where:
V is the rms voltage.
I is the rms current.
P(t) = V(t) × I(t)
)2cos()( tVIVItP
(8)
The average power over an integral number of line cycles (n) is
given by the expression in Equation 9.
nT VIdttP
nT
P0)(
1 (9)
where:
T is the line cycle period.
P is referred to as the active or real power.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 60 of 155
Note that the active power is equal to the dc component of the
instantaneous power signal, P(t), in Equation 9, that is, VI. This
is the relationship used to calculate active power in the ADE5169/
ADE5569. The instantaneous power signal, P(t), is generated by
multiplying the current and voltage signals. The dc component of
the instantaneous power signal is then extracted by LPF2 (low-pass
filter) to obtain the active power information (see Figure 64).
INSTANTANEOUS
POWER S IG NAL P(t) = V × I – V × I × cos(2ωt)
ACTIVE REAL POWER
SIGNAL = V × I
0x19999A
VI
0xCCCCD
0x00000
CURRENT
I(t) = 2 × I × sin(ωt)
VOLTAGE
V(t) = 2 × V × sin(ωt)
07411-039
Figure 64. Active Power Calculation
Because LPF2 does not have an ideal brick wall frequency response
(see Figure 65), the active power signal has some ripple due to the
instantaneous power signal. This ripple is sinusoidal and has a
frequency equal to 2× the line frequency. Because of its sinusoidal
nature, the ripple is removed when the active power signal is
integrated to calculate energy (see the Active Energy
Calculation section).
FREQUENCY (Hz)
–24 1
ATTENUATION (dB)
–20
310 30 100
–12
–16
–8
–4
0
07411-040
Figure 65. Frequency Response of LPF2
Data Sheet ADE5169/ADE5569
Rev. E | Page 61 of 155
Active Power Gain Calibration
Figure 66 shows the signal processing chain for the active power
calculation in the ADE5169/ADE5569. As explained previously,
the active power is calculated by filtering the output of the
multiplier with a low-pass filter. Note that, when reading the
waveform samples from the output of LPF2, the gain of the active
energy can be adjusted by using the multiplier and writing a twos
complement, 12-bit word to the the watt gain register (WGAIN,
Address 0x1D[11:0]). Equation 10 shows how the gain adjustment
is related to the contents of the watt gain register.
+×=
12
2
1WGAIN
PowerActiveWGAINOutput
(10)
For example, when 0x7FF is written to the watt gain register, the
power output is scaled up by 50% (0x7FF = 2047d, 2047/212 = 0.5).
Similarly, 0x800 = −2048d (signed, twos complement), and power
output is scaled by −50%. Each LSB scales the power output by
0.0244%. The minimum output range is given when the watt gain
register contents are equal to 0x800, and the maximum output
range is given by writing 0x7FF to the watt gain register. This
register can be used to calibrate the active power (or energy)
calculation in the ADE5169/ADE5569.
Active Power Offset Calibration
The ADE5169/ADE5569 also incorporate an active power offset
register (WATTOS, Address 0x20[15:0]). It is a signed, twos
complement, 16-bit register that can be used to remove offsets in
the active power calculation (see Figure 66). An offset can exist
in the power calculation due to crosstalk between channels on
the PCB or in the IC itself. The offset calibration allows the
contents of the active power register to be maintained at 0 when
no power is being consumed.
The 256 LSBs (WATTOS = 0x0100) written to the active power
offset register are equivalent to 1 LSB in the waveform sample
register. Assuming the average value, output from LPF2 is
0xCCCCD (838,861d) when inputs on the voltage and current
channels are both at full scale. At −60 dB down on the current
channel (1/1000 of the current channel full-scale input), the
average word value output from LPF2 is 838.861 (838,861/1000).
One LSB in the LPF2 output has a measurement error of
1/838.861 × 100% = 0.119% of the average value. The active
power offset register has a resolution equal to 1/256 LSB of
the waveform register. Therefore, the power offset correction
resolution is 0.000464%/LSB (0.119%/256) at −60 dB.
Active Power Sign Detection
The ADE5169/ADE5569 can detect a change of sign in the active
power. The APSIGN flag (Bit 3) in the Interrupt Status 1 SFR
(MIRQSTL, Address 0xDC) records that a change of sign has
occurred according to the APSIGN bit (Bit 4) in the ACCMODE
register (Address 0x0F). If the APSIGN flag (Bit 3) is set in the
Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), the 8052 core
has a pending ADE interrupt. The ADE interrupt stays active until
the APSIGN status bit is cleared (see the Energy Measurement
Interrupts section).
When the APSIGN bit (Bit 4) in the ACCMODE register
(Address 0x0F) is cleared (default), a transition from positive
to negative active power sets the APSIGN flag (Bit 3) in the
Interrupt Status 1 SFR (MIRQSTL, Address 0xDC).
When the APSIGN bit (Bit 4) in the ACCMODE register
(Address 0x0F) is set, the APSIGN flag (Bit 3) in the MIRQSTL
SFR (Address 0xDC) is set when a transition from negative to
positive active power occurs.
Active Power No Load Detection
The ADE5169/ADE5569 include a no load threshold feature on
the active power that eliminates any creep effects in the meter.
The device accomplishes this by not accumulating energy if the
multiplier output is below the no load threshold. When the active
power is below the no load threshold, the APNOLOAD flag (Bit 0)
in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set.
If the APNOLOAD bit (Bit 0) is set in the Interrupt Enable 1 SFR
(MIRQENL, Address 0xD9), the 8052 core has a pending ADE
interrupt. The ADE interrupt stays active until the APNOLOAD
status bit is cleared (see the Energy Measurement
Interrupts section).
The no load threshold level can be selected by setting the
APNOLOAD bits (Bits[1:0]) in the NLMODE register
(Address 0x0E). Setting these bits to 0b00 disables the no load
detection; setting them to 0b01, 0b10, or 0b11 sets the no load
detection threshold to 0.015%, 0.0075%, or 0.0037% of the multi-
plier full-scale output frequency, respectively. The IEC 62053-21
specification states that the meter must start up with a load of
≤0.4% IPB, which translates to 0.0167% of the full-scale output
frequency of the multiplier.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 62 of 155
ACTIVE ENERGY CALCULATION
As stated in the Active Power Calculation section, active power
is defined as the rate of energy flow. This relationship can be
expressed mathematically, as shown in Equation 11.
dt
dE
P=
(11)
where:
P is power.
E is energy.
Conversely, energy is given as the integral of power.
∫
=dttPE )(
(12)
The ADE5169/ADE5569 achieve the integration of the active
power signal by continuously accumulating the active power signal
in an internal, nonreadable, 49-bit energy register. The WAT T H R
register (Address 0x01) represents the upper 24 bits of this internal
register. This discrete time accumulation or summation is
equivalent to integration in continuous time. Equation 13
expresses the relationship.
×== ∑
∫
∞
=
→1
0
)(lim)(
n
t
TnTPdttPE
(13)
where:
n is the discrete time sample number.
T is the discrete time sample period.
The discrete time sample period (T) for the accumulation register
in the ADE5169/ADE5569 is 1.22 µs (5/MCLK). In addition to
calculating the energy, this integration removes any sinusoidal
components that may be in the active power signal. Figure 66
shows this discrete time integration or accumulation. The active
power signal in the waveform register is continuously added to the
internal active energy register.
The active energy accumulation depends on the setting of
POAM (Bit 1) and ABSAM (Bit 0) in the ACCMODE register
(Address 0x0F). When both bits are cleared, the addition is signed
and, therefore, negative energy is subtracted from the active energy
contents. When both bits are set, the ADE5169/ADE5569 are set
to the more restrictive mode, the positive-only accumulation mode.
When POAM (Bit 1) in the ACCMODE register (Address 0x0F)
is set, only positive power contributes to the active energy
accumulation. When ABSAM (Bit 0) in the ACCMODE register
(Address 0x0F) is set, the absolute active power is used for the
active energy accumulation (see the Watt Absolute Accumulation
Mode section).
The output of the multiplier is divided by the value in the WDIV
register (Address 0x24). If the value in the WDIV register is equal
to 0, the internal active energy register is divided by 1. WDIV is an
8-bit, unsigned register. After dividing by WDIV, the active energy
is accumulated in a 49-bit internal energy accumulation register.
The upper 24 bits of this register are accessible through a read
to the active energy register (WATTHR, Address 0x01[23:0]).
A read to the RWATTHR register (Address 0x02) returns the
contents of the WATTHR register, and the upper 24 bits of the
internal register are cleared. As shown in Figure 66, the active
power signal is accumulated in an internal 49-bit, signed register.
The active power signal can be read from the waveform register
by setting the WAVMODE register (Address 0x0D) and setting
the WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB). Like the current and voltage channel waveform
sampling modes, the waveform data is available at sample rates of
25.6 kSPS, 12.8 kSPS, 6.4 kSPS, and 3.2 kSPS.
WGAIN[11:0]
WDIV[7:0]
LPF2
CURRENT
CHANNEL
VOLTAGE
CHANNEL
OUTPUT LPF2
TIME (nT)
5
MCLK
T
ACTIVE POWER
SIGNAL
++
WATTHR[23:0]
OUTPUTS FROM THE LPF2 ARE
ACCUMULATED ( INTE GRAT E D) IN
THE INT E RNAL ACTIVE E NE RGY REGI S TER
UPPER 24 BIT S ARE
ACCESSIBL E THROUGH
WATTHR[ 23: 0] RE GI STER
23 0
48 0
%
WATTOS[15:0]
26
sgn
252–6 2–7 2–8
+
+
FOR WAVEFORM
SAMPLING
TO
DIGITAL-TO-FREQUENCY
CONVERTER
WAVEFORM
REGISTER
VALUES
07411-041
Figure 66. Active Energy Calculation
Data Sheet ADE5169/ADE5569
Rev. E | Page 63 of 155
Figure 67 shows this energy accumulation for full-scale signals
(sinusoidal) on the analog inputs. The three displayed curves
illustrate the minimum period of time it takes the energy register
to roll over when the active power gain register contents are 0x7FF,
0x000, and 0x800. The watt gain register is used to carry out power
calibration in the ADE5169/ADE5569. As shown, the fastest
integration time occurs when the watt gain register is set to
maximum full scale, that is, 0x7FF.
0x00 0000
0x7F FFFF
0x3F FFFF
0x40 0000
0x80 0000
WATTHR[23:0]
6.823.41 10.2 13.7 TIME (Minutes)
WGAIN = 0x7FF
WGAIN = 0x000
WGAIN = 0x800
0
7411-042
Figure 67. Energy Register Rollover Time for Full-Scale Power
(Minimum and Maximum Power Gain)
Note that the energy register contents roll over to full-scale negative
(0x800000) and continue to increase in value when the power or
energy flow is positive (see Figure 67). Conversely, if the power is
negative, the energy register underflows to full-scale positive
(0x7FFFFF) and continues to decrease in value.
Using the Interrupt Enable 2 SFR (MIRQENM, Address 0xDA),
the ADE5169/ADE5569 can be configured to issue an ADE
interrupt to the 8052 core when the active energy register is half
full (positive or negative) or when an overflow or underflow occurs.
Integration Time Under Steady Load—Active Energy
As mentioned in the Active Energy Calculation section, the
discrete time sample period (T) for the accumulation register is
1.22 μs (5/MCLK). With full-scale sinusoidal signals on the analog
inputs and the WGAIN register (Address 0x1D) set to 0x000, the
average word value from each LPF2 is 0xCCCCD (see Figure 64).
The maximum positive value that can be stored in the internal
49-bit register is 248 (or 0xFFFF FFFF FFFF) before it overflows.
The integration time under these conditions when WDIV = 0 is
calculated in the following equation:
Time = min82.6sec6.40922.1
0xCCCCD
FFFF0xFFFFFFFF s(14)
When WDIV is set to a value other than 0, the integration time
varies, as shown in Equation 15.
Time = TimeWDIV = 0 × WDIV (15)
Active Energy Accumulation Modes
Watt Sig n e d Accumulati on Mode
The ADE5169/ADE5569 active energy default accumulation mode
is a watt signed accumulation that is based on the active power
information.
Watt Positive Only Accumulation Mode
The ADE5169/ADE5569 are placed in watt positive only
accumulation mode by setting the POAM bit (Bit 1) in the
ACCMODE register (Address 0x0F). In this mode, the energy
accumulation is done only for positive power, ignoring any
occurrence of negative power above or below the no load threshold
(see Figure 68). The CF pulse also reflects this accumulation
method when in this mode. The default setting for this mode is
off. Detection of transitions in the direction of power flow and
detection of no load threshold are active in this mode.
POSPOS
INT E RRUPT STATUS RE G ISTERS
NEG
APSI G N FL AG
NO LOAD
THRESHOLD
ACTIVE POWER
NO LOAD
THRESHOLD
ACTIVE ENERGY
07411-043
Figure 68. Energy Accumulation in Positive Only Accumulation Mode
Watt Absolute Accumulation Mode
The ADE5169/ADE5569 are placed in watt absolute accumulation
mode by setting the ABSAM bit (Bit 0) in the ACCMODE register
(Address 0x0F). In this mode, the energy accumulation is done
using the absolute active power, ignoring any occurrence of power
below the no load threshold (see Figure 69). The CF pulse also
reflects this accumulation method when in this mode. The default
setting for this mode is off. Detection of transitions in the direction
of power flow and detection of no load threshold are active in
this mode.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 64 of 155
POSPOS
INTE RRUPT S T AT US REG IST ERS
NEG
APSIGN FL AG
NO L OAD
THRESHOLD
ACTIVE POW ER
NO L OAD
THRESHOLD
A
CTIVE ENERGY
APNOLOAD APNOLOAD
07411-044
Figure 69. Energy Accumulation in Absolute Accumulation Mode
Active Energy Pulse Output
All of the ADE5169/ADE5569 circuitry has a pulse output whose
frequency is proportional to active power (see the Active Power
Calculation section). This pulse frequency output uses the
calibrated signal from the WGAIN register (Address 0x1D)
output, and its behavior is consistent with the setting of the
active energy accumulation mode in the ACCMODE register
(Address 0x0F). The pulse output is active low and should
preferably be connected to an LED, as shown in Figure 80.
Line Cycle Active Energy Accumulation Mode
In line cycle active energy accumulation mode, the energy accumu-
lation of the ADE5169/ADE5569 can be synchronized to the
voltage channel zero crossing so that active energy can be accumu-
lated over an integral number of half-line cycles. The advantage
of summing the active energy over an integer number of line cycles
is that the sinusoidal component in the active energy is reduced to
0. This eliminates any ripple in the energy calculation. Energy is
calculated more accurately and more quickly because the integra-
tion period can be shortened. By using this mode, the energy
calibration can be greatly simplified, and the time required to
calibrate the meter can be significantly reduced.
In the line cycle active energy accumulation mode, the ADE5169/
ADE5569 accumulate the active power signal in the LWATTHR
register (Address 0x03) for an integral number of line cycles, as
shown in Figure 70. The number of half-line cycles is specified in
the LINCYC register (Address 0x12).
The ADE5169/ADE5569 can accumulate active power for up to
65,535 half-line cycles. Because the active power is integrated
on an integral number of line cycles, the CYCEND flag (Bit 2) in
the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) is set at the
end of an active energy accumulation line cycle. If the CYCEND
enable bit (Bit 2) in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB) is set, the 8052 core has a pending ADE interrupt.
The ADE interrupt stays active until the CYCEND status bit is
cleared (see the Energy Measurement Interrupts section). Another
calibration cycle starts as soon as the CYCEND flag is set. If the
LWATTHR register (Address 0x03) is not read before a new
CYCEND flag is set, the LWATTHR register is overwritten by
a new value.
WDIV[7:0]WATTOS[15:0]
WGAIN[11:0]
LPF1
++
LWATTHR[23:0]
ACCUMULATE
ACTIVE ENERGY IN
INTERNAL RE GISTER
AND UPDATE THE
LWATTHR REGISTER
AT T H E E ND O F L INCY C
HALF-LI NE CYCLES
OUTPUT
FROM
LPF2
FROM VOLTAGE
CHANNEL
ADC
23 0
LINCYC[15:0]
48 0
%
ZERO-CROSSING
DETECTION CALIBRATION
CONTROL
TO
DIGITAL-TO-FREQUENCY
CONVERTER
07411-046
Figure 70. Line Cycle Active Energy Accumulation Mode
Data Sheet ADE5169/ADE5569
Rev. E | Page 65 of 155
When a new half-line cycle is written in the LINCYC register
(Address 0x12), the LWATTHR register (Address 0x03) is reset,
and a new accumulation starts at the next zero crossing. The
number of half-line cycles is then counted until LINCYC is
reached. This implementation provides a valid measurement at
the first CYCEND interrupt after writing to the LINCYC register
(see Figure 71). The line active energy accumulation uses the
same signal path as the active energy accumulation. The LSB
size of these two registers is equivalent.
LINCYC
VALUE
CYCE ND IRQ
LWATTHR REGISTER
07411-045
Figure 71. Energy Accumulation When LINCYC Changes
Using the information from Equation 8 and Equation 9


dtft
f
VI
dtVItE
nTnT
2cos
9.8
10
2
0
(16)
where:
n is an integer.
T is the line cycle period.
Because the sinusoidal component is integrated over an integer
number of line cycles, its value is always 0. Therefore,
0
0
nT
VIdtE (17)
E(t) = VInT (18)
Note that in this mode, the 16-bit LINCYC register can hold
a maximum value of 65,535. In other words, the line energy
accumulation mode can be used to accumulate active energy
for a maximum duration of 65,535 half-line cycles. At a 60 Hz
line frequency, the total duration of 65,535/120 Hz = 546 sec.
REACTIVE POWER CALCULATION
Reactive power, a function available for the ADE5169/ADE5569,
is defined as the product of the voltage and current waveforms
when one of these signals is phase-shifted by 90°. The resulting
waveform is called the instantaneous reactive power signal.
Equation 21 gives an expression for the instantaneous reactive
power signal in an ac system when the phase of the current
channel is shifted by 90°.
)sin(2)( tVtV (19)
)sin(2)( tItI
2
sin2)(' tItI (20)
where:
θ is the phase difference between the voltage and current channel.
V is the rms voltage.
I is the rms current.
q(t) = V(t) × I’(t) (21)
q(t) = VI sin (θ) + VI sin(2ωt + θ)
The average reactive power over an integral number of lines (n)
is given in Equation 22.
nT
VIdttq
nT
Q
0
)sin()(
1 (22)
where:
T is the line cycle period.
q is referred to as the reactive power.
Note that the reactive power is equal to the dc component of
the instantaneous reactive power signal, q(t), in Equation 21.
The instantaneous reactive power signal, q(t), is generated by
multiplying the voltage and current channels. In this case, the
phase of the current channel is shifted by 90°. The dc component of
the instantaneous reactive power signal is then extracted by a low-
pass filter to obtain the reactive power information (see Figure 72).
In addition, the phase shifting filter has a nonunity magnitude
response. Because the phase shifted filter has a large attenuation
at high frequency, the reactive power is primarily for calculation
at line frequency. The effect of harmonics is largely ignored in
the reactive power calculation. Note that, because of the magnitude
characteristic of the phase shifting filter, the weight of the reactive
power is slightly different from the active power calculation (see
the Energy Register Scaling section).
The frequency response of the LPF in the reactive signal path is
identical to the one used for LPF2 in the average active power
calculation. Because LPF2 does not have an ideal brick wall
frequency response (see Figure 65), the reactive power signal
has some ripple due to the instantaneous reactive power signal.
This ripple is sinusoidal and has a frequency equal to 2× the line
frequency. Because the ripple is sinusoidal in nature, it is removed
when the reactive power signal is integrated to calculate energy.
The reactive power signal can be read from the waveform register
by setting the WAVMODE register (Address 0x0D) and the
WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB). Like the current and voltage channels waveform
sampling modes, the waveform data is available at sample rates
of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, and 3.2 kSPS.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 66 of 155
Reactive Power Gain Calibration
Figure 72 shows the signal processing chain for the ADE5169/
ADE5569 reactive power calculation. As explained in the Reactive
Power Calculation) section, the reactive power is calculated by
applying a low-pass filter to the instantaneous reactive power
signal. Note that, when reading the waveform samples from the
output of LPF2, the gain of the reactive energy can be adjusted by
using the multiplier and by writing a twos complement, 12-bit
word to the var gain register (VARGAIN, Address 0x1E[11:0]).
Equation 23 shows how the gain adjustment is related to the
contents of the var gain register.
Output VARGAIN =
12
2
1VARGAIN
PowerReactive (23)
The resolution of the VARGAIN register is the same as the
WGAIN register (Address 0x1D) (see the Active Power Gain
Calibration section). VARGAIN can be used to calibrate the
reactive power (or energy) calculation in the ADE5169/ADE5569.
Reactive Power Offset Calibration
The ADE5169/ADE5569 also incorporate a reactive power offset
register (VAROS, Address 0x21). This is a signed, twos comple-
ment, 16-bit register that can be used to remove offsets in the
reactive power calculation (see Figure 72). An offset can exist in
the reactive power calculation due to crosstalk between channels
on the PCB or in the IC itself. The offset calibration allows the
contents of the reactive power register to be maintained at 0 when
no power is being consumed.
The 256 LSBs (VAROS = 0x0100) written to the reactive power
offset register are equivalent to 1 LSB in the WAVMODE register
(Address 0x0D).
Sign of Reactive Power Calculation
Note that the average reactive power is a signed calculation. The
phase shift filter has −90° phase shi when the integrator is enabled
and +90° phase shift when the integrator is disabled. Table 47
summarizes the relationship of the phase difference between the
voltage and the current and the sign of the resulting var calculation.
Table 47. Sign of Reactive Power Calculation
Angle Integrator Sign
0° to +90° Off Positive
−90° to 0° Off Negative
0° to +90° On Positive
−90° to 0° On Negative
Reactive Power Sign Detection
The ADE5169/ADE5569 detect a change of sign in the reactive
power. The VARSIGN flag (Bit 4) in the Interrupt Status 1 SFR
(MIRQSTL, Address 0xDC) records when a change of sign has
occurred according to the VARSIGN bit (Bit 5) in the ACCMODE
register (Address 0x0F). If the VARSIGN bit (Bit 4) is set in the
Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), the 8052 core
has a pending ADE interrupt. The ADE interrupt stays active until
the VARSIGN status bit is cleared (see the Energy Measurement
Interrupts section).
When the VARSIGN bit (Bit 5) in the ACCMODE register
(Address 0x0F) is cleared (default), a transition from positive to
negative reactive power sets the VARSIGN flag (Bit 4) in the
Interrupt Status 1 SFR (MIRQSTL, Address 0xDC).
When VARSIGN in the ACCMODE register (Address 0x0F)
is set, a transition from negative to positive reactive power sets
the VARSIGN flag in the Interrupt Status 1 SFR (MIRQSTL,
Address 0xDC).
Reactive Power No Load Detection
The ADE5169/ADE5569 include a no load threshold feature on the
reactive power that eliminates any creep effects in the meter. The
ADE5169/ADE5569 accomplish this by not accumulating reactive
energy when the multiplier output is below the no load threshold.
When the reactive power is below the no load threshold, the
RNOLOAD flag (Bit 1) in the Interrupt Status 1 SFR (MIRQSTL,
Address 0xDC) is set. If the RNOLOAD bit (Bit 1) is set in the
Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), the 8052 core
has a pending ADE interrupt. The ADE interrupt stays active until
the RNOLOAD status bit is cleared (see the Energy Measurement
Interrupts section).
The no load threshold level can be selected by setting the
VARNOLOAD bits (Bits[3:2])in the NLMODE register
(Address 0x0E). Setting these bits to 0b00 disables the no load
detection, and setting them to 0b01, 0b10, or 0b11 sets the no
load detection threshold to 0.015%, 0.0075%, and 0.0037% of
the full-scale output frequency of the multiplier, respectively.
Data Sheet ADE5169/ADE5569
Rev. E | Page 67 of 155
REACTIVE ENERGY CALCULATION
As for active energy, the ADE5169/ADE5569 achieve the integra-
tion of the reactive power signal by continuously accumulating
the reactive power signal in an internal, nonreadable, 49-bit energy
register. The reactive energy register (VARHR, Address 0x04)
represents the upper 24 bits of this internal register. The VARHR
register and its function are available in the ADE5169/ADE5569.
The discrete time sample period (T) for the accumulation register
in the ADE5169/ADE5569 is 1.22 μs (5/MCLK). As well as
calculating the energy, this integration removes any sinusoidal
components that may be in the active power signal. Figure 72
shows this discrete time integration or accumulation. The reactive
power signal in the waveform register is continuously added to
the internal reactive energy register.
The reactive energy accumulation depends on the setting of
SAVARM (Bit 2) and ABSVARM (Bit 3) in the ACCMODE
register (Address 0x0F). When both bits are cleared, the addition
is signed and, therefore, negative energy is subtracted from the
reactive energy contents. When both bits are set, the ADE5169/
ADE5569 are set to the more restrictive mode, which is the
absolute accumulation mode.
When the SAVARM bit (Bit 2) in the ACCMODE register
(Address 0x0F) is set, the reactive power is accumulated depending
on the sign of the active power. When active power is positive,
the reactive power is added as it is to the reactive energy register.
When active power is negative, the reactive power is subtracted
from the reactive energy accumulator (see the Var Antitamper
Accumulation Mode section).
When the ABSVARM bit (Bit 3) in the ACCMODE register
(Address 0x0F) is set, the absolute reactive power is used for the
reactive energy accumulation (see the Var Absolute Accumulation
Mode section).
The output of the multiplier is divided by VARDIV. If the value
in the VARDIV register (Address 0x25) is equal to 0, the internal
reactive energy register is divided by 1. VARDIV is an 8-bit,
unsigned register. After dividing by VARDIV, the reactive energy is
accumulated in a 49-bit internal energy accumulation register.
The upper 24 bits of this register are accessible through a read to
the reactive energy register (VARHR, Address 0x04[23:0]). A read
to the RVARHR register (Address 0x05) returns the contents of
the VARHR register, and the upper 24 bits of the internal register
are cleared.
As shown in Figure 72, the reactive power signal is accumulated in
an internal 49-bit, signed register. The reactive power signal can be
read from the waveform register by setting the WAVMODE reg-
ister (Address 0x0D) and setting the WFSM bit (Bit 5) in the Inter-
rupt Enable 3 SFR (MIRQENH, Address 0xDB). Like the current
and voltage channel waveform sampling modes, the waveform data
is available at sample rates of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, and
3.2 kSPS.
Figure 67 shows this energy accumulation for full-scale signals
(sinusoidal) on the analog inputs. These curves also apply to the
reactive energy accumulation.
Note that the energy register contents roll over to full-scale negative
(0x800000) and continue to increase in value when the power
or energy flow is positive. Conversely, if the power is negative,
the energy register underflows to full-scale positive (0x7FFFFF)
and continues to decrease in value.
Using the Interrupt Enable 2 SFR (MIRQENM, Address 0xDA),
the ADE5169/ADE5569 can be configured to issue an ADE
interrupt to the 8052 core when the reactive energy register is
half full (positive or negative) or when an overflow or
underflow occurs.
VARGAIN[11:0]
VARDIV[7:0]
LPF2
CURRENT
CHANNEL
VOLTAGE
CHANNEL
OUTPUT LPF2
TIME (nT)
5
MCLK
T
REACT IVE POW E R
SIGNAL
++
V
ARHR[23:0
]
UPPER 24 BITS ARE
ACCESSIBLE THROUGH
VARHR[2 3: 0] REGI STE R
23 0
48 0
WAVEFORM
REGISTER
VALUES
%
VAROS[15:0]
2
6
sgn 2
5
2
–6
2
–7
2
–8
+
+
FOR WAVEFORM
SAMPLING
HPF
PHCAL[7:0]
90° PHASE
SHIFTING FILTER
OUTPUTS FROM THE LPF2 ARE
ACCUMULAT E D (IN TEGRAT ED) IN
THE INTERNAL REACTIVE ENERGY
REGISTER
TO
DIGITAL-TO-FREQUENCY
CONVERTER
07411-047
2
Figure 72. Reactive Energy Calculation
ADE5169/ADE5569 Data Sheet
Rev. E | Page 68 of 155
Integration Time Under Steady Load—Reactive Energy
As mentioned in the Active Energy Calculation section, the
discrete time sample period (T) for the accumulation register is
1.22 μs (5/MCLK). With full-scale sinusoidal signals on the analog
inputs, and with the VARGAIN register (Address 0x1E) and the
VARDIV register (Address 0x25) set to 0x000, the integration time
before the reactive energy register overflows is calculated in
Equation 24.
Time =
min82.6sec6.40922.1
0xCCCCD
FFFF0xFFFFFFFF s (24)
When VARDIV is set to a value other than 0, the integration
time varies, as shown in Equation 25.
Time = TimeVARDIV = 0 × VARDIV (25)
Reactive Energy Accumulation Modes
Var Signed Accumulation Mode
The ADE5169/ADE5569 reactive energy default accumulation
mode is a signed accumulation based on the reactive power
information.
Var Antitamper Accumulation Mode
The ADE5169/ADE5569 are placed in var antitamper accumu-
lation mode by setting SAVARM (Bit 2) in the ACCMODE register
(Address 0x0F). In this mode, the reactive power is accumulated
depending on the sign of the active power. When the active power
is positive, the reactive power is added as it is to the reactive energy
register. When the active power is negative, the reactive power is
subtracted from the reactive energy accumulator (see Figure 73).
The CF pulse also reflects this accumulation method when in this
mode. The default setting for this mode is off. Transitions in the
direction of power flow and no load threshold are active in
this mode.
Var Absolute Accumulation Mode
The ADE5169/ADE5569 are placed in absolute accumulation
mode by setting ABSVARM (Bit 3) in the ACCMODE register
(Address 0x0F). In absolute accumulation mode, the reactive
energy accumulation is done by using the absolute reactive
power and ignoring any occurrence of power below the no load
threshold for the reactive energy (see Figure 74). The CF pulse
also reflects this accumulation method when in the absolute
accumulation mode. The default setting for this mode is off.
Transitions in the direction of power flow and no load threshold
are active in this mode.
POSPOS
INT ERRUP T ST AT US RE G I ST E RS
NEG
VARSI GN FLAG
ACT IVE POWER
NO LOAD
THRESHOLD
NO LOAD
THRESHOLD
REACTIVE ENERGY
NO LOAD
THRESHOLD
REACTI V E PO W E R
NO LOAD
THRESHOLD
07411-048
Figure 73. Reactive Energy Accumulation in
Var Antitamper Accumulation Mode
REACTIVE ENE RGY
NO LOAD
THRESHOLD
NO LOAD
THRESHOLD
REACT IVE P OWE R
0
7411-049
Figure 74. Reactive Energy Accumulation in Absolute Accumulation Mode
Data Sheet ADE5169/ADE5569
Rev. E | Page 69 of 155
Reactive Energy Pulse Output
The ADE5169/ADE5569 provide all the circuitry with a pulse
output whose frequency is proportional to reactive power (see
the Energy to Frequency Conversion section). This pulse freq-
uency output uses the calibrated signal from the VARGAIN
register output, and its behavior is consistent with the setting of
the reactive energy accumulation mode in the ACCMODE register
(Address 0x0F). The pulse output is active low and should
preferably be connected to an LED, as shown in Figure 80.
Line Cycle Reactive Energy Accumulation Mode
In line cycle reactive energy accumulation mode, the energy
accumulation of the ADE5169/ADE5569 can be synchronized
to the voltage channel zero crossing so that reactive energy can
be accumulated over an integral number of half-line cycles. The
advantages of this mode are similar to those described in the Line
Cycle Active Energy Accumulation Mode section.
In line cycle active energy accumulation mode, the ADE5169/
ADE5569 accumulate the reactive power signal in the LVARHR
register (Address 0x06) for an integral number of line cycles, as
shown in Figure 75. The number of half-line cycles is specified
in the LINCYC register (Address 0x12). The ADE5169/ADE5569
can accumulate active power for up to 65,535 half-line cycles.
Because the reactive power is integrated on an integral number
of line cycles, the CYCEND flag (Bit 2) in the Interrupt Status 3
SFR (MIRQSTH, Address 0xDE) is set at the end of a reactive
energy accumulation line cycle. If the CYCEND enable bit (Bit 2)
in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) is set,
the 8052 core has a pending ADE interrupt. The ADE interrupt
stays active until the CYCEND status bit is cleared (see the Energy
Measurement Interrupts section). Another calibration cycle starts
as soon as the CYCEND flag is set. If the LVARHR register
(Address 0x06) is not read before a new CYCEND flag is set,
the LVARHR register is overwritten by a new value.
When a new half-line cycle is written in the LINCYC register
(Address 0x12), the LVARHR register is reset, and a new accum-
ulation starts at the next zero crossing. The number of half-line
cycles is then counted internally until the value program-med in
LINCYC is reached. This implementation provides a valid
measurement at the first CYCEND interrupt after writing to the
LINCYC register. The line reactive energy accumulation uses the
same signal path as the reactive energy accumulation. The LSB
size of these two registers is equivalent.
LPF1
++
ACCUMULATE REACT IVE
ENERGY IN INTERNAL
REG IS TER A ND UPDAT E
THE L V ARHR REG IST ER
AT THE END O F LI N CYC
HAL F-LI NE CYCLES
OUTPUT
FROM
LPF2
FROM VOLTAGE
CHANNEL ADC
23 0
LINCYC[15:0]
48 0
%
ZERO-CROSSING
DETECTION
LVARHR[23:0]
CALIBRATION
CONTROL
VARDIV[7:0]VAROS[15:0]
VARGAIN[11:0]
T
O
DIGITAL-TO-FREQUENCY
CONVERTER
07411-050
Figure 75. Line Cycle Reactive Energy Accumulation Mode
ADE5169/ADE5569 Data Sheet
Rev. E | Page 70 of 155
APPARENT POWER CALCULATION
Apparent power is defined as the maximum power that can be
delivered to a load. Vrms and Irms are the effective voltage and current
delivered to the load, respectively. Therefore, the apparent power
(AP) = Vrms × Irms. This equation is independent of the phase angle
between the current and the voltage.
Equation 29 gives an expression of the instantaneous power signal
in an ac system with a phase shift.
)sin(2)( tVtV rms (26)
)sin(2)( tItI rms (27)
P(t) = V(t) × I(t) (28)
)2cos()cos( tIVIVtP rmsrmsrmsrms (29)
Figure 76 illustrates the signal processing for the calculation of the
apparent power in the ADE5169/ADE5569.
The apparent power signal can be read from the waveform register
by setting the WAVMODE register (Address 0x0D) and setting the
WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB). Like the current and voltage channel waveform
sampling modes, the waveform data is available at sample rates
of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS.
The gain of the apparent energy can be adjusted by using the
multiplier and by writing a twos complement, 12-bit word to the
VAGAIN register (VAGAIN, Address 0x1F[11:0]). Equation 30
shows how the gain adjustment is related to the contents of the
VAGAI N r e gi s te r.
Output VAGAIN =
12
2
1VAGAIN
PowerApparent (30)
For example, when 0x7FF is written to the VAGAIN register, the
power output is scaled up by 50% (0x7FF = 2048d, 2047/212 = 0.5).
Similarly, 0x800 = −2048d (signed, twos complement), and power
output is scaled by −50%. Each LSB represents 0.0244% of the
power output. The apparent power is calculated with the current
and voltage rms values obtained in the rms blocks of the
ADE5169/ADE5569.
Apparent Power Offset Calibration
Each rms measurement includes an offset compensation
register to calibrate and eliminate the dc component in the rms
value (see the Current Channel RMS Calculation section and
the Voltage Channel RMS Calculation section). The rms values
of the voltage and current channels are then multiplied together
in the apparent power signal processing. Because no additional
offsets are created in the multiplication of the rms values, there is
no specific offset compensation in the apparent power signal
processing. The offset compensation of the apparent power
measurement is determined by calibrating each individual
rms measurement.
APPARENT ENERGY CALCULATION
The apparent energy is given as the integral of the apparent power.
Apparent Energy = dttPowerApparent )( (31)
The ADE5169/ADE5569 achieve the integration of the apparent
power signal by continuously accumulating the apparent power
signal in an internal 48-bit register. The apparent energy register
(VAHR, Address 0x07) represents the upper 24 bits of this internal
register. This discrete time accumulation or summation is
equivalent to integration in continuous time. Equation 32
expresses the relationship.
0
0)(lim n
TTnTPowerApparentEnergyApparent (32)
where:
n is the discrete time sample number.
T is the discrete time sample period.
The discrete time sample period (T) for the accumulation register
in the ADE5169/ADE5569 is 1.22 μs (5/MCLK).
V
rms
I
rms
0x1A36E2
APPARENT P OWE R
SIG NAL (P)
CURRENT RMS SI GNAL – I(t )
VOLTAGE RMS SIGNAL – V(t)
0x00
0x1CF68C
0x00
0x1CF68C
VAGAIN
TO
DIGITAL-TO-FREQUENCY
CONVERTER
V
ARMSCFCON
07411-051
Figure 76. Apparent Power Signal Processing
Data Sheet ADE5169/ADE5569
Rev. E | Page 71 of 155
Figure 77 shows this discrete time integration or accumulation.
The apparent power signal is continuously added to the internal
register. This addition is a signed addition even if the apparent
energy theoretically remains positive.
The 49 bits of the internal register are divided by VADIV. If the
value in the VADIV register (Address 0x26) is 0, the internal
apparent energy register is divided by 1. VADIV is an 8-bit,
unsigned register. The upper 24 bits are then written to the 24-bit
apparent energy register (VAHR, Address 0x07[23:0]). The
RVAHR register (Address 0x08), which is 24 bits long, is provided
to read the apparent energy. This register is reset to 0 after a read
operation.
Note that the apparent energy register is unsigned. By setting
VAE HF ( Bit 2 ) and VA E O F ( B i t 5 ) i n t h e Inter r up t E n a b l e 2 S F R
(MIRQENM, Address 0xDA), the ADE5169/ADE5569 can be
configured to issue an ADE interrupt to the 8052 core when the
apparent energy register is half full or when an over flow occurs.
The half-full interrupt for the unsigned apparent energy register
is based on 24 bits, as opposed to 23 bits for the signed active
energy register.
Integration Times Under Steady Load—Apparent Energy
As mentioned in the Apparent Energy Calculation section, the
discrete time sample period (T) for the accumulation register is
1.22 μs (5/MCLK). With full-scale sinusoidal signals on the analog
inputs and the VAGAIN register (Address 0x1F) set to 0x000, the
average word value from the apparent power stage is 0x1A36E2
(see the Apparent Energy Calculation section).
The maximum value that can be stored in the apparent energy
register before it over flows is 224 or 0xFF FFFF. The average
word value is added to the internal register, which can store 248 or
0xFFFF FFFF FFFF before it overflows. Therefore, the integration
time under these conditions, with VADIV = 0, is calculated as
follows:
Time =
min33.3sec199s22.1
0xD055
FFFFFFFF,0xFFFF, (33)
When VADIV is set to a value other than 0, the integration time
varies, as shown in Equation 34.
Time = TimeVADIV = 0 × VADIV (34)
Apparent Energy Pulse Output
All the ADE5169/ADE5569 circuitry has a pulse output whose
frequency is proportional to the apparent power (see the Energy
to Frequency Conversion section). This pulse frequency output
uses the calibrated signal from the VAGAIN register. This output
can also be used to output a pulse whose frequency is
proportional to Irms.
The pulse output is active low and should preferably be connected
to an LED, as shown in Figure 80.
VADIV
APPARENT POWER
or
I
rms
+
+
V
AHR[23:0]
APPARENT POWER OR I
rms
IS
ACCUMULATED (INTE GRAT ED)
IN THE APPARENT ENERGY
REGISTER
23 0
48
0
48 0
%
TIME (nT)
T
APPARENT
POW ER SIGNAL = P
0
7411-052
Figure 77. Apparent Energy Calculation
ADE5169/ADE5569 Data Sheet
Rev. E | Page 72 of 155
Line Cycle Apparent Energy Accumulation Mode
The ADE5169/ADE5569 are designed with a special apparent
energy accumulation mode that simplifies the calibration process.
By using the on-chip, zero-crossing detection, the ADE5169/
ADE5569 accumulate the apparent power signal in the LVAHR
register (Address 0x09) for an integral number of half cycles, as
shown in Figure 78. The line cycle apparent energy accumulation
mode is always active.
The number of half-line cycles is specified in the LINCYC
register (Address 0x12), which is an unsigned 16-bit register.
The ADE5169/ADE5569 can accumulate apparent power for up
to 65,535 combined half cycles. Because the apparent power is
integrated on the same integral number of line cycles as the line
active register and reactive energy register, these values can easily
be compared. The energies are calculated more accurately because
of this precise timing control and provide all the information
needed for reactive power and power factor calculation.
At the end of an energy calibration cycle, the CYCEND flag (Bit 2)
in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) is set.
If the CYCEND enable bit (Bit 2) in the Interrupt Enable 3 SFR
(MIRQENH, Address 0xDB) is set, the 8052 core has a pending
ADE interrupt.
When a new half-line cycle is written in the LINCYC register
(Address 0x12), the LVAHR register (Address 0x09) is reset and a
new accumulation starts at the next zero crossing. The number of
half-line cycles is then counted until LINCYC is reached.
This implementation provides a valid measurement at the first
CYCEND interrupt after writing to the LINCYC register. The line
apparent energy accumulation uses the same signal path as the
apparent energy accumulation. The LSB size of these two registers
is equivalent.
Apparent Power No Load Detection
The ADE5169/ADE5569 include a no load threshold feature on
the apparent power that eliminates any creep effects in the meter.
The ADE5169/ADE5569 accomplish this by not accumulating
energy if the multiplier output is below the no load threshold.
When the apparent power is below the no load threshold, the
VANOLOAD flag (Bit 2) in the Interrupt Status 1 SFR (MIRQSTL,
Address 0xDC) is set.
If the VANOLOAD bit (Bit 2) is set in the Interrupt Enable 1
SFR (MIRQENL, Address 0xD9), the 8052 core has a pending
ADE interrupt. The ADE interrupt stays active until the
VANOLOAD status bit is cleared (see the Energy Measurement
Interrupts section).
The no load threshold level can be selected by setting the
VANOLOAD bits (Bits[5:4]) in the NLMODE register
(Address 0x0E). Setting these bits to 0b00 disables the no load
detection, and setting them to 0b01, 0b10, or 0b11 sets the no
load detection threshold to 0.030%, 0.015%, and 0.0075% of the
full-scale output frequency of the multiplier, respectively.
This no load threshold can also be applied to the Irms pulse output
when selected. In this case, the level of the no load threshold is
the same as for the apparent energy.
AMPERE-HOUR ACCUMULATION
In a tampering situation where no voltage is available to the energy
meter, the ADE5169/ADE5569 are capable of accumulating the
ampere-hours instead of apparent power into the VAHR (Address
0x07), RVAHR (Address 0x08), and LVAHR (Address 0x09)
registers. When VARMSCFCON (Bit 3) of the MODE2 register
(Address 0x0C) is set, the VAHR, RVAHR, and LVAHR registers
and the input for the digital to frequency converter accumulate
Irms instead of apparent power. All the signal processing and
calibration registers available for apparent power and energy
accumulation remain the same when ampere-hour accumulation is
selected. However, the scaling difference between Irms and apparent
power requires independent values for gain calibration in the
VAGAIN (Address 0x1F), VADIV (Address 0x26), CFxNUM
(Address 0x27 and Address 0x29), and CFxDEN (Address 0x28
and Address 0x2A) registers.
LPF1
++
LVAHR[23:0]
LV AHR REGISTE R IS
UPDATE D E V E RY L INCYC
ZE RO CROSSING WIT H T HE
TOTAL APPARE NT ENERGY
DURING THAT DURATION
FROM
VOL TAG E CHANNEL
ADC
23 0
LINCYC[15:0]
48 0
%
ZERO-CROSSING
DETECTION CALIBR
ATION
CONTROL
VADIV[7:0]
APPARENT PO WER
OR I
rms
07411-053
Figure 78. Line Cycle Apparent Energy Accumulation Mode
Data Sheet ADE5169/ADE5569
Rev. E | Page 73 of 155
ENERGY TO FREQUENCY CONVERSION
The ADE5169/ADE5569 also provide two energy to frequency
conversions for calibration purposes. After initial calibration at
manufacturing, the manufacturer or end customer often verifies
the energy meter calibration. One convenient way to do this is for
the manufacturer to provide an output frequency that is propor-
tional to the active power, reactive power, apparent power, or Irms
under steady load conditions. This output frequency can provide
a simple single-wire, optically isolated interface to external
calibration equipment. Figure 79 illustrates the energy to
frequency conversion in the ADE5169/ADE5569.
VAR*
*AVAILABL E ONLY IN THE ADE 5169 AND ADE5569.
VA
CFxSEL[1:0]
WATT
VARMSCFCON
MODE 2 RE GISTER 0x0C
I
rms
CFx PULSE
OUTPUT
CFxNUM
CFxDEN
÷
DFC
07411-054
Figure 79. Energy to Frequency Conversion
Two digital to frequency converters (DFC) are used to generate
the pulsed outputs. When WDIV = 0 or 1, the DFC generates a
pulse each time 1 LSB in the energy register is accumulated. An
output pulse is generated when a CFxNUM/CFxDEN number of
pulses are generated at the DFC output. Under steady load con-
ditions, the output frequency is proportional to the active power,
reactive power, apparent power, or Irms, depending on the
CFxSEL bits in the MODE2 register (Address 0x0C).
Both pulse outputs can be enabled or disabled by clearing or
setting the DISCF1 bit (Bit 1) and the DISCF2 bit (Bit 2) in the
MODE1 register (Address 0x0B), respectively.
Both pulse outputs set separate flags in the Interrupt Status 2 SFR
(MIRQSTM, Address 0xDD): CF1 (Bit 6) and CF2 (Bit 7). If the
CF1 enable bit (Bit 6) and CF2 enable bit (Bit 7) in the Interrupt
Enable 2 SFR (MIRQENM, Address 0xDA) are set, the 8052 core
has a pending ADE interrupt. The ADE interrupt stays active until
the CF1 or CF2 status bit is cleared (see the Energy Measurement
Interrupts section).
Pulse Output Configuration
The two pulse output circuits have separate configuration bits
in the MODE2 register (Address 0x0C). Setting the CFxSEL bits
to 0b00, 0b01, or 0b1X configures the DFC to create a pulse output
proportional to active power, reactive power, or apparent power
or Irms, respectively.
The selection between Irms and apparent power is done by the
VARMSCFCON bit (Bit 3) in the MODE2 register (Address 0x0C).
With this selection, CF2 cannot be proportional to apparent power
if CF1 is proportional to Irms, and CF1 cannot be proportional to
apparent power if CF2 is proportional to Irms.
Pulse Output Characteristic
The pulse output for both DFCs stays low for 90 ms if the pulse
period is longer than 180 ms (5.56 Hz). If the pulse period is
shorter than 180 ms, the duty cycle of the pulse output is 50%.
The pulse output is active low and should preferably be connected
to an LED, as shown in Figure 80.
V
DD
CF
07411-055
Figure 80. CF Pulse Output
The maximum output frequency with ac input signals at full
scale and CFxNUM = 0x00 and CFxDEN = 0x00 is approximately
21.1 kHz.
The ADE5169/ADE5569 incorporate two registers per DFC,
CFxNUM[15:0] and CFxDEN[15:0], to set the CFx frequency.
These unsigned, 16-bit registers can be used to adjust the CFx
frequency to a wide range of values, scaling the output frequency
by 1/216 to 1 with a step of 1/216.
If 0 is written to any of these registers, 1 is applied to the register.
The ratio of CFxNUM/CFxDEN should be <1 to ensure proper
operation. If the ratio of the CFxNUM/CFxDEN registers is >1, the
register values are adjusted to a ratio of 1. For example, if the output
frequency is 1.562 kHz, and the content of CFxDEN is 0 (0x000),
the output frequency can be set to 6.1 Hz by writing 0xFF to the
CFxDEN register.
ENERGY REGISTER SCALING
The ADE5169/ADE5569 provide measurements of active,
reactive, and apparent energy that use separate paths and filtering
for calculation. The difference in data paths can result in small
differences in LSB weight between active, reactive, and apparent
energy registers. These measurements are internally compensated
so that the scaling is nearly one to one. The relationship between
these registers is shown in Table 48.
Table 48. Energy Registers Scaling
Line Frequency = 50 Hz Line Frequency = 60 Hz Integrator
Var = 0.9952 × watt Var = 0.9949 × watt Off
VA = 0.9978 × watt VA = 1.0015 × watt Off
Var = 0.9997 × watt Var = 0.9999 × watt On
VA = 0.9977 × watt VA = 1.0015 × watt On
ADE5169/ADE5569 Data Sheet
Rev. E | Page 74 of 155
ENERGY MEASUREMENT INTERRUPTS
The energy measurement part of the ADE5169/ADE5569 has its
own interrupt vector for the 8052 core, Vector Address 0x004B (see
the Interrupt Vectors section). The bits set in the Interrupt Enable
1 SFR (MIRQENL, Address 0xD9), Interrupt Enable 2 SFR
(MIRQENM, Address 0xDA), and Interrupt Enable 3 SFR
(MIRQENH, Address 0xDB) enable the energy measurement
interrupts that are allowed to interrupt the 8052 core. If an event is
not enabled, it cannot create a system interrupt.
The ADE interrupt stays active until the status bit that created the
interrupt is cleared. The status bit is cleared when a 0 is written to
this register bit.
Data Sheet ADE5169/ADE5569
Rev. E | Page 75 of 155
TEMPERATURE, BATTERY, AND SUPPLY VOLTAGE MEASUREMENTS
The ADE5169/ADE5569 include temperature measurements as
well as battery and supply voltage measurements. These measure-
ments enable many forms of compensation. The temperature and
supply voltage measurements can be used to compensate external
circuitry. The RTC can be calibrated over temperature to ensure
that it does not drift. Supply voltage measurements allow the LCD
contrast to be maintained despite variations in voltage. Battery
measurements allow for low battery detection.
All ADC measurements are configured through the SFRs, as
shown in Table 49.
The temperature, battery, and supply voltage measurements can
be configured to continue functioning in PSM1 and PSM2 modes.
Keeping the temperature measurement active ensures that it is
not necessary to wait for the temperature measurement to settle
before using it for compensation.
Table 49. Temperature, Battery, and Supply Voltage Measurement SFRs
SFR Address R/W Mnemonic Description
0xF9 R/W STRBPER Peripheral ADC strobe period (see Table 50).
0xF3
R/W
DIFFPROG
Temperature and supply delta (see Table 51).
0xD8 R/W ADCGO Start ADC measurement (see Table 52).
0xFA R/W BAT VTH Battery detection threshold (see Table 53).
0xEF R/W VDCINADC V
DCIN
ADC value (see Table 54).
0xDF R/W BATADC Battery ADC value (see Table 55).
0xD7 R/W TEMPADC Temperature ADC value (see Table 56).
Table 50. Peripheral ADC Strobe Period SFR (STRBPER, Address 0xF9)
Bit Mnemonic Default Description
[7:6] Reserved 00 These bits must be kept at 0 for proper operation.
[5:4] VDCIN_PERIOD 00 Period for background external voltage measurements.
VDCIN_PERIOD Result
00 No V
DCIN
measurement
01 8 min
10
2 min
11 1 min
[3:2] BATT_PERIOD 00 Period for background battery level measurements.
BATT_PERIOD Result
00 No battery measurement
01 16 min
10 4 min
11 1 min
[1:0] TEMP_PERIOD 00 Period for background temperature measurements.
TEMP_PERIOD Result
00 No temperature measurement
01 8 min
10 2 min
11 1 min
ADE5169/ADE5569 Data Sheet
Rev. E | Page 76 of 155
Table 51. Temperature and Supply Delta SFR (DIFFPROG, Address 0xF3)
Bit Mnemonic Default Description
[7:6] Reserved 00 Reserved.
[5:3] TEMP_DIFF 00 Difference threshold between last temperature measurement interrupting 8052 and new
temperature measurement that should interrupt 8052.
TEMP_DIFF Result
000 No interrupt
001 1 LSB (~ 0.8°C)
010 2 LSB (~ 1.6°C)
011 3 LSB (~ 2.4°C)
100 4 LSB (~ 3.2°C)
101 5 LSB (~ 4°C)
110 6 LSB (~ 4.8°C)
111
Every temperature measurement
[2:0] VDCIN_DIFF 00 Difference threshold between the last external voltage measurement interrupting 8052 and the new
external voltage measurement that should interrupt 8052.
VDCIN_DIFF Result
000 No interrupt
001 1 LSB (~ 120 mV)
010 2 LSB (~ 240 mV)
011 3 LSB (~ 360 mV)
100 4 LSB (~ 480 mV)
101 5 LSB (~ 600 mV)
110 6 LSB (~ 720 mV)
111 Every V
DCIN
measurement
Table 52. Start ADC Measurement SFR (ADCGO, Address 0xD8)
Bit Bit Address Mnemonic Default Description
7 0xDF PLLACK 0 Set this bit to clear the PLL fault bit, PLL_FLT (Bit 4), in the PERIPH SFR (Address 0xF4).
A PLL fault is generated if a reset is caused because the PLL lost lock.
[6:3] 0xDE to 0xDB Reserved 0000 Reserved.
2 0xDA VDCIN_ADC_GO 0 Set this bit to initiate an external voltage measurement. This bit is cleared when
the measurement request is received by the ADC.
1 0xD9 TEMP_ADC_GO 0 Set this bit to initiate a temperature measurement. This bit is cleared when the
measurement request is received by the ADC.
0
0xD8
BATT_ADC_GO
0
Set this bit to initiate a battery measurement. This bit is cleared when the
measurement request is received by the ADC.
Table 53. Battery Detection Threshold SFR (BATVTH, Address 0xFA)
Bit Mnemonic Default Description
[7:0] BAT VTH 0 The battery ADC value is compared to this register, the battery detection threshold register.
If BATADC is lower than the threshold, an interrupt is generated.
Table 54. VDCINADC Value SFR (VDCINADC, Address 0xEF)
Bit Mnemonic Default Description
[7:0] VDCINADC 0 The V
DCIN
ADC value in this register is updated when an ADC interrupt occurs.
Table 55. Battery ADC Value SFR (BATADC, Address 0xDF)
Bit Mnemonic Default Description
[7:0] BATADC 0 The battery ADC value in this register is updated when an ADC interrupt occurs.
Table 56. Temperature ADC Value SFR (TEMPADC, Address 0xD7)
Bit Mnemonic Default Description
[7:0] TEMPADC 0 The temperature ADC value in this register is updated when an ADC interrupt occurs.
Data Sheet ADE5169/ADE5569
Rev. E | Page 77 of 155
TEMPERATURE MEASUREMENT
To provide a digital temperature measurement, each ADE5169/
ADE5569 includes a dedicated ADC. The 8-bit temperature
ADC value SFR (TEMPADC, Address 0xD7) holds the results
of the temperature conversion. The resolution of the temperature
measurement is 0.83°C/LSB. There are two ways to initiate a
temperature conversion: a single temperature measurement or
background temperature measurements.
Single Temperature Measurement
Set the TEMP_ADC_GO bit (Bit 1) in the start ADC measure-
ment SFR (ADCGO, Address 0xD8) to obtain a temperature
measurement (see Table 52). An interrupt is generated when the
conversion is complete and when the temperature measurement
is available in the temperature ADC value SFR (TEMPADC,
Address 0xD7).
Background Temperature Measurements
Background temperature measurements are disabled by default.
To configure the background temperature measurement mode,
set a temperature measurement interval in the peripheral ADC
strobe period SFR (STRBPER, Address 0xF9). Temperature mea-
surements are then performed periodically in the background (see
Table 50).
When a temperature conversion completes, the new temperature
ADC value is compared to the last temperature ADC value that
created an interrupt. If the absolute difference between the two
values is greater than the setting of the TEMP_DIFF bits in the
temperature and supply delta SFR (DIFFPROG, Address 0xF3[5:3]),
a TEMPADC interrupt is generated (see Table 51). This allows
temperature measurements to take place completely in the back-
ground, requiring MCU activity only if the temperature changes
more than a configurable delta.
To set up background temperature measurement
1. Initiate a single temperature measurement by setting the
TEMP_ADC_GO bit in the start ADC measurement SFR
(ADCGO, Address 0xD8[1]).
2. Upon completion of this measurement, configure the
TEMP_DIFF bits in the temperature and supppy delta SFR
(DIFFPROG, Address 0xF3[5:3]) to establish the change in
temperature that triggers an interrupt.
3. Set up the interval for background temperature measurements
by configuring the TEMP_PERIOD bits in the peripheral
ADC strobe period SFR (STRBPER, Address 0xF9[1:0]).
Temperature ADC in PSM0, PSM1, and PSM2 Modes
Depending on the operating mode of the ADE5169/ADE5569, a
temperature conversion is initiated only by certain actions.
• In PSM0 operating mode, the 8052 is active. Temperature
measurements are available in the background measurement
mode and by initiating a single measurement.
• In PSM1 operating mode, the 8052 is active, and the device
is battery powered. Single temperature measurements
can be initiated by setting the TEMP_ADC_GO bit in the
start ADC measurement SFR (ADCGO, Address 0xD8[1]).
Background temperature measurements are not available.
• In PSM2 operating mode, the 8052 is not active. Temperature
conversions are available through the background measure-
ment mode only.
The temperature ADC value SFR (TEMPADC, Address 0xD7)
is updated with a new value only when a temperature ADC
interrupt occurs.
Temperature ADC Interrupt
The temperature ADC can generate an ADC interrupt when at
least one of the following conditions occurs:
• The difference between the new temperature ADC value and
the last temperature ADC value generating an ADC interrupt
is larger than the value set in the TEMP_DIFF bits.
• The temperature ADC conversion, initiated by setting start
ADC measurement SFR (ADCGO, Address 0xD8), finishes.
When the ADC interrupt occurs, a new value is available in the
temperature ADC value SFR (T EMPADC, Address 0xD7). Note
that there is no flag associated with this interrupt.
BATTERY MEASUREMENT
To provide a digital battery measurement, each ADE5169/
ADE5569 includes a dedicated ADC. The battery measurement
is available in the 8-bit battery ADC value SFR (BATADC,
Address 0xDF). The battery measurement has a resolution of
14.6 mV/LSB. A battery conversion can be initiated by two
methods: a single battery measurement or background battery
measurements.
Single Battery Measurement
To obtain a battery measurement, set the BATT_ADC_GO bit in
the start ADC measurement SFR (ADCGO, Address 0xD8[0]).
An interrupt is generated when the conversion is done and when
the battery measurement is available in the battery ADC value SFR
(BATADC, Address 0xDF).
Background Battery Measurements
To configure background measurements for the battery, establish a
measurement interval in the peripheral ADC strobe period SFR
(STRBPER, Address 0xF9). Battery measurements are then
performed periodically in the background (see Table 50).
When a battery conversion completes, the battery ADC value is
compared to the low battery threshold, established in the battery
detection threshold SFR (BATVTH, Address 0xFA). If the battery
ADC value is below this threshold, a low battery flag is set. This
low battery flag is the FBAT bit (Bit 2) in the power management
interrupt flag SFR (IPSMF, Address 0xF8), used for power supply
management. This low battery flag can be enabled to generate
the PSM interrupt by setting the EBAT bit (Bit 2) in the power
management interrupt enable SFR (IPSME, Address 0xEC).
ADE5169/ADE5569 Data Sheet
Rev. E | Page 78 of 155
This method allows battery measurement to take place completely
in the background, requiring MCU activity only if the battery drops
below a user specified threshold. To set up background battery
measurements, follow these steps:
1. Configure the battery detection threshold SFR (BATVTH,
Address 0xFA) to establish a low battery threshold. If the
BATADC measurement is below this threshold, the FBAT bit
(Bit 2) in the power management interrupt flag SFR (IPSMF,
Address 0xF8) is set.
2. Set up the interval for background battery measurements
by configuring the BATT_PERIOD bits in the peripheral
ADC strobe period SFR (STRBPER, Adress 0xF9[3:2]).
Battery ADC in PSM0, PSM1, and PSM2 Modes
Depending on the operating mode, a battery conversion is
initiated only by certain actions.
• In PSM0 operating mode, the 8052 is active. Battery
measurements are available in the background measurement
mode and by initiating a single measurement.
• In PSM1 operating mode, the 8052 is active, and the device
is battery powered. Single battery measurements can be
initiated by setting the BATT_ADC_GO bit in the start
ADC measurement SFR (ADCGO, Address 0xD8[0]).
Background battery measurements are not available.
• In PSM2 operating mode, the 8052 is not active. Unlike
temperature and VDCIN measurements, the battery
conversions are not available in this mode.
Battery ADC Interrupt
The battery ADC can generate an ADC interrupt when at least
one of the following conditions occurs:
• The new battery ADC value is smaller than the value
set in the battery detection threshold SFR (BATVTH,
Address 0xFA), indicating a battery voltage loss.
• A single battery measurement, initiated by setting the
BATT_ADC_GO bit in the start ADC measurement SFR
(ADCGO, Address 0xD8[0]), finishes.
When the battery flag (FBAT, Bit 2) is set in the power manage-
ment interrupt flag SFR (IPSMF, Address 0xF8), a new ADC
value is available in the battery ADC value SFR (BATADC,
Address 0xDF). This battery flag can be enabled as a source of the
PSM interrupt to generate a PSM interrupt every time the battery
drops below a set voltage threshold or after a single conversion
initiated by setting the BATT_ADC_GO bit in the start ADC
measurement SFR (ADCGO, Address 0xD8[0]) is ready.
The battery ADC value SFR (BATADC, Address 0xDF) is updated
with a new value only when the battery flag (FBAT) is set in the
power management interrupt flag SFR (IPSMF, Address 0xF8).
EXTERNAL VOLTAGE MEASUREMENT
The ADE5169/ADE5569 include a dedicated ADC to provide a
digital measurement of an external voltage on the VDCIN pin. The 8-
bit VDCINADC value SFR (VDCINADC, Address 0xEF) holds the
results of the conversion. The resolution of the external voltage
measurement is 15.3 mV/LSB. There are two ways to initiate an
external voltage conversion: by using a single external voltage
measurement or through background external voltage
measurements.
Single External Voltage Measurement
To obtain an external voltage measurement, set the
VDCIN_ADC_GO bit in the start ADC measurement SFR
(ADCGO, Address 0xD8[2]). An interrupt is generated when the
conversion is done and when the external voltage measurement is
available in the VDCINADC value SFR (VDCINADC, Address 0xEF).
Background External Voltage Measurements
Background external voltage measurements are disabled by
default. To configure the background external voltage measure-
ment mode, set an external voltage measurement interval in the
peripheral ADC strobe period SFR (STRBPER, Address 0xF9).
External voltage measurements are performed periodically in
the background (see Table 50).
When an external voltage conversion is complete, the new
external voltage ADC value is compared to the last external
voltage ADC value that created an interrupt. If the absolute
difference between the two values is greater than the setting of
the VDCIN_DIFF bits in the temperature and supply delta SFR
(DIFFPROG, Address 0xF3[2:0]), a VDCINADC flag is set. This
VDCINADC flag is FVADC (Bit 3) in the power management
interrupt flag SFR (IPSMF, Address 0xF8), which is used for power
supply management. This VDCINADC flag can be enabled to
generate a PSM interrupt by setting the EVA D C bit (Bit 3) in the
power management interrupt enable SFR (IPSME, Address 0xEC).
This method allows external voltage measurements to take place
completely in the background, requiring MCU activity only if
the external voltage has changed more than a configurable delta.
To set up background external voltage measurements
1. Initiate a single external voltage measurement by setting
the VDCIN_ADC_GO bit in the start ADC measurement
SFR (ADCGO, Address 0xD8[2]).
2. Upon completion of this measurement, configure the
VDCIN_DIFF bits in the temperature and supply delta SFR
(DIFFPROG, Address 0xF3[2:0]) to establish the change
in voltage that sets the FVADC bit in the power management
interrupt flag SFR (IPSMF, Address 0xF8[3]).
3. Set up the interval for the background external voltage
measurements by configuring the VDCIN_PERIOD bits in
the peripheral ADC strobe period SFR (STRBPER,
Address 0xF9[5:4]).
Data Sheet ADE5169/ADE5569
Rev. E | Page 79 of 155
External Voltage ADC in PSM1 and PSM2 Modes
An external voltage conversion is initiated only by certain actions
that depend on the operating mode of the ADE5169/ADE5569.
• In PSM0 operating mode, the 8052 is active. External voltage
measurements are available in the background
measurement mode and by initiating a single measurement.
• In PSM1 operating mode, the 8052 is active and the device
is powered from battery. Single external voltage measurements
can be initiated by setting VDCIN_ADC_GO in the start
ADC measurement SFR (ADCGO, Address 0xD8[2]).
Background external voltage measurements are not available.
• In PSM2 operating mode, the 8052 is not active. External
voltage conversions are available through the background
measurement mode only.
The external voltage ADC in the VDCINADC value SFR
(VDCINADC, Address 0xEF) is updated with a new value
only when an external voltage ADC interrupt occurs.
External Voltage ADC Interrupt
The external voltage ADC can generate an ADC interrupt when
at least one of the following conditions occurs:
• The difference between the new external voltage ADC
value and the last external voltage ADC value generating
an ADC interrupt is larger than the value set in the
VDCIN_DIFF bits in the temperature and supply delta
SFR (DIFFPROG, Address 0xF3[2:0]).
• The external voltage ADC conversion, initiated by setting
the VDCIN_ADC_GO bit in the start ADC measurement
SFR (ADCGO, Address 0xD8[2]), finishes.
When the ADC interrupt occurs, a new value is available in the
VDCINADC value SFR (VDCINADC, Address 0xEF). Note that
there is no flag associated with this interrupt.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 80 of 155
8052 MCU CORE ARCHITECTURE
The ADE5169/ADE5569 have an 8052 MCU core and use the
8051 instruction set. Some of the standard 8052 peripherals, such
as the UART, have been enhanced. This section describes the
standard 8052 core and enhancements that have been made to it
in the ADE5169/ADE5569.
The special function register (SFR) space is mapped into the upper
128 bytes of internal data memory space and is accessed by direct
addressing only. It provides an interface between the CPU and
all on-chip peripherals. See Figure 81 for a block diagram showing
the programming model of the ADE5169/ADE5569 via the
SFR area.
All registers except the program counter (PC), instruction register
(IR), and the four general-purpose register banks reside in the
SFR area. The SFRs include control, configuration, and data
registers that provide an interface between the CPU and all on-
chip peripherals.
ENERGY
MEASUREMENT
PC
62kB ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE
PROGRAM/DATA
MEMORY
8051-COMPATIBLE
CORE
2kB XRAM OTHER ON-CHIP
PERIPHERALS:
SERIAL I/O
WDT
TIMERS
BATTERY
ADC
LCD DRIVE R
TEMPERATURE
ADC
RTC
POWER
MANAGEMENT
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
IR
256 BYT E S
GENERAL-
PURPOSE
RAM
REGISTER
BANKS
07411-056
Figure 81. Block Diagram Showing Programming Model via the SFRs
MCU REGISTERS
The registers used by the MCU are summarized in Table 57.
Table 57. 8051 SFRs
Table 58. Program Status Word SFR (PSW, Address 0xD0)
Bit Bit Address Mnemonic Description
7 0xD7 CY Carry flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
6 0xD6 AC Auxiliary carry flag. Modified by ADD and ADDC instructions.
5 0xD5 F0 General-purpose flag available to the user.
[4:3] 0xD4, 0xD3 RS1, RS0 Register bank select bits.
RS1 RS0 Selected Bank
0 0 0
0 1 1
1 0 2
1 1 3
2 0xD2 OV Overflow flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
1 0xD1 F1 General-purpose flag available to the user.
0 0xD0 P Parity bit. The number of bits set in the accumulator added to the value of the parity bit is always an
even number.
SFR Address Bit Addressable Description
ACC 0xE0 Yes Accumulator.
B 0xF0 Yes Auxiliary math.
PSW 0xD0 Yes Program status word (see Table 58).
PCON 0x87 No Program control (see Table 59).
DPL 0x82 No Data pointer low (see Table 60).
DPH 0x83 No Data pointer high (see Table 61).
DPTR 0x82 and 0x83 No Data pointer (see Table 62).
SP 0x81 No Stack pointer (see Table 63).
SPH 0xB7 No Stack pointer high (see Table 64).
STCON 0xBF No Stack boundary (see Table 65).
CFG 0xAF No Configuration (see Table 66).
Data Sheet ADE5169/ADE5569
Rev. E | Page 81 of 155
Table 59. Program Control SFR (PCON, Address 0x87)
Bit Mnemonic Default Description
7 SMOD 0 Double baud rate control.
[6:0] Reserved 0 Reserved. These bits must be kept at 0 for proper operation.
Table 60. Data Pointer Low SFR (DPL, Address 0x82)
Bit Mnemonic Default Description
[7:0] DPL 0 These bits contain the low byte of the data pointer.
Table 61. Data Pointer High SFR (DPH, Address 0x83)
Bit Mnemonic Default Description
[7:0] DPH 0 These bits contain the high byte of the data pointer.
Table 62. Data Pointer SFR (DPTR, Address 0x82 and Address 0x83)
Bit Mnemonic Default Description
[15:0] DP 0 These bits contain the 2-byte address of the data pointer. DPTR is a combination of the DPH and DPL SFRs.
Table 63. Stack Pointer SFR (SP, Address 0x81)
Bit Mnemonic Default Description
[7:0] SP 0 These bits contain the eight LSBs of the pointer for the stack.
Table 64. Stack Pointer High SFR (SPH, Address 0xB7)
Bit Mnemonic Default Description
7 Reserved 1 Reserved. This bit must be set to 1 for proper operation.
6 SBFLG 0 Stack bottom flag.
5 SSA[10] 0 Stack Starting Address Bit 10.
4 SSA[9] 0 Stack Starting Address Bit 9.
3
SSA[8]
1
Stack Starting Address Bit 8.
2 SP[10] 0 Stack Address Bit 10.
1 SP[9] 0 Stack Address Bit 9.
0 SP[8] 1 Stack Address Bit 8.
Table 65. Stack Boundary SFR (STCON, Address 0xBF)
Bit Mnemonic Default Description
[7:3] WTRLINE 0 Contains the stack waterline setting bits.
2 INT_RST 0 Interrupt/reset selection bit.
INT_RST
Result
0 An interrupt is issued when a stack violation occurs
1 A reset is issued when a stack violation occurs
1 SBE 0 Stack boundary enable bit.
0 WTRLFG 0 Waterline flag.
Table 66. Configuration SFR (CFG, Address 0xAF)
Bit Mnemonic Default Description
7 Reserved 1 Reserved. This bit should be left set for proper operation.
6 EXTEN 0 Enhanced UART enable bit.
EXTEN Result
0 Standard 8052 UART without enhanced error checking features
1 Enhanced UART with enhanced error checking (see the UART Additional Features section)
5 SCPS 0 Synchronous communication selection bit.
SCPS Result
0 I2C port is selected for control of the shared I2C/SPI (MOSI, MISO, SCLK, and SS) pins and SFRs
1 SPI port is selected for control of the shared I
2
C/SPI (MOSI, MISO, SCLK, and SS) pins and SFRs
ADE5169/ADE5569 Data Sheet
Rev. E | Page 82 of 155
Bit Mnemonic Default Description
4 MOD38EN 0 38 kHz modulation enable bit.
MOD38EN
Result
0 38 kHz modulation is disabled
1 38 kHz modulation is enabled on the pins selected by the MOD38 bits in the
EPCFG SFR (Address 0x9F[7:0])
[3:2] Reserved 00 Reserved. These bits should be kept at 0 for proper operation.
[1:0] XREN1,
XREN0
01 XREN1, XREN0 Result
XREN1 or XREN0 = 1 Enable MOVX instruction to use 256 bytes of extended RAM
XREN1 and XREN0 = 0 Disable MOVX instruction
BASIC 8052 REGISTERS
Program Counter (PC)
The program counter holds the 2-byte address of the next instruc-
tion to be fetched. The PC is initialized with 0x00 at reset and is
incremented after each instruction is performed. Note that the
amount that is added to the PC depends on the number of bytes
in the instruction; therefore, the increment can range from one
to three bytes. The program counter is not directly accessible to
the user but can be directly modified by CALL and JMP instruc-
tions that change which part of the program is active.
Instruction Register (IR)
The instruction register holds the opcode of the instruction being
executed. The opcode is the binary code that results from assem-
bling an instruction. This register is not directly accessible to
the user.
Register Banks
There are four banks, each containing an 8-byte wide register, for
a total of 32 bytes of registers. These registers are convenient for
temporary storage of mathematical operands. An instruction in-
volving the accumulator and a register can be executed in one clock
cycle, as opposed to two clock cycles, to perform an instruction
involving the accumulator and a literal or a byte of general-purpose
RAM. The register banks are located in the first 32 bytes of RAM.
The active register bank is selected by RS0 and RS1 in the
program status wo r d S F R ( P S W, Address 0xD0[4:3]).
Accumulator
The accumulator is a working register, storing the results of many
arithmetic or logical operations. The accumulator is used in more
than half of the 8052 instructions, where it is usually referred to
as A. The program status word SFR (PSW) constantly monitors the
number of bits that are set in the accumulator to determine if it
has even or odd parity. The accumulator is stored in the SFR
space (see Table 57).
B Register
The B register is used by the multiply and divide instructions,
MUL AB and DIV AB, to hold one of the operands. Because it
is not used for many instructions, it can be used as a scratch pad
register like those in the register banks. The B register is stored
in the SFR space (see Table 57).
Program Status Word (PSW)
The PSW SFR (PSW, Address 0xD0) reflects the status of
arithmetic and logical operations through carry, auxiliary carry,
and overflow flags. The parity flag reflects the parity of the contents
of the accumulator, which can be helpful for communication
protocols. The program status word SFR is bit addressable
(see Table 58).
Data Pointer (DPTR)
The data pointer SFR (DPTR, Address 0x82 and Address 0x83)
is made up of two 8-bit registers: DPL (low byte, Address 0x82),
and DPH (high byte, Address 0x83). These SFRs provide memory
addresses for internal code and data access. The DPTR can be
manipulated as a 16-bit register (DPTR = DPH, DPL) or as two
independent 8-bit registers (DPH and DPL) (see Table 60 and
Table 61).
The 8052 MCU core architecture supports dual data pointers
(see the 8052 MCU Core Architecture section).
Stack Pointer (SP)
The stack pointer SFR (SP, Address 0x81) keeps track of the
current address of the top of the stack. To push a byte of data
onto the stack, the stack pointer is incremented, and the data is
moved to the new top of the stack. To pop a byte of data off the
stack, the top byte of data is moved into the awaiting address, and
the stack pointer is decremented. The stack uses a last in, first
out (LIFO) method of data storage because the most recent
addition to the stack is the first to come off it.
The stack is used during CALL and RET instructions to keep
track of the address to move into the PC when returning from
the function call. The stack is also manipulated when vectoring
for interrupts, to keep track of the prior state of the PC.
Data Sheet ADE5169/ADE5569
Rev. E | Page 83 of 155
The stack resides in the upper part of the extended internal RAM.
The SP bits in the stack pointer SFR (S P, Address 0x81[7:0]) and the
SP bits in the stack pointer high SFR (SPH, Address 0xB7[2:0])
hold the address of the stack in the extended RAM. The advantage
of this solution is that the use of the general-purpose RAM can
be limited to data storage. The use of the extended internal RAM
can be limited to the stack or, alternatively, split between the stack
and data storage if more space is required. This separation limits
the chance of data corruption because the stack can be contained
in the upper section of the XRAM and does not overflow into
the lower section containing data. Data can still be stored in
extended RAM by using the MOVX command.
The default starting address for the stack is 0x100, electing the
upper 1792 bytes of XRAM for the stack operation. The starting
address can be reconfigured to reduce the stack by writing to the
SSA bits in the stack pointer high SFR (SPH, Address 0xB7[5:3]).
These three bits set the value of the three most significant bits of
the stack pointer. For example, setting the SSA bits to a value of
110b moves the default starting address of the stack to 0x600,
allowing the highest 512 bytes of the XRAM to be used for stack
operation. If the stack reaches the top of the XRAM and overflows,
the stack pointer rolls over to the default starting address that is
written in the SSA bits (Address 0xB7[5:3]). Care should be taken
if altering the default starting address of the stack because, should
the stack overflow or underflow, unwanted overwrite operations
may occur.
Stack Boundary Protection
As a warning signal that the stack pointer is extending outside
the specified range, a stack boundary protection feature is included.
This feature is controlled through the stack boundary SFR
(STCON, Address 0xBF) and is disabled by default. To enable
this feature, set the boundary protection enable bit (SBE, Bit 1)
in the STCON SFR.
The stack boundary protection works in two ways to protect the
remainder of the XRAM from being corrupted. The waterline
detection feature monitors the top of the stack and warns the user
when the stack pointer is reaching the overflow point. By setting
the WTRLINE bits in the STCON SFR (Address 0xBF[7:3]), the
level of the waterline below the top of the XRAM can be set. For
example, by setting STCON[7:3] to the maximum value of 0x1F,
the waterline is set to its minimum value of 0x7FF − 0x1F = 0x7F0.
Similarly, by setting STCON[7:3] to 0x1, the waterline is set at the
top of the RAM space, Address 0x7FE. Note that if STCON[7:3]
are set to 000b, the feature is effectively disabled and no interrupt
or reset is generated.
The bottom of the stack is also preserved by the stack boundary
feature. Should the stack pointer be written to a value lower than
the default stack starting address defined in Bits[5:3] of the SPH
SFR, a warning is issued and the perpetrating command is ignored.
The protection for both the waterline and the stack starting
addresses are enabled simultaneously by setting the SBE bit in
the STCON SFR (Address 0xBF[1]).
When enabled, the stack boundary protection can be configured
to either reset the device or trigger an interrupt when a stack viola-
tion occurs. The value of the INT_RST bit of the STCON SFR
(Address 0xBF[2]) determines the response of the device. When
STCON[2] is set to 0x1 and the stack pointer exceeds the waterline,
the device resets immediately, no matter what other routines are
in progress. If an attempt is made to move the stack pointer below
the default stack starting address when STCON[2] is high, a reset
also occurs. If an interrupt response is selected, the watchdog
interrupt service routine is entered, assuming that there is no
higher level interrupt currently being serviced. Note that when
STCON[1] (SBE) is enabled, an interrupt (or reset) is triggered
if the stack boundary is violated, regardless of the status of the
EA bit in the interrupt enable SFR (IE, Address 0xA8[7]). This is
because the watchdog interrupt is automatically configured as a
high priority interrupt and, therefore, is not disabled by clearing
EA. When STCON[1] is low, the feature is completely disabled,
and no pending interrupts are generated.
There are two separate flags associated with the stack boundary
protection, allowing the cause of the violation to be determined.
When the waterline is exceeded, a flag is set in WTRLFG of the
stack boundary SFR (STCON, Address 0xBF[0]), indicating that
the reset/interrupt was initiated by the stack waterline monitor.
This flag remains high until the stack pointer falls below the water-
line and the user clears the flag in software. A waterline or
watchdog reset alone does not clear the flag. To successfully clear
the flag, the software clear must occur while the stack pointer is
below the waterline.
Note that the stack pointer should never be altered while in the
interrupt service routine. Doing so causes the program to return
to a different section of the program and, therefore, malfunction.
An external reset also causes the waterline flag to reset.
When an attempt is made to move the stack pointer below the stack
starting address, a flag (SBFLG) is set in the stack pointer high
SFR (SPH, Address 0xB7[6]), indicating that the reset/interrupt was
initiated by the stack bottom monitor. Once again, a boundary or
watchdog reset alone does not clear this flag, and the user must
clear the flag in software to successfully acknowledge the event.
Note that if SPH[5:3] and SPH[2:0] are altered simultaneously
to reduce the default stack starting address, a stack violation
condition occurs when the stack boundary condition is enabled,
and SPH[6] (the stack bottom flag, SBFLG) is initiated. To avoid
this condition, it is recommended that the default stack starting
address remain at 0x100 or be increased to further up the XRAM.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 84 of 155
A useful implementation of the waterline feature is to determine
the amount of space required for the stack and allow a suitable
default starting address to be selected. This optimizes the use
of the additional XRAM space, allowing it to be used for data
storage. To obtain this information, the waterline should be set
to the estimated stack maximum and the interrupt enabled.
If the stack exceeds the estimated maximum, the interrupt is trig-
gered, and the waterline level should be increased in the interrupt
service routine. Before returning to the main program, the
waterline interrupt status flag (WTRLFG, Bit 0) of the stack
boundary SFR (STCON, Address 0xBF) should be cleared. This
program continues to jump to the waterline service routine
until the stack no longer exceeds the waterline level and the
maximum stack level is determined.
0xF
F
0x7FF
256 BYTES
OF RAM
(DATA)
0x00
{SPH[5: 3] , 0x00}
0x7FF-STCON[7:3]
2kB OF
ON-CHIP XRAM
STACK STARTING
ADDRESS
WATERLINE
0x00
07411-119
Figure 82. Extended Stack Pointer Operation
STANDARD 8052 SFRS
The standard 8052 SFRs include the accumulator (ACC), B, PSW,
DPTR, and SP SFRs, as described in the Basic 8052 Registers
section. The 8052 also defines standard timers, serial port inter-
faces, interrupts, I/O ports, and power-down modes.
Timer SFRs
The 8052 contains three 16-bit timers, the identical Timer 0 and
Timer 1, as well as a Timer 2. These timers can also function as
event counters. Timer 2 has a capture feature in which the value
of the timer can be captured in two 8-bit registers upon the
assertion of an external input signal (see the Timers section).
Serial Port SFRs
The two full-duplex serial port peripherals each require two
registers: one for setting up the baud rate and other comm-
unication parameters, and another register for the transmit/
receive buffer. The ADE5169/ADE5569 also provide enhanced
serial port functionality with a dedicated timer for baud rate
generation with a fractional divisor and additional error detection
(see the UART Serial Interface section and the UART2 Serial
Interface section.)
Interrupt SFR
A two tiered interrupt system is standard in the 8052 core. The
priority level for each interrupt source is individually selectable
as high or low. The ADE5169/ADE5569 enhance this interrupt
system by creating, in essence, a third interrupt tier for a highest
priority power supply management interrupt, PSM (see the
Interrupt System section).
I/O Port SFRs
The 8052 core supports four I/O ports, P0 through P3, where
Port 0 and Port 2 are typically used for access to external code
and data spaces. The ADE5169/ADE5569, unlike standard 8052
products, provide internal nonvolatile flash memory so that an
external code space is unnecessary. The on-chip LCD driver
requires many pins, some of which are dedicated for LCD function-
ality and others that can be configured as LCD or general-
purpose I/O. Due to the limited number of I/O pins, the ADE5169/
ADE5569 do not allow access to external code and data spaces.
The ADE5169/ADE5569 provide 20 pins that can be used for
general-purpose I/O. These pins are mapped to Port 0, Port 1, and
Port 2 and are accessed through three bit-addressable 8052 SFRs:
P0, P1, and P2. Another enhanced feature of the ADE5169/
ADE5569 is that the weak pull-ups standard on 8052 Port 1, Port 2,
and Port 3 can be disabled to make open-drain outputs, as is
standard on Port 0. The weak pull-ups can be enabled on a pin
by pin basis (see the I/O Ports section).
Power Control Register (PCON, Address 0x87)
The 8052 core defines two power-down modes: power-down
and idle. The ADE5169/ADE5569 enhance the power control
capability of the traditional 8052 MCU with additional power
management functions. The POWCON SFR (Address 0xC5) is
used to define power control specific functionality for the
ADE5169/ADE5569. The program control SFR (PCON,
Address 0x87) is not bit addressable (see the Power Management
section).
The ADE5169/ADE5569 provide many other peripherals not
standard to the 8052 core, for example
ADE energy measurement DSP
Full RTC
LCD driver
Battery switchover/power management
Temperature ADC
Battery ADC
SPI/I2C communication
Flash memory controller
Watchdog timer
Secondary UART port
Data Sheet ADE5169/ADE5569
Rev. E | Page 85 of 155
MEMORY OVERVIEW
The ADE5169/ADE5569 contain three memory blocks, as follows:
62 kB of on-chip Flash/EE program and data memory
256 bytes of general-purpose RAM
2 kB of extended internal RAM (XRAM)
The 256 bytes of general-purpose RAM share the upper 128 bytes
of its address space with the SFRs. All of the memory spaces are
shown in Figure 81. The addressing mode specifies which memory
space to access.
General-Purpose RAM
General-purpose RAM resides in Memory Location 0x00 through
Memory Location 0xFF. It contains the register banks.
11
10
01
00
RESET VALUE OF
ST ACK POI NT E R
FO UR BANKS O F EI G HT
REGISTERS R0 TO R7
BIT-ADDRESSABLE
(BIT ADDRESSES)
GENERAL-PURPOSE
AREA
BANKS
SELECTED
VIA
BITS IN PSW
0x
00
0x
08
0x
10
0x
18
0x
20
0x
30
0x
07
0x
0F
0x
17
0x
1F
0x
2F
0x
7F
0
7411-058
Figure 83. Lower 128 Bytes of Internal Data Memory
Address 0x80 through Address 0xFF of general-purpose RAM
are shared with the SFRs. The mode of addressing determines
which memory space is accessed, as shown in Figure 84.
ACCESSI BLE BY
INDIRECT ADDRESSING
ONLY
ACCESSI BLE BY
DIRECT AND
INDIRECT ADDRESSING
0×FF
GE NERAL-P U RP OS E RAM
0×00
0×80
0×7F
ACCESSIBLE BY
DIRECT ADDRESSING
ONLY
SPECIF I C FUNCTIO N REG ISTERS (S FRs)
07411-120
Figure 84. General-Purpose RAM and SFR Memory Address Overlap
Both direct and indirect addressing can be used to access general-
purpose RAM from Address 0x00 through Address 0x7F, but
indirect addressing must be used to access general-purpose
RAM with addresses in the range from 0x80 through 0xFF
because they share the same address space with the SFRs.
The 8052 core also has the means to access individual bits of
certain addresses in the general-purpose RAM and special
function memory spaces. The individual bits of general-purpose
RAM, Address 0x20 to Address 0x2F, can be accessed through
Bit Address 0x00 to Bit Address 0x7F. The benefit of bit addressing
is that the individual bits can be accessed quickly, without the
need for bit masking, which takes more code memory and
execution time. The bit addresses for General-Purpose RAM
Address 0x20 through General-Purpose RAM Address 0x2F
can be seen in Figure 85.
BYTE
A
DDRESS BIT ADDRESSES (HEXA)
0x2F
0x2E
0x2D
0x2C
0x2B
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
7F
77
6F
67
5F
57
4F
47
3F
37
2F
27
1F
17
0F
07
7E
76
6E
66
5E
56
4E
46
3E
36
2E
26
1E
16
0E
06
7D
75
6D
65
5D
55
4D
45
3D
35
2D
25
1D
15
0D
05
7C
74
6C
64
5C
54
4C
44
3C
34
2C
24
1C
14
0C
04
7B
73
6B
63
5B
53
4B
43
3B
33
2B
23
1B
13
0B
03
7A
72
6A
62
5A
52
4A
42
3A
32
2A
22
1A
12
0A
02
79
71
69
61
59
51
49
41
39
31
29
21
19
11
09
01
78
70
68
60
58
50
48
40
38
30
28
20
18
10
08
00
07411-060
Figure 85. Bit-Addressable Area of General-Purpose RAM
Bit addressing can be used for instructions that involve Boolean
variable manipulation and program branching (see the Instruction
Set section).
Special Function Registers (SFRs)
Special function registers are registers that affect the function
of the 8052 core or its peripherals. These registers are located
in RAM at Address 0x80 through Address 0xFF. They are accessible
only through direct addressing, as shown in Figure 84.
The individual bits of some of the SFRs can be accessed for use
in Boolean and program branching instructions. These SFRs are
labeled as bit addressable, and the bit addresses are given in
Table 15.
Extended Internal RAM (XRAM)
The ADE5169/ADE5569 provide 2 kB of extended on-chip
RAM. No external RAM is supported. This RAM is located in
Address 0x00 through Address 0x7FF in the extended RAM space.
To select the extended RAM memory space, the extended indirect
addressing modes are used.
2kB OF
EXT E NDE D I NT E RNAL
RAM (XRAM )
0x7F
F
0x00
07411-061
Figure 86. Extended Internal RAM (XRAM) Space
ADE5169/ADE5569 Data Sheet
Rev. E | Page 86 of 155
Code Memory
Code and data memory is stored in the 62 kB flash memory
space. No external code memory is supported. To access code
memory, code indirect addressing is used.
ADDRESSING MODES
The 8052 core provides several addressing modes. The address-
ing mode determines how the core interprets the memory location
or data value specified in assembly language code. There are six
addressing modes, as shown in Table 67.
Table 67. 8052 Addressing Modes
Addressing Mode Example Bytes
Core Clock
Cycles
Immediate MOV A, #A8h 2 2
MOV DPTR, #A8h 3 3
Direct MOV A, A8h 2 2
MOV A, IE 2 2
MOV A, R0 1 1
Indirect MOV A, @R0 1 2
Extended Direct MOVX A, @DPTR 1 4
Extended Indirect MOVX A, @R0 1 4
Code Indirect
MOVC A, @A+DPTR
1
4
MOVC A, @A+PC 1 4
JMP @A+DPTR 1 3
Immediate Addressing
In immediate addressing, the expression entered after the number
sign (#) is evaluated by the assembler and stored in the memory
address specified. This number is referred to as a literal because
it refers only to a value and not to a memory location. Instructions
using this addressing mode are slower than those between two
registers because the literal must be stored and fetched from
memory. The expression can be entered as a symbolic variable or
an arithmetic expression; the value is computed by the assembler.
Direct Addressing
With direct addressing, the value at the source address is moved
to the destination address. Direct addressing provides the fastest
execution time of all the addressing modes when an instruction
is performed between registers using direct addressing. Note that
indirect or direct addressing modes can be used to access general-
purpose RAM Address 0x00 through Address 0x7F. An instruction
with direct addressing that uses an address between 0x80 and
0xFF is referring to a special function memory location.
Indirect Addressing
With indirect addressing, the value pointed to by the register is
moved to the destination address. For example, to move the
contents of internal RAM Address 0x82 to the accumulator, use
the following two instructions, which require a total of four clock
cycles and three bytes of storage in the program memory:
MOV R0,#82h
MOV A,@R0
Indirect addressing allows addresses to be computed and is
useful for indexing into data arrays stored in RAM.
Note that an instruction that refers to Address 0x00 through
Address 0x7F is referring to internal RAM, and indirect or direct
addressing modes can be used. An instruction with indirect
addressing that uses an address between 0x80 and 0xFF is
referring to internal RAM, not to an SFR.
Extended Direct Addressing
The DPTR register is used to access extended internal RAM in
extended indirect addressing mode. The ADE5169/ADE5569
provide 2 kB of extended internal RAM (XRAM), accessed through
MOVX instructions. External memory spaces are not supported
on the ADE5169/ADE5569.
In extended direct addressing mode, the DPTR register points
to the address of the byte of extended RAM. The following code
moves the contents of extended RAM Address 0x100 to the
accumulator:
MOV DPTR,#100h
MOVX A,@DPTR
These two instructions require a total of seven clock cycles and
four bytes of storage in the program memory.
Extended Indirect Addressing
The extended internal RAM is accessed through a pointer to the
address in indirect addressing mode. The ADE5169/ADE5569
provide 2 kB of extended internal RAM, accessed through MOVX
instructions. External memory is not supported on the ADE5169/
ADE5569.
In extended indirect addressing mode, a register holds the address
of the byte of extended RAM. The following code moves the
contents of extended RAM Address 0x80 to the accumulator:
MOV R0, #80h
MOVX A, @R0
These two instructions require six clock cycles and three bytes
of storage.
Note that there are 2 kB of extended RAM, so both extended
direct and extended indirect addressing can cover the whole
address range. There is a storage and speed advantage to using
extended indirect addressing because the additional byte of
addressing available through the DPTR register that is not
needed is not stored.
From the three examples demonstrating the access of internal
RAM from 0x80 through 0xFF and extended internal RAM from
0x00 through 0xFF, it can be seen that it is most efficient to use
the entire internal RAM accessible through indirect access before
moving to extended RAM.
Data Sheet ADE5169/ADE5569
Rev. E | Page 87 of 155
Code Indirect Addressing
The internal code memory can be accessed indirectly. This can be
useful for implementing lookup tables and other arrays of constants
that are stored in flash memory. For example, to move the data
stored in flash memory at Address 0x8002 into the accumulator,
MOV DPTR,#8002h
CLR A
MOVX A,@A+DPTR
The accumulator can be used as a variable index into the array
of flash memory located at DPTR.
INSTRUCTION SET
Table 68 documents the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles,
resulting in a 4-MIPS peak performance. Note that, throughout this section, A represents the accumulator.
Table 68. Instruction Set
Mnemonic Description Bytes Cycles
Arithmetic
ADD A, Rn Add register to A 1 1
ADD A, @Ri Add indirect memory to A 1 2
ADD A, dir Add direct byte to A 2 2
ADD A, #data Add immediate to A 2 2
ADDC A, Rn 1 1 Add register to A with carry 1 1
ADDC A, @Ri
Add indirect memory to A with carry
1
2
ADDC A, dir Add direct byte to A with carry 2 2
ADDC A, #data Add immediate to A with carry 2 2
SUBB A, Rn Subtract register from A with borrow 1 1
SUBB A, @Ri Subtract indirect memory from A with borrow 1 2
SUBB A, dir Subtract direct from A with borrow 2 2
SUBB A, #data Subtract immediate from A with borrow 2 2
INC A Increment A 1 1
INC Rn Increment register 1 1
INC @Ri Ri increment indirect memory 1 2
INC dir Increment direct byte 2 2
INC DPTR Increment data pointer 1 3
DEC A Decrement A 1 1
DEC Rn Decrement register 1 1
DEC @Ri Decrement indirect memory 1 2
DEC dir Decrement direct byte 2 2
MUL AB Multiply A by B 1 9
DIV AB
Divide A by B
1
9
DA A Decimal Adjust A 1 2
Logic
ANL A, Rn AND register to A 1 1
ANL A, @Ri AND indirect memory to A 1 2
ANL A, dir AND direct byte to A 2 2
ANL A, #data AND immediate to A 2 2
ANL dir, A AND A to direct byte 2 2
ANL dir, #data AND immediate data to direct byte 3 3
ORL A, Rn OR register to A 1 1
ORL A, @Ri OR indirect memory to A 1 2
ORL A, dir OR direct byte to A 2 2
ORL A, #data OR immediate to A 2 2
ORL dir, A OR A to direct byte 2 2
ORL dir, #data
OR immediate data to direct byte
3
3
XRL A, Rn Exclusive-OR register to A 1 1
XRL A, @Ri Exclusive-OR indirect memory to A 2 2
XRL A, #data Exclusive-OR immediate to A 2 2
XRL dir, A Exclusive-OR A to direct byte 2 2
ADE5169/ADE5569 Data Sheet
Rev. E | Page 88 of 155
Mnemonic Description Bytes Cycles
XRL A, dir Exclusive-OR indirect memory to A 2 2
XRL dir, #data Exclusive-OR immediate data to direct 3 3
CLR A Clear A 1 1
CPL A Complement A 1 1
SWAP A
Swap nibbles of A
1
1
RL A Rotate A left 1 1
RLC A Rotate A left through carry 1 1
RR A Rotate A right 1 1
RRC A Rotate A right through carry 1 1
Data Transfer
MOV A, Rn Move register to A 1 1
MOV A, @Ri Move indirect memory to A 1 2
MOV Rn, A Move A to register 1 1
MOV @Ri, A
Move A to indirect memory
1
2
MOV A, dir Move direct byte to A 2 2
MOV A, #data Move immediate to A 2 2
MOV Rn, #data Move register to immediate 2 2
MOV dir, A Move A to direct byte 2 2
MOV Rn, dir
Move register to direct byte
2
2
MOV dir, Rn Move direct to register 2 2
MOV @Ri, #data Move immediate to indirect memory 2 2
MOV dir, @Ri Move indirect to direct memory 2 2
MOV @Ri, dir Move direct to indirect memory 2 2
MOV dir, dir Move direct byte to direct byte 3 3
MOV dir, #data Move immediate to direct byte 3 3
MOV DPTR, #data Move immediate to data pointer 3 3
MOVC A, @A+DPTR Move code byte relative DPTR to A 1 4
MOVC A, @A+PC Move code byte relative PC to A 1 4
MOVX A, @Ri Move external (A8) data to A 1 4
MOVX A, @DPTR Move external (A16) data to A 1 4
MOVX @Ri, A Move A to external data (A8) 1 4
MOVX @DPTR, A Move A to external data (A16) 1 4
PUSH dir Push direct byte onto stack 2 2
POP dir Pop direct byte from stack 2 2
XCH A, Rn Exchange A and register 1 1
XCH A, @Ri
Exchange A and indirect memory
1
2
XCHD A, @Ri Exchange A and indirect memory nibble 1 2
XCH A, dir Exchange A and direct byte 2 2
Boolean
CLR C Clear carry 1 1
CLR bit Clear direct bit 2 2
SETB C Set carry 1 1
SETB bit Set direct bit 2 2
CPL C Complement carry 1 1
CPL bit Complement direct bit 2 2
ANL C, bit AND direct bit and carry 2 2
ANL C, /bit AND direct bit inverse to carry 2 2
ORL C, bit OR direct bit and carry 2 2
ORL C, /bit OR Direct bit inverse to carry 2 2
MOV C, bit
Move direct bit to carry
2
2
MOV bit, C Move carry to direct bit 2 2
Data Sheet ADE5169/ADE5569
Rev. E | Page 89 of 155
Mnemonic Description Bytes Cycles
Branching
JMP @A+DPTR Jump indirect relative to DPTR 1 3
RET Return from subroutine 1 4
RETI Return from interrupt 1 4
ACALL addr11
Absolute jump to subroutine
2
3
AJMP addr11 Absolute jump unconditional 2 3
SJMP rel Short jump (relative address) 2 3
JC rel Jump on carry equal to 1 2 3
JNC rel Jump on carry = 0 2 3
JZ rel Jump on accumulator = 0 2 3
JNZ rel Jump on accumulator ≠ 0 2 3
DJNZ Rn, rel Decrement register, JNZ relative 2 3
LJMP Long jump unconditional 3 4
LCALL addr16 Long jump to subroutine 3 4
JB bit, rel Jump on direct bit = 1 3 4
JNB bit, rel Jump on direct bit = 0 3 4
JBC bit, rel Jump on direct bit = 1 and clear 3 4
CJNE A, dir, rel Compare A, direct JNE relative 3 4
CJNE A, #data, rel Compare A, immediate JNE relative 3 4
CJNE Rn, #data, rel Compare register, immediate JNE relative 3 4
CJNE @Ri, #data, rel Compare indirect, immediate JNE relative 3 4
DJNZ dir, rel
Decrement direct byte, JNZ relative
3
4
Miscellaneous
NOP No operation 1 1
READ-MODIFY-WRITE INSTRUCTIONS
Some 8052 instructions read the latch and others read the pin.
The state of the pin is read for instructions that input a port bit.
Instructions that read the latch rather than the pins are the ones
that read a value, possibly change it, and rewrite it to the latch.
Because these instructions involve modifying the port, it is
assumed that the pins being modified are outputs, so the output
state of the pin is read from the latch. This prevents a possible
misinterpretation of the voltage level of a pin. For example, if a
port pin is used to drive the base of a transistor, a 1 is written to
the bit to turn on the transistor. If the CPU reads the same port
bit at the pin rather than the latch, it reads the base voltage of
the transistor and interprets it as Logic 0. Reading the latch rather
than the pin returns the correct value of 1.
The instructions that read the latch rather than the pins are called
read-modify-write instructions and are listed in Table 69. When
the destination operand is a port or a port bit, these instructions
read the latch rather than the pin.
Table 69. Read-Modify-Write Instructions
Instruction Example Description
ANL ANL P0, A Logic AND
ORL ORL P1, A Logic OR
XRL XRL P2, A Logic XOR
JBC JBC P1.1, LABEL Jump if Bit = 1 and clear bit
CPL CPL P2.0 Complement bit
INC INC P2 Increment
DEC DEC P2 Decrement
DJNZ DJNZ P0, LABEL Decrement and jump if not zero
MOV PX.Y, C1 MOV P0.0, C Move carry to Bit Y of Port X
CLR PX.Y
1
CLR P0.0 Clear Bit Y of Port X
SETB PX.Y
1
SETB P0.0 Set Bit Y of Port X
1 These instructions read the port byte (all eight bits), modify the addressed bit, and
write the new byte back to the latch.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 90 of 155
INSTRUCTIONS THAT AFFECT FLAGS
Many instructions explicitly modify the carry bit, such as the
MOV C bit and CLR C instructions. Other instructions that
affect status flags are listed in this section.
ADD A, Source
This instruction adds the source to the accumulator. No status
flags are referenced by the instruction.
Table 70. ADD A (Source) Affected Status Flags
Flag Description
C
Set if there is a carry out of Bit 7. Cleared otherwise. Used
to indicate an overflow if the operands are unsigned.
OV Set if there is a carry out of Bit 6 or a carry out of Bit 7, but
not if both are set. Used to indicate an overflow for signed
addition. This flag is set if two positive operands yield a
negative result or if two negative operands yield a
positive result.
AC Set if there is a carry out of Bit 3. Cleared otherwise.
ADDC A, Source
This instruction adds the source and the carry bit to the accu-
mulator. The carry status flag is referenced by the instruction.
Table 71. ADDC A (Source) Affected Status Flags
Flag Description
C Set if there is a carry out of Bit 7. Cleared otherwise. Used
to indicate an overflow if the operands are unsigned.
OV Set if there is a carry out of Bit 6 or a carry out of Bit 7, but
not if both are set. Used to indicate an overflow for signed
addition. This flag is set if two positive operands yield a
negative result or if two negative operands yield a
positive result.
AC Set if there is a carry out of Bit 3. Cleared otherwise.
SUBB A, Source
This instruction subtracts the source byte and the carry (borrow)
flag from the accumulator. It references the carry (borrow)
status flag.
Table 72. SUBB A (Source) Affected Status Flags
Flag Description
C Set if there is a borrow needed for Bit 7. Cleared otherwise.
Used to indicate an overflow if the operands are unsigned.
OV Set if there is a borrow needed for Bit 6 or Bit 7, but not for
both. Used to indicate an overflow for signed subtraction.
This flag is set if a negative number subtracted from a
positive number yields a negative result or if a positive
number subtracted from a negative number yields a
positive result.
AC Set if a borrow is needed for Bit 3. Cleared otherwise.
MUL AB
This instruction multiplies the accumulator by the B SFR. This
operation is unsigned. The lower byte of the 16-bit product is
stored in the accumulator and the higher byte is left in the
B register. No status flags are referenced by the instruction.
Table 73. MUL AB Affected Status Flags
Flag Description
C Cleared.
OV Set if the result is greater than 255. Cleared otherwise.
DIV AB
This instruction divides the accumulator by the B SFR. This
operation is unsigned. The integer part of the quotient is stored
in the accumulator and the remainder goes into the B register. No
status flags are referenced by the instruction.
Table 74. DIV AB Affected Status Flags
Flag Description
C Cleared.
OV Cleared unless the B register is equal to 0, in which
case the results of the division are undefined and the
OV flag is set.
DA A
This instruction adjusts the accumulator to hold two 4-bit digits
after the addition of two binary coded decimals (BCDs) with the
ADD or ADDC instructions. If the AC bit is set or if the value of
Bit 0 to Bit 3 exceeds 9, 0x06 is added to the accumulator to cor-
rect the lower four bits. If the carry bit is set when the instruction
begins, or if 0x06 is added to the accumulator in the first step, 0x60
is added to the accumulator to correct the higher four bits.
The carry and AC status flags are referenced by this instruction.
Table 75. DA A Affected Status Flag
Flag Description
C Set if the result is greater than 0x99. Cleared otherwise.
RRC A
This instruction rotates the accumulator to the right through the
carry flag. The old LSB of the accumulator becomes the new carry
flag, and the old carry flag is loaded into the new MSB of the
accumulator.
The carry status flag is referenced by this instruction.
Table 76. RRC A Affected Status Flag
Flag Description
C Equal to the state of ACC[0] before execution of the
instruction.
Data Sheet ADE5169/ADE5569
Rev. E | Page 91 of 155
RLC A
This instruction rotates the accumulator to the left through the
carry flag. The old MSB of the accumulator becomes the new
carry flag, and the old carry flag is loaded into the new LSB of
the accumulator.
The carry status flag is referenced by this instruction.
Table 77. RLC A Affected Status Flag
Flag Description
C Equal to the state of ACC[7] before execution of the
instruction.
CJNE Destination, Source, Relative Jump
This instruction compares the source value to the destination
value and branches to the location set by the relative jump if
they are not equal. If the values are equal, program execution
continues with the instruction after the CJNE instruction.
No status flags are referenced by this instruction.
Table 78. CJNE Destination (Source, Relative Jump) Affected
Status Flag
Flag Description
C Set if the source value is greater than the destination
value. Cleared otherwise.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 92 of 155
DUAL DATA POINTERS
Each ADE5169/ADE5569 incorporates two data pointers. The
second data pointer is a shadow data pointer and is selected via
the data pointer control SFR (DPCON, Address 0xA7). DPCON
features automatic hardware post-increment and postdecrement,
as well as an automatic data pointer toggle.
Note that this is the only section of the data sheet where the
main and shadow data pointers are distinguished. Whenever the
data pointer (DPTR) is mentioned elsewhere in the data sheet,
active DPTR is implied.
In addition, only the MOVC/MOVX @DPTR instructions
automatically postincrement and postdecrement the DPTR.
Other MOVC/MOVX instructions, such as MOVC PC or
MOVC @Ri, do not cause the DPTR to automatically
postincrement and postdecrement.
To illustrate the operation of DPCON, the following code copies
256 bytes of code memory at Address 0xD000 into XRAM, starting
from Address 0x0000:
MOV DPTR,#0 ;Main DPTR = 0
MOV DPCON,#55H ;Select shadow DPTR
;DPTR1 increment mode
;DPTR0 increment mode
;DPTR auto toggling ON
MOV DPTR,#0D000H ;DPTR = D000H
MOVELOOP: CLR A
MOVC A,@A+DPTR ;Get data
;Post Inc DPTR
;Swap to Main DPTR(Data)
MOVX @DPTR,A ;Put ACC in XRAM
;Increment main DPTR
;Swap Shadow DPTR(Code)
MOV A, DPL
JNZ MOVELOOP
Table 79. Data Pointer Control SFR (DPCON, Address 0xA7)
Bit Mnemonic Default Description
7 0 Not implemented. Write don’t care.
6 DPT 0 Data pointer automatic toggle enable. Cleared by the user to disable autoswapping of the DPTR.
Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction.
[5:4] DP1m1,
DP1m0
0 Shadow data pointer mode. These bits enable extra modes of the shadow data pointer operation,
allowing more compact and more efficient code size and execution.
DP1m1 DP1m0 Result (Behavior of the Shadow Data Pointer)
0 0 8052 behavior.
0 1 DPTR is postincremented after a MOVX or MOVC instruction.
1 0 DPTR is postdecremented after a MOVX or MOVC instruction.
1 1 DPTR LSB is toggled after a MOVX or MOVC instruction. This instruction can be
useful for moving 8-bit blocks to/from 16-bit devices.
[3:2] DP0m1,
DP0m0
0 Main data pointer mode. These bits enable extra modes of the main data pointer operation, allowing
more compact and more efficient code size and execution.
DP0m1 DP0m0 Result (Behavior of the Main Data Pointer)
0 0 8052 behavior.
0 1 DPTR is postincremented after a MOVX or MOVC instruction.
1 0 DPTR is postdecremented after a MOVX or MOVC instruction.
1
1
DPTR LSB is toggled after a MOVX or MOVC instruction. This instruction is useful
for moving 8-bit blocks to/from 16-bit devices.
1 0 Not implemented. Write don’t care.
0 DPSEL 0 Data pointer select. Cleared by the user to select the main data pointer, meaning that the contents of
this 16-bit register are placed into the DPL SFR and DPH SFR. Set by the user to select the shadow data
pointer, meaning that the contents of a separate 16-bit register appear in the DPL SFR and DPH SFR.
Data Sheet ADE5169/ADE5569
Rev. E | Page 93 of 155
INTERRUPT SYSTEM
The unique power management architecture of the ADE5169/
ADE5569 includes an operating mode (PSM2) where the 8052
MCU core is shut down. Events can be configured to wake the
8052 MCU core from the PSM2 operating mode. A distinction is
drawn here between events that can trigger the wake-up of the
8052 MCU core and events that can trigger an interrupt when
the MCU core is active. Events that can wake the core are referred
to as wake-up events, whereas events that can interrupt the
program flow when the MCU is active are called interrupts. See
the 3.3 V Peripherals and Wake-Up Events section to learn more
about events that can wake the 8052 core from PSM2 mode.
The ADE5169/ADE5569 provide 12 interrupt sources with three
priority levels. The power management interrupt is at the highest
priority level. The other two priority levels are configurable through
the interrupt priority SFR (IP, Address 0xB8) and the Interrupt
Enable and Priority 2 SFR (IEIP2, Address 0xA9).
STANDARD 8052 INTERRUPT ARCHITECTURE
The 8052 standard interrupt architecture includes two tiers of
interrupts, where some interrupts are assigned a high priority
and others are assigned a low priority.
PRIORITY 1
PRIORITY 0
HIGH
LOW
07411-062
Figure 87. Standard 8052 Interrupt Priority Levels
A Priority 1 interrupt can interrupt the service routine of a
Priority 0 interrupt, and if two interrupts of different priorities
occur at the same time, the Priority 1 interrupt is serviced first.
An interrupt cannot be interrupted by another interrupt of the
same priority level. If two interrupts of the same priority level
occur simultaneously, a polling sequence is observed (see the
Interrupt Priority section).
INTERRUPT ARCHITECTURE
The ADE5169/ADE5569 possess advanced power supply man-
agement features. To ensure a fast response to time critical power
supply issues, such as a loss of line power, the power supply
management interrupt should be able to interrupt any interrupt
service routine. To enable the user to have full use of the standard
8052 interrupt priority levels, an additional priority level is added
for the power supply management (PSM) interrupt. The PSM
interrupt is the only interrupt at this highest interrupt priority level.
PRIORITY 1
PRIORITY 0
PSM
HIGH
LOW
07411-063
Figure 88. Interrupt Architecture
See the Power Supply Management (PSM) Interrupt section for
more information on the PSM interrupt.
INTERRUPT REGISTERS
The control and configuration of the interrupt system are carried out via four interrupt-related SFRs, which are discussed in this section.
Table 80. Interrupt SFRs
SFR Address Default Bit Addressable Description
IE 0xA8 0x00 Yes Interrupt enable (see Table 81).
IP 0xB8 0x00 Yes Interrupt priority (see Table 82).
IEIP2 0xA9 0xA0 No Interrupt Enable and Priority 2 (see Table 83).
WDCON 0xC0 0x10 Yes Watchdog timer (see Table 88 and the Writing to the Watchdog Timer SFR
(WDCON, Address 0XC0) section).
Table 81. Interrupt Enable SFR (IE, Address 0xA8)
Bit Bit Address Mnemonic Description
7 0xAF EA Enables all interrupt sources. Set by the user. Cleared by the user to disable all interrupt sources.
6 0xAE ETEMP Enables the temperature ADC interrupt. Set by the user.
5 0xAD ET2 Enables the Timer 2 interrupt. Set by the user.
4 0xAC ES Enables the UART serial port interrupt. Set by the user.
3 0xAB ET1 Enables the Timer 1 interrupt. Set by the user.
2 0xAA EX1 Enables the External Interrupt 1 (INT1). Set by the user.
1 0xA9 ET0 Enables the Timer 0 interrupt. Set by the user.
0 0xA8 EX0 Enables External Interrupt 0 (INT0). Set by the user.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 94 of 155
Table 82. Interrupt Priority SFR (IP, Address 0xB8)
Bit Bit Address Mnemonic Description
7 0xBF PADE ADE energy measurement interrupt priority (1 = high, 0 = low).
6 0xBE PTEMP Temperature ADC interrupt priority (1 = high, 0 = low).
5 0xBD PT2 Timer 2 interrupt priority (1 = high, 0 = low).
4 0xBC PS UART serial port interrupt priority (1 = high, 0 = low).
3 0xBB PT1 Timer 1 interrupt priority (1 = high, 0 = low).
2 0xBA PX1 INT1 (External Interrupt 1) priority (1 = high, 0 = low).
1 0xB9 PT0 Timer 0 interrupt priority (1 = high, 0 = low).
0 0xB8 PX0 INT0 (External Interrupt 0) priority (1 = high, 0 = low).
Table 83. Interrupt Enable and Priority 2 SFR (IEIP2, Address 0xA9)
Bit Mnemonic Description
7 PS2 UART2 serial port interrupt priority (1 = high, 0 = low).
6 PTI RTC interrupt priority (1 = high, 0 = low).
5 ES2 Enables the UART2 serial port interrupt. Set by the user.
4 PSI SPI/I
2
C interrupt priority (1 = high, 0 = low).
3 EADE Enables the energy metering interrupt (ADE). Set by the user.
2 ETI Enables the RTC interval timer interrupt. Set by the user.
1
EPSM
Enables the PSM power supply management interrupt. Set by the user.
0 ESI Enables the SPI/I2C interrupt. Set by the user.
INTERRUPT PRIORITY
If two interrupts of the same priority level occur simultaneously, the polling sequence is observed as shown in Table 84.
Table 84. Priority Within Interrupt Level
Source
Priority
Description
IPSM 0 (highest) Power supply management interrupt.
IRTC 1 RTC interval timer interrupt.
IADE 2 ADE energy measurement interrupt.
WDT 3 Watchdog timer overflow interrupt.
ITEMP 4 Temperature ADC interrupt.
IE0 5 External Interrupt 0.
TF0 6 Timer/Counter 0 interrupt.
IE1 7 External Interrupt 1.
TF1 8 Timer/Counter 1 interrupt.
ISPI/I2CI 9 SPI/I2C interrupt.
RI/TI 10 UART serial port interrupt.
TF2/EXF2 11 Timer/Counter 2 interrupt.
RI2/TI2
12 (lowest)
UART2 serial port interrupt.
Data Sheet ADE5169/ADE5569
Rev. E | Page 95 of 155
INTERRUPT FLAGS
The interrupt flags and status flags associated with the interrupt vectors are shown in Table 85 and Table 86, respectively. Most of the
interrupts have flags associated with them.
Table 85. Interrupt Flags1
Interrupt Source Flag Bit Name Description
IE0 TCON[1] IE0 External Interrupt 0.
TF0 TCON[5] TF0 Timer 0.
IE1 TCON[3] IE1 External Interrupt 1.
TF1 TCON[7] TF1 Timer 1.
RI + TI SCON[1] TI Transmit interrupt.
SCON[0] RI Receive interrupt.
RI2 + TI2 SCON2[1] TI2 Transmit 2 interrupt.
SCON2[0] RI2 Receive 2 interrupt.
TF2 + EXF2 T2CON[7] TF2 Timer 2 overflow flag.
T2CON[6] EXF2 Timer 2 external flag.
ITEMP (Temperature ADC) N/A N/A Temperature ADC interrupt. Does not have an interrupt flag associated with it.
IPSM (Power Supply) IPSMF[6] FPSM PSM interrupt flag.
IADE (Energy Measurement DSP) MIRQSTL[7] ADEIRQFLAG Read MIRQSTH, MIRQSTM, MIRQSTL.
1 N/A means not applicable
Table 86. Status Flags1
Interrupt Source Flag Bit Name Description
ITEMP (Temperature ADC) N/A N/A Temperature ADC interrupt. Does not have a status flag associated with it.
ISPI/I2CI SPI2CSTAT2 N/A SPI interrupt status register.
SPI2CSTAT N/A I2C interrupt status register.
IRTC (RTC Interval Timer) TIMECON[6] ALFLAG RTC alarm flag.
TIMECON[2] ITFLAG RTC interrupt flag.
WDT (Watchdog Timer) WDCON[2] WDS Watchdog timeout flag.
1 N/A means not applicable.
2 There is no specific flag for ISPI/I2CI; however, all flags for SPI2CSTAT need to be read to assess the reason for the interrupt.
A functional block diagram of the interrupt system is shown in
Figure 89. Note that the PSM interrupt is the only interrupt in
the highest priority level.
If an external wake-up event occurs to wake the ADE5169/
ADE5569 from PSM2 mode, a pending external interrupt is
generated. When the EX0 bit (Bit 0) or the EX1 bit (Bit 2) in the
interrupt enable SFR (IE, Address 0xA8) is set to enable external
interrupts, the program counter is loaded with the IE0 or IE1
interrupt vector. The IE0 and IE1 interrupt flags (Bit 1 and Bit 3,
respectively) in the Timer/Counter 0 and Timer/Counter 1 control
SFR (TCON, Address 0x88) are not affected by events that occur
when the 8052 MCU core is shut down during PSM2 mode (see
the Power Supply Management (PSM) Interrupt section).
The temperature ADC and I2C/SPI interrupts are latched such
that pending interrupts cannot be cleared without entering their
respective interrupt service routines. Clearing the I2C/SPI status
bits in the SPI interrupt status SFR (SPISTAT, Address 0xEA) does
not cancel a pending I2C/SPI interrupt.
These interrupts remain pending until the I2C/SPI interrupt
vectors are enabled. Their respective interrupt service routines
are entered shortly thereafter.
The RTC interrupts are driven by the alarm and interval flags.
Pending RTC interrupts can be cleared without entering the
interrupt service routine by clearing the corresponding RTC
flag in software. Entering the interrupt service routine alone
does not clear the RTC interrupt.
Figure 89 shows how the interrupts are cleared when the inter-
rupt service routines are entered. Some interrupts with multiple
interrupt sources are not automatically cleared, specifically, the
PSM, ADE, UART, UART2, and Timer 2 interrupt vectors. Note
that the INT0 and INT1 interrupts are cleared only if the external
interrupt is configured to be triggered by a falling edge by setting
IT0 (Bit 0) and IT1 (Bit 2) in the Timer/Counter 0 and Timer/
Counter 1 control SFR (TCON, Address 0x88). If INT0 or INT1
is configured to interrupt on a low level, the interrupt service
routine is reentered until the respective pin goes high.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 96 of 155
IPSMF FPSM
(IPSMF[6])
IPSME
INDIVIDUAL
INTERRUPT
ENABLE
IE/IEIP2 REGISTERS IP/IEIP2 REGISTERS
WATCHDOG TIMEOUT
WDIR
LOW HIGH HIGHEST
INTERVAL
ALARM
MIRQSTH MIRQSTM MIRQSTL
MIRQENH MIRQENM MIRQENL
MIRQSTL[7]
TE M P ADC I NTERRUP T
INT0
IT0
0
1IE0
TF0
INT1
IT1
0
1
TF1
CFG[5]
0
1
I
2
C INTERRUPT
SPI INT E RRUP T
RI
TI
INTERRUPT
POLLING
SEQUENCE
PSM
RTC
ADE
WATCHDOG
TEMP ADC
EXTERNAL
INTERRUPT 0
TIMER 0
EXTERNAL
INTERRUPT 1
TIMER 1
I
2
C/SPI
UART
TF2
EXF2
TIMER 2
AUTOMATIC
CLE AR SIG NAL
LEGEND
IT0
IE1
IT1
PSM2
PSM2
RI2
TI2
UART2
PRIORITY LEVEL
GLOBAL
INTERRUPT
ENABL E (EA)
IN/OUT
LATCH
RESET
IN/OUT
LATCH
RESET
07411-064
Figure 89. Interrupt System Functional Block Diagram
Data Sheet ADE5169/ADE5569
Rev. E | Page 97 of 155
INTERRUPT VECTORS
When an interrupt occurs, the program counter is pushed onto the
stack, and the corresponding interrupt vector address is loaded
into the program counter. When the interrupt service routine is
complete, the program counter is popped off the stack by a RETI
instruction. This allows program execution to resume from where
it was interrupted. The interrupt vector addresses are shown in
Table 87.
Table 87. Interrupt Vector Addresses
Source Vector Address
IE0 0x0003
TF0 0x000B
IE1 0x0013
TF1 0x001B
RI + TI 0x0023
TF2 + EXF2 0x002B
ITEMP (Temperature ADC)
0x0033
ISPI/I2CI 0x003B
IPSM (Power Supply) 0x0043
IADE (Energy Measurement DSP) 0x004B
IRTC (RTC Interval Timer) 0x0053
WDT (Watchdog Timer) 0x005B
RI2 + TI2 0x0063
INTERRUPT LATENCY
The 8052 architecture requires that at least one instruction execute
between interrupts. To ensure this, the 8052 MCU core hardware
prevents the program counter from jumping to an interrupt
service routine (ISR) immediately after completing a RETI
instruction or an access of the IP and IE SFRs.
The shortest interrupt latency is 3.25 instruction cycles, 800 ns
with a clock of 4.096 MHz. The longest interrupt latency for a
high priority interrupt results when a pending interrupt is gen-
erated during a low priority interrupt RETI, followed by a multiply
instruction. This results in a maximum interrupt latency of 16.25
instruction cycles, 4 µs with a clock of 4.096 MHz.
CONTEXT SAVING
When the 8052 vectors to an interrupt, only the program counter
is saved on the stack. Therefore, the interrupt service routine must
be written to ensure that registers used in the main program are
restored to their pre-interrupt state. Common SFRs that can be
modified in the ISR are the accumulator register and the PSW
register. Any general-purpose registers that are used as scratch
pads in the ISR should also be restored before exiting the interrupt.
The following example 8052 code shows how to restore some
commonly used registers:
GeneralISR:
; save the current accumulator value
PUSH ACC
; save the current status and register bank
selection
PUSH PSW
; service interrupt
…
; restore the status and register bank
selection
POP PSW
; restore the accumulator
POP ACC
RETI
ADE5169/ADE5569 Data Sheet
Rev. E | Page 98 of 155
WATCHDOG TIMER
The watchdog timer generates a device reset or interrupt within
a reasonable amount of time if the ADE5169/ADE5569 enter an
erroneous state, possibly due to a program-ming error or electrical
noise. The watchdog is enabled, by default, with a timeout of 2 sec
and creates a system reset if not cleared within 2 sec. The watchdog
function can be disabled by clearing the watchdog enable bit
(WDE, Bit 1) in the watchdog timer SFR (WDCON,
Address 0xC0).
The watchdog circuit generates a system reset or interrupt (WDS,
Bit 2) if the user program fails to set the WDE bit within a pre-
determined amount of time (set by the PRE bits, Bits[7:4]).
The watchdog timer is clocked from the 32.768 kHz external
crystal connected between the XTAL1 and XTAL2 pins.
The WDCON SFR can be written to by user software only if the
double write sequence described in Table 88 is initiated on every
write access to the WDCON SFR.
To prevent any code from inadvertently disabling the watchdog,
a watchdog protection can be activated. This watchdog protection
locks in the watchdog enable and event settings so they cannot
be changed by user code. The protection is activated by clearing
a watchdog protection bit in the flash memory. The watchdog
protection bit is the most significant bit at Address 0xF7FF of
the flash memory. When this bit is cleared, the WDIR bit (Bit 3) is
forced to 0, and the WDE bit is forced to 1. Note that the sequence
for configuring the flash protection bits must be followed to
modify the watchdog protection bit at Address 0xF7FF (see the
Protecting the Flash Memory section).
Table 88. Watchdog Timer SFR (WDCON, Address 0xC0)
Bit Address Mnemonic Default Description
[7:4] 0xC7 to 0xC4 PRE 7 Watchdog prescaler. In normal mode, the 16-bit watchdog timer is clocked by the input
clock (32.768 kHz). The PRE bits determine which of the upper bits of the counter are used
as the watchdog output, as follows:
1
2
2
9
XTAL
tPRE
WATCHDOG
PRE Result (Watchdog Timeout)
0000 15.6 ms
0001 31.2 ms
0010 62.5 ms
0011 125 ms
0100 250 ms
0101 500 ms
0110 1 sec
0111 2 sec
1000 0 sec, automatic reset
1001 0 sec, serial download reset
1010 to 1111 Not a valid selection
3 0xC3 WDIR 0 Watchdog interrupt response bit. When cleared, the watchdog generates a system reset
when the watchdog timeout period has expired. When set, the watchdog generates an
interrupt when the watchdog timeout period has expired.
2 0xC2 WDS 0 Watchdog status bit. This bit is set to indicate that a watchdog timeout has occurred. It is
cleared by writing a 0 or by an external hardware reset. A watchdog reset does not clear
WDS; therefore, it can be used to distinguish between a watchdog reset and a hardware
reset from the RESET pin.
1 0xC1 WDE 1 Watchdog enable bit. When set, this bit enables the watchdog and clears its counter. The
watchdog counter is subsequently cleared again whenever WDE is set. If the watchdog is
not cleared within its selected timeout period, it generates a system reset or watchdog
interrupt, depending on the WDIR bit.
0 0xC0 WDWR 0 Watchdog write enable bit (see the Writing to the Watchdog Timer SFR (WDCON, Address 0xC0)
section).
Data Sheet ADE5169/ADE5569
Rev. E | Page 99 of 155
Table 89. Watchdog and Flash Protection Byte in Flash (Flash Address = 0xF7FF)
Bit Mnemonic Default Description
7 WDPROT_PROTKY7 1 This bit holds the protection for the watchdog timer and the seventh bit of the flash protection key.
When this bit is cleared, the watchdog enable and event bits, WDE and WDIR, cannot be changed
by user code. The watchdog configuration is then fixed to WDIR = 0 and WDE = 1. The watchdog
timeout set using the PRE bits (Bits[7:4]) can still be modified by user code.
The value of this bit is also used to set the flash protection key. If this bit is cleared to protect the
watchdog, then the default value for the flash protection key is 0x7F instead of 0xFF (see the
Protecting the Flash Memory section for more information on how to clear this bit).
[6:0] PROTKY 0xFF These bits hold the flash protection key. The contents of this flash address are compared to the flash
protection key SFR (PROTKY, Address 0xBB) when the protection is being set or changed. If the two
values match, the new protection is written to the Flash Address 0x3FFF to Flash Address 0x3FFB.
See the Protecting the Flash Memory section for more information on how to configure these bits.
WRITING TO THE WATCHDOG TIMER SFR
(WDCON, ADDRESS 0xC0)
Writing data to the WDCON SFR involves a double instruction
sequence. The WDWR bit (Bit 0) must be set, and the following
instruction must be a write instruction to the WDCON SFR.
; Disable Watchdog
CLR EA
SETB WDWR
CLR WDE
SETB EA
This sequence is necessary to protect the WDCON SFR from
code execution upsets that may unintentionally modify this SFR.
Interrupts should be disabled during this operation due to the
consecutive instruction cycles.
WATCHDOG TIMER INTERRUPT
If the watchdog timer is not cleared within the watchdog timeout
period, a system reset occurs unless the watchdog timer interrupt is
enabled. The watchdog timer interrupt response bit (WDIR, Bit 3)
is located in the watchdog timer SFR (WDCON, Address 0xC0).
Enabling the WDIR bit allows the program to examine the stack
or other variables that may have led the program to execute
inappropriate code. The watchdog timer interrupt also allows
the watchdog to be used as a long interval timer.
Note that WDIR is automatically configured as a high priority
interrupt. This interrupt cannot be disabled by the EA bit (Bit 7)
in the interrupt enable SFR (IE, Address 0xA8; see Table 81). Even
if all the other interrupts are disabled, the watchdog is kept active to
watch over the program.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 100 of 155
LCD DRIVER
Using shared pins, the LCD module is capable of directly
driving an LCD panel of 17 × 4 segments without compromising
any ADE5169/ADE5569 functions. It is capable of driving LCDs
with 2×, 3×, and 4× multiplexing. The LCD wave-form voltages
generated through internal charge pump circuitry support up to
5 V LCDs. An external resistor ladder for LCD waveform voltage
generation is also supported.
Each ADE5169/ADE5569 has an embedded LCD control circuit,
driver, and power supply circuit. The LCD module is functional
in all operating modes (see the Operating Modes section) and can
store up to four different screens in memory for scrolling purposes.
LCD REGISTERS
There are eight LCD control registers that configure the driver
for the specific type of LCD in the end system and set up the user
display preferences. The LCD configuration SFR (LCDCON,
Address 0x95), LCD Configuration X SFR (LCDCONX,
Address 0x9C), and LCD Configuration Y SFR (LCDCONY,
Address 0xB1) contain general LCD driver configuration infor-
mation including the LCD enable and reset, as well as the method
of LCD voltage generation and multiplex level. The LCD clock SFR
(LCDCLK, Address 0x96) configures timing settings for LCD
frame rate and blink rate. LCD pins are configured for LCD
functionality in the LCD segment enable SFR (LCDSEGE,
Address 0x97) and the LCD Segment Enable 2 SFR (LCDSEGE2,
Address 0xED).
Table 90. LCD Driver SFRs
SFR Address R/W Mnemonic Description
0x95 R/W LCDCON LCD configuration (see Table 91).
0x96 R/W LCDCLK LCD clock (see Table 95).
0x97 R/W LCDSEGE LCD segment enable (see Table 98).
0x9C R/W LCDCONX LCD Configuration X (see Table 92).
0xAC R/W LCDPTR LCD pointer (see Table 99).
0xAE
R/W
LCDDAT
LCD data (see Table 100).
0xB1 R/W LCDCONY LCD Configuration Y (see Table 94).
0xED R/W LCDSEGE2 LCD Segment Enable 2 (see Table 101).
Table 91. LCD Configuration SFR (LCDCON, Address 0x95)
Bit Mnemonic Default Description
7 LCDEN 0 LCD enable. If this bit is set, the LCD driver is enabled.
6 LCDRST 0 LCD data registers reset. If this bit is set, the LCD data registers are reset to 0.
5 BLINKEN 0 Blink mode enable bit. If this bit is set, blink mode is enabled. The blink mode is configured by
BLKMOD (Bits[7:6]) and BLKFREQ (Bits[5:4]) in the LCD clock SFR (LCDCLK, Address 0x96).
4 LCDPSM2 0 Forces LCD off when in PSM2 (sleep) mode. Note that the internal voltage reference must be enabled by
setting REF_BAT_EN (Bit 3) in the peripheral configuration SFR (PERIPH, Address 0xF4) to allow LCD
operation in PSM2.
LCDPSM2 Result
0 The LCD is disabled or enabled in PSM2 by LCDEN (Bit 7)
1 The LCD is disabled in PSM2 regardless of LCDEN setting
3 CLKSEL 0 LCD clock selection.
CLKSEL Result
0 f
LCDCLK
= 2048 Hz
1 f
LCDCLK
= 128 Hz
2 BIAS 0 Bias mode.
BIAS
Result
0 1/2
1 1/3
[1:0] LMUX 01 LCD multiplex level.
LMUX Result
00 Reserved
01 2× multiplexing; COM3/FP27 is used as FP27, and COM2/FP28 is used as FP28
10
3× multiplexing; COM3/FP27 is used as FP27, and COM2/FP28 is used as COM2
11 4× multiplexing; COM3/FP27 is used as COM3, and COM2/FP28 is used as COM2
Data Sheet ADE5169/ADE5569
Rev. E | Page 101 of 155
Table 92. LCD Configuration X SFR (LCDCONX, Address 0x9C)
Bit Mnemonic Default Description
7 Reserved 0 Reserved.
6 EXTRES 0 External resistor ladder selection bit.
EXTRES Result
0 External resistor ladder is disabled. Charge pump is enabled
1 External resistor ladder is enabled. Charge pump is disabled
[5:0] BIASLVL 0 Bias level selection bits (see Table 93).
Table 93. LCD Bias Voltage When Contrast Control Is Enabled
BIASLVL[5] VA (V)
1/2 Bias 1/3 Bias
VB V
C V
B V
C
0
31
]0:4[BIASLVL
VREF VB = VA V
C = 2 × VA VB = 2 × VA VC = 3 × VA
1
31
]0:4[
1BIASLVL
VREF VB = VA VC = 2 × VA VB = 2 × VA VC = 3 × VA
Table 94. LCD Configuration Y SFR (LCDCONY, Address 0xB1)
Bit Mnemonic Default Description
7 AUTOSCREENSCROLL 0 When set, the four screens scroll automatically. The scrolling item is selected by the
BLKFREQ bits in the LCD clock SFR (LCDCLK, Address 0x96[5:4]). If both BLINKEN in
the LCD configuration SFR (LCDCON, Address 0x95[5]) and AUTOSCREENSCROLL
are set, this bit preempts the blinking mode.
6 INV_LVL 0 Frame inversion mode enable bit. If this bit is set, frames are inverted every other
frame. If this bit is cleared, frames are not inverted.
[5:4] Reserved 00 These bits should be kept cleared to 0 for proper operation.
[3:2] SCREEN_SEL 00 These bits select the screen that is being output on the LCD pins. Values of 0, 1, 2,
and 3 select Screen 0, Screen 1, Screen 2, and Screen 3, respectively.
1 UPDATEOVER 0 Update finished flag bit. This bit is updated by the LCD driver. When set, this bit
indicates that the LCD memory has been updated and a new frame has begun.
0 REFRESH 0 Refresh LCD data memory bit. This bit should be set by the user. When set, the
LCD driver does not use the data in the LCD data registers to update the display.
The LCD data registers can be updated by the 8052. When cleared, the LCD driver
uses the data in the LCD data registers to update the display at the next frame.
Table 95. LCD Clock SFR (LCDCLK, Address 0x96)
Bit Mnemonic Default Description
[7:6] BLKMOD 00 Blink mode clock source configuration bits.
BLKMOD Result
00 The blink rate is controlled by software; the display is off
01 The blink rate is controlled by software; the display is on
10 The blink rate is 2 Hz
11 The blink rate is set by the BLKFREQ bits
[5:4] BLKFREQ 00 Blink rate configuration bits. These bits control the LCD blink rate if BLKMOD (Bits[7:6]) = 11.
BLKFREQ Result (Blink Rate)
00 1 Hz
01 1/2 Hz
10 1/3 Hz
11 1/4 Hz
[3:0] FD 0000 LCD frame rate selection bits (see Table 96 and Table 97).
ADE5169/ADE5569 Data Sheet
Rev. E | Page 102 of 155
Table 96. LCD Frame Rate Selection for fLCDCLK = 2048 Hz (LCDCON[3] = 0)
2× Multiplexing 3× Multiplexing 4× Multiplexing
FD3 FD2 FD1 FD0 f
LCD
(Hz) Frame Rate (Hz) f
LCD
(Hz) Frame Rate (Hz) f
LCD
(Hz) Frame Rate (Hz)
0 0 0 1 256 128
1
341.3 170.7
1
512 128
1
0 0 1 0 170.7 85.3 341.3 113.8
1
341.3 85.3
0 0 1 1 128 64 256 85.3 256 64
0 1 0 0 102.4 51.2 204.8 68.3 204.8 51.2
0 1 0 1 85.3 42.7 170.7 56.9 170.7 42.7
0 1 1 0 73.1 36.6 146.3 48.8 146.3 36.6
0 1 1 1 64 32 128 42.7 128 32
1 0 0 0 56.9 28.5 113.8 37.9 113.8 28.5
1 0 0 1 51.2 25.6 102.4 34.1 102.4 25.6
1 0 1 0 46.5 23.25 93.1 31 93.1 23.25
1
0
1
1
42.7
21.35
85.3
28.4
85.3
21.35
1 1 0 0 39.4 19.7 78.8 26.3 78.8 19.7
1 1 0 1 36.6 18.3 73.1 24.4 73.1 18.3
1 1 1 0 34.1 17.05 68.3 22.8 68.3 17.05
1 1 1 1 32 16 64 21.3 64 16
0 0 0 0 16 8 32 10.7 32 8
1 Not within the range of typical LCD frame rates.
Table 97. LCD Frame Rate Selection for fLCDCLK = 128 Hz (LCDCON[3] = 1)
2× Multiplexing 3× Multiplexing 4× Multiplexing
FD3 FD2 FD1 FD0 f
LCD
(Hz) Frame Rate (Hz) f
LCD
(Hz) Frame Rate (Hz) f
LCD
(Hz) Frame Rate (Hz)
0 0 0 1 32 161 32 10.7 32 8
0 0 1 0 21.3 10.6 32 10.7 32 8
0 0 1 1 16 8 32 10.7 32 8
0 1 0 0 16 8 32 10.7 32 8
0 1 0 1 16 8 32 10.7 32 8
0 1 1 0 16 8 32 10.7 32 8
0 1 1 1 16 8 32 10.7 32 8
1
0
0
0
16
8
32
10.7
32
8
1 0 0 1 16 8 32 10.7 32 8
1 0 1 0 16 8 32 10.7 32 8
1 0 1 1 16 8 32 10.7 32 8
1 1 0 0 16 8 32 10.7 32 8
1
1
0
1
16
8
32
10.7
32
8
1 1 1 0 16 8 32 10.7 32 8
1 1 1 1 128 64 128 42.7 128 32
0 0 0 0 64 32 64 21.3 64 16
1 Not within the range of typical LCD frame rates.
Table 98. LCD Segment Enable SFR (LCDSEGE, Address 0x97)
Bit Mnemonic Default Description
7 FP25EN 0 FP25 function select bit. 0 = general-purpose I/O, 1 = LCD function.
6 FP24EN 0 FP24 function select bit. 0 = general-purpose I/O, 1 = LCD function.
5 FP23EN 0 FP23 function select bit. 0 = general-purpose I/O, 1 = LCD function.
4 FP22EN 0 FP22 function select bit. 0 = general-purpose I/O, 1 = LCD function.
3 FP21EN 0 FP21 function select bit. 0 = general-purpose I/O, 1 = LCD function.
2 FP20EN 0 FP20 function select bit. 0 = general-purpose I/O, 1 = LCD function.
[1:0] Reserved 0 These bits must be kept at 0 for proper operation.
Data Sheet ADE5169/ADE5569
Rev. E | Page 103 of 155
Table 99. LCD Pointer SFR (LCDPTR, Address 0xAC)
Bit Mnemonic Default Description
7 R/W 0 Read or write LCD bit. If this bit is set to 1, the data in the LCD data SFR (LCDDAT, Address 0xAE)
is written to the address indicated by the ADDRESS bits (LCDPTR[3:0]).
6 Reserved 0 Reserved.
[5:4] RAM2SCREEN 0 These bits select the screen recipient of the data memory action.
[3:0] ADDRESS 0 LCD memory address (see Table 102).
Table 100. LCD Data SFR (LCDDAT, Address 0xAE)
Bit Mnemonic Default Description
[7:0] LCDDATA 0 Data to be written into or read out of the LCD memory SFRs.
Table 101. LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED)
Bit Mnemonic Default Description
[7:4] Reserved 0 Reserved.
3 FP19EN 0 FP19 function select bit. 0 = general-purpose I/O, 1 = LCD function.
2 FP18EN 0 FP18 function select bit. 0 = general-purpose I/O, 1 = LCD function.
1 FP17EN 0 FP17 function select bit. 0 = general-purpose I/O, 1 = LCD function.
0 FP16EN 0 FP16 function select bit. 0 = general-purpose I/O, 1 = LCD function.
LCD SETUP
The LCD configuration SFR (LCDCON, Address 0x95) configures
the LCD module to drive the type of LCD in the user end system.
The BIAS bit (Bit 2) and the LMUX bits (Bits[1:0]) in this SFR
should be set according to the LCD specifications.
The COM2/FP28 and COM3/FP27 pins default to LCD segment
lines. Selecting the 3× multiplex level in the LCD configuration SFR
(LCDCON, Address 0x95) by setting LMUX[1:0] to 10 changes the
FP28 pin functionality to COM2. The 4× multiplex level selection,
LMUX[1:0] = 11, changes the FP28 pin functionality to COM2
and the FP27 pin functionality to COM3.
The LCD segments of FP0 to FP15 are enabled by default. Addi-
tional pins are selected for LCD functionality in the LCD segment
enable SFR (LCDSEGE, Address 0x97) and LCD Segment Enable 2
SFR (LCDSEGE2, Address 0xED), where there are individual
enable bits for the FP16 to FP25 segment pins. The LCD pins do
not need to be enabled sequentially. For example, if the Timer 2
input, which is the alternate function of FP23, is required, any of
the other shared pins, FP16 to FP25 for the ADE5169 and FP16
to FP26 for the ADE5569, can be enabled instead.
The Display Element Control section contains details about setting
up the LCD data memory to turn individual LCD segments on
and off. Setting the LCDRST bit (Bit 6) in the LCD configuration
SFR (LCDCON, Address 0x95) resets the LCD data memory to
its default (0). A power-on reset also clears the LCD data memory.
LCD TIMING AND WAVEFORMS
An LCD segment acts like a capacitor that is charged and dis-
charged at a certain rate. This rate, the refresh rate, determines the
visual characteristics of the LCD. A slow refresh rate results in
the LCD blinking on and off between refreshes. A fast refresh rate
presents a screen that appears to be continuously lit. In addition, a
faster refresh rate consumes more power.
The frame rate, or refresh rate, for the LCD module is derived
from the LCD clock, fLCDCLK. The LCD clock is selected as 2048 Hz
or 128 Hz by the CLKSEL bit (Bit 3) in the LCD configuration
SFR (LCDCON, Address 0x95). The minimum refresh rate needed
for the LCD to appear solid (without blinking) is independent of
the multiplex level.
The LCD waveform frequency, fLCD, is the frequency at which the
LCD switches the active common line. Thus, the LCD waveform
frequency depends heavily on the multiplex level. The frame rate
and LCD waveform frequency are set by fLCDCLK, the multiplex
level, and the FD frame rate selection bits in the LCD clock SFR
(LCDCLK, Address 0x96[3:0]).
The LCD module provides 16 different frame rates for fLCDCLK =
2048 Hz, ranging from 8 Hz to 128 Hz for an LCD with 4× multi-
plexing. Fewer options are available with fLCDCLK = 128 Hz, ranging
from 8 Hz to 32 Hz for a 4× multiplexed LCD. The 128 Hz clock
is beneficial for battery operation because it consumes less power
than the 2048 Hz clock. The frame rate is set by the FD bits in
the LCD clock SFR (LCDCLK, Address 0x96[3:0]); see Table 96
and Table 97.
The LCD waveform is inverted at twice the LCD waveform fre-
quency, fLCD. This way, each frame has an average dc offset of 0.
ADC offset degrades the lifetime and performance of the LCD.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 104 of 155
BLINK MODE
Blink mode is enabled by setting the BLINKEN bit (Bit 5) in the
LCD configuration SFR (LCDCON, Address 0x95). This mode
is used to alternate between the LCD on state and LCD off state
so that the LCD screen appears to blink. There are two blink
modes: a software controlled blink mode and an automatic
blink mode.
Software Controlled Blink Mode
The LCD blink rate can be controlled by user code by toggling
the BLKMOD bits (Bits[7:6]) in the LCD clock SFR (LCDCLK,
Address 0x96) to turn the display on and off at a rate that is
determined by the MCU code.
Automatic Blink Mode
There are five blink rates. These blink rates are selected by the
BLKMOD bits (Bits[7:6]) and the BLKFREQ bits (Bits[5:4]) in
the LCD clock SFR (LCDCLK, Address 0x96); see Table 95.
SCROLLING MODE
The ADE5169/ADE5569 can store up to four screens in
memory. The LCD driver can use any of these screens by setting
the SCREEN_SEL bits (Bits[3:2]) in the LCD Configuration Y SFR
(LC D C ONY, Address 0xB1) and clearing the refresh bit (Bit 0)
in the same register. The software scrolling of the screens can then
be achieved by a one-command instruction.
Automatic Scrolling Mode
The ADE5169/ADE5569 provide automatic scrolling between the
screens using the five available blink rates. Setting the AUTO-
SCREENSCROLL bit (Bit 7) in the LCD Configuration Y SFR
(LCDCONY, Address 0xB1), as well as the BLINKEN bit (Bit 5)
in the LCD configuration SFR (LCDCON, Address 0x95) enables
this mode. To allow the scrolling frequency to be selected, the
BLKMOD bits (Bits[7:6]) in the LCD clock SFR (LCDCLK,
Address 0x96) should both be set to 1. The scrol-ling rates are then
selected by the BLKFREQ bits (Bits[5:4]) in the LCD clock SFR
(LCDCLK, Address 0x96); see Table 95. Automatic scrolling mode
is available in all operating modes.
DISPLAY ELEMENT CONTROL
Four banks of 15 bytes of data memory located in the LCD module
control the on or off state of each segment of the LCD. The LCD
data memory is stored in Address 0 through Address 14 in the
LCD module, with two extra bits defining which one of the four
screens is being addressed.
Each byte configures the on and off states of two segment lines.
The LSBs store the state of the even numbered segment lines, and
the MSBs store the state of the odd numbered segment lines. For
example, LCD Data Address 0 refers to segment Line 1 and Line 0
(see Table 102). Note that the LCD data memory is maintained
in the PSM2 operating mode.
The LCD data memory is accessed indirectly through the LCD
pointer SFR (LCDPTR, Address 0xAC) and LCD data SFR
(LCDDAT, Address 0xAE). Moving a value to the LCDPTR SFR
selects the LCD screen and data byte to be accessed and initiates
a read or write operation (see Table 99).
Table 102. LCD Data Memory Accessed Indirectly Through LCD Pointer SFR (LCDPTR, Address 0xAC) and LCD Data SFR
(LCDDAT, Address 0xAE)1, 2, 3
LCD Pointer SFR (LCDPTR, Address 0xAC) LCD Data SFR (LCDDAT, Address 0xAE)
LCD Memory Address COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
0x0E N/A N/A N/A N/A FP28 FP28 FP28 FP28
0x0D
FP27
FP27
FP27
FP27
N/A
N/A
N/A
N/A
0x0C FP25 FP25 FP25 FP25 FP24 FP24 FP24 FP24
0x0B FP23 FP23 FP23 FP23 FP22 FP22 FP22 FP22
0x0A FP21 FP21 FP21 FP21 FP20 FP20 FP20 FP20
0x09 FP19 FP19 FP19 FP19 FP18 FP18 FP18 FP18
0x08
FP17
FP17
FP17
FP17
FP16
FP16
FP16
FP16
0x07 FP15 FP15 FP15 FP15 FP14 FP14 FP14 FP14
0x06 FP13 FP13 FP13 FP13 FP12 FP12 FP12 FP12
0x05 FP11 FP11 FP11 FP11 FP10 FP10 FP10 FP10
0x04 FP9 FP9 FP9 FP9 FP8 FP8 FP8 FP8
0x03 FP7 FP7 FP7 FP7 FP6 FP6 FP6 FP6
0x02 FP5 FP5 FP5 FP5 FP4 FP4 FP4 FP4
0x01 FP3 FP3 FP3 FP3 FP2 FP2 FP2 FP2
0x00 FP1 FP1 FP1 FP1 FP0 FP0 FP0 FP0
1 COMx designates the common lines.
2 FPx designates the segment lines.
3 N/A means not applicable.
Data Sheet ADE5169/ADE5569
Rev. E | Page 105 of 155
Writing to LCD Data Registers
To update the LCD data memory, first set the LSB of the LCD
Configuration Y SFR (LCDCONY, Address 0xB1) to freeze the
data being displayed on the LCD while updating it. This operation
ensures that the data displayed on the screen does not change while
the data is being changed. Then, move the data to the LCD data
SFR (LCDDAT, Address 0xAE) prior to accessing the LCD
pointer SFR (LCDPTR, Address 0xAC). The address of the LCD
screen should be consistent with the data changed. When the MSB
of the LCD pointer SFR (LCDPTR, Address 0xAC) is set, the
contents of the LCD data SFR (LCDDAT, Address 0xAE) are
transferred to the internal LCD data memory designated by the
address in the LCD pointer SFR (LCDPTR, Address 0xAC) and
the screen designator. Clear the LSB of the LCD Configuration Y
SFR (LCDCONY, Address 0xB1) when all of the data memory has
been updated to allow the use of the new LCD setup for display.
Sample 8052 code to update the segments attached to Pin FP10
and Pin FP11 on Screen 1 is as follows:
ORL LCDCONY,#01h ;start updating the data
MOV LCDDAT,#FFh
MOV LCDPTR,#80h OR 05h
ANL LCDCONY,#0FEh ;update finished
Reading LCD Data Registers
When the MSB of the LCD pointer SFR (LCDPTR, Address 0xAC)
is cleared, the contents of the LCD data memory of the correspond-
ing screen designated by LCDPTR are transferred to the LCD data
SFR (LCDDAT, Address 0xAE).
Sample 8052 code to read the contents of LCD Data Memory
Address 0x07 on Screen 1, which holds the on and off state of
the segments attached to FP14 and FP15, is as follows:
MOV LCDPTR,#07h
MOV R1, LCDDAT
VOLTAGE GENERATION
The ADE5169/ADE5569 provide two ways to generate the LCD
waveform voltage levels. The on-chip charge pump option can
generate 5 V. This makes it possible to use 5 V LCDs with the 3.3 V
ADE5169/ADE5569. There is also an option to use an external
resistor ladder with a 3.3 V LCD. The EXTRES bit (Bit 6) in the
LCD Configuration X SFR (LCDCONX, Address 0x9C) selects
the resistor ladder or charge pump option.
When selecting how to generate the LCD waveform voltages,
the following should be considered:
• Lifetime performance power consumption
• Contrast control
Lifetime Performance Power Consumption
In most LCDs, a high amount of current is required when the LCD
waveforms change state. The external resistor ladder option draws a
constant amount of current, whereas the charge pump circuitry
allows dynamic current consumption. If the LCD module is used
with the internal charge pump option when the display is disabled,
the voltage generation is disabled so that no power is consumed by
the LCD function. This feature results in significant power savings
if the display is turned off during battery operation.
Contrast Control
The electrical characteristics of the liquid in the LCD change
over temperature. This requires adjustments in the LCD waveform
voltages to ensure a readable display. An added benefit of the
internal charge pump voltage generation is a configurable bias
voltage that can be compensated over temperature and supply
to maintain contrast on the LCD. These compensations can be
performed based on the ADE5169/ADE5569 temperature and
supply voltage measurements (see the Temperature, Battery, and
Supply Voltage Measurements section). This dynamic contrast
control is not easily implemented with external resistor ladder
voltage generation.
The LCD bias voltage sets the contrast of the display when the
charge pump provides the LCD waveform voltages. The ADE5169/
ADE5569 provide 64 bias levels selected by the BIASLVL bits
(Bits[5:0]) in the LCD Configuration X SFR (LCDCONX,
Address 0x9C). The voltage level on LCDVA, LCDVB, and LCDVC
depends on the internal voltage reference value (VREF), BIASLVL
selection, and the biasing selected, as described in Table 93.
Lifetime Performance
DC offset on a segment degrades its performance over time.
The voltages generated through the internal charge pump switch
faster than those generated by the external resistor ladder, reducing
the likelihood of a dc voltage being applied to a segment and
increasing the lifetime of the LCD.
LCD EXTERNAL CIRCUITRY
The voltage generation selection is made by the EXTRES bit (Bit 6)
in the LCD Configuration X SFR (LCDCONX, Address 0x9C).
This bit is cleared by default for charge pump voltage generation,
but it can be set to enable an external resistor ladder.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 106 of 155
Charge Pump
Voltage generation through the charge pump requires external
capacitors to store charge. The external connections to LCDVA,
LCDVB, and LCDVC, as well as to LCDVP1 and LCDVP2, are
shown in Figure 90.
LCDVC
LCDVB
LCDVA
LCDVP1
LCDVP2
CHARGE PUM P
AND
LCD WAV E F ORM
CIRCUITRY 100nF
470nF
470nF
470nF
07411-065
Figure 90. External Circuitry for Charge Pump Option
External Resistor Ladder
Set the EXTRES bit (Bit 6) in the LCD Configuration X SFR
(LCDCONX, Address 0x9C) to enable the external resistor ladder
option. When EXTRES = 1, the LCD waveform voltages are sup-
plied by the external resistor ladder. Because the LCD voltages
are not generated on chip, the LCD bias compensation that is
implemented to maintain contrast over temperature and
supply is not possible.
The external circuitry needed for the resistor ladder option is
shown in Figure 91. The resistors required should be in the range
of 10 kΩ to 100 kΩ and should be based on the current required
by the LCD being used.
LCDVC
LCDVB
LCDVA
LCDVP1
LCDVP2
LCD WAVEFORM
CIRCUITRY
07411-066
Figure 91. External Circuitry for External Resistor Ladder Option
LCD FUNCTION IN PSM2 MODE
LCDPSM2 (Bit 4) and LCDEN (Bit 7) in the LCD configuration
SFR (LCDCON, Address 0x95) control the LCD functionality
in the PSM2 operating mode (see Table 103).
Note that the internal voltage reference must be enabled by set-
ting REF_BAT_EN (Bit 3) in the peripheral configuration SFR
(PERIPH, Address 0xF4) to allow LCD operation in PSM2 mode
(see Table 20).
Table 103. Bits Controlling LCD Functionality in PSM2 Mode
LCDPSM2 LCDEN Result
0 0 The display is off in PSM2.
0 1 The display is on in PSM2.
1 X The display is off in PSM2.
In addition, note that the LCD configuration and data memory
are retained when the display is turned off.
Example LCD Setup
An example of how to set up the LCD peripheral for a specific
LCD is described in this section with the following parameters:
Type of LCD: 5 V, 4× multiplexed with 1/3 bias, 96 segments
Voltage generation: internal charge pump
Refresh rate: 64 Hz
A 96-segment LCD with 4× multiplexing requires 96/4 = 24
segment lines. Sixteen pins, FP0 to FP15, are automatically
dedicated for use as LCD segments. Eight more pins must be
chosen for the LCD function. Because the LCD has 4× multi-
plexing, all four common lines are used. As a result, COM2/FP28
and COM3/FP27 cannot be used as segment lines. Based on the
alternate functions of the pins used for FP16 through FP25, FP16 to
FP23 are chosen for the eight remaining segment lines. These pins
are enabled for LCD functionality in the LCD segment enable SFR
(LCDSEGE, Address 0x97) and the LCD Segment Enable 2 SFR
(LCDSEGE2, Address 0xED).
To determine the contrast setting for this 5 V LCD, see Table 93
for the BIASLVL bit settings in the LCD Configuration X SFR
(LCDCONX, Address 0x9C) that correspond to a VC of 5 V in
1/3 bias mode. The maximum bias level setting for this LCD is
BIASLVL = 101110.
The LCD is set up with the following 8052 code:
; set up LCD pins to have LCD functionality
MOV LCDSEGE,#FP20EN+FP21EN+FP22EN+FP23EN
MOV LCDSEGE2,#FP16EN+FP17EN+FP18EN+FP19EN
; set up LCDCON for fLCDCLK = 2048Hz, 1/3 bias
and 4x multiplexing
MOV LCDCON,#BIAS+LMUX1+LMUX0
; set up LCDCONX for charge pump and
BIASLVL[110111]
MOV
LCDCONX,#BIASLVL5+BIASLVL4+BIASLVL3+BI
ASLVL2+BIASLVL1+BIASLVL0
; set up refresh rate for 64Hz with fLCDCLK =
2048 Hz
MOV LCDCLK,#FD3+FD2+FD1+FD0
; set up LCD data registers with data to be
displayed using
; LCDPTR and LCDDAT registers
; turn all segments on FP27 ON
ORL LCDCONY,#01h ; start data memory
refresh
MOV LCDDAT,#F0H
MOV LCDPTR, #80h OR 0DH
ANL LCDCONY,#0FEh ; end of data memory
refresh
ORL LCDCON,#LCDEN ; enable LCD
To set up the same 3.3 V LCD for use with an external resistor
ladder,
; setup LCDCONX for external resistor ladder
MOV LCDCONX,#EXTRES
Data Sheet ADE5169/ADE5569
Rev. E | Page 107 of 155
FLASH MEMORY
FLASH MEMORY OVERVIEW
Flash memory is a type of nonvolatile memory that is in-circuit
programmable. The default, erased state of a byte of flash memory
is 0xFF. When a byte of flash memory is programmed, the required
bits change from 1 to 0. The flash memory must be erased to turn
the 0s back to 1s. A byte of flash memory cannot, however, be
erased individually. The entire segment, or page, of flash memory
that contains the byte must be erased.
The ADE5169/ADE5569 provide 62 bytes of flash program/
information memory. This memory is segmented into 124 pages
that each contain 512 bytes. To reprogram one byte of flash
memory, the other 511 bytes in that page must be erased. The
flash memory can be erased by page or all at once in a mass erase.
There is a command to verify that a flash write operation has
completed successfully. The ADE5169/ADE5569 flash memory
controller also offers configurable flash memory protection.
The 62 bytes of flash memory are provided on chip to facilitate
code execution without any external discrete ROM device require-
ments. The program memory can be programmed in circuit, using
the serial download mode provided or using conventional third-
party memory programmers.
Flash/EE Memory Reliability
The flash memory arrays on the ADE5169/ADE5569 are fully
qualified for two key Flash/EE memory characteristics: Flash/EE
memory cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. In real
terms, a single endurance cycle is composed of four independent,
sequential events, as follows:
1. Initial page erase sequence
2. Read/verify sequence
3. Byte program sequence
4. Second read/verify sequence
In reliability qualification, every byte in both the program and
data Flash/EE memory is cycled from 0x00 to 0xFF until a first
fail is recorded, signifying the endurance limit of the on-chip
Flash/EE memory.
As indicated in Table 4, the ADE5169/ADE5569 flash memory
endurance qualification has been carried out in accordance with
JEDEC Standard 22 Method A117 over the industrial temperature
range of −40°C, +25°C, +85°C, and +125°C. The results allow the
specification of a minimum endurance figure over supply and
temperature of 100,000 cycles, with a minimum endurance figure
of 20,000 cycles of operation at 25°C.
Retention is the ability of the flash memory to retain its
programmed data over time. Again, the devices have been
qualified in accordance with the formal retention lifetime
specification, JEDEC Standard 22 Method A117, at a specific
junction temperature (TJ = 55°C). As part of this qualification
procedure, the flash memory is cycled to its specified endurance
limit, as described previously, before data retention is charac-
terized. This means that the flash memory is guaranteed to retain
its data for its full specified retention lifetime every time the
flash memory is reprogrammed. It should also be noted that
retention lifetime, based on an activation energy of 0.6 eV, derates
with TJ, as shown in Figure 92.
40 60 70 90
T
J
JUNCTION TEM P ERATURE (° C)
RETENTION
(Years)
250
200
150
100
50
050 80 110
300
100
ANALOG D E V ICES
SPECIFICATION
100 YEARS MIN.
AT T
J
= 55
°
C
07411-067
Figure 92. Flash/EE Memory Data Retention
FLASH MEMORY ORGANIZATION
The ADE5169/ADE5569 contain a 64 kB array of Flash/EE
program memory. The upper 2 kB contain permanently embedded
firmware, allowing in circuit serial download, serial debug, and
nonintrusive single pin emulation. The 2 kB of embedded firmware
also contain essential coefficients that provide calibration to
peripherals such as the ADCs and reference. The embedded
firmware contained in the upper 2 kB of Flash/EE memory is
not accessible by the user.
EMBEDDED DOWNL OAD/ DEBUG KE RNEL
PERMANE NTL Y E MBE DDE D FIRMWARE AL LOWS
CODE TO BE DO WNL O ADE D T O ANY O F THE
62 kB O F ON-CHIP PROGRAM MEM ORY.
THE KERNE L P ROGRAM AP PE ARS AS NO P
INSTRUCT I ONS T O USER CODE.
62 kB OF FLAS H/EE P ROG RAM M E M O RY
ARE AVAI L ABLE T O T HE US E R. ALL OF T HI S
SPACE CAN BE PROG RAMM E D FROM T HE
PERMANE NTL Y E M BEDDE D DO WNL O AD/DEBUG
KERNEL OR IN P ARAL LEL P ROGRAM M I NG MO DE .
USER PROG RAM M EM ORY
0×FFFF
2kB
0×F800
0×F7FF
62kB
0×0000
07411-229
Figure 93. Flash Memory Organization
ADE5169/ADE5569 Data Sheet
Rev. E | Page 108 of 155
The lower 62 bytes are available to the user for program storage
or as nonvolatile data memory. They are segmented into 124 pages
of 512 bytes each. It is up to the user to decide which flash memory
pages are to be used for data memory. It is recommended that
each page be dedicated solely to program or data memory so
that an instance does not arise where the program counter is
loaded with data memory instead of an opcode from the program
memory or where program memory is erased to update a byte
of data memory.
The flash memory can be protected from read or write/erase access.
The protection is implemented in the upper page of user program
memory. The last sixteen bytes from this page are used to confi-
gure the write/erase protection for each of the pages. The four
bytes that remain are used for configuring read protection of
the flash memory. The read protection is selected in groups of
four pages. Finally, there is a byte used to store the key required
for modifying the protection scheme. If any code protection is
required, the page of information memory must be write/erase
protected at a minimum.
Thus, it is recommended that if code protection is enabled, the
last page of user accessible flash memory be used only to store
data that does not need modification in the field. If the firmware
requires protection and may need updating in the future, the
last page should be reserved for constants used by the user code
that do not require modification during emulation or debug.
Page 0 through Page 122 are, therefore, available for general
program and data memory use. It is recommended that Page 123
be used for constants or code that do not require future modifica-
tions. Note that the last 20 bytes of Page 123 are reserved for the
flash memory protection and are, therefore, unavailable to the user.
USING THE FLASH MEMORY
The 62 bytes of flash memory are configured as 124 pages, each
comprising 512 bytes. As with the other ADE5169/ADE5569
peripherals, the interface to this memory space is via a group of
registers mapped in the SFR space. The flash data SFR (EDATA,
Address 0xBC), holds the byte of data to be accessed. The byte of
flash memory is addressed via the flash high byte address SFR
(EADRH, Address 0xC7) and the flash low byte address SFR
(EADRL, Address 0xC6).
Table 104. Flash SFRs
SFR Address Default
Bit
Addressable Description
ECON 0xB9 0x00 No Flash control
FLSHKY 0xBA 0xFF No Flash key
PROTKY 0xBB 0xFF No Flash
protection key
EDATA 0xBC 0x00 No Flash data
EADRL 0xC6 0x00 No Flash low byte
address
EADRH 0xC7 0x00 No Flash high byte
address
ECON is an 8-bit flash control SFR (Address 0xB9) that can be
written to with one of five flash memory access commands to
trigger various read, write, erase, and verify functions. Figure 94
demonstrates the steps required for access to the flash memory.
EADRH
FLSHKY
EADRL
ADDRESS ADDRESS
DECODER
FL S HKY = 0x3B?
PROTECTION
DECODER
ECON
COMMAND
ACCESS
ALLOWED?
FLASH
PROTECTION KEY
TRUE: ACCE S S
ALLOWED
ECON = 0
FALSE: ACCESS
DENIE D
ECON = 1
07411-069
Figure 94. Flash Memory Read/Write/Erase Protection Block Diagram
Data Sheet ADE5169/ADE5569
Rev. E | Page 109 of 155
0x3E00
0x3DFF
0x3C00
0x3BFF
0x3A00
0x39FF
0x3800
0x37FF
0x3600
0x35FF
0x3400
0x33FF
0x3200
0x31FF
0x3000
0x2FFF
0x2E00
0x2DFF
0x2C00
0x2BFF
0x2A00
0x29FF
0x2800
0x27FF
0x2600
0x25FF
0x2400
0x23FF
0x2200
0x21FF
0x2000
0x3FFF
READ
PROTECT
BIT 7
READ
PROTECT
BIT 6
READ
PROTECT
BIT 5
READ
PROTECT
BIT 4
PAGE 30
PAGE 29
PAGE 28
PAGE 27
PAGE 26
PAGE 25
PAGE 24
PAGE 23
PAGE 22
PAGE 21
PAGE 20
PAGE 19
PAGE 18
PAGE 17
PAGE 16
PAGE 31 0x1E00
0x1DFF
0x1C00
0x1BFF
0x1A00
0x19FF
0x1800
0x17FF
0x1600
0x15FF
0x1400
0x13FF
0x1200
0x11FF
0x1000
0x0FFF
0x0E00
0x0DFF
0x0C00
0x0BFF
0x0A00
0x09FF
0x0800
0x07FF
0x0600
0x05FF
0x0400
0x03FF
0x0200
0x01FF
0x0000
0x1FFF
READ
PROTECT
BIT 3
READ
PROTECT
BIT 2
READ
PROTECT
BIT 1
READ
PROTECT
BIT 0
PAGE 14
PAGE 13
PAGE 12
PAGE 11
PAGE 10
PAGE 9
PAGE 8
PAGE 7
PAGE 6
PAGE 5
PAGE 4
PAGE 3
PAGE 2
PAGE 1
PAGE 0
PAGE 15
0x7E00
0x7DFF
0x7C00
0x7BFF
0x7A00
0x79FF
0x7800
0x77FF
0x7600
0x75FF
0x7400
0x73FF
0x7200
0x71FF
0x7000
0x6FFF
0x6E00
0x6DFF
0x6C00
0x6BFF
0x6A00
0x69FF
0x6800
0x67FF
0x6600
0x65FF
0x6400
0x63FF
0x6200
0x61FF
0x6000
0x7FFF
CONTAINS PROTECTION SETTINGS
READ
PROTECT
BIT 15
READ
PROTECT
BIT 14
READ
PROTECT
BIT 13
READ
PROTECT
BIT 12
PAGE 62
PAGE 61
PAGE 60
PAGE 59
PAGE 58
PAGE 57
PAGE 56
PAGE 55
PAGE 54
PAGE 53
PAGE 52
PAGE 51
PAGE 50
PAGE 49
PAGE 48
PAGE 63 0x5E00
0x5DFF
0x5C00
0x5BFF
0x5A00
0x59FF
0x5800
0x57FF
0x5600
0x55FF
0x5400
0x53FF
0x5200
0x51FF
0x5000
0x4FFF
0x4E00
0x4DFF
0x4C00
0x4BFF
0x4A00
0x49FF
0x4800
0x47FF
0x4600
0x45FF
0x4400
0x43FF
0x4200
0x41FF
0x4000
0x5FFF
READ
PROTECT
BIT 11
READ
PROTECT
BIT 10
READ
PROTECT
BIT 9
READ
PROTECT
BIT 8
PAGE 46
PAGE 45
PAGE 44
PAGE 43
PAGE 42
PAGE 41
PAGE 40
PAGE 39
PAGE 38
PAGE 37
PAGE 36
PAGE 35
PAGE 34
PAGE 33
PAGE 32
PAGE 47
07411-068
0xBE00
0xBDFF
0xBC00
0xBBFF
0xBA00
0xB9FF
0xB800
0xB7FF
0xB600
0xB5FF
0xB400
0xB3FF
0xB200
0xB1FF
0xB000
0xAFFF
0xAE00
0xADFF
0xAC00
0xABFF
0xAA00
0xA9FF
0xA800
0xA7FF
0xA600
0xA5FF
0xA400
0xA3FF
0xA200
0xA1FF
0xA000
0xBFFF
READ
PROTECT
BIT 23
READ
PROTECT
BIT 22
READ
PROTECT
BIT 21
READ
PROTECT
BIT 20
PAGE 94
PAGE 93
PAGE 92
PAGE 91
PAGE 90
PAGE 89
PAGE 88
PAGE 87
PAGE 86
PAGE 85
PAGE 84
PAGE 83
PAGE 82
PAGE 81
PAGE 80
PAGE 95 0x9E00
0x9DFF
0x9C00
0x9BFF
0x9A00
0x99FF
0x9800
0x97FF
0x9600
0x95FF
0x9400
0x93FF
0x9200
0x91FF
0x9000
0x8FFF
0x8E00
0x8DFF
0x8C00
0x8BFF
0x8A00
0x89FF
0x8800
0x87FF
0x8600
0x85FF
0x8400
0x83FF
0x8200
0x81FF
0x8000
0x9FFF
READ
PROTECT
BIT 19
READ
PROTECT
BIT 18
READ
PROTECT
BIT 17
READ
PROTECT
BIT 16
PAGE 78
PAGE 77
PAGE 76
PAGE 75
PAGE 74
PAGE 73
PAGE 72
PAGE 71
PAGE 70
PAGE 69
PAGE 68
PAGE 67
PAGE 66
PAGE 65
PAGE 64
PAGE 79
0xF7FF
0xF600
0xF5FF
0xF400
0xF3FF
0xF200
0xF1FF
0xF000
0xEFFF
0xEE00
0xEDFF
0xEC00
0xEBFF
0xEA00
0xE9FF
0xE800
0xE7FF
0xE600
0xE5FF
0xE400
0xE3FF
0xE200
0xE1FF
0xE000
READ
PROTECT
BIT 30
READ
PROTECT
BIT 29
READ
PROTECT
BIT 28
PAGE 123
PAGE 122
PAGE 121
PAGE 120
PAGE 119
PAGE 118
PAGE 117
PAGE 116
PAGE 115
PAGE 114
PAGE 113
PAGE 112
0xDE00
0xDDFF
0xDC00
0xDBFF
0xDA00
0xD9FF
0xD800
0xD7FF
0xD600
0xD5FF
0xD400
0xD3FF
0xD200
0xD1FF
0xD000
0xCFFF
0xCE00
0xCDFF
0xCC00
0xCBFF
0xCA00
0xC9FF
0xC800
0xC7FF
0xC600
0xC5FF
0xC400
0xC3FF
0xC200
0xC1FF
0xC000
0xDFFF
READ
PROTECT
BIT 27
READ
PROTECT
BIT 26
READ
PROTECT
BIT 25
READ
PROTECT
BIT 24
PAGE 110
PAGE 109
PAGE 108
PAGE 107
PAGE 106
PAGE 105
PAGE 104
PAGE 103
PAGE 102
PAGE 101
PAGE 100
PAGE 99
PAGE 98
PAGE 97
PAGE 96
PAGE 111
Figure 95. Flash Memory Organization
ADE5169/ADE5569 Data Sheet
Rev. E | Page 110 of 155
ECON—Flash Control SFR
Programming the flash memory is done through the flash control
SFR (ECON, Address 0xB9). This SFR allows the user to read,
write, erase, or verify the 62 kB of flash memory. As a method
of security, a key must be written to the flash key SFR (FLSHKY,
Address 0xBA) to initiate any user access to the flash memory.
Upon completion of the flash memory operation, the FLSHKY
SFR is reset so that it must be written to before another flash
memory operation. Requiring the key to be set before an access
to the flash memory decreases the likelihood of user code or data
being overwritten by a runaway program.
The program counter, PC, is held on the instruction where
the ECON SFR is written to until the flash memory controller
finishes the requested operation. Then the PC increments to con-
tinue with the next instruction. Any interrupt requests that occur
while the flash controller is performing an operation are not
handled until the flash operation is complete. All peripherals,
such as timers and counters, continue to operate as configured
throughout the flash memory access.
Table 105. Flash Control SFR (ECON, Address 0xB9)
Bit Mnemonic Default Value Description
[7:0] ECON 0 1 Write byte. The value in the EDATA SFR (Address 0xBC) is written to the flash memory, at the
page address given by EADRH (Address 0xC7) and EADRL (Address 0xC6). Note that the byte
being addressed must be pre-erased.
2 Erase page. A 512-byte page of flash memory address is erased. The page is selected by the
address in the EADRH and EADRL SFRs. Any address in the page can be written to EADRH and
EADRL to select it for erasure.
3 Erase all. All 62 kB of the available flash memory are erased. Note that this command is used
during serial mode and parallel download mode but should not be executed by user code.
4 Read byte. The byte in the flash memory, addressed by EADRH and EADRL, is read into EDATA.
5 Reserved.
6 Reserved.
7 Reserved.
8 Protect code (see the Protecting the Flash Memory section).
Table 106. Flash Key SFR (FLSHKY, Address 0xBA)
Bit Mnemonic Default Description
[7:0] FLSHKY 0xFF The contents of this SFR are compared to the flash key, 0x3B. If the two values match, the next ECON SFR
operation is allowed (see the Protecting the Flash Memory section).
Table 107. Flash Protection Key SFR (PROTKY, Address 0xBB)
Bit Mnemonic Default Description
[7:0] PROTKY 0xFF The contents of this SFR are compared to the flash memory location at Address 0xF7EB. If the two values
match, the update of the write/erase and read protection setup is allowed (see the Protecting the Flash
Memory section).
If the protection key in the flash is 0xFF, the PROTKY SFR value is not used for comparison. The PROTKY SFR is
also used to write the protection key in the flash. This is done by writing the desired value in PROTKY and
writing 0x08 in the ECON SFR. This operation can be done only once.
Table 108. Flash Data SFR (EDATA, Address 0xBC)
Bit Mnemonic Default Description
[7:0] EDATA 0 Flash pointer data.
Table 109. Flash Low Byte Address SFR (EADRL, Address 0xC6)
Bit Mnemonic Default Description
[7:0] EADRL 0 Flash pointer low byte address.
Table 110. Flash High Byte Address SFR (EADRH, Address 0xC7)
Bit Mnemonic Default Description
[7:0] EADRH 0 Flash pointer high byte address.
Data Sheet ADE5169/ADE5569
Rev. E | Page 111 of 155
Flash Functions
The following sample 8052 code is provided to demonstrate how to
use the the flash functions. For these examples, Flash Memory
Byte 0x3C00 is accessed.
Write Byte
Write 0xF3 into Flash Memory Byte 0x3C00.
MOV EDATA, #F3h ; Data to be written
MOV EADRH, #3Ch ; Set up byte address
MOV EADRL, #00h
MOV FLSHKY, #3Bh ; Write flash security
key.
MOV ECON, #01H ; Write byte
Erase Page
Erase the page containing Flash Memory Byte 0x3C00.
MOV EADRH, #3Ch ; Select page through
byte address
MOV EADRL, #00h
MOV FLSHKY, #3Bh ; Write flash security
key.
MOV ECON, #02H ; Erase Page
Erase All
Erase all of the 62 kB flash memory.
MOV FLSHKY, #3Bh ; Write flash security
key.
MOV ECON, #03H ; Erase all
Read Byte
Read Flash Memory Byte 0x3C00.
MOV EADRH, #3Ch ; Set up byte address
MOV EADRL, #00h
MOV FLSHKY, #3Bh ; Write flash security
key.
MOV ECON, #04H ; Read byte
; Data is ready in EDATA register
Note that the read byte command can be used to view the status
of the protection bytes located in the upper 21 bytes, Page 123.
The write byte command is not valid for this area.
PROTECTING THE FLASH MEMORY
Two forms of protection are offered for this flash memory: read
protection and write/erase protection. The read protection ensures
that any pages that are read protected cannot be read by the end
user. The write protection ensures that the flash memory cannot
be erased or written over. This protects the final product from
tampering and can prevent the code from being overwritten in
the event of a runaway program.
Write/erase protection is individually selectable for all 124 pages.
Read protection is selected in groups of four pages (see Figure 95
for the groupings). The protection bits are stored in the last flash
memory locations, Address 0xF7EB through Address 0xF7FF
(see Figure 96). Sixteen bytes are reserved for write/erase pro-
tection, four bytes for read protection, and another byte to set
the flash protection key (PROTKY, Address 0xBB). The user must
enable write/erase protection for the last page, at a minimum, for
the entire protection scheme to work.
Note that the read protection does not prevent MOVC commands
from being executed within the code.
There is an additional layer of protection offered by a flash pro-
tection security key (PROTKY) that can be set up by the user so
that the protection scheme cannot be changed without this key.
After the protection key has been configured, it cannot be
modified.
Enabling Flash Protection by Code
The protection bytes in the flash can be programmed by using
the flash controller command and programming the ECON
SFR to 0x08. Issuing the ECON protection command initiates
the programming of one byte of protection data. The EADRL
(Address 0xC6) and EDATA (Address 0xBC) data pointer SFRs
are used to store the least significant address and data bytes,
respectively. Note that the EADRH data pointer SFR is not used
in this command.
The following sequence should be followed to enable the flash
protection:
1. Set the EDATA flash data pointer with the write/erase or
read protection data. When erased, the protection bits default
to 1, like any other bit of flash memory. The default protection
setting is for no protection. To enable protection, write a 0 to
the bits corresponding to the pages that should be protected.
Note that when setting the read protection, each protection
bit protects four pages.
2. Set the EADRL flash data pointer with the least significant
byte of the protection address. For example, to access the
protection on Page 112 through Page 119 (Address 0xF7FE),
EADRL should be written to 0xFE.
3. Enable access to the flash by writing 0x3B to the FLSHKY
SFR (Address 0xBA).
4. Issue the protection command by writing 0x08 to the
ECON SFR (Address 0xB9).
Step 1 to Step 3 should be repeated for each byte that requires
protection. While configuring the final byte of write/read pro-
tection, the PROTKY SFR (Address 0xBB) can be enabled for a
further level of code security. If enabled, the flash protection key is
required to modify the protection scheme. To enable the flash
protection key, the Flash Location 0xF7EB where the PROTKY
is located should be written to using the flash control SFR (ECON,
Address 0xB9). The PROTKY can be written to any 8-bit value;
once configured, it cannot be modified. To enable the PROTKY
and activate the flash protection, the device must be reset.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 112 of 155
Note that after the PROTKY has been activated by a reset, any
further changes to the protection require the new 8-bit protection
key to be written to the PROTKY SFR prior to issuing the ECON
command. The PROTKY SFR is cleared automatically when the
ECON 0x08 command is issued and, therefore, the user must
ensure that the correct value is written to the PROTKY SFR each
time that the protection scheme is changed.
The most significant bit of 0xF7FF is used to enable the lock
mechanism for the watchdog (see the Watchdog Timer section
for more information).
The following code provides an example of how the write/erase
protection can be enabled on the first page and the PROTKY set
to 0xA3. Note that to activate the following protection, the device
requires a reset.
; enable write/erase protection on the first
page only
MOV EDATA, #0FEH ; clear bit WP 0
MOV EADRL, #0F0H ; write address to F7F0h
MOV FLSHKY, #3BH ; enable flash access
MOV ECON, #08H ;issue protection
command
;enable write/erase protection on last page
(this is required for any protection to be
activated)
MOV EDATA, #0F7H ; clear bit WP123
MOV EADRL, #0FFH ; write address to F7FFh
MOV FLSHKY, #3BH ; enable flash access
MOV ECON, #08H ;issue protection
command
;set up PROTKY to A3h
MOV EDATA, #0A3H ; set PROTKY to A3h
MOV EADRL, #0EBH ; write address to F7EBh
MOV FLSHKY, #3BH ; enable flash access
MOV ECON, #08H ; issue protection
command
Note that after the PROTKY is changed to 0xA3, as shown in
the preceding example code, all future modifications of the pro-
tection scheme require that the PROTKY SFR be set to 0xA3
prior to issuing the ECON protection command.
07411-124
PROTKY
0xF600
0
xF7EB
0xF7EF
0xF7FF WDOG
LOCK WP
123 WP
122 WP
121 WP
120
WP
115 WP
114 WP
113 WP
112
WP
119 WP
118 WP
117 WP
116
WP
107 WP
106 WP
105 WP
104
WP
111 WP
110 WP
109 WP
108
WP
11 WP
10 WP
9WP
8
WP
15 WP
14 WP
13 WP
12
WP
3WP
2WP
1WP
0
WP
7WP
6WP
5WP
4
RP
108–111
RP
104–107
RP
100–103
RP
96–99
RP
64–67
RP
68–71
RP
72–75
RP
76–79
RP
80–83
RP
84–87
RP
88–91
RP
92–95
RP
32–35
RP
36–39
RP
40–43
RP
44–47
RP
48–51
RP
52–55
RP
56–59
RP
60–63
RP
0–3
RP
4–7
RP
8–11
RP
12–15
RP
16–19
RP
20–23
RP
24–27
RP
28–31
RP
120–123
RP
116–119
RP
112–115
PROTECTION KEY
Figure 96. Flash Protection in Page 124
Data Sheet ADE5169/ADE5569
Rev. E | Page 113 of 155
Enabling Flash Protection by Emulator Commands
Another way to set the flash protection bytes is to use the reserved
emulator commands available only in download mode. These
commands write directly to the SFRs and can be used to duplicate
the operation described in the Enabling Flash Protection by Code
section. When these flash bytes are written, the device can exit
emulation mode by reset and the protections are effective. This
method can be used in production and implemented after
downloading the program. The commands used for this opera-
tion are an extension of the commands listed in Application
Note AN-1074, Understanding the Serial Download Protocol
(Formerly uC004).
Command with ASCII Code I or 0x49 writes the data into R0.
Command with ASCII Code F or 0x46 writes R0 into the
SFR address defined in the data of this command.
Omitting the protocol defined in the Application Note AN-1074,
the sequence to load protections is similar to the sequence men-
tioned in the Enabling Flash Protection by Code section, except
that two emulator commands are necessary to replace one assembly
command. For example, to write the protection value in the
EADRH SFR (Address 0xC7), the following two commands
must be executed:
Command I with data = value of Protection Byte 0x3FFF
Command F with data = 0xC7
With this protocol, the protection can be written to the flash
memory using the same sequence described in the Enabling
Flash Protection by Code section. When the device is reset, the
protection is effective.
Notes on Flash Protection
The flash protection scheme is disabled by default so that none
of the pages of the flash are protected from reading or writing/
erasing.
The last page must be write/erase protected for the protection
scheme to work.
To activate the protection settings, the ADE5169/ADE5569
must be reset after configuring the protection.
After configuring protection on the last page and resetting the
device, protections that have been enabled can be removed only
by mass erasing the flash memory. The protection bits are never
truly write protected. Protection bits can be program modified
from a 1 to a 0, even after the last page has been protected. In this
way, more protection can be added, but none can be removed.
When the last page is read protected, the protection bits can still
be read by the user code. All other bits on this page are not available
for reading.
The protection scheme is intended to protect the end system. Pro-
tection should be disabled while developing and emulating code.
Flash Memory Timing
Typical program and erase times for the flash memory are shown
in Table 111.
Table 111. Flash Memory Program and Erase Times
Command Bytes Affected Flash Memory Timing
Write Byte 1 byte 30 μs
Erase Page 512 bytes 20 ms
Erase All 62 kB 2.5 sec
Read Byte 1 byte 100 ns
Note that the core microcontroller operation is idled until the
requested flash memory operation is complete. In practice, this
means that even though the flash operation is typically initiated
with a two machine cycle MOV instruction to write to the flash
control SFR (ECON, Address 0xB9), the next instruction is not
executed until the Flash/EE operation is complete. This means
that the core cannot respond to interrupt requests until the Flash/
EE operation is complete, although the core peripheral functions
such as counters/timers continue to count, as configured, through-
out this period.
IN-CIRCUIT PROGRAMMING
Serial Downloading
The ADE5169/ADE5569 facilitate code download via the
standard UART serial port. The devices enter serial download
mode after a reset or a power cycle if the SDEN pin is pulled low
through an external 1 kΩ resistor. Once in serial download mode,
the hidden embedded download kernel executes. This allows the
user to download code to the full 62 kB of flash memory while the
device is in circuit in its target application hardware.
Protection configured in the last page of the ADE5169/ADE5569
affects whether flash memory can be accessed in serial download
mode. Read protected pages cannot be read. Write/erase protected
pages cannot be written or erased. The configuration bits cannot be
programmed in serial download mode.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 114 of 155
TIMERS
Each ADE5169/ADE5569 has three 16-bit timers/counters:
Timer/Counter 0, Timer/Counter 1, and Timer/ Counter 2. The
timer/counter hardware is included on chip to relieve the processor
core of overhead inherent in implementing timer/counter func-
tionality in software. Each timer/counter con-sists of two 8-bit
registers: THx and TLx (x = 0, 1, or 2). All three timers can be
configured to operate as timers or as event counters.
When functioning as a timer, the TLx SFR is incremented every
machine cycle. Thus, it can be thought of as counting machine
cycles. Because a machine cycle on a single cycle core consists of
one core clock period, the maximum count rate is the core
clock frequency.
When functioning as a counter, the TLx SFR is incremented by
a 1-to-0 transition at its corresponding external input pin: T0,
T1, or T2. When the samples show a high in one cycle and a low
in the next cycle, the count is incremented. Because it takes two
machine cycles (two core clock periods) to recognize a 1-to-0
transition, the maximum count rate is half the core clock frequency.
There are no restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled at least once
before it changes, it must be held for a minimum of one full
machine cycle. User configuration and control of all timer
operating modes is achieved via the SFRs listed in Table 112.
Table 112. Timer SFRs
SFR Address Bit Addressable Description
TCON 0x88 Yes Timer/Counter 0 and Timer/Counter 1 control (see Table 114).
TMOD 0x89 No Timer/Counter 0 and Timer/Counter 1 mode (see Table 113).
TL0 0x8A No Timer 0 low byte (see Table 117).
TL1 0x8B No Timer 1 low byte (see Table 119).
TH0
0x8C
No
Timer 0 high byte (see Table 116).
TH1 0x8D No Timer 1 high byte (see Table 118).
T2CON 0xC8 Yes Timer/Counter 2 control (see Table 115).
RCAP2L 0xCA No Timer 2 reload/capture low byte (see Table 123).
RCAP2H 0xCB No Timer 2 reload/capture high byte (see Table 122).
TL2 0xCC No Timer 2 low byte (see Table 121).
TH2 0xCD No Timer 2 high byte (see Table 120).
TIMER REGISTERS
Table 113. Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, Address 0x89)
Bit
Mnemonic
Default
Description
7 Gate1 0 Timer 1 gating control. Set by software to enable Timer/Counter 1 only when the INT1 pin is high and the TR1
control bit (Address 0x88[6]) is set. Cleared by software to enable Timer 1 whenever the TR1 control bit is set.
6 C/T1 0 Timer 1 timer or counter select bit. Set by software to select counter operation (input from the T1 pin). Cleared by
software to select the timer operation (input from the internal system clock).
[5:4] T1/M1,
T1/M0
00 Timer 1 mode select bits.
T1/M1, T1/M0 Result
00 TH1 (Address 0x8D) operates as an 8-bit timer/counter. TL1 (Address 0x8B) serves as a
5-bit prescaler.
01
16-bit timer/counter. TH1 and TL1 are cascaded; there is no prescaler.
10 8-bit autoreload timer/counter. TH1 holds a value to reload into TL1 each time TL1 overflows.
11 Timer/Counter 1 stopped.
3 Gate0 0 Timer 0 gating control. Set by software to enable Timer/Counter 0 only when the INT0 pin is high and the TR0
control bit (Address 0x88[4]) is set. Cleared by software to enable Timer 0 whenever the TR0 control bit is set.
2 C/T0 0 Timer 0 timer or counter select bit. Set by software to the select counter operation (input from the T0 pin).
Cleared by software to select the timer operation (input from the internal system clock).
[1:0] T0/M1,
T0/M0
00 Timer 0 mode select bits.
T0/M1, T0/M0 Result
00 TH0 (Address 0x8C) operates as an 8-bit timer/counter. TL0 (Address 0x8A) serves as a
5-bit prescaler.
01 16-bit timer/counter. TH0 and TL0 are cascaded; there is no prescaler.
10 8-bit autoreload timer/counter. TH0 holds a value to reload into TL0 each time TL0 overflows.
11 TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an
8-bit timer only, controlled by the Timer 1 control bits.
Data Sheet ADE5169/ADE5569
Rev. E | Page 115 of 155
Table 114. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, Address 0x88)
Bit Bit Address Mnemonic Default Description
7 0x8F TF1 0 Timer 1 overflow flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware
when the program counter (PC) vectors to the interrupt service routine.
6 0x8E TR1 0 Timer 1 run control bit. Set by the user to turn on Timer/Counter 1. Cleared by the user to turn
off Timer/Counter 1.
5 0x8D TF0 0 Timer 0 overflow flag. Set by hardware on a Timer/Counter 0 overflow. Cleared by hardware
when the PC vectors to the interrupt service routine.
4 0x8C TR0 0 Timer 0 run control bit. Set by the user to turn on Timer/Counter 0. Cleared by the user to turn
off Timer/Counter 0.
3 0x8B IE11 0 External Interrupt 1 (INT1) flag. Set by hardware by a falling edge or by a zero level applied to
the external interrupt pin, INT1, depending on the state of Bit IT1. Cleared by hardware when
the PC vectors to the interrupt service routine only if the interrupt was transition activated. If level
activated, the external requesting source, rather than the on-chip hardware, controls the
request flag.
2 0x8A IT11 0 External Interrupt 1 (IE1) trigger type. Set by software to specify edge sensitive detection, that is,
a 1-to-0 transition. Cleared by software to specify level sensitive detection, that is, zero level.
1 0x89 IE0
1
0 External Interrupt 0 (INT0) flag. Set by hardware by a falling edge or by a zero level applied to
the external interrupt pin, INT0, depending on the state of Bit IT0. Cleared by hardware when
the PC vectors to the interrupt service routine only if the interrupt was transition activated. If
level activated, the external requesting source, rather than the on-chip hardware, controls the
request flag.
0
0x88
IT01
0
External Interrupt 0 (IE0) trigger type. Set by software to specify edge sensitive detection, that is,
a 1-to-0 transition. Cleared by software to specify level sensitive detection, that is, zero level.
1 These bits are not used to control Timer/Counter 0 and Timer/Counter 1 but are, instead, used to control and monitor the external INT0 and INT1 interrupt pins.
Table 115. Timer/Counter 2 Control SFR (T2CON, Address 0xC8)
Bit Bit Address Mnemonic Default Description
7 0xCF TF2 0 Timer 2 overflow flag. Set by hardware on a Timer 2 overflow. TF2 cannot be set when either
RCLK = 1 or TCLK = 1. Cleared by user software.
6 0xCE EXF2 0 Timer 2 external flag. Set by hardware when either a capture or reload is caused by a negative
transition on the T2EX pin and EXEN2 = 1. Cleared by user software.
5 0xCD RCLK 0 Receive clock enable bit. Set by the user to enable the serial port to use Timer 2 overflow pulses
for its receive clock in Serial Port Mode 1 and Serial Port Mode 3. Cleared by the user to enable
Timer 1 overflow to be used for the receive clock.
4 0xCC TCLK 0 Transmit clock enable bit. Set by the user to enable the serial port to use Timer 2 overflow pulses
for its transmit clock in Serial Port Mode 1 and Serial Port Mode 3. Cleared by the user to enable
Timer 1 overflow to be used for the transmit clock.
3
0xCB
EXEN2
0
Timer 2 external enable flag. Set by the user to enable a capture or reload to occur as a result of
a negative transition on the T2EX pin if Timer 2 is not being used to clock the serial port. Cleared
by the user for Timer 2 to ignore events at T2EX.
2 0xCA TR2 0 Timer 2 start/stop control bit. Set by the user to start Timer 2. Cleared by the user to stop Timer 2.
1 0xC9 C/T2 0 Timer 2 timer or counter function select bit. Set by the user to select the counter function (input
from the external T2 pin). Cleared by the user to select the timer function (input from the on-chip
core clock).
0 0xC8 CAP2 0 Timer 2 capture/reload select bit. Set by the user to enable captures on negative transitions at
the T2EX pin if EXEN2 = 1. Cleared by the user to enable autoreloads with Timer 2 overflows or
negative transitions at the T2EX pin when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is
ignored and the timer is forced to autoreload on Timer 2 overflow.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 116 of 155
Table 116. Timer 0 High Byte SFR (TH0, Address 0x8C)
Bit Mnemonic Default Description
[7:0] TH0 0 Timer 0 data high byte.
Table 117. Timer 0 Low Byte SFR (TL0, Address 0x8A)
Bit Mnemonic Default Description
[7:0] TL0 0 Timer 0 data low byte.
Table 118. Timer 1 High Byte SFR (TH1, Address 0x8D)
Bit Mnemonic Default Description
[7:0] TH1 0 Timer 1 data high byte.
Table 119. Timer 1 Low Byte SFR (TL1, Address 0x8B)
Bit Mnemonic Default Description
[7:0] TL1 0 Timer 1 data low byte.
Table 120. Timer 2 High Byte SFR (TH2, Address 0xCD)
Bit Mnemonic Default Description
[7:0] TH2 0 Timer 2 data high byte.
Table 121. Timer 2 Low Byte SFR (TL2, Address 0xCC)
Bit Mnemonic Default Description
[7:0] TL2 0 Timer 2 data low byte.
Table 122. Timer 2 Reload/Capture High Byte SFR
(RCAP2H, Address 0xCB)
Bit Mnemonic Default Description
[7:0] TH2 0 Timer 2 reload/capture high byte.
Table 123. Timer 2 Reload/Capture Low Byte SFR (RCAP2L,
Address 0xCA)
Bit Mnemonic Default Description
[7:0] TL2 0 Timer 2 reload/capture low byte.
TIMER 0 AND TIMER 1
Timer 0 High/Low and Timer 1 High/Low Data Registers
Each timer consists of two 8-bit SFRs. For Timer 0, they are
Timer 0 high byte (TH0, Address 0x8C) and Timer 0 low byte
(TL0, Address 0x8A). For Timer 1, they are Timer 1 high byte
(TH1, Address 0x8D) and Timer 1 low byte (TL1, Address 0x8B).
These SFRs can be used as independent registers or combined
into a single 16-bit register, depending on the timer mode
configuration (see Table 116 to Table 119).
Timer/Counter 0 and Timer/Counter 1 Operating Modes
This section describes the operating modes for Timer/Counter 0
and Timer/Counter 1. Unless otherwise noted, these modes of
operation are the same for both Timer 0 and Timer 1.
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter. Figure 97 shows
Mode 0 operation. Note that the divide-by-12 prescaler is not
present on the single cycle core.
INTERRUPT
TH0
(8 BITS )
TL0
(5 BITS)
CONTROL
TF0
TR0
P0.6/T0
GATE
INT0
f
CORE
C/T 0 = 0
C/T0 = 1
07411-071
Figure 97. Timer/Counter 0, Mode 0
In this mode, the timer register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, it sets the timer overflow
flag, TF0 (Address 0x88[5]). TF0 can then be used to request an
interrupt. The counter input is enabled when TR0 = 1 and either
Gate0 = 0 or INT0 = 1. Setting Gate0 = 1 allows the timer to be
controlled by the external input, INT0, to facilitate pulse width
measurements. TR0 is a control bit located in the Timer/Counter 0
and Timer/Counter 1 control SFR (TCON, Address 0x88[4]);
the Gate0/Gate1 bits are in Timer/Counter 0 and Timer/Counter 1
mode SFR (TMOD, Address 0x89, Bit 3 and Bit 7, respectively).
The 13-bit register consists of all eight bits of the Timer 0 high
byte SFR (TH0, Address 0x8C) and the lower five bits of the
Timer 0 low byte SFR (TL0, Address 0x8A). The upper three bits
ofthe TL0 SFR are indeterminate and should be ignored. Setting
the run flag (TR0, Address 0x88[4]) does not clear the registers.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0 except that the Mode 1 timer
register runs with all 16 bits. Mode 1 is shown in Figure 98.
GATE
f
CORE
0
7411-072
INTERRUPT
TH0
(8 BITS)
TL0
(8 BITS)
CONTROL
TF0
TR0
INT0
P0.6/T0
C/T0 = 0
C/T0 = 1
Figure 98. Timer/Counter 0, Mode 1
Data Sheet ADE5169/ADE5569
Rev. E | Page 117 of 155
Mode 2 (8-Bit Timer/Counter with Autoreload)
Mode 2 configures the timer SFR (TH0, Address 0x8C) as an 8-bit
counter (TL0, Address 0x8A) with automatic reload, as shown in
Figure 99. Overflow from TL0 not only sets TF0 (Address 0x88[5])
but also reloads TL0 with the contents of TH0, which is preset by
software. The reload leaves TH0 unchanged.
TF0 INTERRUPT
P0.6/T0
GATE
INT0
C/T 0 = 0
C/T 0 = 1
fCORE
07411-073
RELOAD
TH0
(8 BITS)
TL0
(8 BITS)
CONTROL
TR0
Figure 99. Timer/Counter 0, Mode 2
Mode 3 (Two 8-Bit Timer/Counters)
Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in
Mode 3 simply holds its count. The effect is the same as setting
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. This configuration is shown in Figure 100.
TL0 uses the Timer 0 control bits, C/T0, Gate0 (see Table 113),
TR0, TF0 (see Table 114), and the INT0 pin. TH0 is locked into
a timer function (counting machine cycles) and takes over the
use of TR1 and TF1 from Timer 1. Therefore, TH0 controls the
Timer 1 interrupt. Mode 3 is provided for applications requiring
an extra 8-bit timer or counter.
When Timer 0 is in Mode 3, Timer 1 can be turned on and off
by switching it out of and into its own Mode 3, or it can be used
by the serial interface as a baud rate generator. In fact, Timer 1
can be used in any application not requiring an interrupt from
Timer 1 itself.
CONTROL
CORE
CLK/12
TF0
TL0
(8 BITS)
INTERRUPT
P0.6/T0
GATE
TR0
TF1
TH0
(8 BITS)
INTERRUPT
fCORE
/12
TR1
0INT
fCORE
07411-074
C/T 0 = 0
C/T 0 = 1
Figure 100. Timer/Counter 0, Mode 3
TIMER 2
Timer/Counter 2 Data Registers
Timer/Counter 2 also has two pairs of 8-bit data registers asso-
ciated with it: Timer 2 high byte SFR (TH2, Address 0xCD),
Timer 2 low byte SFR (TL2, Address 0xCC), Timer 2 reload/
capture high byte SFR (RCAP2H, Address 0xCB), and Timer 2
reload/capture low byte SFR (RCAP2L, Address 0xCA). These
SFRs are used both as timer data registers and as timer capture/
reload registers (see Table 120 to Table 123).
Timer/Counter 2 Operating Modes
The following sections describe the operating modes for Timer/
Counter 2. The operating modes are selected by bits in the Timer/
Counter 2 control SFR (T2CON, Address 0xC8), as shown in
Table 115 and Table 124.
Table 124. T2CON Operating Modes
RCLK or TCLK CAP2 TR2 Mode
0 0 1 16-bit autoreload
0 1 1 16-bit capture
1 X 1 Baud rate
X X 0 Off
16-Bit Autoreload Mode
The 16-bit autoreload mode has two options that are selected by
EXEN2 (Bit 3) in the Timer/Counter 2 control SFR (T2CON,
Address 0xC8). If EXEN2 = 0 when Timer 2 rolls over, it not only
sets TF2 but also causes the Timer 2 SFRs to be reloaded with the
16-bit value in both the Timer 2 reload/capture high byte SFR
(RCAP2H, Address 0xCB) and Timer 2 reload/capture low byte
SFR (RCAP2L, Address 0xCA), which are preset by software. If
EXEN2 = 1, Timer 2 performs the same events as when EXEN2 = 0
but adds a 1-to-0 transition at the external input pin, T2EX, which
triggers the 16-bit reload and sets EXF2 (T2CON[6]). Autoreload
mode is shown in Figure 101.
16-Bit Capture Mode
The 16-bit capture mode has two options that are selected by
EXEN2 (Bit 3) in the Timer/Counter 2 control SFR (T2CON,
Address 0xC8). If EXEN2 = 0, Timer 2 is a 16-bit timer or counter
that, upon overflowing, sets the Timer 2 overflow bit (TF2, Bit 7).
This bit can be used to generate an interrupt. If EXEN2 = 1, then
Timer 2 performs the same events as when EXEN2 = 0, but it
adds a l-to-0 transition on the T2EX external input, causing the
current value in the Timer 2 SFRs, TL2 (Address 0xCC) and TH2
(Address 0xCD) to be captured into the RCAP2L (Address 0xCA)
and RCAP2H (Address 0xCB) SFRs, respectively. In addition, the
transition at T2EX causes the EXF2 bit (Bit 6) in the T2CON SFR
(Address 0xC8) to be set, and EXF2, like TF2, can generate an
interrupt. Capture mode is shown in Figure 102. The baud rate
generator mode is selected by RCLK = 1 and/or TCLK = 1.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 118 of 155
In either case, if Timer 2 is used to generate the baud rate, the TF2
interrupt flag does not occur. Therefore, Timer 2 interrupts do not
occur and do not need to be disabled.
In this mode, the EXF2 flag can, however, still cause interrupts
that can be used as a third external interrupt. Baud rate
generation is described as part of the UART serial port operation in
the UART Serial Interface section.
TR2
CONTROL
TL2
(8 BITS) TH2
(8 BITS)
RELOAD
TF2
EXF2
TIMER
INTERRUPT
EXEN2
CONTROL
TRANSITION
DETECTOR RCAP2LRCAP2H
C/T2 = 0
P1.4/T2
P1.3/
T2EX
C/T2 = 1
f
CORE
07411-075
Figure 101. Timer/Counter 2, 16-Bit Autoreload Mode
TF2
P1.4/T2
P1.3/
T2EX
TR2
CONTROL
TL2
(8 BITS) TH2
(8 BITS)
CAPTURE
EXF2
TIMER
INTERRUPT
EXEN2
CONTROL
TRANSITION
DETECTOR RCAP2L RCAP2H
C/T2 = 1
C/T2 = 0
fCORE
07411-076
Figure 102. Timer/Counter 2, 16-Bit Capture Mode
Data Sheet ADE5169/ADE5569
Rev. E | Page 119 of 155
PHASE-LOCKED LOOP (PLL)
The ADE5169/ADE5569 are intended for use with a 32.768 kHz
watch crystal. A PLL locks onto a multiple of this frequency to
provide a stable 4.096 MHz clock for the system. The core can
operate at this frequency or at binary submultiples of it to allow
power savings when maximum core performance is not required.
The default core clock is the PLL clock divided by 4, or 1.024 MHz.
The ADE energy measurement clock is derived from the PLL
clock and is maintained at 4.096/5 MHz (or 819.2 kHz) across
all CD settings.
The PLL is controlled by the CD bits in the power control SFR
(POWCON, Address 0xC5[2:0]). To prevent erroneous changes
to the POWCON SFR, a key is required to modify the register.
First, the key SFR (KYREG, Address 0xC1) is written with the
key, 0xA7, and then a new value is written to the POWCON SFR.
If the PLL loses lock, the MCU is reset and PLL_FLT is set in the
peripheral configuration SFR (PERIPH, Address 0xF4[4]). Set the
PLLACK bit in the start ADC measurement SFR (ADCGO,
Address 0xD8[7]) to acknowledge the PLL fault, clearing the
PLL_FLT bit.
PLL REGISTERS
Table 125. Power Control SFR (POWCON, Address 0xC5)
Bit Mnemonic Default Description
7 Reserved 1 Reserved.
6 METER_OFF 0 Set this bit to 1 to turn off the modulators and energy metering DSP circuitry to reduce power if
metering functions are not needed in PSM0.
5 Reserved 0 This bit should be kept at 0 for proper operation.
4 COREOFF 0 Set this bit to 1 to shut down the core if in the PSM1 operating mode.
3 Reserved Reserved.
[2:0] CD 010 Controls the core clock frequency (f
CORE
). f
CORE
= 4.096 MHz/2
CD
.
CD Result (f
CORE
in MHz)
000 4.096
001 2.048
010 1.024
011 0.512
100 0.256
101 0.128
110 0.064
111 0.032
Writing to the Power Control SFR (POWCON, Address 0xC5)
Note that writing data to the POWCON SFR involves writing 0xA7 into the key SFR (KYREG, Address 0xC1), followed by a write to the
POWCON SFR.
Table 126. Key SFR (KYREG, Address 0xC1)
Bit Mnemonic Default Description
[7:0] KYREG 0 Write 0xA7 to the KYREG SFR before writing to the POWCON SFR to unlock it.
Write 0xEA to the KYREG SFR before writing to the INTPR, HTHSEC, SEC, MIN, or HOUR timekeeping
registers to unlock them (see the RTC Registers section).
ADE5169/ADE5569 Data Sheet
Rev. E | Page 120 of 155
REAL-TIME CLOCK (RTC)
The ADE5169/ADE5569 have an embedded RTC (see Figure 103).
The external 32.768 kHz crystal is used as the clock source for
the RTC. Calibration is provided to compensate the nominal
crystal frequency and for variations in the external crystal
frequency over temperature. By default, the RTC is active in all
the power saving modes. The RTC counters retain their values
through watchdog resets and external resets and are reset only
during a power-on reset.
The ADE5169/ADE5569 provide two ways to access the RTC
data: by direct access through SFRs for configuration and by
indirect access through address and data SFRs for the timekeeping
registers and some other configurations. The address and data
SFRs act as pointers to the RTC internal registers.
ACCESS TO RTC SFRs
Access to the RTC SFRs is achieved by reading or writing to the
SFR addresses that are detailed in the Access to Internal RTC
Registers section. Writing to the indirect registers is protected
by a key, as explained in the Writing to Internal RTC Registers
section. Reading is not protected.
ACCESS TO INTERNAL RTC REGISTERS
Access to the internal RTC measurement registers is achieved by
writing to the RTC pointer address SFR (RTCPTR, Address 0xA3).
The RTCPTR register selects the RTC register to be accessed and
determines if a read or a write is performed (see Table 130).
Writing to Internal RTC Registers
The RTC circuitry runs off a 32.768 kHz clock. The timekeeping
registers, HTHSEC, SEC, MIN, HOUR, DAY, DATE, MONTH,
and YEAR are updated with a 32.768 kHz clock. However, the
TIMECON (Address 0xA1) and TIMECON2 (Address 0xA2)
SFRs and the INTVAL register (Address 0x09) are updated with
a 128 Hz clock. It takes up to two 128 Hz clock cycles from when
the MCU writes to the TIMECON or TIMECON2 SFR, or the
INTVAL register until it is successfully updated in the RTC.
When the RTCW_RB bit in the RTCPTR SFR (Address 0xA3[7])
is set, the contents of the RTCDAT SFR (Address 0xA4) are
transferred to the internal RTC register designated by the address
in the RTCPTR SFR. To protect the RTC timekeeping registers
from runaway code, a key must be written to the KYREG SFR
(Address 0xC1) to obtain write access to any of the RTC indirect
registers. The KYREG SFR should be set to 0xEA to unlock the
timekeeping registers and is reset to 0 after a timekeeping register
is written.
The RTC registers can be written using the following 8052
assembly code:
MOV RTCKey, #0EAh
CALL UpdateRTC
…
UpdateRTC:
MOV KYREG, RTCKey
MOV RTCDAT, #30
MOV RTCPTR, #82h
MOV KYREG, RTCKey
MOV RTCDAT, #05
MOV RTCPTR, #83h
MOV KYREG, RTCKey
MOV RTCDAT, #04
MOV RTCPTR, #84h
MOV RTCKey, #00h
RET
Reading Internal RTC Registers
When Bit 7 of the RTCPTR SFR is cleared, the contents of the
internal RTC data register designated by the address in RTCPTR
are transferred to the RTCDAT SFR. The RTC cannot be stopped
to read the current time because stopping the RTC introduces
an error in its timekeeping. Therefore, the RTC is read on-the-fly,
and the counter registers must be checked for overflow. This
can be accomplished using the following 8052 assembly code:
ReadAgain:
MOV RTCPTR #01 ; Read HTHSEC using
Bank 0
MOV R0, RTCDAT
MOV RTCPTR, #02 ; Read SEC
MOV R1, RTCDAT
MOV RTCPTR, #03 ; Read MIN
MOV R2, RTCDAT
MOV RTCPTR, #04 ; Read HOUR
MOV R3, RTCDAT
MOV RTCPTR, #01 ; Read HTHSEC
MOV A, RTCDAT
CJNE A, 00h, ReadAgain ; 00h is R0 in
Bank 0
Data Sheet ADE5169/ADE5569
Rev. E | Page 121 of 155
8-BIT
PRESCALER
HUNDREDTHS COUNTER
HTHSEC
SECOND COUNTER
SEC
MINUTE COUNTER
MIN
HOUR COUNTER
HOUR ITEN
RTC INTERRUPT
8-BIT
INTERVAL COUNTER
INTVAL
INTERVAL
TIMEBASE
SELECTION
MUX
32.768kHz
CRYSTAL
ITS1 ITS0
EQUAL?
CALIBRATION
RTCCOMP
TEMPCAL
CALIBRATED
32.768kHz
ALARM SECOND
AL_SEC
DAY COUNTER
DAY
DAY COUNTER
DATE
MONTH COUNTER
MONTH
YEAR COUNTER
YEAR
EQUAL?
ALARM MINUTE
AL_MIN
EQUAL?
ALARM HOUR
AL_HOUR
EQUAL?
ALARM DAY
AL_DAY
EQUAL?
ALARM DATE
AL_DATE
EQUAL?
ALDAT_EN
ALDAY_EN
ALHR_EN
ALMIN_EN
ALSEC_EN
ALFLAG
COMPENSATION
TEMPERATURE
ADC
(x)
2
07411-123
Figure 103. RTC Implementation
RTC SFRS
Table 127. List of RTC SFRs
SFR Address Bit Addressable Description
TIMECON 0xA1 No RTC configuration (see Table 128).
TIMECON2 0xA2 No RTC Configuration 2 (see Table 129).
RTCPTR 0xA3 No RTC pointer address (see Table 130).
RTCDAT 0xA4 No RTC pointer data (see Table 131).
KYREG 0xC1 No Key (see Table 126).
RTCCOMP 0xF6 No RTC nominal compensation (see Table 132).
TEMPCAL 0xF7 No RTC temperature compensation (see Table 133).
ADE5169/ADE5569 Data Sheet
Rev. E | Page 122 of 155
Table 128. RTC Configuration SFR (TIMECON, Address 0xA1)
Bit Mnemonic Default1 Description
7 Reserved N/A Reserved.
6 ALFLAG 0 Alarm flag. This bit is set when the RTC registers match the enabled alarm registers. It can be cleared by
the user to indicate that the alarm has been serviced.
[5:4] ITS1, ITS0 0 INTVAL timebase select bits.
ITS1, ITS0 Timebase
00 1/128 sec
01
Second
10 Minute
11 Hour
3 SIT 0 Interval timer one-time alarm.
SIT Result
0 The ITFLAG flag is set after INTVAL counts, and then another interval count starts.
1 The ITFLAG flag is set after one time interval.
2 ITFLAG 0 Interval timer flag. This bit is set when the configured time interval has elapsed. It can be cleared by the
user to indicate that the alarm event has been serviced.
1 ITEN 0 Interval timer enable.
ITEN Result
0 The interval timer is disabled, and the 8-bit interval timer counter is reset.
1 Set this bit to 1 to enable the interval timer.
0 Unused N/A Unused.
1 N/A means not applicable.
Table 129. RTC Configuration 2 SFR (TIMECON2, Address 0xA2)
Bit Mnemonic Default Description
[7:5] Reserved N/A1 Reserved.
4 ALDAT_EN 0 Alarm date enable. When this bit is set, the data in the AL_DATE register (Address 0x0E) is compared to
the data in the RTC DATE register (Address 0x06). If the two values match, and any other enabled RTC
alarms also match, the ALFLAG in the TIMECON SFR (Address 0xA1[6]) is set. If enabled, an RTC interrupt occurs.
3 ALDAY_EN 0 Alarm day enable. When this bit is set, the data in the AL_DAY register (Address 0x0D) is compared to the
data in the RTC DAY register (Address 0x05). If the two values match and any other enabled RTC alarms
also match, the ALFLAG in the TIMECON SFR (Address 0xA1[6]) is set. If enabled, an RTC interrupt occurs.
2 ALHR_EN 0 Alarm hour enable. When this bit is set, the data in the AL_HOUR register (Address 0x0C) is compared to
the data in the RTC HOUR register (Address 0x04). If the two values match and any other enabled RTC
alarms also match, the ALFLAG in the TIMECON SFR (Address 0xA1[6]) is set. If enabled, an RTC interrupt occurs.
1 ALMIN_EN 0 Alarm minute enable. When set, the data in the AL_MIN register (Address 0x0B) is compared to the data in
the RTC MIN register (Address 0x03). If the two values match and any other enabled RTC alarms also
match, the ALFLAG in the TIMECON SFR (Address 0xA1[6]) is set. If enabled, an RTC interrupt occurs.
0 ALSEC_EN 0 Alarm second enable. When this bit is set, the data in the AL_SEC register (Address 0x0A) is compared to
the data in the RTC SEC register (Address 0x02). If the two values match and any other enabled RTC alarms
also match, the ALFLAG in the TIMECON SFR (Address 0xA1[6]) is set. If enabled, an RTC interrupt occurs.
1 N/A means not applicable
Data Sheet ADE5169/ADE5569
Rev. E | Page 123 of 155
Table 130. RTC Pointer Address SFR (RTCPTR, Address 0xA3)
Bit Mnemonic Default Description
7 RTCW_RB 0 Read/write selection.
RTCW_RB
Result
0 The RTC register at RTC_ADDRESS (Bits[4:0]) is read into the RTCDAT SFR
(Address 0xA4).
1 The data in the RTCDAT SFR is written in the RTC register at RTC_ADDRESS
(Bits[4:0]). This operation is completed only if the KYREG SFR (Address
0xC1) is set to 0xEA, the instruction before writing to the RTCDAT SFR.
[6:5] Reserved Not applicable. Reserved.
[4:0] RTC_ADDRESS 0 Target address for read/write operation.
Table 131. RTC Pointer Data SFR (RTCDAT, Address 0xA4)
Bit Mnemonic Default Description
[7:0] RTC_DATA 0 Location of data for read/write RTC operation.
Table 132. RTC Nominal Compensation SFR (RTCCOMP, Address 0xF6)
Bit Mnemonic Default Description
[7:0] RTCCOMP 0 Holds the nominal RTC compensation value at 25°C. Note that this register is reset after a
watchdog reset, an external reset, or a power-on reset (POR).
Table 133. RTC Temperature Compensation SFR (TEMPCAL, Address 0xF7)
Bit Mnemonic Default Description
[7:0]
TEMPCAL
0
Calibrates the RTC over temperature. This allows the external crystal shift to be compensated
over temperature. Note that this register is reset after a watchdog reset, an external reset, or a
power-on reset (POR).
ADE5169/ADE5569 Data Sheet
Rev. E | Page 124 of 155
RTC REGISTERS
Table 134. RTC Register List1
Address
RTCPTR[4:0] Mnemonic R/W Length
Signed/
Unsigned
Default
Value Description
0x00 Reserved N/A N/A N/A N/A Reserved.
0x01 HTHSEC R/W 8 U 0
Counter. Updates every 1/128 second, referenced from the
calibrated 32.768 kHz clock. It overflows from 127 to 00,
incrementing the seconds counter, SEC.
0x02 SEC R/W 8 U 0
Counter. Updates every second, referenced from the calibrated
32.768 kHz clock. It overflows from 59 to 00, incrementing the
minutes counter, MIN.
0x03 MIN R/W 8 U 0
Counter. Updates every minute, referenced from the calibrated
32.768 kHz clock. It overflows from 59 to 00, incrementing the
hours counter, HOUR.
0x04 HOUR R/W 8 U 0
Counter. Updates every hour, referenced from the calibrated
32.768 kHz clock. It overflows from 23 to 00, incrementing the DAY
and DATE counters.
0x05 DAY R/W 8 U 0
Counter. Updates every day, referenced from the calibrated 32.768 kHz
clock. It overflows from 6 to 0.
0x06 DATE R/W 8 U 1
Counter. Updates every day, referenced from the calibrated 32.768 kHz
clock. It overflows from 28/29/30 or 31 to 01, depending on the month,
incrementing the month counter, MONTH.
0x07 MONTH R/W 8 U 1
Counter. Starts at 1 and updates every month, referenced from the
calibrated 32.768 kHz clock. It overflows from 12 to 01, incrementing
the year counter, YEAR.
0x08 YEAR R/W 8 U 0
Counter. Updates every year, referenced from the calibrated
32.768 kHz clock.
0x09 INTVAL R/W 8 U 0
Interval timer. Counts according to the timebase established in the
ITS bits of the RTC configuration SFR (TIMECON, Address 0xA1[5:4]).
When the number of counts is equal to INTVAL, ITFLAG (TIMECON[2])
is set, and a pending RTC interrupt is created, if enabled. Note that
the interval counter is eight bits, so it could count up to 255 sec, for
example.
0x0A AL_SEC R/W 8 U 0
Alarm second register. When this register matches the SEC register,
and the ALSEC_EN bit (TIMECON2, Address 0xA2[0]) is set, ALFLAG
(TIMECON[6]) is issued if all other enabled alarms match their
corresponding timekeeping register. If enabled, a pending RTC
interrupt is generated.
0x0B AL_MIN R/W 8 U 0
Alarm minute register. When this register matches the MIN register
and the ALMIN_EN bit (TIMECON2, Address 0xA2[1]) is set, ALFLAG
(TIMECON[6]) is issued if all other enabled alarms match their
corresponding timekeeping register. If enabled, a pending RTC
interrupt is generated.
0x0C AL_HOUR R/W 8 U 0
Alarm hour register. When this register matches the HOUR register
and the ALHR_EN bit (TIMECON2, Address 0xA2[2]) is set, ALFLAG
(TIMECON[6]) is issued if all other enabled alarms match their
corresponding timekeeping register. If enabled, a pending RTC
interrupt is generated.
0x0D AL_DAY R/W 8 U 0
Alarm day register. When this register matches the DAY register
and the ALDAY_EN bit (TIMECON2, Address 0xA2[3]) is set, ALFLAG
(TIMECON[6]) is issued if all other enabled alarms match their
corresponding timekeeping registers. If enabled, a pending RTC
interrupt is generated.
0x0E AL_DATE R/W 8 U 0
Alarm date register. When this register matches the DATE register
and the ALDAT_EN bit (TIMECON2, Address 0xA2[4]) is set, ALFLAG
(TIMECON[6]) is issued if all other enabled alarms match their
corresponding timekeeping registers. If enabled, a pending RTC
interrupt is generated.
0x0F RTC_CAL R/W 8 U 0 Configuration of the RTC calibration output (see Table 135).
1 N/A means not applicable.
Data Sheet ADE5169/ADE5569
Rev. E | Page 125 of 155
Table 135. RTC Calibration Configuration Register (RTC_CAL, Address 0x0F)
Bit Mnemonic Default Description
7 CAL_EN_PSM2 0 When this bit is set and the CAL_EN bit is set, the RTC output is present on P0.5/MISO/ZX in PSM2
mode. The RTC output is disabled on all other pins in PSM2 mode.
6 CAL_EN 0 RTC calibration enable output.
CAL_EN Result
0 The RTC calibration output signal is disabled
1 The RTC calibration output signal is enabled and present on the pins selected by
the RTC_P2P3, RTC_P1P2, RTC_P0P7, and RTC_P0P5 bits (Bits[3:0]).
[5:4] FSEL[1:0] 00 RTC calibration output frequency selection.
FSEL Frequency Calibration Window
00 1 Hz 30.5 sec
01 512 Hz 30.5 sec
10 500 Hz 0.244 sec
11 16 kHz 0.244 sec
3 RTC_P2P3 0 When this bit is set and the CAL_EN bit is set, the RTC output is present on the P2.3/SDEN/TxD2 pin.
2 RTC_P1P2 0 When this bit is set and the CAL_EN bit is set, the RTC output is present on the P1.2/FP25/ZX pin.
1 RTC_P0P7 0 When this bit is set and the CAL_EN bit is set, the RTC output is present on the P0.7/SS/T1/RxD2 pin.
0 RTC_P0P5 0 When this bit is set and the CAL_EN bit is set, the RTC output is present on the P0.5/MISO/ZX pin.
RTC CALENDAR
The RTC has a full calendar, taking into account leap years. The rollover of the date to increment the month is implemented according to the
parameters shown in Table 136.
Table 136. Month Rollover
MONTH Register Rollover Value Estimated Month
0x01 31 January
0x02 28 or 29 days (see Table 137) February
0x03 31 March
0x04 30 April
0x05 31 May
0x06 30 June
0x07 31 July
0x08 31 August
0x09 30 September
0x0A 31 October
0x0B 30 November
0x0C 31 December
ADE5169/ADE5569 Data Sheet
Rev. E | Page 126 of 155
Table 137. Leap Years—Rollover After 29 Days
YEAR Register Estimated Year
0d04 2004
0d08 2008
0d12 2012
0d16 2016
0d20 2020
0d24 2024
0d28 2028
0d32 2032
0d36 2036
0d40
2040
0d44 2044
0d48 2048
0d52 2052
0d56 2056
0d60 2060
0d64 2064
0d68 2068
0d72 2072
0d76 2076
0d80 2080
0d84 2084
0d88 2088
0d92 2092
0d96 2096
RTC INTERRUPTS
The RTC alarm and interval timer interrupts are enabled by
setting the ETI bit in the Interrupt Enable and Priority 2 SFR
(IEIP2, Address 0xA9[2]). When an alarm or interval timer event
occurs, the corresponding flag is set and a pending RTC interrupt
is generated. If the RTC interrupt is enabled, the program vectors
to the RTC interrupt address, and the corresponding RTC flag
can be cleared in software. Moving to the RTC interrupt address
alone does not automatically clear the flag. To successfully
acknowledge the interrupt event, the flag must be cleared by
software. If the RTC interrupt is disabled when the event occurs,
the pending interrupt remains until the corresponding RTC flag
is cleared. Therefore, the ALFLAG and ITFLAG flags (Bit 6 and
Bit 2, respectively, in the RTC configuration SFR (TIMECON,
Address 0xA1)) drive the RTC interrupt and should be managed
by the user to keep track of the RTC events.
Note that, if the ADE5169/ADE5569 are awakened by an RTC
event, either the ALFLAG or ITFLAG, then the pending RTC
interrupt, must be serviced before the devices can go back to sleep
again. The ADE5169/ADE5569 keep waking up until this interrupt
has been serviced.
Interval Timer Alarm
The RTC can be used as an interval timer. When the interval timer
is enabled by setting ITEN (TIMECON[1]), the interval timer
clock source selected by the ITS1 and ITS0 bits (TIMECON[5:4]) is
passed through to an 8-bit counter. This counter increments on
every interval timer clock pulse until the 8-bit counter is equal to
the value in the alarm interval register. Then an alarm event is
generated, setting the ITFLAG bit (TIMECON[2]) and creating
a pending RTC interrupt. If the SIT bit (TIMECON[3]) is cleared,
the 8-bit counter is cleared and starts counting again. If the SIT
bit is set, the 8-bit counter is held in reset after the alarm occurs.
Take care when changing the interval timer timebase. The
recommended procedure is as follows:
1. If the INTVAL register is to be modified, write to the I N T VA L
register first. Then wait for one 128 Hz clock cycle to syn-
chronize with the RTC, 64,000 cycles at a 4.096 MHz
instruction cycle clock.
2. Disable the interval timer by clearing ITEN (TIMECON[1]).
Then wait for one 128 Hz clock cycle to synchronize with the
RTC, 64,000 cycles at a 4.096 MHz instruction cycle clock.
3. Read the TIMECON SFR to ensure that the ITEN bit is
cleared. If it is not, wait for another 128 Hz clock cycle.
4. Set the timebase bits, ITS1 and ITS0 (TIMECON[5:4]) to
configure the interval. Wait for a 128 Hz clock cycle for this
change to take effect.
RTC Wake-Up Alarm
The RTC can be used with an alarm to wake up periodically. The
alarm registers (AL_SEC, AL_MIN, AL_HOUR, AL_DAY, and
AL_DATE) should be set to the specific time that the alarm event
is required, and the corresponding ALxxx_EN bits must be set in
the RTC Configuration 2 SFR (TIMECON2, Address 0xA2). The
enabled alarm registers are then compared to their respective
RTC registers (SEC, MIN, HOUR, DAY, and DATE). When all
enabled alarms match their corresponding RTC registers, the alarm
flag is set, and a pending interrupt is generated. If the alarm flag
(ALFLAG, TIMECON[6]) is enabled, an RTC interrupt occurs
and the program vectors to the RTC interrupt address.
Data Sheet ADE5169/ADE5569
Rev. E | Page 127 of 155
RTC CRYSTAL COMPENSATION
The RTC provides registers to compensate for the tolerance of
the crystal frequency and its variation over temperature. Up to
±248 ppm frequency error can be calibrated out by the RTC
circuitry. The compensation is fully digital and implemented
by adding or subtracting pulses from the crystal clock signal.
The resolution of the RTC nominal compensation SFR
(RTCCOMP, Address 0xF6) is ±2 ppm/LSB, or 0.17 sec/day/LSB.
The RTC compensation circuitry adds the RTC temperature com-
pensation SFR (TEMPCAL, Address 0xF7) and the RTCCOMP
SFR to determine how much compensation is required. The sum
of these two registers is limited to ±248 ppm, or 42.85 sec/day.
RTC Calibration
The nominal crystal frequency can be calibrated by adjusting
the RTCCOMP SFR so that the clock going into the RTC is
precisely 32.768 kHz at 25°C.
Calibration Flow
An RTC calibration pulse output is on up to four pins configured
by the four LSBs in the RTC calibration configuration register
(RTC_CAL, Address 0x0F). Enable the RTC output by setting
the CAL_EN bit (RTC_CAL[6]).
The RTC calibration is accurate to within ±2 ppm over a 30.5 sec
window in all operational modes: PSM0, PSM1, and PSM2. Two
output frequencies are offered for the normal RTC mode: 1 Hz
with the FSEL bits = 00 and 512 Hz with the FSEL bits = 01
(RTC_CAL[5:4]).
A shorter window of 0.244 sec is offered for fast calibration during
PSM0 or PSM1 mode. Two output frequencies are offered for this
RTC calibration output mode: 500 Hz with the FSEL bits = 10 and
16 kHz with the FSEL bits = 11 (RTC_CAL[5:4]). Note that for the
0.244 sec calibration window, the RTC is clocked 125 times
faster than in the normal mode, resulting in timekeeping registers
that represent seconds/125, minutes/125, and hours/125, instead
of seconds, minutes, and hours. Therefore, this mode should be
used for calibration only.
Table 138. RTC Calibration Options
Option FSEL Bits
Calibration
Window (sec)
fRTCCAL
(Hz)
Normal Mode 0 00 30.5 1
Normal Mode 1 01 30.5 512
Calibration Mode 0 10 0.244 500
Calibration Mode 1 11 0.244 16,000
When no RTC compensation is applied, with RTCCOMP and
TEMPCAL equal to zero, the nominal compensation required
to account for the error in the external crystal can be determined.
In this case, it is not necessary to wait for an entire calibration
window to determine the error in the pulse output. Calculating
the error in frequency between two consecutive pulses on the
RTC calibration pin is sufficient.
The value to write to the RTCCOMP SFR is calculated from the
% error or seconds per day error on the frequency output. Each
bit of the RTCCOMP SFR represents 2 ppm of correction, where
1 sec/day error is equal to 11.57 ppm.
RTCCOMP = 5000 × (% Error)
RTCCOMP =
57
.112
1
×
× (second/day Error)
During calibration, user software writes the current time to the
RTC. Refer to the Access to Internal RTC Registers section for
more information on how to read and write to the RTC time
keeping registers.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 128 of 155
UART SERIAL INTERFACE
The ADE5169/ADE5569 UART can be configured in one of
four modes.
Shift register with baud rate fixed at fCORE/12
8-bit UART with variable baud rate
9-bit UART with baud rate fixed at fCORE/64 or fCORE/32
9-bit UART with variable baud rate
Variable baud rates are defined by using an internal timer to
generate any rate between 300 bauds/sec and 115,200 bauds/sec.
The UART serial interface provided in the ADE5169/ADE5569
is a full duplex serial interface. It is also receive buffered by storing
the first received byte in a receive buffer until the reception of
the second byte is complete. The physical interface to the UART
is provided via the RxD (P1.0/RxD) and TxD (P1.1/TxD) pins,
and the firmware interface is through the SFRs, as presented in
Table 139.
Both the serial port receive and transmit registers are accessed
through the serial port buffer SFR (SBUF, Address 0x99). Writing
to SBUF loads the transmit register, and reading SBUF accesses
a physically separate receive register.
An enhanced UART mode is offered by using the UART timer and
by providing enhanced frame error, break error, and overwrite
error detection. This mode is enabled by setting the EXTEN bit
in the configuration SFR (CFG, Address 0xAF[6]) (see the UART
Additional Features section). The enhanced serial baud rate control
SFR (SBAUDT, Address 0x9E) and UART timer fractional divider
SFR (SBAUDF, Address 0x9D) are used to configure the UART
timer and to indicate the enhanced UART errors.
UART SFRs
Table 139. Serial Port SFRs
SFR Address Bit Addressable Description
SCON 0x98 Yes Serial communications control (see Table 140).
SBUF 0x99 No Serial port buffer (see Table 141).
SBAUDT 0x9E No Enhanced serial baud rate control (see Table 142).
SBAUDF 0x9D No UART timer fractional divider (see Table 143).
Table 140. Serial Communications Control SFR (SCON, Address 0x98)
Bit Bit Address Mnemonic Default Description
[7:6] 0x9F, 0x9E SM0, SM1 00 UART serial mode select bits. These bits select the serial port operating mode.
SM0, SM1 Result (Selected Operating Mode)
00 Mode 0, shift register, fixed baud rate (fCORE/12)
01 Mode 1, 8-bit UART, variable baud rate
10 Mode 2, 9-bit UART, fixed baud rate (fCORE/32) or (fCORE/16)
11 Mode 3, 9-bit UART, variable baud rate
5 0x9D SM2 0 Multiprocessor communication enable bit. Enables multiprocessor communication in Mode 2
and Mode 3, and framing error detection in Mode 1.
In Mode 0, SM2 should be cleared.
In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received. If SM2 is
cleared, RI is set as soon as the byte of data is received.
In Mode 2 or Mode 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0.
If SM2 is cleared, RI is set as soon as the byte of data is received.
4 0x9C REN 0 Serial port receive enable bit. Set by user software to enable serial port reception. Cleared
by user software to disable serial port reception.
3 0x9B TB8 0 Serial port transmit (Bit 9). The data loaded into TB8 is the ninth data bit transmitted in
Mode 2 and Mode 3.
2 0x9A RB8 0 Serial port receiver (Bit 9). The ninth data bit received in Mode 2 and Mode 3 is latched into
RB8. For Mode 1, the stop bit is latched into RB8.
1 0x99 TI 0 Serial port transmit interrupt flag. Set by hardware at the end of the eighth bit in Mode 0 or
at the beginning of the stop bit in Mode 1, Mode 2, and Mode 3. TI must be cleared by
user software.
0 0x98 RI 0 Serial port receive interrupt flag. Set by hardware at the end of the eighth bit in Mode 0 or
halfway through the stop bit in Mode 1, Mode 2, and Mode 3. RI must be cleared by
user software.
Data Sheet ADE5169/ADE5569
Rev. E | Page 129 of 155
Table 141. Serial Port Buffer SFR (SBUF, Address 0x99)
Bit Mnemonic Default Description
[7:0] SBUF 0 Serial port data buffer.
Table 142. Enhanced Serial Baud Rate Control SFR (SBAUDT, Address 0x9E)
Bit Mnemonic Default Description
7 OWE 0 Overwrite error. This bit is set when new data is received and RI = 1 (Bit 0 in the SCON SFR,
Address 0x98). It indicates that SBUF was not read before the next character was transferred in,
causing the prior SBUF data to be lost. Write a 0 to this bit to clear it.
6 FE 0 Frame error. This bit is set when the received frame does not have a valid stop bit. This bit is read
only and is updated every time a frame is received.
5 BE 0 Break error. This bit is set whenever the receive data line (Rx) is low for longer than a full transmission
frame, which is the time required for a start bit, eight data bits, a parity bit, and half a stop bit. This
bit is updated every time a frame is received.
[4:3] SBTH 00 Extended divider ratio for baud rate setting, as shown in Table 144.
[2:0] DIV 000 Binary divider (see Table 144).
DIV Result
000 Divide by 1
001
Divide by 2
010
Divide by 4
011 Divide by 8
100 Divide by 16
101 Divide by 32
110 Divide by 64
111 Divide by 128
Table 143. UART Timer Fractional Divider SFR (SBAUDF, Address 0x9D)
Bit Mnemonic Default Description
7 UARTBAUDEN 0 UART baud rate enable. Set to enable UART timer to generate the baud rate. When set, the SMOD
bit (PCON, Address 0x87[7]), the TCLK bit (T2CON, Address 0xC8[4]), and the RCLK bit (T2CON,
Address 0xC8[5]) are ignored. Cleared to let the baud rate be generated as per a standard 8052.
6 Not implemented Not implemented, write don’t care.
[5:0] SBAUDF 0 UART timer fractional divider.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 130 of 155
Table 144. Common Baud Rates Using the UART Timer with a 4.096 MHz PLL Clock
Ideal Baud CD SBTH DIV SBAUDT SBAUDF % Error
115,200 0 0 1 0x01 0x87 +0.16
115,200 1 0 0 0x00 0x87 +0.16
57,600 0 0 2 0x02 0x87 +0.16
57,600 1 0 1 0x01 0x87 +0.16
38,400 0 0 2 0x02 0xAB −0.31
38,400 1 0 1 0x01 0xAB −0.31
38,400 2 0 0 0x00 0xAB −0.31
19,200 0 0 3 0x03 0xAB −0.31
19,200 1 0 2 0x02 0xAB −0.31
19,200 2 0 1 0x01 0xAB −0.31
19,200 3 0 0 0x00 0xAB −0.31
9600 0 0 4 0x04 0xAB −0.31
9600 1 0 3 0x03 0xAB −0.31
9600 2 0 2 0x02 0xAB −0.31
9600 3 0 1 0x01 0xAB −0.31
9600 4 0 0 0x00 0xAB −0.31
4800 0 0 5 0x05 0xAB −0.31
4800 1 0 4 0x04 0xAB −0.31
4800 2 0 3 0x03 0xAB −0.31
4800 3 0 2 0x02 0xAB −0.31
4800 4 0 1 0x01 0xAB −0.31
4800 5 0 0 0x00 0xAB −0.31
2400 0 0 6 0x06 0xAB −0.31
2400 1 0 5 0x05 0xAB −0.31
2400 2 0 4 0x04 0xAB −0.31
2400 3 0 3 0x03 0xAB −0.31
2400 4 0 2 0x02 0xAB −0.31
2400 5 0 1 0x01 0xAB −0.31
2400 6 0 0 0x00 0xAB −0.31
300
0
2
7
0x17
0xAB
−0.31
300 1 1 7 0x0F 0xAB −0.31
300 2 0 7 0x07 0xAB −0.31
300 3 0 6 0x06 0xAB −0.31
300 4 0 5 0x05 0xAB −0.31
300
5
0
4
0x04
0xAB
−0.31
300 6 0 3 0x03 0xAB −0.31
300 7 0 2 0x02 0xAB −0.31
Data Sheet ADE5169/ADE5569
Rev. E | Page 131 of 155
UART OPERATION MODES
Mode 0 (Shift Register with Baud Rate Fixed at fCORE/12)
Mode 0 is selected when the SM0 and SM1 bits in the serial
communications control SFR (SCON, Address 0x98[7:6]) are
cleared. In this shift register mode, serial data enters and exits
through the RxD pin. The TxD pin outputs the shift clock. The
baud rate is fixed at fCORE/12. Eight data bits are transmitted or
received.
Transmission is initiated by any instruction that writes to the
serial port buffer SFR (SBUF, Address 0x99). The data is shifted
out of the Pin RxD line. The eight bits are transmitted with the
least significant bit (LSB) first.
Reception is initiated when the serial port receive enable bit,
REN (SCON[4]), is 1, and the serial port receive interrupt bit, RI
(SCON[0]), is 0. When RI is cleared, the data is clocked into the
Pin RxD line, and the clock pulses are output from the Pin TxD
line as shown in Figure 104.
RxD
(DATA OUT)
TxD
(SHIFT CL OCK)
DATA BIT 0 DATA BI T 1 DATA BI T 6 DATA BIT 7
07411-078
Figure 104. 8-Bit Shift Register Mode
Mode 1 (8-Bit UART with Variable Baud Rate)
Mode 1 is selected by clearing the SM0 bit (SCON[7]) and setting
the SM1 bit (SCON[6]). Each data byte (LSB first) is preceded by
a start bit (0) and followed by a stop bit (1). Therefore, each frame
consists of 10 bits transmitted on the TxD pin or received on the
RxD pin.
The baud rate is set by a timer overflow rate. Timer 1 or Timer 2
can be used to generate baud rates, or both timers can be used
simultaneously where one generates the transmit rate and the
other generates the receive rate. There is also a dedicated timer
for baud rate generation, the UART timer, which has a fractional
divisor to precisely generate any baud rate (see the UART Timer
Generated Baud Rates section).
Transmission is initiated by a write to the serial port buffer SFR
(SBUF, Address 0x99). Next, a stop bit (1) is loaded into the ninth
bit position of the internal serial port shift register. The data is
output bit by bit until the stop bit appears on the TxD pin and
the transmit interrupt flag, TI (Address 0x98[1]), is automati-
cally set, as shown in Figure 105.
TxD
TI
(SCON[1])
START
BIT D0 D1 D2 D3 D4 D5 D6 D7
STOP BIT
SET INT E RRUP T
(FOR EXAMPLE,
READY F OR MORE DAT A)
07411-079
Figure 105. 8-Bit Variable Baud Rate
Reception is initiated when a 1-to-0 transition is detected on the
RxD pin. Assuming that a valid start bit is detected, character
reception continues. The eight data bits are clocked into the
internal serial port shift register.
All of the following conditions must be met at the time the final
shift pulse is generated to receive a character:
• If the extended UART is disabled (EXTEN = 0 in the CFG
SFR, Address 0xAF[6]), RI (SCON[0]) must be 0 to receive
a character. This ensures that the data in the SBUF SFR is not
overwritten if the last received character has not been read.
• If frame error checking is enabled by setting SM2 (SCON[5]),
the received stop bit must be set to receive a character. This
ensures that every character received comes from a valid
frame, with both a start bit and a stop bit.
If any of these conditions is not met, the received frame is irre-
trievably lost, and the receive interrupt flag (RI, SCON[0]) is
not set.
If the received frame meets these conditions, the following
events occur:
• The eight bits in the receive shift register are latched into
the SBUF SFR.
• The ninth bit (stop bit) is clocked into RB8 (SCON[2]).
• The receiver interrupt flag (RI, SCON[0]) is set.
Mode 2 (9-Bit UART with Baud Rate Fixed at fCORE/64 or
fCORE/32)
Mode 2 is selected by setting SM0 and clearing SM1. In this mode,
the UART operates in 9-bit mode with a fixed baud rate. The baud
rate is fixed at fCORE/64 by default, although setting the SMOD bit in
the program control SFR (PCON, Address 0x87[7]) doubles the
frequency to fCORE/32. Eleven bits are transmitted or received: a start
bit (0), eight data bits, a programmable ninth bit, and a stop bit (1).
The ninth bit is most often used as a parity bit or as part of a multi-
processor communication protocol, although it can be used for
anything, including a ninth data bit, if required.
To use the ninth data bit as part of a communication protocol for
a multiprocessor network such as RS-485, the ninth bit is set to
indicate that the frame contains the address of the device with
which the master wants to communicate. The devices on the net-
work are always listening for a packet with the ninth bit set and
are configured such that if the ninth bit is cleared, the frame is not
valid, and a receive interrupt is not generated. If the ninth bit is set,
all devices on the network receive the address and obtain a receive
character interrupt. The devices examine the address and, if it
matches one of the preprogrammed addresses of the device, that
device configures itself to listen to all incoming frames, even those
with the ninth bit cleared. Because the master has initiated commu-
nication with that device, all the following packets with the ninth
bit cleared are intended specifically for that addressed device until
another packet with the ninth bit set is received. If the address
does not match, the device continues to listen for address packets.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 132 of 155
To transmit, the eight data bits must be written into the serial
port buffer SFR (SBUF, Address 0x99). The ninth bit must be
written to TB8 in the serial communications control SFR (SCON,
Address 0x98[3]). When transmission is initiated, the eight data
bits from SBUF are loaded into the transmit shift register (LSB
first). The ninth data bit, held in TB8, is loaded into the ninth bit
position of the transmit shift register. The transmission starts at the
next valid baud rate clock. The serial port transmit interrupt flag
(TI, SCON[1]) is set as soon as the transmission completes, when
the stop bit appears on TxD.
All of the following conditions must be met at the time the final
shift pulse is generated to receive a character:
If the extended UART is disabled (EXTEN = 0 in the CFG
SFR, Address 0xAF[6]), RI (SCON[0]) must be 0 to receive
a character. This ensures that the data in SBUF is not over
written if the last received character has not been read.
If multiprocessor communication is enabled by setting
SM2 (SCON[5]), the received ninth bit must be set to receive a
character. This ensures that only frames with the ninth bit
set, which are frames that contain addresses, generate a
receive interrupt.
If any of these conditions is not met, the received frame is irre-
trievably lost, and the receive interrupt flag (RI in the SCON
SFR) is not set.
Reception for Mode 2 is similar to that of Mode 1. The eight
data bytes are input at RxD (LSB first) and loaded onto the receive
shift register. If the received frame meets the previous criteria,
the following events occur:
The eight bits in the receive shift register are latched into
the SBUF SFR.
The ninth data bit is latched into RB8 in the SCON SFR.
The receiver interrupt flag (RI in the SCON SFR) is set.
Mode 3 (9-Bit UART with Variable Baud Rate)
Mode 3 is selected by setting both SM0 and SM1 in the SCON
SFR. In this mode, the 8052 UART serial port operates in 9-bit
mode with a variable baud rate. The baud rate is set by a timer
overflow rate. Timer 1 or Timer 2 can be used to generate baud
rates, or both timers can be used simultaneously where one
generates the transmit rate and the other generates the receive
rate. There is also a dedicated timer for baud rate generation,
the UART timer, which has a fractional divisor to precisely
generate any baud rate (see the UART Timer Generated Baud
Rates section). The operation of the 9-bit UART is the same as
for Mode 2, but the baud rate can be varied.
In all four modes, transmission is initiated by any instruction
that uses SBUF as a destination register. Reception is initiated in
Mode 0 when RI = 0 and REN = 1 in the SCON SFR. Reception
is initiated in the other modes by the incoming start bit if REN = 1.
UART BAUD RATE GENERATION
Mode 0 Baud Rate Generation
The baud rate in Mode 0 is fixed.
Mode 0 Baud Rate =
12
CORE
f
Mode 2 Baud Rate Generation
The baud rate in Mode 2 depends on the value of the SMOD
bit in the program control SFR (PCON, Address 0x87[7]). If
SMOD = 0, the baud rate is 1/32 of the core clock. If SMOD = 1,
the baud rate is 1/16 of the core clock.
Mode 2 Baud Rate =
32
2SMOD
fCORE
Mode 1 and Mode 3 Baud Rate Generation
The baud rates in Mode 1 and Mode 3 are determined by the
overflow rate of the timer generating the baud rate, that is,
Timer 1, Timer 2, or the dedicated baud rate generator, the
UART timer, which has an integer and a fractional divisor.
Timer 1 Generated Baud Rates
When Timer 1 is used as the baud rate generator, the baud rates
in Mode 1 and Mode 3 are determined by the Timer 1 overflow
rate. The value of SMOD (PCON[7]) is as follows:
Mode 1 or Mode 3 Baud Rate =
32
2SMOD
Timer 1 Overflow Rate
The Timer 1 interrupt should be disabled in this application.
The timer itself can be configured for either timer or counter
operation and in any of its three running modes. In the most
typical application, it is configured for timer operation in auto
reload mode (high nibble of TMOD = 0010 binary, see Table 113).
In that case, the baud rate is given by the following formula:
Mode 1 or Mode 3 Baud Rate = )256(32
2TH1
fCORE
SMOD
Timer 2 Generated Baud Rates
Baud rates can also be generated by using Timer 2. Using Timer 2
is similar to using Timer 1 in that the timer must overflow 16 times
before a bit is transmitted or received. Because Timer 2 has a
16-bit autoreload mode, a wider range of baud rates is possible.
Mode 1 or Mode 3 Baud Rate = 16
1 × Timer 2 Overflow Rate
Therefore, when Timer 2 is used to generate baud rates, the
timer increments every two clock cycles rather than every core
machine cycle, as before. It increments six times faster than
Timer 1, and, therefore, baud rates six times faster are possible.
Data Sheet ADE5169/ADE5569
Rev. E | Page 133 of 155
Because Timer 2 has 16-bit autoreload capability, very low baud
rates are still possible. Timer 2 is selected as the baud rate generator
by setting RCLK and/or TCLK in the Timer/Counter 2 control
SFR (T2CON, Address 0xC8[5:4]). The baud rates for transmit
and receive can be simultaneously different. Setting RCLK and/or
TCLK puts Timer 2 into its baud rate generator mode, as shown in
Figure 107.
In this case, the baud rate is given by the following formula:
Mode 1 or Mode 3 Baud Rate =

)]2:2(65536[16( LRCAPHRCAP
fCORE
UART Timer Generated Baud Rates
The high integer dividers in a UART block mean that high speed
baud rates are not always possible. In addition, generating baud
rates requires the exclusive use of a timer, rendering it unusable
for other applications when the UART is required. To address this
problem, each ADE5169/ADE5569 has a dedicated baud rate
timer (UART timer) specifically for generating highly accurate
baud rates. The UART timer can be used instead of Timer 1 or
Timer 2 for generating very accurate high speed UART baud
rates, including 115,200 bps. This timer also allows a much wider
range of baud rates to be obtained. In fact, every desired bit rate
from 12 bps to 393,216 bps can be generated to within an error
of ±0.8%. The UART timer also frees up the other three timers,
allowing them to be used for different applications. A block
diagram of the UART timer is shown in Figure 106.
÷(1 + SBAUDF/64)
UART TIMER
Rx/Tx CLO CK
f
CORE
UARTBAUDEN
Rx CLO CK
Tx CLOCK
TIMER 1/TIMER 2
Rx CLOCK
FRACTIONAL
DIVIDE
R
0
0
1
1
TIMER 1/TIMER 2
Tx CLOCK
÷32
÷2
DIV + SBTH
07411-081
Figure 106. UART Timer, UART Baud Rate
Two SFRs, the enhanced serial baud rate control SFR (SBAUDT,
Address 0x9E) and UART timer fractional divider SFR (SBAUDF,
Address 0x9D), are used to control the UART timer. SBAUDT
is the baud rate control SFR; it sets up the integer divider (the DIV
bits, Bits[2:0]) and the extended divider (the SBTH bits, Bits[4:3])
for the UART timer.
The appropriate value to write to the DIV bits and the SBTH bits
can be calculated using the following formula, where fCORE is
defined in the POWCON SFR (see Table 26). Note that the DIV
value must be rounded down to the nearest integer.

2log
16
log
RateBaud
f
SBTHDIV
CORE
f
CORE
T2 PIN
(P1.4/T2/FP23)
T2EX PIN
(P1.3/T2EX/FP24)
TR2
CONTROL
TL2
(8 BIT S) TH2
(8 BITS)
RELOAD
EXEN2
CONTROL
TRANSITION
DETECTOR
EXF 2 TIMER 2
INTERRUPT
RCAP2L RCAP2H
TIMER 2
OVERFLOW
2
16
16
RCLK
TCLK
Rx
CLOCK
Tx
CLOCK
0
0
1
1
10 SMOD
TIMER 1
OVERFLOW
C/T2 = 0
C/T2 = 1
NOTE: AVAIL ABI LI T Y O F ADDIT IONAL
EXT E RNA L I NTERRUP T
07411-080
P1.4/T2/FP23
Figure 107. Timer 2, UART Baud Rates
ADE5169/ADE5569 Data Sheet
Rev. E | Page 134 of 155
SBAUDF is the fractional divider ratio required to achieve the
required baud rate. The appropriate value for SBAUDF can be
calculated with the following formula:
SBAUDF = 64 ×
1
216 RateBaud
f
SBTHDIV
CORE
Note that SBAUDF should be rounded to the nearest integer.
After the values for DIV and SBAUDF are calculated, the actual
baud rate can be calculated with the following formula:
Acutal Baud Rate =
64
1216 SBAUDF
f
SBTHDIV
CORE
For example, to obtain a baud rate of 9600 bps while operating
at a core clock frequency of 4.096 MHz and with the PLL CD
bits equal to 0
DIV + SBTH = )2log(
960016
000,096,4
log
= 4.74 = 4
Note that the DIV result is rounded down.
SBAUDF = 64 × 1
9600216
000,096,4
4
= 42.67 = 0x2B
Thus, the actual baud rate is 9570 bps, resulting in a 0.31% error.
UART ADDITIONAL FEATURES
Enhanced Error Checking
The extended UART provides frame error, break error, and over
write error detection. Framing errors occur when a stop bit is
not present at the end of the frame. A missing stop bit implies
that the data in the frame may not have been received properly.
Break error detection indicates whether the RxD line has been low
for longer than a 9-bit frame. It indicates that the data just received,
a 0 or null character, is not valid because the master has discon-
nected. Overwrite error detection indicates when the received data
has not been read fast enough and, as a result, a byte of data has
been lost.
The 8052 standard UART offers frame error checking for an 8-bit
UART through SM2 (Bit 5) and RB8 (Bit 2) in the serial commun-
ications control SFR (SCON, Address 0x98). Setting the SM2 bit
prevents frames without a stop bit from being received. The stop bit
is latched into the RB8 bit. This bit can be examined to determine
if a valid frame was received. The 8052 does not, however, provide
frame error checking for a 9-bit UART.
This enhanced error checking functionality is available through
the frame error bit, FE, in the enhanced serial baud rate control
SFR (SBAUDT, Address 0x9E[6]). The FE bit is set on framing
errors for both 8-bit and 9-bit UARTs.
Rx
RI
FE
EXTEN = 1
D7D6D5D4D3D2D1D0 STOP
START
07411-082
Figure 108. UART Timing in Mode 1
D7D6D5D4D3D2D1D0 D8 STOP
START
07411-083
Rx
RI
FE
EXTEN = 1
Figure 109. UART Timing in Mode 2 and Mode 3
The 8052 standard UART does not provide break error detection.
However, for an 8-bit UART, a break error can be detected when
the received character is 0, a null character, and when there is a
no stop bit because the RB8 bit is low. Break error detection is not
possible for a 9-bit 8052 UART because the stop bit is not recorded.
The ADE5169/ADE5569 enhanced break error detection is
available through the BE bit (SBAUDT[5]).
The 8052 standard UART prevents overwrite errors by not allowing
a character to be received when RI, the receive interrupt flag
(SCON[0]), is set. However, it does not indicate if a character
has been lost because the RI bit is set when the frame is received.
The enhanced UART overwrite error detection provides this infor-
mation. When the enhanced 8052 UART is enabled, a frame is
received regardless of the state of the RI flag. If RI = 1 when a new
byte is received, the byte in SCON is overwritten, and the overwrite
error flag, OWE2 in the Serial Communications Control 2 SFR
(SCON2, Address 0xE1[5]), is set. The overwrite error flag is
cleared when SBUF is read.
The extended UART is enabled by setting the EXTEN bit in the
configuration SFR (CFG, Address 0xAF[6]).
UART TxD Signal Modulation
There is an internal 38 kHz signal that can be OR’ed with the
UART transmit signal for use in remote control applications
(see the 38 kHz Modulation section).
Data Sheet ADE5169/ADE5569
Rev. E | Page 135 of 155
UART2 SERIAL INTERFACE
The ADE5169/ADE5569 UART2 is an 8-bit or 9-bit UART with
variable baud rate.
Variable baud rates are defined by using an internal timer to
generate any rate between 300 bauds/sec and 115,200 bauds/sec.
The UART2 serial interface provided in the ADE5169/ADE5569 is
a full duplex serial interface. It is also receive buffered by storing
the first received byte in a receive buffer until the reception of
the second byte is complete. The physical interface to the UART
is provided via the RxD2 (P0.7/SS/T1/RxD2) pin and the TxD2
(SDEN/P2.3/TxD2) pin, whereas the firmware interface is through
the SFRs presented in Table 145.
Both the serial port receive and transmit registers are accessed
through the SBUF2 SFR (Address 0xEB). Writing to SBUF2 loads
the transmit register, and reading SBUF2 accesses a physically
separate receive register.
An enhanced UART2 mode is offered by using the UART2 timer
and providing enhanced frame error, break error, and overwrite
error detection. The SBAUD2 SFR (Address 0xEE) is used to
configure the UART2 timer and to indicate the enhanced
UART2 errors.
UART2 SFRS
Table 145. Serial Port 2 SFRs
SFR Address Bit Addressable Description
SCON2 0xE1 No Serial Communications Control 2 (see Table 146).
SBUF2 0xEB No Serial Port 2 buffer (see Table 147).
SBAUD2 0xEE No Enhanced Serial Baud Rate Control 2 (see Table 148).
Table 146. Serial Communications Control 2 SFR (SCON2, Address 0xE1)1
Bit Mnemonic Default Description
7 N/A N/A Reserved.
6 EN-T8 0 9-bit UART, variable baud rate enable bit. When set, the UART2 is in 9-bit mode.
5 OWE2 0 Overwrite error. This bit is set when new data is received and RI2 = 1 in the SCON SFR. It indicates
that SBUF2 was not read before the next character was transferred in, causing the prior SBUF2
data to be lost. Write a 0 to this bit to clear it.
4 FE2 0 Frame error. This bit is set when the received frame does not have a valid stop bit. This bit is read
only and is updated every time a frame is received.
3 BE2 0 Break error. This bit is set whenever the receive data line (RxD2) is low for longer than a full
transmission frame, the time required for a start bit, eight data bits, a parity bit, and half a stop bit.
This bit is updated every time a frame is received.
2 REN2 0 Serial Port 2 receive enable bit. Set by user software to enable serial port reception. Cleared by
user software to disable serial port reception.
1 TI2 0 Serial Port 2 transmit interrupt flag. Set by hardware at the end of the eighth bit, TI2 must be
cleared by user software.
0 RI2 0 Serial Port 2 receive interrupt flag. Set by hardware at the end of the eighth bit, RI2 must be
cleared by user software.
1 N/A means not applicable.
Table 147. Serial Port 2 Buffer SFR (SBUF2, Address 0xEB)
Bit Mnemonic Default Description
[7:0] SBUF2 0 Serial Port 2 data buffer.
Table 148. Enhanced Serial Baud Rate Control 2 SFR (SBAUD2, Address 0xEE)
Bit Mnemonic Default Description
7 TB8_2 0 Serial port transmit (Bit 9). The data loaded into TB8_2 is the ninth data bit transmitted in 9-bit mode.
6 RB8_2 0 Serial port receive (Bit 9). The ninth data bit received in 9-bit mode is latched into RB8_2. For
8-bit mode, the stop bit is latched into RB8_2.
5 SBF2 Fractional divider Boolean. When set, SBAUDF2 = 0x2B. When cleared, SBAUDF2 = 0x07.
[4:3] SBTH2 0 Extended divider ratio for baud rate setting (see Table 149).
ADE5169/ADE5569 Data Sheet
Rev. E | Page 136 of 155
Bit Mnemonic Default Description
[2:0] DIV2 000 Binary divider.
DIV2
Result
000 Divide by 1 (see Table 149)
001 Divide by 2 (see Table 149)
010 Divide by 4 (see Table 149)
011 Divide by 8 (see Table 149)
100 Divide by 16 (see Table 149)
101 Divide by 32 (see Table 149)
110 Divide by 164 (see Table 149)
111
Divide by 128 (see Table 149)
Table 149. Common Baud Rates Using the UART2 Timer with a 4.096 MHz PLL Clock
Ideal Baud CD SBTH2 DIV2 SBF2 % Error
115,200 0 0 1 0 +0.16
115,200 1 0 0 0 +0.16
57,600 0 0 2 0 +0.16
57,600 1 0 1 0 +0.16
38,400 0 0 2 1 −0.31
38,400
1
0
1
1
−0.31
38,400 2 0 0 1 −0.31
19,200 0 0 3 1 −0.31
19,200 1 0 2 1 −0.31
19,200 2 0 1 1 −0.31
19,200 3 0 0 1 −0.31
9600 0 0 4 1 −0.31
9600 1 0 3 1 −0.31
9600 2 0 2 1 −0.31
9600 3 0 1 1 −0.31
9600 4 0 0 1 −0.31
4800 0 0 5 1 −0.31
4800 1 0 4 1 −0.31
4800 2 0 3 1 −0.31
4800
3
0
2
1
−0.31
4800 4 0 1 1 −0.31
4800 5 0 0 1 −0.31
2400 0 0 6 1 −0.31
2400 1 0 5 1 −0.31
2400 2 0 4 1 −0.31
2400 3 0 3 1 −0.31
2400 4 0 2 1 −0.31
2400
5
0
1
1
−0.31
2400 6 0 0 1 −0.31
300 0 2 7 1 −0.31
300
1
1
7
1
−0.31
300 2 0 7 1 −0.31
300 3 0 6 1 −0.31
300 4 0 5 1 −0.31
300 5 0 4 1 −0.31
300 6 0 3 1 −0.31
300 7 0 2 1 −0.31
Data Sheet ADE5169/ADE5569
Rev. E | Page 137 of 155
UART2 OPERATION MODES
The UART2 has two operation modes in which each data byte
(LSB first) is preceded by a start bit (0), followed by a stop bit (1).
Therefore, each frame consists of 10 bits transmitted on the
TxD2 pin or received on the RxD2 pin.
The baud rate is set by a dedicated timer for baud rate genera-
tion, the UART2 timer, which has a fractional divisor to precisely
generate any baud rate.
Transmission is initiated by a write to the Serial Port 2 buffer SFR
(SBUF2, Address 0xEB). Next, a stop bit (1) is loaded into the
ninth bit position of the serial port shift register. The data is output
bit by bit until the stop bit appears on the TxD2 pin, and the
Serial Port 2 transmit interrupt flag, TI2 (SCON2[1]) is auto-
matically set, as shown in Figure 110.
TxD2
TI2
(SCON2[1])
START
BIT D0 D1 D2 D3 D4 D5 D6 D7
STOP BIT
SET INT ERRUPT
(FOR EXAMPLE,
READY FOR MORE DAT A)
07411-188
Figure 110. 8-Bit Variable Baud Rate
Reception is initiated when a 1-to-0 transition is detected on the
RxD2 pin. Assuming that a valid start bit is detected, character
reception continues. The eight data bits are clocked into the serial
port shift register.
All of the following conditions must be met at the time the final
shift pulse is generated to receive a character:
If the extended UART is disabled (EXTEN = 0, CFG[6]),
RI2 (SCON2[0]) must be 0 to receive a character. This ensures
that the data in the SBUF2 SFR is not overwritten if the last
received character has not been read.
If frame error checking is enabled by setting FE2 (SCON2[4]),
the received stop bit must be set to receive a character. This
ensures that every character received comes from a valid
frame, with both a start bit and a stop bit.
If any of these conditions is not met, the received frame is irre-
trievably lost, and the Serial Port 2 receive interrupt flag, RI2
(SCON2[0]), is not set.
If the received frame meets the preceding conditions, the following
events occur:
The eight bits in the receive shift register are latched into
SBUF2.
The Serial Port 2 receiver interrupt flag (RI2) is set.
Transmission is initiated by any instruction that uses SBUF2 as
a destination register. Reception is initiated by the incoming start
bit if REN2 = 1 in the SCON2 SFR, Address0xE1[2].
9-Bit UART2 with Variable Baud Rate
Setting EN-T8 (SCON2[6]) selects the 9-bit mode. In this mode,
the UART2 serial port operates in 9-bit mode with a variable baud
rate. The baud rate is set by a dedicated timer for baud rate
generation, the UART2 timer, which has a fractional divisor to
precisely generate any baud rate (see the UART2 Timer Generated
Baud Rates section). The operation of the 9-bit UART2 is the same
as for the 9-bit mode of the UART.
In both modes, transmission is initiated by any instruction that
uses SBUF2 as a destination register. Reception is initiated in
8-bit mode when RI2 = 0 and REN2 = 1 in the SCON2 SFR.
Reception is initiated in the 9-bit mode by the incoming start
bit if REN2 = 1.
UART2 BAUD RATE GENERATION
The baud rate is determined by the overflow rate of the dedicated
baud rate generator, the UART2 timer, which has an integer and
fractional divisor.
UART2 Timer Generated Baud Rates
The enhanced Serial Baud Rate Control 2 SFR (SBAUD2,
Address 0xEE) is used to control the UART2 timer. SBAUD2 is
the baud rate control SFR; it sets up the integer divider (DIV2,
SBAUD2[2:0]) and the extended divider (SBTH2, SBAUD2[4:3])
for the UART2 timer.
The desired value to write to DIV2 and to SBTH2 can be
calculated using the following formula, where fcore is defined in
the POWCON SFR. Note that the DIV2 value must be rounded
down to the nearest integer.
DIV2 + SBTH2 =

2log
16
log
RateBaud
fCORE
SBAUDF2 is the fractional divider ratio required to achieve the
required baud rate. The appropriate value for SBAUDF2 can be
calculated with the following formula:
SBAUDF2 = 1
216
64 22
RateBaud
f
SBTHDIV
CORE
Note that SBAUDF2 can take only two values, 0x2B or 0x07, by
clearing or by setting the SBF2 bit (SBAUD2[5]), respectively.
These values were chosen to provide an accurate baud rate for
300, 2400, 4800, 9600, 19,200, 38,400, 57,600, and 115,200 bps.
When DIV2 and SBAUDF2 are calculated, the actual baud rate
can be calculated, using the following formula:
Actual Baud Rate =
64
2
1216 22 SBAUDF
f
SBTHDIV
CORE
ADE5169/ADE5569 Data Sheet
Rev. E | Page 138 of 155
For example, to get a baud rate of 9600 while operating at
a core clock frequency of 4.096 MHz, with the PLL CD bits
(POWCON[2:0]) equal to 0
DIV2 + SBTH2 = log(4,096,000/(16 × 9600))/log2 =
4.74 = 4
Note that the DIV result is rounded down.
SBAUDF2 = 64 × (4,096,000/(16 × 23 × 9600) − 1) =
42.67 = 0x2B
Therefore, the actual baud rate is 9570 bps, which gives an error
of 0.31%.
UART2 ADDITIONAL FEATURES
Enhanced Error Checking
The extended UART2 provides frame error, break error, and
overwrite error detection. Framing errors occur when a stop bit
is not present at the end of the frame. A missing stop bit implies
that the data in the frame may not have been received properly.
Break error detection indicates whether the RxD2 line is low for
longer than a 9-bit frame. It indicates that the data just received,
a 0 or NULL character, is not valid because the master has discon-
nected. Overwrite error detection indicates whether the received
data is not read fast enough and, as result, a byte of data is lost.
Data Sheet ADE5169/ADE5569
Rev. E | Page 139 of 155
SERIAL PERIPHERAL INTERFACE (SPI)
The ADE5169/ADE5569 integrate a complete hardware serial
peripheral interface on chip. The SPI is full duplex so that eight bits
of data are synchronously transmitted and simultaneously received.
This SPI implementation is double buffered, allowing users to
read the last byte of received data while a new byte is shifted in.
The next byte to be transmitted can be loaded while the current
byte is shifted out.
The SPI port can be configured for master or slave operation.
The physical interface to the SPI is via the MISO (P0.5/MISO/ZX),
MOSI (P0.4/MOSI/SDATA), SCLK (P0.6/SCLK/T0), and SS
(P0.7/SS/T1/RxD2) pins, while the firmware interface is via the
SFRs listed in Table 150.
Note that the SPI pins are shared with the I2C pins. Therefore, the
user can enable only one interface at a time. The SCPS bit in the
configuration SFR (CFG, Address 0xAF[5]) selects which
peripheral is active.
SPI REGISTERS
Table 150. SPI SFR List
SFR Address Mnemonic R/W Length (Bits) Default Description
0x9A SPI2CTx W 8 0 SPI/I2C transmit buffer (see Table 151).
0x9B SPI2CRx R 8 0 SPI/I2C receive buffer (see Table 152).
0xE8 SPIMOD1 R/W 8 0x10 SPI Configuration SFR 1 (see Table 153).
0xE9 SPIMOD2 R/W 8 0 SPI Configuration SFR 2 (see Table 154).
0xEA SPISTAT R/W 8 0 SPI interrupt status (see Table 155).
Table 151. SPI/I2C Transmit Buffer SFR (SPI2CTx, Address 0x9A)
Bit Mnemonic Default Description
[7:0] SPI2CTx 0 SPI or I2C transmit buffer. When the SPI2CTx SFR is written, its content is transferred to the transmit
FIFO input. When a write is requested, the FIFO output is sent on the SPI or I2C bus.
Table 152. SPI/I2C Receive Buffer SFR (SPI2CRx, Address 0x9B)
Bit Mnemonic Default Description
[7:0] SPI2CRx 0 SPI or I2C receive buffer. When the SPI2CRx SFR is read, one byte from the receive FIFO output is
transferred to the SPI2CRx SFR. A new data byte from the SPI or I2C bus is written to the FIFO input.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 140 of 155
Table 153. SPI Configuration SFR 1 (SPIMOD1, Address 0xE8)
Bit Bit Address Mnemonic Default Description
[7:6] 0xEF to 0xEE Reserved 00 Reserved.
5 0xED INTMOD 0 SPI interrupt mode.
INTMOD Result
0 SPI interrupt is set when the SPI Rx buffer is full
1 SPI interrupt is set when the SPI Tx buffer is empty
4 0xEC AUTO_SS 1 SS output control (see Figure 111).
AUTO_SS Result
0 The SS pin is held low while this bit is cleared, allowing manual chip select
control using the SS pin
1 Single byte read or write; the SS pin goes low during a single byte
transmission and then returns high
Continuous transfer; the SS pin goes low during the duration of the
multibyte continuous transfer and then returns high
3 0xEB SS_EN 0 Slave mode, SS input enable.
When this bit is set to Logic 1, the SS pin is defined as the slave select input pin for the
SPI slave interface.
2 0xEA RxOFW 0 Receive buffer overflow write enable.
RxOFW Result
0 If the SPI2CRx SFR has not been read when a new data byte is received,
the new byte is discarded
1 If the SPI2CRx SFR has not been read when a new data byte is received,
the new byte overwrites the old data
[1:0] 0xE9 to 0xE8 SPIR 00 Master mode, SPI SCLK frequency.
SPIR Result (f
CORE
= 4.096 MHz)
00 f
CORE
/8 = 512 kHz
01
fCORE/16 = 256 kHz
10 f
CORE
/32 = 128 kHz
11 f
CORE
/64 = 64 kHz
Data Sheet ADE5169/ADE5569
Rev. E | Page 141 of 155
Table 154. SPI Configuration SFR 2 (SPIMOD2, Address 0xE9)
Bit Mnemonic Default Description
7 SPICONT 0 Master mode, SPI continuous transfer mode enable bit.
SPICONT Result
0 The SPI interface stops after one byte is transferred and SS is deasserted. A new data transfer can
be initiated after a stalled period.
1 The SPI interface continues to transfer data until no valid data is available in the SPI2CTx SFR.
SS remains asserted until the SPI2CTx SFR and the transmit shift registers are empty.
6 SPIEN 0 SPI interface enable bit.
SPIEN Result
0 The SPI interface is disabled.
1 The SPI interface is enabled.
5 SPIODO 0 SPI open-drain output configuration bit.
SPIODO Result
0 Internal pull-up resistors are connected to the SPI outputs.
1 The SPI outputs are open drain and need external pull-up resistors. The pull-up voltage should
not exceed the specified operating voltage.
4 SPIMS_b 0 SPI master mode enable bit.
SPIMS_b Result
0 The SPI interface is defined as a slave.
1 The SPI interface is defined as a master.
3 SPICPOL 0 SPI clock polarity configuration bit (see Figure 113).
SPICPOL Result
0 The default state of SCLK is low, and the first SCLK edge is rising. Depending on the SPICPHA bit,
the SPI data output changes state on the falling or rising edge of SCLK, whereas the SPI data input
is sampled on the rising or falling edge of SCLK.
1 The default state of SCLK is high, and the first SCLK edge is falling. Depending on the SPICPHA
bit, the SPI data output changes state on the rising or falling edge of SCLK, whereas the SPI data
input is sampled on the falling or rising edge of SCLK.
2 SPICPHA 0 SPI clock phase configuration bit (see Figure 113).
SPICPHA Result
0 The SPI data output changes state when SS goes low at the second edge of SCLK and then every
two subsequent edges, whereas the SPI data input is sampled at the first SCLK edge and then
every two subsequent edges.
1 The SPI data output changes state at the first edge of SCLK and then every two subsequent
edges, whereas the SPI data input is sampled at the second SCLK edge and then every two
subsequent edges.
1 SPILSBF 0 Master mode, LSB first configuration bit.
SPILSBF Result
0 The MSB of the SPI outputs is transmitted first.
1 The LSB of the SPI outputs is transmitted first.
0 TIMODE 1 Transfer and interrupt mode of the SPI interface.
TIMODE Result
1 See Bit 5, Bit 4, and Bit 1 of Table 155 for mode selection.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 142 of 155
Table 155. SPI Interrupt Status SFR (SPISTAT, Address 0xEA)
Bit Mnemonic Default Description
7 BUSY 0 SPI peripheral busy flag.
BUSY Result
0 The SPI peripheral is idle.
1 The SPI peripheral is busy transferring data in slave or master mode.
6 MMERR 0 SPI multimaster error flag. Write a 0 to this bit to clear it.
MMERR Result
0 A multiple master error has not occurred.
1 If the SS_EN bit (SPIMOD1, Address 0xE8[3]) is set, enabling the slave select input and asserting
the SS pin while the SPI peripheral is transferring data as a master, this flag is raised to indicate
the error. Write a 0 to this bit to clear it.
5 SPIRxOF 0 SPI receive overflow error flag. Write a 0 to this bit to clear it.
SPIRxOF TIMODE Result
0 X1 The SPI2CRx SFR (Address 0x9B) contains valid data.
1 1
Set if the SPI2CRx SFR is not read before the end of the next byte transfer. If the RxOFW
bit (SPIMOD1, Address 0xE8[2]) is set and this condition occurs, SPI2CRx is overwritten.
4 SPIRxIRQ 0 SPI receive mode interrupt flag. Write a 0 to this bit to clear it.
SPIRxIRQ TIMODE Result
0 X1 The SPI2CRx SFR does not contain new data.
1 0
Set when the SPI2CRx SFR contains new data. If the SPI/I2C interrupt is enabled, an
interrupt is generated when this bit is set. If the SPI2CRx SFR is not read before the
end of the current byte transfer, the transfer stops and the SS pin is deasserted.
1 1 The SPI2CRx SFR contains new data.
3 SPIRxBF 0 Status bit for the SPI Rx buffer. When set, the Rx FIFO is full. A read of the SPI2CRx SFR clears this flag.
2 SPITxUF 0 Status bit for SPI Tx buffer. When set, the Tx FIFO is underflowing and data can be written into SPI2CTx
(Address 0x9A). Write a 0 to this bit to clear it.
1 SPITxIRQ 0 SPI transmit mode interrupt flag. Write a 0 to this bit to clear it.
SPITxIRQ TIMODE Result
0 X1 The SPI2CTx SFR is full.
1 0 The SPI2CTx SFR is empty.
1 1
Set when the SPI2CTx SFR is empty. If the SPI/I2C interrupt is enabled, an interrupt is
generated when this bit is set. If new data is not written to the SPI2CTx SFR before the
end of the current byte transfer, the transfer stops and the SS pin is deasserted.
0 SPITxBF 0 Status bit for the SPI Tx buffer. When set, the SPI Tx buffer is full. Write a 0 to this bit to clear it.
1 X means don’t care.
SPI PINS
MISO (Master In, Slave Out Data I/O Pin)
The MISO (P0.5/MISO/ZX) pin is configured as an input line
in master mode and as an output line in slave mode. The MISO
line on the master (data in) should be connected to the MISO
line in the slave device (data out). The data is transferred as byte
wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin)
The MOSI (P0.4/MOSI/SDATA) pin is configured as an output
line in master mode and as an input line in slave mode. The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). The data is transferred as byte
wide (8-bit) serial data, MSB first.
SCLK (Serial Clock I/O Pin)
The master serial clock (SCLK) is used to synchronize the data
being transmitted and received through the MOSI and MISO data
lines. The SCLK (P0.6/SCLK/T0) pin is configured as an output
in master mode and as an input in slave mode.
In master mode, the bit rate, polarity, and phase of the clock are
controlled by SPI Configuration SFR 1 (SPIMOD1, Address 0xE8)
and SPI Configuration SFR 2 (SPIMOD2, Address 0xE9).
In slave mode, the SPIMOD2 SFR (Address 0xE9) must be
configured with the phase and polarity of the expected input
clock.
In both master and slave modes, the data is transmitted on one
edge of the SCLK signal and sampled on the other. It is important,
therefore, that the SPICPOL and SPICPHA bits (SPIMOD2[3:2])
be configured the same for the master and slave devices.
Data Sheet ADE5169/ADE5569
Rev. E | Page 143 of 155
SS (Slave Select Pin)
In SPI slave mode, a transfer is initiated by the assertion of SS
low. The SPI port then transmits and receives 8-bit data until
the data is concluded by the deassertion of SS according to the
AUTO_SS bit setting (SPIMOD1[4]). In slave mode, SS is always
an input.
In SPI master mode, the SS (P0.7/SS/T1/RxD2) pin can be used
to control data transfer to a slave device. In the automatic slave
select control mode, the SS pin is asserted low to select the slave
device and then raised to deselect the slave device after the transfer
is complete. Automatic slave select control is enabled by setting
the AUTO_SS bit (SPIMOD1[4]).
In a multimaster system, the SS pin can be configured as an
input so that the SPI peripheral can operate as a slave in some
situations and as a master in others. In this case, the slave selects
for the slaves controlled by this SPI peripheral should be
generated with general I/O pins.
SPI MASTER OPERATING MODES
The double buffered receive and transmit registers can be used to
maximize the throughput of the SPI peripheral by continuously
streaming out data in master mode. The continuous transmit mode
is designed to use the full capacity of the SPI. In this mode, the
master transmits and receives data until the SPI/I2C transmit
buffer SFR (SPI2CTx, Address 0x9A) is empty at the start of a byte
transfer. Continuous mode is enabled by setting the SPICONT bit
(SPIMOD2[7]). The SPI peripheral also offers a single byte read/
write function.
In master mode, the type of transfer is handled automatically,
depending on the configuration of the SPICONT bit. The
following procedures show the sequence of events that should be
performed for each master operating mode. Based on the SS
configuration, some of these events take place automatically.
Procedures for Using SPI as a Master
Single-Byte Write Mode, SPICONT (SPIMOD2[7]) = 0
1. Write to the SPI2CTx SFR.
2. SS is asserted low, and a write routine is initiated.
3. The SPITxIRQ interrupt flag (SPISTAT[1]) is set when the
SPI2CTx register is empty.
4. SS is deasserted high.
5. Write to the SPI2CTx SFR to clear the SPITxIRQ
interrupt flag.
Continuous Mode, SPICONT (SPIMOD2[7]) = 1
1. Write to the SPI2CTx SFR.
2. SS is asserted low, and a write routine is initiated.
3. Wait for the SPITxIRQ interrupt flag to write to SPI2CTx SFR.
4. Transfer continues until the SPI2CTx register and transmit
shift registers are empty.
5. The SPITxIRQ interrupt flag is set when the SPI2CTx
register is empty.
6. SS is deasserted high.
7. Write to the SPI2CTx SFR to clear the SPITxIRQ
interrupt flag.
Figure 111 shows the SPI output for certain automatic chip select
and continuous mode selections. Note that if the continuous mode
is not used, a short delay is inserted between transfers.
SCLK
SS
DOUT
DIN DIN1 DIN2
AUTO _S S = 1
SPICONT = 0
SCLK
SS
DOUT
DIN DIN1
AUTO _S S = 1
SPICONT = 1 DIN2
AUTO _S S = 0
SPICONT = 0
(MANUAL SS CONT ROL)
DOUT1 DOUT2
DOUT1 DOUT2
SCLK
SS
DOUT
DIN DIN1 DIN2
DOUT1 DOUT2
07411-084
Figure 111. Automatic Chip Select and Continuous Mode Output
Note that reading the contents of the SPI/I2C receive buffer SFR
(SPI2CRx, Address 0x9B) should be done using a 2-cycle instruc-
tion set, such as MOV A or SPI2CRX. Using a 3-cycle instruction
set, such as MOV 0x3D or SPI2CRX, does not transfer the right
information into the target register.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 144 of 155
SPI INTERRUPT AND STATUS FLAGS
The SPI interface has several status flags that indicate the status
of the double buffered receive and transmit registers. Figure 112
shows when the status and interrupt flags are raised. The transmit
interrupt occurs when the transmit shift register is loaded with the
data in the SPI/I2C transmit buffer SFR (SPI2CTx, Address 0x9A).
If the SPI master is in transmit operating mode and the SPI2CTx
SFR has not been written with new data by the beginning of the
next byte transfer, the transmit operation stops.
When a new byte of data is received in the SPI/I2C receive buffer
SFR (SPI2CRx, Address 0x9B), the SPI receive interrupt flag,
SPIRxIRQ (SPISTAT, Address 0xEA[4]), is raised.
If the data in the SPI/I2C receive buffer SFR (SPI2CRx, Address
0x9B) is not read before new data is ready to be loaded into the
SPI2CRx SFR, an overflow condition occurs. This overflow
condition, indicated by the SPIRxOF flag (SPISTAT[5]), forces the
new data to be discarded or overwritten, depending on the setting
of the RxOFW bit (SPIMOD1, Address 0xE8[2]).
SPITx
TRANSMIT SHI FT REG I STER
SPITxIRQ = 1
SPI Tx (EM P TY)
TRANSMI T SHI F T REGI STE R
STOPS TRANSFER IF TIMODE = 1
SPIRx
RECEIVE SHIFT REGISTER
SPIRxIRQ = 1
SPIRx (FULL)
RECEIVE SHIFT REGISTER
SPIRxO F = 1
07411-085
Figure 112. SPI Receive and Transmit Interrupt and Status Flags
SCLK
(SPICPOL = 0)
MISO
SCLK
(SPICPOL = 1)
MOSI
SPIRx AND
SPITx FLAGS
WITH INTMOD = 1
SPIRx AND
SPITx FLAGS
WITH INTMOD = 0
SS
SPIRx AND
SPITx FLAGS
WITH INTMOD = 0
SPI CP HA = 1
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB ?
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB ?
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB?
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB?
MISO
MOSI
SPIRx AND
SPITx FLAGS
WITH INTMOD = 1
SPICPHA = 0
07411-086
Figure 113. SPI Timing Configurations
Data Sheet ADE5169/ADE5569
Rev. E | Page 145 of 155
I2C-COMPATIBLE INTERFACE
The ADE5169/ADE5569 support a fully licensed I2C interface.
The I2C interface is implemented as a full hardware master.
SDATA (P0.4/MOSI/SDATA) is the data I/O pin, and SCLK
(P0.6/SCLK/T0) is the serial clock. These two pins are shared with
the MOSI and SCLK pins of the on-chip SPI interface. Therefore,
the user can enable only one interface at a time on these pins. The
SCPS bit in the configuration SFR (CFG, Address 0xAF[5]) selects
which peripheral is active.
The two pins used for data transfer, SDATA and SCLK, are
configured in a wire-AND format that allows arbitration in a
multimaster system.
The transfer sequence of an I2C system consists of a master device
initiating a transfer by generating a start condition while the bus
is idle. The master transmits the address of the slave device and
the direction of the data transfer in the initial address transfer. If
the slave acknowledges, the data transfer is initiated. This continues
until the master issues a stop condition and the bus becomes idle.
SERIAL CLOCK GENERATION
The I2C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (256 kHz) or in standard mode (32 kHz).
The bit rate is defined in the I2CMOD SFR (Address 0xE8)
as follows:
]0:1[2
216 CRI
CORE
SCLK
f
f
SLAVE ADDRESSES
The I2C slave address SFR (I2CADR, Address 0xE9) contains
the slave device ID. The LSB of this register contains a read/write
request. A write to this SFR starts the I2C communication.
I2C REGISTERS
The I2C peripheral interface consists of five SFRs.
I2CMOD
SPI2CSTAT
I2CADR
SPI2CTx
SPI2CRx
Because the SPI and I2C serial interfaces share the same pins,
they also share the same SFRs, such as the SPI2CTx and SPI2CRx
SFRs. In addition, the I2CMOD, I2CADR, and SPI2CSTAT SFRs
are shared with the SPIMOD1, SPIMOD2, and SPISTAT SFRs,
respectively.
Table 156. I2C SFR List
SFR Address Mnemonic R/W Length Default Description
0x9A SPI2CTx W 8 SPI/I2C transmit buffer (see Table 151).
0x9B SPI2CRx R 8 0 SPI/I2C receive buffer (see Table 152).
0xE8 I2CMOD R/W 8 0 I2C mode (see Table 157).
0xE9 I2CADR R/W 8 0 I2C slave address (see Table 158).
0xEA SPI2CSTAT R/W 8 0 I2C interrupt status (see Table 159).
Table 157. I2C Mode SFR (I2CMOD, Address 0xE8)
Bit Bit Address Mnemonic Default Description
7 0xEF I2CEN 0 I2C enable bit. When this bit is set to Logic 1, the I2C interface is enabled. A write to the
I2CADR SFR (Address 0xE9) starts a communication.
[6:5] 0xEE to 0xED I2CR 00 I2C SCLK frequency.
I2CR Result
00 fCORE/16 = 256 kHz if fCORE = 4.096 MHz
01 fCORE/32 = 128 kHz if fCORE = 4.096 MHz
10 fCORE/64 = 64 kHz if fCORE = 4.096 MHz
11 fCORE/128 = 32 kHz if fCORE = 4.096 MHz
[4:0] 0xEC to 0xE8 I2CRCT 00000 Configures the length of the I2C received FIFO buffer. The I2C peripheral stops when
I2CRCT[4:0] + 1 byte have been read, or if an error occurs.
Table 158. I2C Slave Address SFR (I2CADR, Address 0xE9)
Bit Mnemonic Default Description
[7:1] I2CSLVADR 0 Address of the I2C slave being addressed. Writing to this register starts the I2C transmission (read or write).
0 I2CR_W 0 Command bit for read or write. When this bit is set to Logic 1, a read command is transmitted on the
I2C bus. Data from the slave in the SPI2CRx SFR (Address 0x9B) is expected after a command byte.
When this bit is set to Logic 0, a write command is transmitted on the I2C bus. Data to the slave is
expected in the SPI2CTx SFR.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 146 of 155
Table 159. I2C Interrupt Status SFR (SPI2CSTAT, Address 0xEA)
Bit Mnemonic Default Description
7 I2CBUSY 0 This bit is set to Logic 1 when the I
2
C interface is used. When set, the Tx FIFO is emptied.
6
I2CNOACK
0
I2C no acknowledgement transmit interrupt. This bit is set to Logic 1 when the slave device does
not send an acknowledgement. The I2C communication is stopped after this event. Write a 0 to this
bit to clear it.
5 I2CRxIRQ 0 I
2
C receive interrupt. This bit is set to Logic 1 when the receive FIFO is not empty. Write a 0 to this
bit to clear it.
4 I2CTxIRQ 0 I2C transmit interrupt. This bit is set to Logic 1 when the transmit FIFO is empty. Write a 0 to this bit
to clear it.
[3:2] I2CFIFOSTAT 00 Status bits for 3- or 4-byte deep I2C FIFO. The FIFO monitored in these two bits is the one currently
used in I2C communication (receive or transmit) because only one FIFO is active at a time.
I2CFIFOSTAT Result
00 FIFO empty
01 Reserved
10 FIFO half full
11
FIFO full
1 I2CACC_ERR 0 Set when trying to write and read at the same time. Write a 0 to this bit to clear it.
0 I2CTxWR_ERR 0 Set when a write is attempted when the I
2
C transmit FIFO is full. Write a 0 to this bit to clear it.
READ AND WRITE OPERATIONS
SCLK
SDATA
START BY
MASTER ACK BY
SLAVE ACK BY
MASTER
FRAME 2
DATA BYTE 1 FROM M AS TER
FRAME 1
SERI AL BUS ADDRE S S BY TE
1 9 91
A0A1A2A3A4A5A6 R/W D0D1D2D3D4D5D6D7
9
1
D0D1D2D3D4
D5D6D7
FRAME N + 1
DATA BYTE N FROM S LAVE
STOP BY
MASTER
NACK BY
MASTER
07411-087
Figure 114. I2C Read Operation
SCLK
SDATA
START BY
MASTER ACK BY
SLAVE ACK BY
SLAVE
FRAME 2
DATA BYTE 1 FROM M AS TER
FRAME 1
SERI AL BUS ADDRE S S BY TE
1 9 91
STOP BY
MASTER
A0A1A2A3A4A5A6 R/W D0D1D2D3D4
D5D6D7
07411-088
Figure 115. I2C Write Operation
Figure 114 and Figure 115 depict I2C read and write operations,
respectively. Note that the LSB of the I2CADR SFR (Address 0xE9)
is used to select whether a read or write operation is performed
on the slave device. During the read operation, the master acknowl-
edgements are generated automatically by the I2C peripheral. The
master generated no acknowledge (NACK) before the end of
a read operation is also automatically generated after the I2CRCT
bits in the I2CMOD SFR (Address 0xE8[4:0]) have been read from
the slave. If the I2CADR register is updated during a transmission,
the master generates a start condition instead of a stop at the end
of the read or write operation and then continues with the next
communication.
Reading the SPI/I2C Receive Buffer SFR (SPI2CRx,
Address 0x9B)
Reading the SPI2CRx SFR should be done with a 2-cycle
instruction, such as
Mov a, spi2cr x or Mov R0, spi2crx .
A 3-cycle instruction, such as
Mov 3dh, spi2crx
does not transfer the right data into RAM Address 0x3D.
Data Sheet ADE5169/ADE5569
Rev. E | Page 147 of 155
I2C RECEIVE AND TRANSMIT FIFOS
The I2C peripheral has a 4-byte receive FIFO and a 4-byte transmit
FIFO. The buffers reduce the overhead associated with using
the I2C peripheral. Figure 116 shows the operation of the I2C
receive and transmit FIFOs.
The Tx FIFO buffer can be loaded with four bytes to be transmitted
to the slave at the beginning of a write operation. When the trans-
mit FIFO is empty, the I2C transmit interrupt flag (I2CTxIRQ) is
set in the I2C interrupt status SFR (SPI2CSTAT, Address 0xEA[4]),
and the PC vectors to the I2C interrupt vector if this interrupt is
enabled. If a new byte is not loaded into the Tx FIFO before it is
needed in the transmit shift register, the communication stops. An
error, such as not receiving an acknowledgement, also causes the
communication to terminate. In case of an error during a write
operation, the Tx FIFO is flushed.
The Rx FIFO buffer allows four bytes to be read in from the slave
before the MCU has to read the data. A receive interrupt can be
generated after each byte is received or when the Rx FIFO is full. If
the peripheral is reading from a slave address, the communication
stops when the number of received bytes equals the number set in
the I2CRCT bits in the I2CMOD SFR (Address 0xE8[4:0]). An
error, such as not receiving an acknowledgement, also causes the
communication to terminate.
I
2
CTx
4-BYTE FIFO
MOV I
2
CTx, TxDAT A1
MOV I
2
CTx, TxDAT A2
MOV I
2
CTx, TxDAT A3
MOV I
2
CTx, TxDAT A4
CODE TO FILL Tx FIFO:
TRANSMIT SHIFT REGISTER
I
2
CRx
RECEIVE SHIFT REGISTER
4-BYTE FIFO
CODE TO RE AD Rx FIFO :
MOV A, I
2
CRx; RESULT : A = RxDATA1
MOV A, I
2
CRx; RESULT : A = RxDATA2
MOV A, I
2
CRx; RESULT : A = RxDATA3
MOV A, I
2
CRx; RESULT : A = RxDATA4
TxDATA1
TxDATA2
TxDATA3
TxDATA4
RxDATA4
RxDATA3
RxDATA2
RxDATA1
07411-089
Figure 116. I2C FIFO Operation
ADE5169/ADE5569 Data Sheet
Rev. E | Page 148 of 155
I/O PORTS
PARALLEL I/O
The ADE5169/ADE5569 use three input/output ports to
exchange data with external devices. In addition to performing
general-purpose I/O, some ports are capable of driving an LCD
or performing alternate functions for the peripherals available on
chip. In general, when a peripheral is enabled, the pins associated
with it cannot be used as general-purpose I/Os. The I/O port can
be configured through the SFRs listed in Table 160.
Table 160. I/O Port SFRs
SFR Address Bit Addressable Description
P0 0x80 Yes Port 0
P1 0x90 Yes Port 1
P2 0xA0 Yes Port 2
EPCFG 0x9F No Extended port
configuration
PINMAP0 0xB2 No Port 0 weak
pull-up enable
PINMAP1 0xB3 No Port 1 weak
pull-up enable
PINMAP2 0xB4 No Port 2 weak
pull-up enable
The three bidirectional I/O ports have internal pull-ups that can
be enabled or disabled individually for each pin. The internal
pull-ups are enabled by default. Disabling an internal pull-up
causes a pin to become open drain. Weak internal pull-ups are
configured through the PINMAPx SFRs.
Figure 117 shows a typical bit latch and I/O buffer for an I/O pin.
The bit latch (one bit in the SFR of each port) is represented as a
Type D flip flop, which clocks in a value from the internal bus
in response to a write to latch signal from the CPU. The Q out-
put of the flip flop is placed on the internal bus in response to a
read latch signal from the CPU. The level of the port pin itself is
placed on the internal bus in response to a read pin signal from
the CPU. Some instructions that read a port activate the read latch
signal, and others activate the read pin signal. See the Read-
Modify-Write Instructions section for details.
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
Q
LATCH
DV
DD
Px.x
PIN
INTERNAL
PULL-UP
ALTERNATE
OUTPUT
FUNCTION
ALTERNATE
INPUT
FUNCTION
Q
CLOSED:PINMAPx.x = 0
OPEN: PINMAPx.x = 1
0
7411-090
Figure 117. Port 0 Bit Latch and I/O Buffer
Weak Internal Pull-Ups Enabled
A pin with weak internal pull-up enabled is used as an input by
writing a 1 to the pin. The pin is pulled high by the internal pull-
up, and the pin is read using the circuitry shown in Figure 117.
If the pin is driven low externally, it sources current because of
the internal pull-up.
A pin with internal pull-up enabled is used as an output by writing
a 1 or a 0 to the pin to control the level of the output. If a 0 is
written to the pin, it drives a logic low output voltage (VOL) and
is capable of sinking 1.6 mA.
Open Drain (Weak Internal Pull-Ups Disabled)
When the weak internal pull-up on a pin is disabled, the pin
becomes open drain. Use this open-drain pin as a high impedance
input by writing a 1 to the pin. The pin is read using the circuitry
shown in Figure 117. The open-drain option is preferable for
inputs because it draws less current than the internal pull-ups
that were enabled.
38 kHz Modulation
Each ADE5169/ADE5569 provides a 38 kHz modulation signal.
The 38 kHz modulation is accomplished by internally XOR’ing
the level written to the I/O pin with a 38 kHz square wave. Then,
when a 0 is written to the I/O pin, it is modulated as shown in
Figure 118.
38kHz MO DUL ATI O N
SIGNAL
38kHz MO DULAT E D
OUTPUT PIN
LEVEL WRIT T EN
TO MOD38
07411-091
Figure 118. 38 kHz Modulation
Uses for this 38 kHz modulation include IR modulation of a
UART transmit signal or a low power signal to drive an LED.
The modulation can be enabled or disabled with the MOD38EN
bit in the configuration SFR (CFG, Address 0xAF[4]). The 38 kHz
modulation is available on eight pins, which are selected by the
MOD38 bits in the extended port configuration SFR (EPCFG,
Address 0x9F[7:0]).
Data Sheet ADE5169/ADE5569
Rev. E | Page 149 of 155
I/O REGISTERS
Table 161. Extended Port Configuration SFR (EPCFG, Address 0x9F)
Bit Mnemonic Default Description
7
MOD38_FP21
0
Set this bit to 1 to enable 38 kHz modulation on the P1.6/FP21 pin.
6 MOD38_FP22 0 Set this bit to 1 to enable 38 kHz modulation on the P1.5/FP22 pin.
5 MOD38_TxD2 0 Set this bit to 1 to enable 38 kHz modulation on the SDEN/P2.3/TxD2 pin.
4 MOD38_TxD 0 Set this bit to 1 to enable 38 kHz modulation on the P1.1/TxD pin.
3 MOD38_CF1 0 Set this bit to 1 to enable 38 kHz modulation on the P0.2/CF1 pin.
2 MOD38_SSb 0 Set this bit to 1 to enable 38 kHz modulation on the P0.7/SS/T1/RxD2 pin.
1
MOD38_MISO
0
Set this bit to 1 to enable 38 kHz modulation on the P0.5/MISO/ZX pin.
0 MOD38_CF2 0 Set this bit to 1 to enable 38 kHz modulation on the P0.3/CF2 pin.
Table 162. Port 0 Weak Pull-Up Enable SFR (PINMAP0, Address 0xB2)
Bit
Mnemonic
Default
Description
7 PINMAP0.7 0 The weak pull-up on P0.7 is disabled when this bit is set.
6 PINMAP0.6 0 The weak pull-up on P0.6 is disabled when this bit is set.
5 PINMAP0.5 0 The weak pull-up on P0.5 is disabled when this bit is set.
4 PINMAP0.4 0 The weak pull-up on P0.4 is disabled when this bit is set.
3 PINMAP0.3 0 The weak pull-up on P0.3 is disabled when this bit is set.
2 PINMAP0.2 0 The weak pull-up on P0.2 is disabled when this bit is set.
1 PINMAP0.1 0 The weak pull-up on P0.1 is disabled when this bit is set.
0 PINMAP0.0 0 The weak pull-up on P0.0 is disabled when this bit is set.
Table 163. Port 1 Weak Pull-Up Enable SFR (PINMAP1, Address 0xB3)
Bit Mnemonic Default Description
7 PINMAP1.7 0 The weak pull-up on P1.7 is disabled when this bit is set.
6 PINMAP1.6 0 The weak pull-up on P1.6 is disabled when this bit is set.
5 PINMAP1.5 0 The weak pull-up on P1.5 is disabled when this bit is set.
4 PINMAP1.4 0 The weak pull-up on P1.4 is disabled when this bit is set.
3
PINMAP1.3
0
The weak pull-up on P1.3 is disabled when this bit is set.
2 PINMAP1.2 0 The weak pull-up on P1.2 is disabled when this bit is set.
1 PINMAP1.1 0 The weak pull-up on P1.1 is disabled when this bit is set.
0 PINMAP1.0 0 The weak pull-up on P1.0 is disabled when this bit is set.
Table 164. Port 2 Weak Pull-Up Enable SFR (PINMAP2, Address 0xB4)
Bit Mnemonic Default Description
[7:6] Reserved 0 Reserved. Should be left cleared.
5 PINMAP2.5 0 The weak pull-up on RESET is disabled when this bit is set.
4
Reserved
0
Reserved. Should be left cleared.
3 PINMAP2.3 0 Reserved. Should be left cleared.
2 PINMAP2.2 0 The weak pull-up on P2.2 is disabled when this bit is set.
1 PINMAP2.1 0 The weak pull-up on P2.1 is disabled when this bit is set.
0 PINMAP2.0 0 The weak pull-up on P2.0 is disabled when this bit is set.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 150 of 155
Table 165. Port 0 SFR (P0, Address 0x80)
Bit Bit Address Mnemonic Default Description1
7 0x87 T1 1 This bit reflects the state of the P0.7/SS/T1/RxD2 pin. It can be written to or read.
6 0x86 T0 1 This bit reflects the state of the P0.6/SCLK/T0 pin. It can be written to or read.
5 0x85 ZX 1 This bit reflects the state of the P0.5/MISO/ZX pin. It can be written to or read.
4 0x84 1 This bit reflects the state of the P0.4/MOSI/SDATA pin. It can be written to or read.
3 0x83 CF2 1 This bit reflects the state of the P0.3/CF2 pin. It can be written to or read.
2 0x82 CF1 1 This bit reflects the state of the P0.2/CF1 pin. It can be written to or read.
1 0x81 1 This bit reflects the state of the P0.1/FP19 pin. It can be written to or read.
0 0x80 INT1 1 This bit reflects the state of the BCTRL/INT1/P0.0 pin. It can be written to or read.
1 When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set.
Table 166. Port 1 SFR (P1, Address 0x90)
Bit Bit Address Mnemonic Default Description1
7 0x97 1 This bit reflects the state of the P1.7/FP20 pin. It can be written to or read.
6 0x96 1 This bit reflects the state of the P1.6/FP21 pin. It can be written to or read.
5 0x95 1 This bit reflects the state of the P1.5/FP22 pin. It can be written to or read.
4 0x94 T2 1 This bit reflects the state of the P1.4/T2/FP23 pin. It can be written to or read.
3 0x93 T2EX 1 This bit reflects the state of the P1.3/T2EX/FP24 pin. It can be written to or read.
2 0x92 ZX1 1 This bit reflects the state of the P1.2/FP25/ZX pin. It can be written to or read.
1
0x91
TxD
1
This bit reflects the state of the P1.1/TxD pin. It can be written to or read.
0 0x90 RxD 1 This bit reflects the state of the P1.0/RxD pin. It can be written to or read.
1 When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set.
Table 167. Port 2 SFR (P2, Address 0xA0)
Bit Bit Address Mnemonic Default Description
1
[7:4] 0xA7 to 0xA4 0x1F These bits are unused and should remain set.
3 0xA3 P2.3 1 This bit reflects the state of the SDEN/P2.3/TxD2 pin. It can be written only.
2 0xA2 P2.2 1 This bit reflects the state of the P2.2/FP16 pin. It can be written to or read.
1 0xA1 P2.1 1 This bit reflects the state of the P2.1/FP17 pin. It can be written to or read.
0 0xA0 P2.0 1 This bit reflects the state of the P2.0/FP18 pin. It can be written to or read.
1 When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set.
Data Sheet ADE5169/ADE5569
Rev. E | Page 151 of 155
Table 168. Port 0 Alternate Functions
Pin No. Alternate Function Alternate Function Enable
P0.0 BCTRL external battery control input Set INT1PRG = X01 in the interrupt pins configuration SFR (INTPR, Address 0xFF[3:1]).
INT1 external interrupt Set EX1 in the interrupt enable SFR (IE, Address 0xA8[2]).
INT1 wake-up from PSM2 operating mode Set INT1PRG = 11X in the interrupt pins configuration SFR (INTPR, Address 0xFF[3:1]).
P0.1 FP19 LCD segment pin Set FP19EN in the LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED[3]).
P0.2 CF1 ADE calibration frequency output Clear the DISCF1 bit in the ADE energy measurement internal MODE1 register
(Address 0x0B[1]).
P0.3 CF2 ADE calibration frequency output Clear the DISCF2 bit in the ADE energy measurement internal MODE1 register
(Address 0x0B[2]).
P0.4 MOSI SPI data line Set the SCPS bit in the configuration SFR (CFG, Address 0xAF[5]), and set the
SPIEN bit in SPI Configuration SFR 2 (SPIMOD2, Address 0xE9[6]).
SDATA I2C data line Clear the SCPS bit in the configuration SFR (CFG, Address 0xAF[5]), and set the
I2CEN bit in the I
2
C mode SFR (I2CMOD, Address 0xE8[7]).
P0.5 MISO SPI data line Set the SCPS bit in the configuration SFR (CFG, Address 0xAF[5]), and set the
SPIEN bit in SPI Configuration SFR 2 (SPIMOD2, Address 0xE9[6]).
Zero-Crossing Detection 2 Set the ZX2 bit in the MODE3 energy measurement SFR (MODE3, Address 0x2B[0]).
P0.6 SCLK serial clock for I2C or SPI Set the I2CEN bit in the I2C mode SFR (I2CMOD, Address 0xE8[7]) or the SPIEN bit in
SPI Configuration SFR 2 (SPIMOD2, Address 0xE9[6]) to enable the I2C or SPI interface.
T0 Timer 0 input Set the C/T0 bit in the Timer/Counter 0 and Timer/Counter 1 mode SFR (TMOD,
Address 0x89[2]) to enable T0 as an external event counter.
P0.7 SS SPI slave select input for SPI in slave mode Set the SS_EN bit in SPI Configuration SFR 1 (SPIMOD1, Address 0xE8[3]).
SS
SPI slave select output for SPI in master
mode
Set the SPIMS_b bit in SPI Configuration SFR 2 (SPIMOD2, Address 0xE9[4]).
T1 Timer 1 input Set the C/T1 bit in the Timer/Counter 0 and Timer/Counter 1 mode SFR (TMOD,
Address 0x89[6]) to enable T1 as an external event counter.
RxD2 receiver data input for UART2 Set the REN2 bit in the Serial Communications Control 2 SFR (SCON2, Address 0xE1[2]).
RxD2 edge wake-up from PSM2 operating
mode
Set RXPROG bits = 11 in the peripheral configuration SFR (PERIPH, Address 0xF4[1:0]).
Table 169. Port 1 Alternate Functions
Pin No. Alternate Function Alternate Function Enable
P1.0 RxD receiver data input for UART Set the REN bit in the serial communications control SFR (SCON, Address 0x98[4]).
P1.1 TxD transmitter data output for UART This pin becomes TxD as soon as data is written into SBUF.
P1.2 FP25 LCD segment pin Set the FP25EN bit in the LCD segment enable SFR (LCDSEGE, Address 0x97[7]).
Zero-Crossing Detection 1 Set the ZX1 bit in the MODE3 energy measurement register (MODE3, Address 0x2B[1]).
P1.3 FP24 LCD segment pin Set the FP24EN bit in the LCD segment enable SFR (LCDSEGE, Address 0x97[6]).
T2EX Timer 2 control input Set the EXEN2 bit in the Timer/Counter 2 control SFR (T2CON, Address 0xC8[3]).
P1.4 FP23 LCD segment pin Set the FP23EN bit in the LCD segment enable SFR (LCDSEGE, Address 0x97[5]).
T2 Timer 2 input Set the C/T2 bit in the Timer/Counter 2 control SFR (T2CON, Address 0xC8[1]) to
enable T2 as an external event counter.
P1.5 FP22 LCD segment pin Set the FP22EN bit in the LCD segment enable SFR (LCDSEGE, Address 0x97[4]).
P1.6 FP21 LCD segment pin Set the FP21EN bit in the LCD segment enable SFR (LCDSEGE, Address 0x97[3]).
P1.7 FP20 LCD segment pin Set the FP20EN bit in the LCD segment enable SFR (LCDSEGE, Address 0x97[2]).
Table 170. Port 2 Alternate Functions
Pin No. Alternate Function Alternate Function Enable
P2.0 FP18 LCD segment pin Set the FP18EN bit in the LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED[2]).
P2.1 FP17 LCD segment pin Set the FP17EN bit in the LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED[1]).
P2.2 FP16 LCD segment pin Set the FP16EN bit in the LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED[0]).
P2.3 SDEN serial download pin sampled on reset;
P2.3 is an output only; TxD2 is the transmitter
data output for UART2
Enabled by default. This pin becomes TxD2 as soon as data is written into SBUF2.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 152 of 155
PORT 0
Port 0 is controlled directly through the bit-addressable Port 0
SFR (P0, Address 0x80). The weak internal pull-ups for Port 0
are configured through the Port 0 weak pull-up enable SFR
(PINMAP0, Address 0xB2); they are enabled by default. The
weak internal pull-up is disabled by writing a 1 to PINMAP0[x].
Port 0 pins also have various secondary functions, as described
in Table 168. The alternate functions of Port 0 pins can be activated
only if the corresponding bit latch in the Port 0 SFR contains a 1.
PORT 1
Port 1 is an 8-bit bidirectional port controlled directly through
the bit-addressable Port 1 SFR (P1, Address 0x90). The weak
internal pull-ups for Port 1 are configured through the Port 1
weak pull-up enable SFR (PINMAP1, Address 0xB3); they are
enabled by default. The weak internal pull-up is disabled by writing
a 1 to PINMAP1[x].
Port 1 pins also have various secondary functions, as described in
Table 169. The alternate functions of Port 1 pins can be activated
only if the corresponding bit latch in the Port 1 SFR contains a 1.
PORT 2
Port 2 is a 4-bit bidirectional port controlled directly through
the bit-addressable Port 2 SFR (P2, Address 0xA0). Note that
P2.3 can be used as an output only. Consequently, any read
operation, such as a CPL P2.3, cannot be executed on this I/O.
The weak internal pull-ups for Port 2 are configured through the
Port 2 weak pull-up enable SFR (PINMAP2, Address 0xB4); they
are enabled by default. The weak internal pull-up is disabled by
writing a 1 to PINMAP2[x].
Port 2 pins also have various secondary functions, as described
in Table 170. The alternate functions of Port 2 pins can be activated
only if the corresponding bit latch in the Port 2 SFR contains a 1.
Data Sheet ADE5169/ADE5569
Rev. E | Page 153 of 155
DETERMINING THE VERSION OF THE ADE5169/ADE5569
Each ADE5169/ADE5569 holds in its internal flash registers a
value that defines its version. This value helps to determine if
users have the latest version of the device. The version of the
ADE5169/ADE5569 that corresponds to this data sheet is
ADE5169/ADE5569 V2.3.
This value can be accessed as follows:
1. Launch HyperTerminal with a 9600 baud rate.
2. Put the device in serial download mode by first
holding SDEN to logic low, then resetting the device.
3. Hold the SDEN pin.
4. Press and release the RESET pin.
A string should appear on the HyperTerminal containing the
device name and version number, for example, ADE5169 V2.3
or ADE5569 V2.3.
ADE5169/ADE5569 Data Sheet
Rev. E | Page 154 of 155
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC S TANDARDS MS-026-BCD
051706-A
TOP VIEW
(PINS DO W N)
1
16
17 33
32
48
4964
0.27
0.22
0.17
0.50
BSC
LEAD P ITCH
12.20
12.00 SQ
11.80
PIN 1
1.60
MAX
0.75
0.60
0.45
10.20
10.00 SQ
9.80
VIEW A
0.20
0.09
1.45
1.40
1.35
0.08
COPLANARITY
VIEW A
ROTAT E D 90° CCW
SEATING
PLANE
0.15
0.05
7°
3.5°
0°
Figure 119. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 Antitamper
di/dt
Sensor
Interface Var
Flash
(kB) Temperature Range Package Description Package Option
ADE5169ASTZF62 Yes Yes Yes 62 −40°C to +85°C 64-Lead LQFP ST-64-2
ADE5169ASTZF62-RL Yes Yes Yes 62 −40°C to +85°C 64-Lead LQFP, 13” Tape & Reel ST-64-2
ADE5569ASTZF62 No Yes Yes 62 −40°C to +85°C 64-Lead LQFP ST-64-2
ADE5569ASTZF62-RL No Yes Yes 62 −40°C to +85°C 64-Lead LQFP, 13” Tape & Reel ST-64-2
1 All models have W + VA + rms, 5 V LCD, and RTC.
2 Z = RoHS Compliant Part.
Data Sheet ADE5169/ADE5569
Rev. E | Page 155 of 155
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
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D07411-0-10/15(E)