Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design LM4120 SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 LM4120 Precision Micropower Low Dropout Voltage Reference 1 Features 3 Description * * * * * * * * The LM4120 device is a precision low-power, low dropout bandgap voltage reference with up to 5-mA output current source and sink capability. 1 * * Small SOT23-5 Package Low Dropout Voltage: 120 mV Typical at 1 mA High Output Voltage Accuracy: 0.2% Source and Sink Current Output: 5 mA Supply Current: 160 A Typical Low Temperature Coefficient: 50 ppm/C Enable Pin Fixed Output Voltages: 1.8, 2.048, 2.5, 3, 3.3, 4.096, and 5 V Industrial Temperature Range: -40C to 85C (For Extended Temperature Range, -40C to 125C, Contact TI) 2 Applications * * * * * * * * * * Portable, Battery-Powered Equipment Instrumentation and Process Control Automotive and Industrial Test Equipment Data Acquisition Systems Precision Regulators Battery Chargers Base Stations Communications Medical Equipment This series reference operates with input voltages as low as 2 V and up to 12 V, consuming 160-A (typical) supply current. In power-down mode, device current drops to less than 2 A. The LM4120 comes in two grades (A and Standard) and seven voltage options for greater flexibility. The best grade devices (A) have an initial accuracy of 0.2%, while the standard have an initial accuracy of 0.5%, both with a temperature coefficient of 50 ppm/C ensured from -40C to 125C. The very low dropout voltage, low supply current, and power-down capability of the LM4120 make this product an ideal choice for battery-powered and portable applications. The device performance is ensured over the industrial temperature range (-40C to 85C), while certain specifications are ensured over the extended temperature range (-40C to 125C). Contact TI for full specifications over the extended temperature range. The LM4120 is available in a standard 5-pin SOT-23 package. Device Information(1) PART NUMBER LM4120 PACKAGE SOT-23 (5) BODY SIZE (NOM) 1.60 mm x 2.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM4120 SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 3 3 4 4 4 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 10 7.3 Feature Description................................................. 10 7.4 Device Functional Modes........................................ 10 8 Application and Implementation ........................ 11 8.1 Application Information............................................ 11 8.2 Typical Application .................................................. 14 9 Power Supply Recommendations...................... 15 10 Layout................................................................... 16 10.1 Layout Guidelines ................................................. 16 10.2 Layout Example ................................................... 16 11 Device and Documentation Support ................. 17 11.1 11.2 11.3 11.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 17 17 17 17 12 Mechanical, Packaging, and Orderable Information ........................................................... 17 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (February 2016) to Revision F * Added updated Layout Example ......................................................................................................................................... 16 Changes from Revision D (July 2015) to Revision E * 2 Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1 Changes from Revision B (April 2013) to Revision C * Page Added updated Layout Example .......................................................................................................................................... 16 Changes from Revision C (April 2013) to Revision D * Page Page Changed layout of National Data Sheet to TI format ........................................................................................................... 14 Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4120 LM4120 www.ti.com SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 5 Pin Configuration and Functions DBV Package 5-Pin SOT-23 Top View Pin Functions PIN I/O DESCRIPTION NAME NO. Enable 3 I GND 2 -- Negative supply or ground connection REF 1 -- REF pin. This pin must be left unconnected. VIN 4 I Positive supply VOUT 5 O Reference output Pulled to input for normal operation. Forcing this pin to ground will turn off the output. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Maximum voltage on input or enable pins MIN MAX UNIT -0.3 14 V Output short-circuit duraion Power dissipation (TA = 25C) Lead temperature Indefinite (2) 350 mW Soldering, (10 sec.) 260 C Vapor Phase (60 sec.) 215 C Infrared (15 sec.) 220 C 150 C Storage temperature, Tstg (1) (2) -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Without PCB copper enhancements. The maximum power dissipation must be derated at elevated temperatures and is limited by TJMAX (maximum junction temperature), RJA (junction-to-ambient thermal resistance) and TA (ambient temperature). The maximum power dissipation at any temperature is: PDissMAX = (TJMAX - TA) / RJA up to the value listed in the Absolute Maximum Ratings. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged device model (CDM), per JEDEC specification JESD22C101 (2) 750 Machine Model 200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4120 3 LM4120 SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 www.ti.com 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Ambient temperature -40 85 C Junction temperature -40 125 C 6.4 Thermal Information LM4120 THERMAL METRIC (1) DBV [SOT-23] UNIT 5 PINS RJA Junction-to-ambient thermal resistance 170.4 C/W RJC(top) Junction-to-case (top) thermal resistance 123.9 C/W RJB Junction-to-board thermal resistance 30.4 C/W JT Junction-to-top characterization parameter 17.2 C/W JB Junction-to-board characterization parameter 29.9 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics unless otherwise specified, VIN = 3.3 V, ILOAD = 0, COUT = 0.01 F, TA = Tj = 25C. PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT 1.8 V, 2.048 V, AND 2.5 V VOUT TCVOUT/C VOUT/VIN Output voltage initial accuracy LM4120A-1.800 LM4120A-2.048 LM4120A-2.500 0.2% LM4120-1.800 LM4120-2.048 LM4120-2.500 0.5% Temperature coefficient -40C TA +125C 3.3 V VIN 12 V Line regulation 0 mA ILOAD 1 mA VOUT/ILOAD 1 mA ILOAD 5 mA Load regulation Dropout voltage (3) (2) (3) 4 -40C TA 85C 0.01 0.03 -40C TA 85C -40C TA 85C 0.01 0.04 %/mA 0.12 45 65 120 150 -40C TA 85C 80 -40C TA 85C 180 180 -40C TA 85C %/V 0.08 0.1 0.04 ILOAD = 1 mA ppm/c 0.17 0.01 -5 mA ILOAD -1 mA ILOAD = 5 mA (1) 50 0.008 -1 mA ILOAD 0 mA ILOAD = 0 mA VIN-VOUT 14 0.0007 mV 210 250 Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Averaging Outgoing Quality Level (AOQL). Typical numbers are at 25C and represent the most likely parametric norm. Dropout voltage is the differential voltage between VOUT and VIN at which VOUT changes 1% from VOUT at VIN = 3.3 V for 1.8 V, 2 V, 2.5 V, and VOUT + 1 V for others. For 1.8-V option, dropout voltage is not ensured over temperature. A parasitic diode exists between input and output pins; it will conduct if VOUT is pulled to a higher voltage than VIN. Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4120 LM4120 www.ti.com SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 Electrical Characteristics (continued) unless otherwise specified, VIN = 3.3 V, ILOAD = 0, COUT = 0.01 F, TA = Tj = 25C. PARAMETER TEST CONDITIONS VN Output (4) IS Supply current ISS Power-down supply current VH Logic high input voltage VL Logic low input voltage IH Logic high input current IL Logic low input current (1) TYP (2) 0.1 Hz to 10 Hz 20 10 Hz to 10 kHz 36 160 -40C TA 85C Enable = 0.4 V -40C TJ 85C Enable = 0.2 V VOUT Long term stability (5) (6) UNIT VPP 250 A 1 A 2 V 2.4 0.4 -40C TA 85C V 0.2 7 -40C TA 85C A 15 0.1 VIN = 12 V, VOUT = 0 Thermal hysteresis (1) 2.4 Short circuit current Hyst MAX 275 -40C TA 85C -40C TA 85C VIN = 3.3 V, VOUT = 0 ISC MIN A 15 -40C TA 85C 6 30 mA 17 -40C TA 85C 6 30 -40C TA 125C 0.5 mV/V 1000 hrs @ 25C 100 ppm 3 V, 3.3 V, 4.096 V, AND 5 V VOUT Output voltage initial accuracy LM4120A-3.000 LM4120A-3.300 LM4120A-4.096 LM4120A-5.000 0.2% LM4120-3.000 LM4120-3.300 LM4120-4.096 LM4120-5.000 0.5% TCVOUT/C Temperature coefficient -40C TA 125C VOUT/VIN Line regulation (VOUT + 1 V) VIN 12 V 0 mA ILOAD 1 mA VOUT/ILOAD 1 mA ILOAD 5 mA Load regulation Dropout voltage (3) (5) (6) 0.0007 0.008 -40C TA 85C 0.03 -40C TA 85C -40C TA 85C 0.08 0.04 0.1 0.01 45 -40C TA 85C %/mA 0.12 65 80 120 -40C TA 85C 150 180 180 -40C TA 85C %/V 0.17 0.01 0.04 ILOAD = 1 mA ppm/c 0.01 -5 mA ILOAD -1 mA ILOAD = 5 mA (4) 50 -1 mA ILOAD 0 mA ILOAD = 0 mA VIN-VOUT 14 mV 210 250 Output noise voltage is proportional to VOUT. VN for other voltage option is calculated using (VN(1.8 V) / 1.8) x VOUT. VN (2.5 V) = (36 VPP / 1.8) x 2.5 = 46 VPP. Thermal hysteresis is defined as the change in 25C output voltage before and after exposing the device to temperature extremes. Long term stability is change in VREF at 25C measured continuously during 1000 hours. Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4120 5 LM4120 SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 www.ti.com Electrical Characteristics (continued) unless otherwise specified, VIN = 3.3 V, ILOAD = 0, COUT = 0.01 F, TA = Tj = 25C. PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT 3 V, 3.3 V, 4.096 V, AND 5 V (continued) VN Output noise voltage (4) IS Supply current ISS Power-down supply current VH Logic high input voltage VL Logic low input voltage IH Logic high input current IL Logic low input current 0.1 Hz to 10 Hz 20 10 Hz to 10 kHz 36 160 -40C TA 85C Enable = 0.4 V -40C TJ 85C Enable = 0.2 V VOUT 6 Long term stability (5) (6) 2 0.4 0.2 7 -40C TA 85C A V 2.4 -40C TA 85C 15 0.1 V A A 15 -40C TA 85C Short circuit current Thermal hysteresis A 1 -40C TA 85C 2.4 VIN = 12 V, VOUT = 0 Hyst 250 275 -40C TA 85C VOUT = 0 ISC VPP 6 30 17 -40C TA 85C 6 mA 30 -40C TA 125C 0.5 mV/V 1000 hours @ 25C 100 ppm Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4120 LM4120 www.ti.com SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 6.6 Typical Characteristics unless otherwise specified, VIN = 3.3 V, VOUT = 2.5 V, ILOAD = 0, COUT = 0.022 F, TA = 25C, and VEN = VIN Figure 1. Long Term Drift Figure 2. Typical Temperature Drift Figure 3. Short Circuit Current vs Temperature Figure 4. Dropout Voltage vs Output Error Figure 5. Dropout Voltage vs Load Current Figure 6. Line Regulation Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4120 7 LM4120 SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 www.ti.com Typical Characteristics (continued) unless otherwise specified, VIN = 3.3 V, VOUT = 2.5 V, ILOAD = 0, COUT = 0.022 F, TA = 25C, and VEN = VIN 8 Figure 7. Load Regulation Figure 8. GND Pin Current Figure 9. GND Pin Current at No Load vs Temperature Figure 10. GND Pin Current vs Load Figure 11. 0.1-Hz to 10-Hz Output Noise Figure 12. Output Impedance vs Frequency Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4120 LM4120 www.ti.com SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 Typical Characteristics (continued) unless otherwise specified, VIN = 3.3 V, VOUT = 2.5 V, ILOAD = 0, COUT = 0.022 F, TA = 25C, and VEN = VIN Figure 13. PSRR vs Frequency Figure 14. Enable Response Figure 15. Load Step Response Figure 16. Line Step Response Figure 17. Thermal Hysteresis Figure 18. Enable Pin Current Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4120 9 LM4120 SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 www.ti.com 7 Detailed Description 7.1 Overview The LM4120 device is a precision bandgap voltage reference available in seven different voltage options with up to 5-mA current source and sink capability. This series reference can operate with input voltages from 2 V to 12 V while consuming 160-A (typical) supply current. In power-down mode, device current drops to less than 2 A. The LM4120 is available in two grades, A and Standard. The best grade devices (A) have an initial accuracy of 0.2% with a TEMPCO of 50 ppm/C ensured from -40C to 125C. 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Enable The ENABLE analog input pin with limited hysteresis generally requires 6 A (typical) of current to start up the part. During normal operation, the Enable pin must be connected to the VIN pin. There is a minimum slew rate on this pin of about 0.003 V/s to prevent glitches on the output. All of these conditions can easily be met with ordinary CMOS or TTL logic. The Enable pin can also be used to remotely operate the LM4120 by pulling up the Enable pin voltage to the input voltage level. When remotely shutting down the LM4120, the Enable pin must be pulled down to the ground. Floating this pin is not recommended. 7.3.2 Reference The REF pin must remain unconnected in all cases. The reference pin is sensitive to noise, and capacitive loading. Therefore, during the PCB layout care must be taken to keep this pin isolated as much as possible. 7.4 Device Functional Modes Table 1 describes the functional modes of the LM4120. Table 1. Enable Pin Mode Summary 10 ENABLE PIN CONNECTION LOGIC STATE DESCRIPTION EN = VIN 1 Normal Operation. LM4120 starts up. EN = GND 0 LM4120 in shutdown mode Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4120 LM4120 www.ti.com SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The standard application circuit for the LM4120 is shown in Figure 29. The device is designed to be stable with ceramic output capacitors in the range of 0.022 F to 0.047 F. The minimum required output capacitor is 0.022 F. These capacitors typically have an ESR of about 0.1 to 0.5 . Smaller ESR can be tolerated, but larger ESR cannot be tolerated. The output capacitor can be increased to improve load transient response, up to about 1 F. However, values above 0.047 F must be tantalum. With tantalum capacitors in the 1-F range, a small capacitor between the output and the reference pin is required. This capacitor will typically be in the 50-pF range. Care must be taken when using output capacitors of 1 F or larger. These applications must be thoroughly tested over temperature, line, and load. An input capacitor is typically not required. However, a 0.1-F ceramic can be used to help prevent line transients from entering the LM4120. Larger input capacitors must be tantalum or aluminum. The reference pin is sensitive to noise, and capacitive loading. Therefore, the PCB layout must isolate this pin as much as possible. The enable pin is an analog input with very little hysteresis. About 6 A into this pin is required to turn the part on, and it must be taken close to GND to turn the part off (see Electrical Characteristics for thresholds). If the shutdown feature is not required, then this pin can safely be connected directly to the input supply. Figure 19. Voltage Reference With Negative Output Circuit Figure 20. Precision High-Current Low-Dropout Regulator Circuit Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4120 11 LM4120 SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 www.ti.com Application Information (continued) Figure 21. Precision High-Current Negative Voltage Regulator Circuit Figure 22. Voltage Reference With Complimentary Output Circuit Figure 23. Precision High-Current Low-Dropout Regulator Circuit 12 Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4120 LM4120 www.ti.com SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 Application Information (continued) Figure 24. Stacking Voltage References Circuit Figure 25. Precision Voltage Reference With Force and Sense Output Circuit Figure 26. Programmable Current Source Circuit Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4120 13 LM4120 SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 www.ti.com Application Information (continued) Figure 27. Precision Regulator With Current Limiting Circuit Figure 28. Power Supply Splitter Circuit 8.2 Typical Application Figure 29. Standard Application Circuit 8.2.1 Design Requirements For this design example, use the parameters listed in Table 2 as the input parameters. Table 2. Design Parameters 14 PARAMETER EXAMPLE VALUE Output Voltage VOUT 1.8 V, 2.048 V, 2.5 V, 3 V, 3.3 V, 4.096 V, 5 V Input Voltage Range VIN VOUT 120 mV to 12 V Load Current 1 mA (typical) Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4120 LM4120 www.ti.com SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 8.2.2 Detailed Design Procedure 8.2.2.1 Input Capacitors Although not always required, an input capacitor is recommended. A supply bypass capacitor on the input assures that the reference is working from a source with low impedance, which improves stability. A bypass capacitor can also improve transient response by providing a reservoir of stored energy that the reference can utilize in case where the load current demand suddenly increases. The value used for CIN may be used without limit. 8.2.2.2 Output Capacitors The LM4120 may require a 0.022-F to 1-F output capacitor for loop stability (compensation) as well as transient response. During the sudden changes in load current demand, the output capacitor must source or sink current during the time it takes the control loop of the LM4120 to respond. 8.2.3 Application Curves Figure 30. Start-Up Response Figure 31. Load Step Response 9 Power Supply Recommendations Noise on the power-supply input can effect the output noise, but can be reduced by using an optional bypass capacitor between the input pin and the ground. A ceramic input capacitor more than 0.1 F or higher can be used for that purpose. Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4120 15 LM4120 SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 www.ti.com 10 Layout 10.1 Layout Guidelines The mechanical stress due to PC board mounting can cause the output voltage to shift from its initial value. The center of a PC board generally has the highest mechanical and thermal expansion stress. Mounting the device near the edges or the corners of the board where mechanical stress is at its minimum. References in SOT packages are generally less prone to assembly stress than devices in Small Outline (SOIC) package. A mechanical isolation of the device by creating an island by cutting a U shape slot (U - SLOT) on the PCB while mounting the device helps in reducing the impact of the PC board stresses on the output voltage of the reference. This approach would also provide some thermal isolation from the rest of the circuit. Figure 32 shows a recommended printed board layout for LM4120 along with an in-set diagram. The in-set diagram exhibits a slot cut on three sides of the reference IC, which provides a relief to the IC from external PCB stress. 10.2 Layout Example PCB Top View VOUT PCB Length VIN LM4120 PCB Side View STRESS U - SLOT REF GND STRESS EN U - SLOT VOUT LM4120 REF PCB Length GND Set CIN close to VIN and GND EN CIN REF COUT LM4120 VIN Set COUT close to VOUT and GND VOUT Figure 32. Typical Layout Example With LM4120 16 Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4120 LM4120 www.ti.com SNVS049F - FEBRUARY 2000 - REVISED MARCH 2016 11 Device and Documentation Support 11.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. 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Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4120 17 PACKAGE OPTION ADDENDUM www.ti.com 4-Nov-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM4120AIM5-1.8/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R21A LM4120AIM5-2.0/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R14A LM4120AIM5-2.5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 R08A LM4120AIM5-2.5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R08A LM4120AIM5-3.0 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 R15A LM4120AIM5-3.0/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R15A LM4120AIM5-3.3 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 R16A LM4120AIM5-3.3/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R16A LM4120AIM5-4.1/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R17A LM4120AIM5-5.0 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 R18A LM4120AIM5-5.0/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R18A LM4120AIM5X-1.8/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R21A LM4120AIM5X-2.0/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R14A LM4120AIM5X-2.5/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R08A LM4120AIM5X-3.0/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R15A LM4120AIM5X-3.3/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R16A LM4120AIM5X-4.1 NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 R17A LM4120AIM5X-4.1/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R17A LM4120AIM5X-5.0/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R18A Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 4-Nov-2016 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM4120IM5-1.8/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R21B LM4120IM5-2.0/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R14B LM4120IM5-2.5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R08B LM4120IM5-3.0 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 R15B LM4120IM5-3.0/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R15B LM4120IM5-3.3 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 R16B LM4120IM5-3.3/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R16B LM4120IM5-4.1/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R17B LM4120IM5-5.0/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R18B LM4120IM5X-1.8/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R21B LM4120IM5X-2.0/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R14B LM4120IM5X-2.5/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R08B LM4120IM5X-3.0/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R15B LM4120IM5X-3.3/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R16B LM4120IM5X-4.1/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R17B LM4120IM5X-5.0/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 R18B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 4-Nov-2016 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ B0 (mm) K0 (mm) P1 (mm) LM4120AIM5-1.8/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120AIM5-2.0/NOPB SOT-23 DBV 5 1000 178.0 LM4120AIM5-2.5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 LM4120AIM5-2.5/NOPB SOT-23 DBV 5 1000 Q3 178.0 8.4 3.2 3.2 1.4 4.0 8.0 LM4120AIM5-3.0 SOT-23 DBV 5 Q3 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120AIM5-3.0/NOPB SOT-23 DBV LM4120AIM5-3.3 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 LM4120AIM5-3.3/NOPB SOT-23 Q3 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120AIM5-4.1/NOPB LM4120AIM5-5.0 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 LM4120AIM5-5.0/NOPB Q3 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120AIM5X-1.8/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120AIM5X-2.0/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120AIM5X-2.5/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120AIM5X-3.0/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120AIM5X-3.3/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120AIM5X-4.1/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120AIM5X-4.1 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 Device Package Package Pins Type Drawing LM4120AIM5X-5.0/NOPB SOT-23 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120IM5-1.8/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120IM5-2.0/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120IM5-2.5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120IM5-3.0 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120IM5-3.0/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120IM5-3.3 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120IM5-3.3/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120IM5-4.1/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120IM5-5.0/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120IM5X-1.8/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120IM5X-2.0/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120IM5X-2.5/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120IM5X-3.0/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120IM5X-3.3/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120IM5X-4.1/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM4120IM5X-5.0/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 *All dimensions are nominal Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM4120AIM5-1.8/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120AIM5-2.0/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120AIM5-2.5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120AIM5-2.5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120AIM5-3.0 SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120AIM5-3.0/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120AIM5-3.3 SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120AIM5-3.3/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120AIM5-4.1/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120AIM5-5.0 SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120AIM5-5.0/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120AIM5X-1.8/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LM4120AIM5X-2.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LM4120AIM5X-2.5/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LM4120AIM5X-3.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LM4120AIM5X-3.3/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LM4120AIM5X-4.1 SOT-23 DBV 5 3000 210.0 185.0 35.0 LM4120AIM5X-4.1/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LM4120AIM5X-5.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LM4120IM5-1.8/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120IM5-2.0/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120IM5-2.5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120IM5-3.0 SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120IM5-3.0/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120IM5-3.3 SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120IM5-3.3/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120IM5-4.1/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120IM5-5.0/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM4120IM5X-1.8/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LM4120IM5X-2.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LM4120IM5X-2.5/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LM4120IM5X-3.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LM4120IM5X-3.3/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LM4120IM5X-4.1/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LM4120IM5X-5.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 3 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. 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