MX29F400BRC-70 - Macronix International Co., Ltd.

P/N:PM0439 REV. 0.9, AUG. 01, 1998

MX29F400T/B

4M-BIT [512Kx8/156Kx16] CMOS FLASH MEMORY

ADVANCED INFORMATION

• Status Reply

- Data polling & Toggle bit for detection of program and

erase cycle completion.

• Ready/Busy pin (RY/BY)

- Provides a hardware method of detecting program or

erase cycle completion.

- Sector protect/unprotect for 5V only system or 5V/12V

system.

• Sector protection

- Hardware method to disable any combination of

sectors from program or erase operations

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Boot Code Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

• Low VCC write inhibit- 3.2V

• Package type:

- 44-pin SOP

- 48-pin TSOP

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power

supply Flash

FEATURES

• 524,288 x 8/262,144 x 16 switchable

• Single power supply operation

- 5.0V only operation for read, erase and program

operation

• Fast access time: 70/90/120ns

• Low power consumption

- 30mA maximum active current

- 1uA typical standby current

• Command register architecture

- Byte/word Programming (7us/14us typical)

- Block Erase (Block structure 16K-Bytex1,

- 8K-Bytex2, 32K-Bytex1, and 64K-Byte x7)

• Auto Erase (chip & block) and Auto Program

- Automatically erase any combination of sectors with

Erase Suspend capability.

- Automatically program and verify data at specified

address

• Erase suspend/Erase Resume

- Suspends an erase operation to read data from, or

program data to, another sector that is not being erased,

then resumes the erase.

GENERAL DESCRIPTION

The MX29F400T/B is a 4-mega bit Flash memory orga-

nized as 512K bytes of 8 bits or 256K words of 16 bits.

MXIC's Flash memories offer the most cost-effective and

reliable read/write non-volatile random access memory.

The MX29F400T/B is packaged in 44-pin SOP, 48-pin

TSOP. It is designed to be reprogrammed and erased in-

system or in-standard EPROM prog rammers .

The standard MX29F400T/B off ers access times as f ast

as 70ns, allo wing oper ation of high-speed microproces-

sors without wait states. To eliminate bus contention, the

MX29F400T/B has separate chip enable (CE) and out-

put enab le (OE) controls.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

MX29F400T/B uses a command register to manage this

functionality. The command register allows for 100% TTL

le v el control inputs and fix ed power supply le v els during

erase and programming, while maintaining maximum

EPROM compatibility.

MXIC Flash technology reliably stores memory contents

even after 100,000 erase and program cycles. The MXIC

cell is designed to optimize the er ase and programming

mechanisms. In addition, the combination of advanced

tunnel oxide processing and low internal electric fields

for erase and programming operations produces reliable

cycling. The MX29F400T/B uses a 5.0V±10% VCC sup-

ply to perform the High Reliability Erase and auto Pro-

gram/Erase algorithms.

The highest degree of latch-up protection is achieved with

MXIC's proprietary non-epi process. Latch-up protec-

tion is proved for stresses up to 100 milliamps on ad-

dress and data pin from -1V to VCC + 1V.

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

PIN CONFIGURATIONS

44 SOP(500 mil)

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A17 Address Input

Q0~Q14 Data Input/Output

Q15/A-1 Q15(Word mode)/LSB addr(Byte mode)

CE Chip Enable Input

WE Write Enable Input

BYTE Word/Byte Selction input

RESET Hardware Reset Pin/Sector Protect Unlock

OE Output Enable Input

RY/BY Ready/Busy Output

VCC Power Supply Pin (+5V)

GND Ground Pin

48 TSOP (Standard Type) (12mm x 20mm) 48 TSOP (Reverse Type) (12mm x 20mm)

RY/BY

A17

GND

Q10

Q11

RESET

A10

A11

A12

A13

A14

A15

A16

BYTE

GND

Q15/A-1

Q14

Q13

Q12

VCC

MX29F400T/B

A15

A14

A13

A12

A11

A10

RESET

RY/BY

A17

A16

BYTE

GND

Q15/A-1

Q14

Q13

Q12

VCC

Q11

Q10

GND

MX29F400T/B

A15

A14

A13

A12

A11

A10

RESET

RY/BY

A17

A16

BYTE

GND

Q15/A-1

Q14

Q13

Q12

VCC

Q11

Q10

GND

MX29F400T/B

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

Sector Size Address Range (in hexadecimal)

(Kbytes/ (x8) (x16)

Sector A17 A16 A15 A1 4 A 13 A12 Kwords) Address Range Address Range

SA0 0 0 0 X X X 64/32 00000h-0FFFFh 00000h-07FFFh

SA1 0 0 1 X X X 64/32 10000h-1FFFFh 08000h-0FFFFh

SA2 0 1 0 X X X 64/32 20000h-2FFFFh 10000h-17FFFh

SA3 0 1 1 X X X 64/32 30000h-3FFFFh 18000h-1FFFFh

SA4 1 0 0 X X X 64/32 40000h-4FFFFh 20000h-27FFFh

SA5 1 0 1 X X X 64/32 50000h-5FFFFh 28000h-2FFFFh

SA6 1 1 0 X X X 64/32 60000h-6FFFFh 30000h-37FFFh

SA7 1 1 1 0 X X 32/16 70000h-77FFFh 38000h-3BFFFh

SA81111008/4 78000h-79FFFh 3C000h-3CFFFh

SA91111018/4 7A000h-7BFFFh 3D000h-3DFFFh

SA10 1 1111X16/8 7C000h-7FFFFh 3E000h-3FFFFh

Sector Size Address Range (in hexadecimal)

(Kbytes/ (x8) (x16)

Sector A17 A16 A15 A1 4 A 13 A12 Kwords) Address Range Address Range

SA000000X16/8 00000h-03FFFh 00000h-01FFFh

SA10000108/4 04000h-05FFFh 02000h-02FFFh

SA20000118/4 06000h-07FFFh 03000h-03FFFh

SA3 0 0 0 1 X X 32/16 08000h-0FFFFh 04000h-07FFFh

SA4 0 0 1 X X X 64/32 10000h-1FFFFh 08000h-0FFFFh

SA5 0 1 0 X X X 64/32 20000h-2FFFFh 10000h-17FFFh

SA6 0 1 1 X X X 64/32 30000h-3FFFFh 18000h-1FFFFh

SA7 1 0 0 X X X 64/32 40000h-4FFFFh 20000h-27FFFh

SA8 1 0 1 X X X 64/32 50000h-5FFFFh 28000h-2FFFFh

SA9 1 1 0 X X X 64/32 60000h-6FFFFh 30000h-37FFFh

SA10 1 1 1 X X X 64/32 70000h-7FFFFh 38000h-3FFFFh

Note: Address range is A17~A-1 in b yte mode and A17~A0 in word mode.

BLOCK STRUCTURE

MX29F400T TOP BOOT SECTOR ADDRESS TABLE

MX29F400B BOTTOM BOOT SECTOR ADDRESS TABLE

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

BLOCK DIAGRAM

CONTROL

INPUT

LOGIC

PROGRAM/ERASE

HIGH V OLTAGE

WRITE

STATE

MACHINE

(WSM)

STATE

MX29F400T/B

FLASH

ARRAY

X-DECODER

ADDRESS

LATCH

AND

BUFFER

Y-PASS GATE

Y-DECODER

ARRAY

SOURCE

COMMAND

DATA

DECODER

COMMAND

DATA LATCH

I/O BUFFER

PGM

DATA

PROGRAM

DATA LATCH

SENSE

AMPLIFIER

Q0-Q15/A-1

A0-A17

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

AUTOMATIC PROGRAMMING

The MX29F400T/B is byte programmable using the Au-

tomatic Programming algorithm. The Automatic Program-

ming algorithm makes the external system do not need

to have time out sequence or to verify the data pro-

gr ammed. The typical room temperature chip program-

ming time of the MX29F400T/B is less than 4 seconds.

AUT OMATIC CHIP ERASE

The entire chip is bu lk erased using 10 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typical erasure at room temperature is accomplished in

less than 4 second. The Automatic Erase algorithm au-

tomatically programs the entire array prior to electrical

erase. The timing and verification of electrical erase are

controlled internally within the device.

AUT OMATIC BLOCK ERASE

The MX29F400T/B is block(s) erasable using MXIC's Auto

Block Er ase algorithm. Block erase modes allow b loc ks

of the array to be erased in one erase cycle. The Auto-

matic Block Er ase algorithm automatically programs the

specified block(s) prior to electrical erase. The timing

and verification of electrical erase are controlled inter-

nally within the device .

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the

user to only write program set-up commands (include 2

unlock write cycle and A0H) and a program command

(program data and address). The device automatically

times the programming pulse width, provides the program

verification, and counts the number of sequences. A sta-

tus bit similar to DATA polling and a status bit toggling

between consecutive read cycles, provides feedback to

the user as to the status of the prog ramming operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stan-

dard microprocessor write timings. The device will auto-

matically pre-program and verify the entire array. Then

the device automatically times the erase pulse width, pro-

vides the erase verification, and counts the number of

sequences. A status bit toggling between consecutive

read cycles, provides f eedbac k to the user as to the sta-

tus of the programming oper ation.

machine which controls the erase and programming cir-

cuitry. During write cycles, the command register inter-

nally latches address and data needed f or the program-

ming and erase operations. During a system write cycle,

addresses are latched on the f alling edge, and data are

latched on the rising edge of WE .

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, reli-

ability, and cost effectiveness. The MX29F400T/B elec-

trically erases all bits simultaneously using Fowler-

Nordheim tunneling. The b ytes are programmed b y us-

ing the EPROM programming mechanism of hot elec-

tron injection.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Er ase

Suspend command. After Erase Suspend is completed,

the device stays in read mode. After the state machine

has completed its task, it will allow the command register

to respond to its full command set.

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Reset 1 XXXH F0H

Read 1 RA RD

Read Silicon ID Word 4 555H AAH 2AAH 55H 555H 90H ADI DDI

Byte 4 AAAH AAH 555H 55H AAAH 90H ADI DDI

Porgram Word 4 555H AAH 2AAH 55H 555H A0H PA PD

Byte 4 AAAH AAH 555H 55H AAAH A0H PA PD

Chip Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H

Sector Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H

Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SA 30H

Sector Erase Suspend 1 XXXH B0H

Sector Erase Resume 1 XXXH 30H

Unlock for sector 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H

protect/unprotect

TABLE1. SOFTWARE COMMAND DEFINITIONS

Note that the Erase Suspend (B0H) and Erase Resume

(30H) commands are valid only while the Sector Er ase

operation is in progress. Either of the two reset com-

mand sequences will reset the device(when applicable).

COMMAND DEFINITIONS

Device operations are selected by writing specific address

and data sequences into the command register. Wr iting

incorrect address and data values or writing them in the

improper sequence will reset the device to the read mode.

Table 1 defines the valid register command sequences.

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code.

(Refer to table 3)

DDI = Data of Device identifier : C2H for manufacture code, 23H/ABH for device code.

X = X can be VIL or VIH

RA=Address of memory location to be read.

RD=Data to be read at location RA.

2.PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.

SA = Address to the sector to be erased.

3.The system should generate the f ollowing address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or 555H

to Address A10~A-1 in byte mode.

Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector

Address (SA). Write Sequence may be initiated with A11~A17 in either state.

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

Pins CE OE WE A0 A1 A6 A9 Q0 ~ Q7

Mode

Read Silicon ID L L H L L X VID(2) C2H

Manfacturer Code(1)

Read Silicon ID L L H H L X VID(2) 23H/ABH

De vice Code(1)

Read L L H A0 A1 A6 A9 DOUT

Standby H X X X X X X HIGH Z

Output Disable L H H X X X X HIGH Z

Write LHLA0A1A6A9 D

IN(3)

Sector Protect with 12V L VID(2) L X X L VID(2) X

system(6)

Chip Unprotect with 12V L VID(2) L X X H VID(2) X

system(6)

Verify Sector Protect L L H X H X VID(2) Code(5)

with 12V system

Sector Protect without 12V L H L X X L H X

system (6)

Chip Unprotect without 12V L H L X X H H X

system (6)

Verify Sector Protect/Unprotect L L H X H X H Code(5)

without 12V system (7)

Reset X X X X X X X HIGH Z

TABLE 2. MX29F400T/B BUS OPERATION

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 13V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H means unprotected.

Code=01H means protected.

A17~A12=Sector address for sector protect.

6. Refer to sector protect/unprotect algorithm and waveform.

Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command.

7. The "verify sector protect/unprotect without 12V sysytem" is only following "Sector protect/unprotect without 12V system"

command.

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

READ/RESET COMMAND

The read or reset operation is initiated by writing the read/

reset command sequence into the command register.

Microprocessor read cycles retriev e arr ay data. The de-

vice remains enabled f or reads until the command regis-

ter contents are altered.

If program-fail or erase-fail happen, the write of F0H will

reset the device to abort the operation. A valid command

must then be written to place the device in the desired

state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where

the local CPU alters memory contents. As such, manu-

facturer and device codes must be accessible while the

device resides in the target system. PROM program-

mers typically access signature codes by raising A9 to a

high voltage. However, multiplexing high voltage onto ad-

dress lines is not generally desired system design prac-

tice.

The MX29F400T/B contains a Silicon-ID-Read operation

to supplement traditional PROM programming method-

ology. The operation is initiated by wr iting the read sili-

con ID command sequence into the command register.

Following the command write, a read cycle with

A1=VIL,A0=VIL retrieves the manufacturer code of C2H.

A read cycle with A1=VIL, A0=VIH returns the device code

of 23H for MX29F400T, ABH for MX29F400B .

SET-UP AUTOMATIC CHIP/BLOCK ERASE

Pins A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)

Manufacture code VIL VIL 1 1 0 0 0 0 1 0 C2H

De vice code VIH VIL 0 0 1 0 0 0 1 1 23H

for MX29F400T

De vice code VIH VIL 1 0 1 0 1 0 1 1 ABH

for MX29F400B

Protected Sector X VIH 0 0 0 0 0 0 0 1 01H

Unprotected Sector X VIH 0 0 0 0 0 0 0 0 00H

TABLE 3. EXPANDED SILICON ID CODE

COMMANDS

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command 80H. Two more "unlock" write cycles

are then f ollo wed b y the chip er ase command 10H.

The Automatic Chip Erase does not require the device to

be entirely pre-programmed prior to e x ecuting the Auto-

matic Chip Erase. Upon executing the Automatic Chip

Erase, the device automatically will program and verify

the entire memory for an all-zero data pattern. When the

device is automatically verified to contain an all-zero pat-

tern, a self-timed chip erase and verify begin. The erase

and verify operations are completed when the data on

Q7 is "1" at which time the device returns to the Read

mode. The system is not required to pro vide any control

or timing during these operations.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array(no

erase v erification command is required).

If the Erase operation w as unsuccessful, the data on Q5

is "1"(see Table 4), indicating an Erase Failure.

The automatic erase begins on the rising edge of the last

WE pulse in the command sequence and terminates

when the data on Q7 is "1" and the data on Q6 stops

toggling for two consecutive read cycles, at which time

the de vice returns to the Read mode.

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

erase margin has been achieved for the memor y array

(no erase verification command is required). Sector erase

is a six-bus cycle operation. There are two "unlock" write

cycles. These are followed by writing the set-up com-

mand 80H. Two more "unloc k" write cycles are then f ol-

lowed by the sector erase command 30H. The sector

address is latched on the falling edge of WE, while the

command(data) is latched on the rising edge of WE. Block

addresses selected are loaded into internal register on

the sixth falling edge of WE. Each successive block load

cycle started by the falling edge of WE must begin within

80ms from the rising edge of the preceding WE. Other-

wise, the loading period ends and internal auto block erase

cycle starts. (Monitor Q3 to determine if the sector erase

timer window is still open, see section Q3, Sector Erase

Timer.) Any command other than Block Erase(30H) or

Erase Suspend(B0H) during the time-out period resets

the de vice to read mode .

ERASE COMMANDS

The Automatic Block Erase does not require the device

to be entirely pre-progr ammed prior to executing the A u-

tomatic Set-up Block Erase command and Automatic

Block Erase command. Upon executing the Automatic

Block Erase command, the device automatically will pro-

gr am and verify the bloc k(s) memory for an all-z ero data

pattern. The system is not required to provide any con-

trols or timing during these operations.

When the bloc k(s) is automatically v erified to contain an

all-zero pattern, a self-timed block erase and verify be-

gin. The erase and verify operations are complete when

the data on Q7 is "1" and the data on Q6 stops toggling

for two consecutive read cycles, at which time the device

returns to the Read mode. The system is not required to

provide an y control or timing during these operations.

When using the Automatic Block Erase algorithm, note

that the erase automatically terminates when adequate

Status Q7 Q6 Q5 Q3 Q2 RY/BY

Byte Program in Auto Program Algorithm Q7 Toggle 0 0 1 0

Auto Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase Suspend Read 1 1 0 0 Toggle 1

In Progress (Erase Suspended Sector) (Note1)

Erase Suspended Mode Erase Suspend Read Data Data Data Data Data 1

(Non-Erase Suspended Sector)

Erase Suspend Program Q7 Toggle 0 0 1 0

(Non-Erase Suspended Sector) (Note2) (Note3)

Byte Program in Auto Program Algorithm Q7 Toggle 1 0 1 0

Exceeded Program/Erase in Auto Erase Algorithm 0 Toggle 1 1 N/A 0

Time Limits Erase Suspended Mode Erase Suspend Program Q7 Toggle 1 1 N/A 0

(Non-Erase Suspended Sector)

Table 4. Write Operation Status

Notes:

1.Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.

2.Performing successive read operations from any address will cause Q6 to toggle.

3.Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the Q2 bit.

However, successive reads from the erase-suspended sector will cause Q2 to toggle.

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

ERASE SUSPEND

This command only has meaning while the state machine

is executing Automatic Block Erase operation, and there-

fore will only be responded during Automatic Block Erase

operation. However, When the Erase Suspend command

is written during the sector erase time-out, the device

immediately terminates the time-out period and suspends

the erase operation. After this command has been ex-

ecuted, the command register will initiate erase suspend

mode. The state machine will return to read mode auto-

matically after suspend is ready. At this time, state ma-

chine only allows the command register to respond to

the Read Memory Array, Erase Resume and program

commands.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend pro-

gram operation is complete, the system can once again

read arra y data within non-suspended bloc ks .

ERASE RESUME

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all other

conditions.Another Erase Suspend command can be

written after the chip has resumed erasing.

SET-UP AUTOMATIC PROGRAM COMMANDS

To initiate Automatic Progr am mode, A three-cycle com-

mand sequence is required. There are two "unlock" write

cycles. These are f ollowed by writing the A utomatic Pro-

gram command A0H.

Once the Automatic Program command is initiated, the

ne xt WE pulse causes a tr ansition to an activ e program-

ming operation. Addresses are latched on the falling edge,

and data are internally latched on the rising edge of the

WE pulse. The r ising edge of WE also begins the pro-

gramming oper ation. The system is not required to pro-

vide further controls or timings. The device will automati-

cally provide an adequate internally generated program

pulse and verify margin.

If the program opetation was unsuccessful, the data on

Q5 is "1"(see Table 4), indicating a program failure. The

automatic programming operation is completed when the

data read on Q6 stops toggling f or two consecutiv e read

cycles and the data on Q7 and Q6 are equivalent to data

written to these two bits, at which time the device returns

to the Read mode(no program verify command is re-

quired).

DATA POLLING-Q7

The MX29F400T/B also features Data Polling as a

method to indicate to the host system that the Automatic

Program or Erase algorithms are either in progress or

completed.

While the Automatic Programming algorithm is in opera-

tion, an attempt to read the device will produce the

complement data of the data last written to Q7. Upon

completion of the Automatic Program Algorithm an at-

tempt to read the device will produce the true data last

written to Q7. The Data Polling feature is valid after the

rising edge of the fourth WE pulse of the f our write pulse

sequences f or automatic program.

While the A utomatic Erase algorithm is in operation, Q7

will read "0" until the erase operation is competed. Upon

completion of the erase operation, the data on Q7 will

read "1". The Data P olling feature is valid after the rising

edge of the sixth WE pulse of six write pulse sequences

f or automatic chip/sector erase .

The Data Polling feature is activ e during Automatic Pro-

gram/Erase algorithm or sector erase time-out.(see sec-

tion Q3 Sector Erase Timer)

RY/BY:Ready/Busy

The R Y/By is a dedicated, open-dr ain output pin that in-

dicates whether an A utomatic Erase/Progr am algorithm

is in progress or complete. The RY/BY status is valid af-

ter the rising edge of the final WE pulse in the command

sequence. Since R Y/BY is an open-drain output, se veral

R Y/BY pins can be tied together in parallel with a pull-up

resistor to Vcc.

If the output is low (Busy), the device is activ ely erasing

or programming. (This includes programming in the Erase

Suspend mode.)If the output is high (Ready), the de vice

is ready to read array data (including during the Erase

Suspend mode), or is in the standby mode .

Table 4 shows the outputs f or RY/BY.

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates

whether a par ticular sector is actively eraseing (that is,

the Automatic Erase alorithm is in process), or whether

that sector is erase-suspended. Toggle Bit I is valid after

the rising edge of the final WE pulse in the command

sequence.

Q2 toggles when the system reads at addresses within

those sectors that hav e been selected for erasure . (The

system may use either OE or CE to control the read

cycles.) But Q2 cannot distinguish whether the sector is

actively erasing or is erase-suspended. Q6, by compari-

son, indicates whether the device is actively erasing, or

is in Erase Suspend, but cannot distinguish which sec-

tors are selected f or erasure. Thus , both status bits are

required for sectors and mode information. Refer to Table

4 to compare outputs f or Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to de-

termine whether a toggle bit is toggling. Typically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the de vice has com-

pleted the program or er ase operation. The system can

read arra y data on Q7-Q0 on the following read cycle.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the system

also should note whether the value of Q5 is high (see

the section on Q5). If it is, the system should then deter-

mine again whether the toggle bit is toggling, since the

toggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfuly completed the program or erase opera-

tion. If it is still toggling, the device did not complete the

operation successfully, and the system must write the

reset command to return to reading array data.

The remaining scenario is that system initially determines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previous paragraph. Alternatively,

it may choose to perform other system tasks. In this

case, the system m ust start at the beginning of the algo-

rithm when it retur ns to deter mine the status of the op-

eration.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-

gram or Erase algorithm is in progress or complete, or

whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address, and is valid after

the rising edge of the final WE pulse in the command

sequence(prior to the program or erase operation), and

during the sector time-out.

During an Automatic Prog ram or Erase algorithm opera-

tion, successive read cycles to an y address cause Q6 to

toggle. The system may use either OE or CE to control

the read cycles. When the operation is complete, Q6 stops

toggling.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Q6 toggles and

returns to reading array data. If not all selected sectors

are protected, the A utomatic Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

The system can use Q6 and Q2 together to determine

whether a sector is actively erasing or is erase sus-

pended. When the de vice is activ ely er asing (that is, the

Automatic Erase algorithm is in progress), Q6 toggling.

When the device enters the Erase Suspend mode, Q6

stops toggling. However , the system must also use Q2 to

determine which sectors are erasing or erase-suspended.

Alternatively, the system can use Q7.

If a program address falls within a protected sector, Q6

toggles for approximately 2 us after the program com-

mand sequence is written, then returns to reading arra y

data.

Q6 also toggles during the erase-suspend-program mode,

and stops toggling once the Automatic Program algorithm

is complete.

Table 4 shows the outputs f or Toggle Bit I on Q6.

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

Q5 Q3

Exceeded Timing Limits

Q5 will indicate if the program or erase time has exceeded

the specified limits(internal pulse count). Under these

conditions Q5 will produce a "1". This time-out condition

indicates that the program or erase cycle was not suc-

cessfully completed. Data P olling and Toggle Bit are the

only operating functions of the device under this condi-

tion.

If this time-out condition occurs during sector erase op-

eration, it specifies that a particular sector is bad and it

may not be reused. Howe ver , other sectors are still func-

tional and may be used for the program or erase opera-

tion. The device must be reset to use other sectors. Write

the Reset command sequence to the device, and then

e x ecute program or er ase command sequence. This al-

lows the system to contin ue to use the other active sec-

tors in the de vice .

If this time-out condition occurs during the chip erase op-

eration, it specifies that the entire chip is bad or combina-

tion of sectors are bad.

If this time-out condition occurs during the byte program-

ming operation, it specifies that the entire sector contain-

ing that byte is bad and this sector maynot be reused,

(other sectors are still functional and can be reused).

The time-out condition ma y also appear if a user tries to

program a non blank location without erasing. In this case

the de vice locks out and ne v er completes the A utomatic

Algorithm operation. Hence, the system never reads a

v alid data on Q7 bit and Q6 nev er stops toggling. Once

the Device has exceeded timing limits, the Q5 bit will

indicate a "1". Please note that this is not a device f ailure

condition since the de vice w as incorrectly used.

DATA PROTECTION

The MX29F400T/B is designed to offer protection against

accidental erasure or programming caused by spurious

system level signals that may exist during power transi-

tion. During power up the device automatically resets

the state machine in the Read mode. In addition, with its

control register architecture, alteration of the memory

contents only occurs after successful completion of spe-

cific command sequences. The device also incorporates

several features to prevent inadver tent write cycles re-

sulting from VCC power-up and power-down transition or

system noise.

Sector Erase Timer

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-out is complete. Data Polling

and Toggle Bit are valid after the initial sector erase com-

mand sequence.

If Data P olling or the Toggle Bit indicates the device has

been written with a valid erase command, Q3 may be

used to determine if the sector erase timer window is still

open. If Q3 is high ("1") the inter nally controlled erase

cycle has begun; attempts to write subsequent com-

mands to the device will be ignored until the erase op-

eration is completed as indicated by Data Polling or Toggle

Bit. If Q3 is low ("0"), the device will accept additional

sector erase commands. To insure the command has

been accepted, the system software should check the

status of Q3 prior to and follo wing each subsequent sec-

tor erase command. If Q3 were high on the second sta-

tus check, the command may not ha v e been accepted.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will

not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE =

VIH or WE = VIH. To initiate a write cycle CE and WE

must be a logical z ero while OE is a logical one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween its VCC and GND.

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

SECTOR PROTECTION WITH 12V SYSTEM

The MX29F400T/B features hardware sector protection.

This feature will disable both program and erase opera-

tions f or these sectors protected. To activate this mode ,

the programming equipment m ust force VID on address

pin A9 and control pin OE, (suggest VID = 12V) A6 = VIL

and CE = VIL.(see Table 2) Programming of the protec-

tion circuitry begins on the falling edge of the WE pulse

and is terminated on the rising edge. Please refer to

sector protect algorithm and wa vef orm.

To verify programming of the protection circuitry , the pro-

gramming equipment must force VID on address pin A9 (

with CE and OE at VIL and WE at VIH). When A1=1, it

will produce a logical "1" code at device output Q0 for a

protected sector . Otherwise the device will produce 00H

for the unprotected sector. In this mode, the

addresses,except for A1, are don't care. Address loca-

tions with A1 = VIL are reserved to read manufacturer

and device codes .(Read Silicon ID)

It is also possible to determine if the sector is protected

in the system by writing a Read Silicon ID command.

P erforming a read operation with A1=VIH, it will produce

a logical "1" at Q0 f or the protected sector.

CHIP UNPROTECT WITH 12V SYSTEM

The MX29F400T/B also features the chip unprotect mode,

so that all sectors are unprotected after chip unprotect is

completed to incorporate any changes in the code. It is

recommended to protect all sectors before activating chip

unprotect mode.

To activate this mode, the programming equipment must

force VID on control pin OE and address pin A9. The CE

pins must be set at VIL. Pins A6 must be set to VIH.(see

Table 2) Refer to chip unprotect algorithm and waveform

for the chip unprotect algorithm. The unprotection

mechanism begins on the falling edge of the WE pulse

and is terminated on the rising edge.

It is also possible to determine if the chip is unprotected in

the system by writing the Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

00H at data outputs(Q0-Q7) for an unprotected sector. It

is noted that all sectors are unprotected after the chip

unprotect algorithm is completed.

PO WER-UP SEQ UENCE

The MX29F400T/B powers up in the Read only mode. In

addition, the memory contents ma y only be altered after

successful completion of the predefined command se-

quences.

SECTOR PROTECTION WITHOUT 12V

SYSTEM

The MX29F400T/B also feature a hardware sector

protection method in a system without 12V power suppply.

The programming equipment do not need to supply 12

volts to protect sectors. The details are shown in sector

protect algorithm and waveform.

CHIP UNPROTECT WITHOUT 12V SYSTEM

The MX29F400T/B also feature a hardware chip

unprotection method in a system without 12V power

supply. The programming equipment do not need to

supply 12 volts to unprotect all sectors. The details are

shown in chip unprotect algorithm and waveform.

ABSOLUTE MAXIMUM RATINGS

RATING VALUE

Ambient Operating Temperature 0oC to 70oC

Storage Temperature -65oC to 125oC

Applied Input Voltage -0.5V to 7.0V

Applied Output Voltage -0.5V to 7.0V

VCC to Ground P otential -0.5V to 7.0V

A9 & OE -0.5V to 13.5V

NOTICE:

Stresses greater than those listed under ABSOLUTE MAXI-

MUM RATINGS ma y cause permanent damage to the device.

This is a stress rating only and functional oper ational sections

of this specification is not implied. Exposure to absolute maxi-

mum rating conditions for extended period may affect reliabil-

ity.

NOTICE:

Specifications contained within the following tables are sub-

ject to change.

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

CAPACITANCE TA = 25oC, f = 1.0 MHz

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

CIN Input Capacitance 8 pF VIN = 0V

COUT Output Capacitance 12 pF VOUT = 0V

READ OPERATION

DC CHARACTERISTICS TA = 0oC T O 70oC, VCC = 5V±±

±±

±10%

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ILI Input Leakage Current 1 uA VIN = GND to VCC

ILO Output Leakage Current 10 uA VOUT = GND to VCC

ISB1 Standby VCC current 1 mA CE = VIH

ISB2 1 5 uA CE = VCC + 0.3V

ICC1 Operating VCC current 30 mA IOUT = 0mA, f=1MHz

ICC2 50 mA IOUT= 0mA, f=10MHz

VIL Input Low Voltage -0.3(NOTE 1) 0.8 V

VIH Input High Voltage 2.0 VCC + 0.3 V

VOL Output Low Voltage 0.45 V IOL = 2.1mA

VOH Output High Voltage 2. 4 V IOH = -400uA

NOTES:

1.VIL min. = -1.0V for pulse width ≤ 50 ns.

VIL min. = -2.0V for pulse width ≤ 20 ns.

2.VIH max. = VCC + 1.5V for pulse width ≤ 20 ns

If VIH is over the specified maximum value, read operation

cannot be guaranteed.

AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ± ±

± ±

± 10%

29F400T/B-70 29F400T/B-90 29F400T/B-12

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS

tACC Address to Output Delay 70 90 120 n s CE=OE=VIL

tCE CE to Output Delay 70 90 120 n s OE=VIL

tOE OE to Output Delay 40 40 50 ns CE=VIL

tDF OE High to Output Float (Note1) 0 20 0 30 0 30 ns CE=VIL

tOH Address to Output hold 0 0 0 ns CE=OE=VIL

NOTE:

1. tDF is defined as the time at which the output achieves the

open circuit condition and data is no longer driven.

TEST CONDITIONS:

• Input pulse levels: 0.45V/2.4V

• Input rise and fall times: ≤ 10ns

• Output load: 1 TTL gate + 100pF (Including scope and

jig)

• Reference levels for measuring timing: 0.8V, 2.0V

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

READ TIMING WA VEFORMS

Addresses

tACC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

HIGH Z HIGH Z

D ATA V alid

tOE tDF

tCE

Outputs

tOH

ADD V alid

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

NOTES:

1. VIL min. = -0.6V for pulse width ≤ 20ns.

2. If VIH is over the specified maximum value, programming

operation cannot be guranteed.

3. ICCES is specified with the device de-selected. If the de-

vice is read during erase suspend mode, current dra w is the

sum of ICCES and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.

DC CHARA CTERISTICS TA = 0oC to 70oC , VCC = 5V ± 10%

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ICC1 (Read) Operating VCC Current 30 mA IOUT=0mA, f=1MHz

ICC2 50 mA IOUT=0mA, F=10MHz

ICC3 (Program) 50 mA In Programming

ICC4 (Erase) 50 mA In Erase

ICCES VCC Erase Suspend Current 2 mA CE=VIH, Erase Suspended

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ±±

±±

± 10%

29F400T/B-70 29F400T/B-90 29F400T/B-12

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS

tOES OE setup time 50 50 50 n s

tCWC Command programming cycle 70 90 120 ns

tCEP WE programming pulse width 35 45 50 ns

tCEPH1 WE programming pluse width High 20 20 20 n s

tCEPH2 WE programming pluse width High 20 20 20 n s

tAS Address setup time 0 0 0 ns

tAH Address hold time 45 45 50 ns

tDS Data setup time 30 45 50 ns

tDH Data hold time 0 0 0 ns

tCES CE setup time 0 0 0 ns

tCESC CE setup time before command write 0 0 0 ns

tDF Output disable time (Note 1) 30 40 40 ns

tVA Verify access time 70 90 120 ns

tAETC Total erase time in auto chip erase 4(TYP.) 4(TYP.) 4(TYP.) s

tAETB Total erase time in auto block erase 1(TYP.) 1(TYP.) 1(TYP.) s

tAVT Total programming time in auto verify 7/14 7/14 7/14 us

(byte/ word program time)

tET Standby time in erase 10 10 10 ms

tBALC Block address load cycle 0.3 30 0.3 30 0.3 30 us

tBAL Block address load time 80 80 80 us

tCH CE Hold Time 0 0 0 ns

tCS CE setup to WE going low 0 0 0 ns

tVLHT Voltge Transition Time 4 4 4 us

tOESP OE Setup Time to WE Active 4 4 4 us

tWPP1 Write pulse width for sector protect 10 10 10 us

tWPP2 Write pulse width for sector unprotect 12 12 12 ms

NOTES:

1. tDF defined as the time at which the output achieves the

open circuit condition and data is no longer driven.

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

SWITCHING TEST CIRCUITS

SWITCHING TEST WAVEFORMS

DEVICE UNDER

TEST

DIODES=IN3064

OR EQUIVALENT

CL 6.2K ohm

1.8K ohm +5V

CL=100pF Including jig capacitance

2.0V 2.0V

0.8V

TEST POINTS

2.4V

0.45V

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".

Input pulse rise and fall times are <20ns.

OUTPUT

INPUT

COMMAND WRITE TIMING W A VEFORM

Addresses

DIN

tDS

tAH

Data

tDH

tCS tCH

tCWC

tCEPH1

tCEP

tOES

tAS

VCC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

ADD V alid

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

AUTOMATIC PROGRAMMING TIMING

AUTOMATIC PROGRAMMING TIMING WAVEFORM (WORD MODE)

WAVEFORM

One byte data is programmed. Verify in fast algorithm

and additional programming by exter nal control are not

required because these operations are executed auto-

matically by internal control circuit. Programming comple-

tion can be verified by D ATA polling and toggle bit check-

ing after automatic verification starts. Device outputs

D ATA during programming and DATA after programming

on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling,

timing wa vef orm)

tCWC

tAS

tCEP

tDS tDH tDF

Vcc 5V

Q0,Q1,

Q4(Note 1)

A11~A17

tCEPH1

tAH

ADD V alid

tCESC

Command In

ADD V alid

A0~A10

Command InCommand In Data In DATA

Command In Command InCommand In Data In DATADATA

tAVT

tOE

DATA polling

2AAH

555H 555H

(Q0~Q7)

Command #55H Command #A0H

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

Command #AAH

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART (WORD MODE)

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Program Data/Address

Write Data A0H Address 555H

YES

Toggle Bit Checking

Q6 not Toggled

Verify Byte Ok

YES

Q5 = 1

Reset

Auto Program Completed

Auto Program Exceed

Timing Limit

Invalid

Command

YES

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

AUTOMATIC CHIP ERASE TIMING WAVEFORM

All data in chip are erased. External er ase verification is

not required because data is erased automatically by

internal control circuit. Erasure completion can be veri-

fied by DATA polling and toggle bit checking after auto-

matic erase starts. De vice outputs 0 during erasure and

1 after erasure on Q7.(Q6 is f or toggle bit; see toggle bit,

D ATA polling, timing wa vef orm)

AUTOMATIC CHIP ERASE TIMING WAVEFORM (WORD MODE)

tCWC

tAS

tCEP

tDS tDH tDF

Vcc 5V

Q0,Q1,

Q4(Note 1)

A11~A17

tCEPH1

tAH

tCESC

Command In

A0~A10

Command InCommand In

Command In Command InCommand In

tAETC

tDPA

DATA polling

2AAH

555H 555H

Command #AAH Command #55H Command #80H

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

555H 2AAH 555H

Command In

Command #AAH

Command In

Command #55H

Command In

Command #10H

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART (WORD MODE)

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

YES

Toggle Bit Checking

Q6 not Toggled

Write Data 10H Address 555H

Write Data 55H Address 2AAH

Reset

Auto Chip Erase Exceed

Timing Limit

DATA Polling

Q7 = 1 YES

Q5 = 1

Auto Chip Erase Completed

Invalid

Command

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

AUTOMATIC BLOCK ERASE TIMING

AUTOMATIC BLOCK ERASE TIMING WAVEFORM (WORD MODE)

WAVEFORM

Block data indicated b y A12 to A17 are erased. External

erase v erify is not required because data are erased au-

tomatically by internal control circuit. Erasure comple-

tion can be verified by DAT A polling and toggle bit chec k-

ing after automatic erase starts. Device outputs 0 during

erasure and 1 after erasure on Q7.(Q6 is for toggle bit;

see toggle bit, D ATA polling, timing wa v ef orm)

tCWC

tAS

tCEP

tDS tDH tDF

Vcc 5V

Q0,Q1,

Q4(Note 1)

A12~A17

tCEPH1

tAH

tCESC

Command In

A0~A10

Command InCommand In

Command In Command InCommand In

tAETB

tDPA

DATA polling

2AAH

555H 555H

Command #AAH Command #55H Command #80H

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

555H 2AAH

Command In

Command #AAH

Command In

Command #55H

Command In

Command #30H

Block

Address 0 Block

Address 1

tBAL

tCEPH2

Block

Address N

Command In Command In

Command In

Command #30H

Command In

Command #30H

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

AUTOMATIC BLOCK ERASE ALGORITHM FLOWCHART (WORD MODE)

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

YES

Toggle Bit Checking

Q6 not Toggled

Write Data 30H Sector Address

Write Data 55H Address 2AAH

Reset

Auto Block Erase Exceed

Timing Limit

DATA Polling

Q7 = 1

Q5 = 1

Auto Block Erase Completed

Load Other Sector Addrss If Necessary

(Load Other Sector Address)

YES

Last Block

to Erase

Time-out Bit

Checking Q3=1 ?

Toggle Bit Checking

Q6 Toggled ? Invalid Command

YES

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

ERASE SUSPEND/ERASE RESUME FLOWCHART

START

Write Data B0H

Toggle Bit checking Q6

not toggled

YES

Write Data 30H

Continue Erase

Reading or

Programming End

Read Array or

Program

Another

Erase Suspend ? NO

YES

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITH 12V

tOE

Data

12V

tOESP

tWPP 1

tVLHT

Verify

01H

A17-A12 Sector Address

tOE

Data

12V

tOESP

tWPP 2

tVLHT

Verify

00H

Sector Address

A17-A12

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

Set Up Sector Addr

(A17,A16,A15,A14,A13,A12)

PLSCNT=1

Sector Protection

Complete

Data=01H?

Yes

OE=VID,A9=VID,CE=VIL

A6=VIL

Activate WE Pulse

Time Out 10us

Set WE=VIH, CE=OE=VIL

A9 should remain VID

Read from Sector

Addr=SA, A1=1

Protect Another

Sector?

Remove VID from A9

Write Reset Command

Device Failed

PLSCENT=32?

Yes

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

Protect All Sectors

PLSCNT=1

Chip Unprotect

Complete

Data=00H?

Yes

Set OE=A9=VID

CE=VIL,A6=1

Activate WE Pulse

Time Out 12ms

Set OE=CE=VIL

A9=VID,A1=1

Set Up First Sector Addr

All sectors have

been verified?

Remove VID from A9

Write Reset Command

Device Failed

PLSCENT=1000?

Increment

PLSCENT

Read Data from Device

Yes

Increment

Sector Addr

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V

tOE

Data

Verify

00H

Note: Must issue "unlock for sector protect/unprotect" command

before sector unprotection for a system without 12V provided.

Sector

Addresss

A15-A12

tCEP

Toggle bit polling

Don't care

* See the following Note!

tOE

Data

* See the following Note!

Verify

01H

A15-A12 Sector Address

Note: Must issue "unlock for sector protect/unprotect" command

before sector protection for a system without 12V provided.

Toggle bit polling

Don't care

tCEP

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

Set Up Sector Addr

(A17,A16,A15,A14,A13,A12)

PLSCNT=1

Sector Protection

Complete

Data=01H?

Yes

OE=VIH,A9=VIH

CE=VIL,A6=VIL

Activate WE Pulse to start

Data don't care

Set CE=OE=VIL

A9=VIH

Read from Sector

Addr=SA, A1=1

Protect Another

Sector?

Write Reset Command

Device Failed

PLSCENT=32?

Yes

Increment PLSCNT

Write "unlock for sector protect/unprotect"

Command(Table1)

Toggle bit checking

Q6 not Toggled No

Yes

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

Protect All Sectors

PLSCNT=1

Chip Unprotect

Complete

Data=00H?

Yes

Set OE=A9=VIH

CE=VIL,A6=1

Activate WE Pulse to start

Data don't care

Set OE=CE=VIL

A9=VIH,A1=1

Set Up First Sector Addr

All sectors have

been verified?

Write Reset Command

Device Failed

PLSCENT=1000?

Increment

PLSCENT

Read Data from Device

Yes

Increment

Sector Addr

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

Write "unlock for sector protect/unprotect"

Command (Table 1)

Toggle bit checking

Q6 not Toggled

Yes

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

ID CODE READ TIMING WAVEFORM

tACC

tCE

tACC

tOE

tOH tOH

tDF

DATA OUT

C2H 58H/59H

VID

VIH

VIL

ADD

A1-A8

A10-A16

ADD

DATA OUT

DATA

Q0-Q7

VCC 5V

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

ORDERING INFORMATION

PLASTIC PACKAGE (Top Boot Sector as an sample. For Bottom Boot Sector ones,MX29F400Txx will

change to MX29F400Bxx)

PAR T NO. A CCESS TIME OPERATING CURRENT STANDBY CURRENT PA C KA GE

(ns) MAX.(mA) MAX.(uA)

MX29F400TMC-70 70 50 100 44 Pin SOP

MX29F400TMC-90 90 50 100 44 Pin SOP

MX29F400TMC-12 120 50 100 44 Pin SOP

MX29F400TTC-70 70 50 100 48 Pin TSOP

(Normal T ype)

MX29F400TTC-90 90 50 100 48 Pin TSOP

(Normal T ype)

MX29F400TTC-12 120 50 100 48 Pin TSOP

(Normal T ype)

MX29F400TRC-70 7 0 50 10 0 48 Pin TSOP

(Reverse Type)

MX29F400TRC-90 9 0 50 10 0 48 Pin TSOP

(Reverse Type)

MX29F400TRC-12 1 20 50 10 0 48 Pin TSOP

(Reverse Type)

INDEX

P/N:PM0439

MX29F400T/B

REV. 0.9, AUG. 01, 1998

ITEM MILLIMETERS INCHES

A 20.0 ± .20 .787 ± .008

B 18.40 ± .10 .724 ± .004

C 12.20 max. .480 max.

D 0.15 [Typ.] .006 [Typ.]

E .80 [Typ.] .031 [Typ.]

F .20 ± .10 .008 ±.004

G .30 ± .10 .012 ± .004

H .50 [Typ.] .020 [Typ.]

I .45 max. .018 max.

J 0 ~ .20 0 ~ .008

K 1.00 ± .10 .039 ± .004

L 1.27 max. .050 max.

M .50 .020

N 0 ~ 5 ° .500

NOTE: Each lead centerline is located within

.25 mm[.01 inch] of its true position

[TP] at maximum material condition.

48-PIN PLASTIC TSOP

44-PIN PLASTIC SOP

ITEM MILLIMETERS INCHES

A 28.70 max. 1.130 max.

B 1.10 [REF] .043 [REF]

C 1.27 [TP] .050 [TP]

D .40 ± .10 [Typ.] .016 ± .004 [Typ.]

E .010 min. .004 min.

F 3.00 max. .118 max.

G 2.80 ± .13 .110 ± .005

H 16.04 ± .30 .631 ± .012

I 12.60 .496

J 1.72 .068

K .15 ± .10 [Typ.] .006 ± .004 [Typ.]

L .80 ± .20 .031 ± .008

NOTE: Each lead centerline is located

within .25 mm[.01 inch] of its true

position [TP] at maximum material

condition.

122

2344

DC B

EFGHIJ

INDEX

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:+886-3-578-8888

FAX:+886-3-578-8887

EUROPE OFFICE:

TEL:+32-2-456-8020

FAX:+32-2-456-8021

JAPAN OFFICE:

TEL:+81-44-246-9100

FAX:+81-44-246-9105

SINGAPORE OFFICE:

TEL:+65-747-2309

FAX:+65-748-4090

TAIPEI OFFICE:

TEL:+886-3-509-3300

FAX:+886-3-509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-453-8088

FAX:+1-408-453-8488

CHICAGO OFFICE:

TEL:+1-847-963-1900

FAX:+1-847-963-1909

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.

MX29F400T/B

INDEX