INDEX ADVANCED INFORMATION MX29F400T/B 4M-BIT [512Kx8/156Kx16] CMOS FLASH MEMORY FEATURES * 524,288 x 8/262,144 x 16 switchable * Single power supply operation - 5.0V only operation for read, erase and program operation * Fast access time: 70/90/120ns * Low power consumption - 30mA maximum active current - 1uA typical standby current * Command register architecture - Byte/word Programming (7us/14us typical) - Block Erase (Block structure 16K-Bytex1, - 8K-Bytex2, 32K-Bytex1, and 64K-Byte x7) * Auto Erase (chip & block) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability. - Automatically program and verify data at specified address * Erase suspend/Erase Resume - Suspends an erase operation to read data from, or program data to, another sector that is not being erased, then resumes the erase. * Status Reply - Data polling & Toggle bit for detection of program and erase cycle completion. * Ready/Busy pin (RY/BY) - Provides a hardware method of detecting program or erase cycle completion. - Sector protect/unprotect for 5V only system or 5V/12V system. * Sector protection - Hardware method to disable any combination of sectors from program or erase operations * 100,000 minimum erase/program cycles * Latch-up protected to 100mA from -1V to VCC+1V * Boot Code Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector * Low VCC write inhibit- 3.2V * Package type: - 44-pin SOP - 48-pin TSOP * Compatibility with JEDEC standard - Pinout and software compatible with single-power supply Flash GENERAL DESCRIPTION The MX29F400T/B is a 4-mega bit Flash memory organized as 512K bytes of 8 bits or 256K words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29F400T/B is packaged in 44-pin SOP, 48-pin TSOP. It is designed to be reprogrammed and erased insystem or in-standard EPROM programmers. level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. The standard MX29F400T/B offers access times as fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29F400T/B has separate chip enable (CE) and output enable (OE) controls. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F400T/B uses a 5.0V10% VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F400T/B uses a command register to manage this functionality. The command register allows for 100% TTL The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V. P/N:PM0439 REV. 0.9, AUG. 01, 1998 1 INDEX MX29F400T/B PIN DESCRIPTION PIN CONFIGURATIONS NC RY/BY A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 MX29F400T/B 44 SOP(500 mil) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RESET WE A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC 48 TSOP (Standard Type) (12mm x 20mm) A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET NC NC RY/BY NC A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MX29F400T/B 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SYMBOL PIN NAME A0~A17 Address Input Q0~Q14 Data Input/Output Q15/A-1 Q15(Word mode)/LSB addr(Byte mode) CE Chip Enable Input WE Write Enable Input BYTE Word/Byte Selction input RESET Hardware Reset Pin/Sector Protect Unlock OE Output Enable Input RY/BY Ready/Busy Output VCC Power Supply Pin (+5V) GND Ground Pin 48 TSOP (Reverse Type) (12mm x 20mm) A16 BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND CE A0 A16 BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND CE A0 P/N:PM0439 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MX29F400T/B 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET NC NC RY/BY NC A17 A7 A6 A5 A4 A3 A2 A1 REV. 0.9, AUG. 01, 1998 2 INDEX MX29F400T/B BLOCK STRUCTURE MX29F400T TOP BOOT SECTOR ADDRESS TABLE Sector A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 X X X X X X X 0 1 1 1 X X X X X X X X 0 0 1 X X X X X X X X 0 1 X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 32/16 8/4 8/4 16/8 Address Range (in hexadecimal) (x8) (x16) Address Range Address Range 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-77FFFh 78000h-79FFFh 7A000h-7BFFFh 7C000h-7FFFFh 00000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3BFFFh 3C000h-3CFFFh 3D000h-3DFFFh 3E000h-3FFFFh MX29F400B BOTTOM BOOT SECTOR ADDRESS TABLE Sector A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 0 0 1 X X X X X X X 0 1 1 X X X X X X X X X 0 1 X X X X X X X X 16/8 8/4 8/4 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Address Range (in hexadecimal) (x8) (x16) Address Range Address Range 00000h-03FFFh 04000h-05FFFh 06000h-07FFFh 08000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh 00000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh Note: Address range is A17~A-1 in byte mode and A17~A0 in word mode. P/N:PM0439 REV. 0.9, AUG. 01, 1998 3 INDEX MX29F400T/B BLOCK DIAGRAM CE OE WE CONTROL INPUT HIGH VOLTAGE LOGIC LATCH BUFFER Y-DECODER AND X-DECODER ADDRESS A0-A17 PROGRAM/ERASE WRITE STATE MACHINE (WSM) STATE REGISTER MX29F400T/B FLASH ARRAY Y-PASS GATE SENSE AMPLIFIER PGM DATA HV ARRAY SOURCE HV COMMAND DATA DECODER COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q15/A-1 I/O BUFFER P/N:PM0439 REV. 0.9, AUG. 01, 1998 4 INDEX MX29F400T/B AUTOMATIC PROGRAMMING AUTOMATIC ERASE ALGORITHM The MX29F400T/B is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence or to verify the data programmed. The typical room temperature chip programming time of the MX29F400T/B is less than 4 seconds. MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles, provides feedback to the user as to the status of the programming operation. AUTOMATIC CHIP ERASE The entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 4 second. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE . AUTOMATIC BLOCK ERASE MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX29F400T/B electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection. The MX29F400T/B is block(s) erasable using MXIC's Auto Block Erase algorithm. Block erase modes allow blocks of the array to be erased in one erase cycle. The Automatic Block Erase algorithm automatically programs the specified block(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set. AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm requires the user to only write program set-up commands (include 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provides feedback to the user as to the status of the programming operation. P/N:PM0439 REV. 0.9, AUG. 01, 1998 5 INDEX MX29F400T/B TABLE1. SOFTWARE COMMAND DEFINITIONS Command Bus First Bus Cycle Cycle Addr Data Second Bus Cycle Third Bus Cycle Fourth Bus Cycle Addr Data Addr Data Addr Data Reset 1 XXXH F0H Read 1 RA Read Silicon ID Word 4 555H AAH 2AAH 55H 555H 90H ADI DDI Byte 4 AAAH AAH 555H AAAH 90H ADI DDI Word 4 555H AAH 2AAH 55H 555H A0H PA PD Byte 4 AAAH AAH 555H 55H AAAH A0H PA PD Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH Byte 6 AAAH AAH 555H AAAH 80H Word 6 555H AAH 2AAH 55H 555H Byte 6 AAAH AAH 555H Sector Erase Suspend 1 XXXH B0H Sector Erase Resume 1 XXXH 30H Unlock for sector 6 555H AAH Porgram Chip Erase Sector Erase Fifth Bus Cycle Addr Sixth Bus Cycle Data Addr Data RD 55H 55H 55H 2AAH 55H 2AAH 55H 555H 10H AAAH AAH 555H AAAH 10H 80H 555H 2AAH 55H SA 30H AAAH 80H AAAH AAH 555H SA 30H 555H 80H 555H 2AAH 55H AAH AAH 55H 55H 555H 20H protect/unprotect Note: 1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code. (Refer to table 3) DDI = Data of Device identifier : C2H for manufacture code, 23H/ABH for device code. X = X can be VIL or VIH RA=Address of memory location to be read. RD=Data to be read at location RA. 2.PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address to the sector to be erased. 3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or 555H to Address A10~A-1 in byte mode. Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A11~A17 in either state. COMMAND DEFINITIONS Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Either of the two reset command sequences will reset the device(when applicable). Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 1 defines the valid register command sequences. P/N:PM0439 REV. 0.9, AUG. 01, 1998 6 INDEX MX29F400T/B TABLE 2. MX29F400T/B BUS OPERATION Pins Mode Read Silicon ID Manfacturer Code(1) Read Silicon ID Device Code(1) Read Standby Output Disable Write Sector Protect with 12V system(6) Chip Unprotect with 12V system(6) Verify Sector Protect with 12V system Sector Protect without 12V system (6) Chip Unprotect without 12V system (6) Verify Sector Protect/Unprotect without 12V system (7) Reset CE OE WE A0 A1 A6 A9 Q0 ~ Q7 L L H L L X VID(2) C2H L L H H L X VID(2) 23H/ABH L H L L L L X H H VID(2) H X H L L A0 X X A0 X A1 X X A1 X A6 X X A6 L A9 X X A9 VID(2) DOUT HIGH Z HIGH Z DIN(3) X L VID(2) L X X H VID(2) X L L H X H X VID(2) Code(5) L H L X X L H X L H L X X H H X L L H X H X H Code(5) X X X X X X X HIGH Z NOTES: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1. 2. VID is the Silicon-ID-Read high voltage, 11.5V to 13V. 3. Refer to Table 1 for valid Data-In during a write operation. 4. X can be VIL or VIH. 5. Code=00H means unprotected. Code=01H means protected. A17~A12=Sector address for sector protect. 6. Refer to sector protect/unprotect algorithm and waveform. Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command. 7. The "verify sector protect/unprotect without 12V sysytem" is only following "Sector protect/unprotect without 12V system" command. P/N:PM0439 REV. 0.9, AUG. 01, 1998 7 INDEX MX29F400T/B READ/RESET COMMAND SET-UP AUTOMATIC CHIP/BLOCK ERASE COMMANDS The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H. If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid command must then be written to place the device in the desired state. The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device automatically will program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. SILICON-ID-READ COMMAND Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design practice. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase verification command is required). The MX29F400T/B contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A1=VIL,A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of 23H for MX29F400T, ABH for MX29F400B. If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating an Erase Failure. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. TABLE 3. EXPANDED SILICON ID CODE Pins Manufacture code Device code for MX29F400T Device code for MX29F400B Protected Sector Unprotected Sector A0 VIL VIH A1 VIL VIL Q7 1 0 Q6 1 0 Q5 0 1 Q4 0 0 Q3 0 0 Q2 0 0 Q1 1 1 Q0 0 1 Code(Hex) C2H 23H VIH VIL 1 0 1 0 1 0 1 1 ABH X X VIH VIH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 01H 00H P/N:PM0439 REV. 0.9, AUG. 01, 1998 8 INDEX MX29F400T/B ERASE COMMANDS erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE, while the command(data) is latched on the rising edge of WE. Block addresses selected are loaded into internal register on the sixth falling edge of WE. Each successive block load cycle started by the falling edge of WE must begin within 80ms from the rising edge of the preceding WE. Otherwise, the loading period ends and internal auto block erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Block Erase(30H) or Erase Suspend(B0H) during the time-out period resets the device to read mode. The Automatic Block Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Block Erase command and Automatic Block Erase command. Upon executing the Automatic Block Erase command, the device automatically will program and verify the block(s) memory for an all-zero data pattern. The system is not required to provide any controls or timing during these operations. When the block(s) is automatically verified to contain an all-zero pattern, a self-timed block erase and verify begin. The erase and verify operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Block Erase algorithm, note that the erase automatically terminates when adequate Table 4. Write Operation Status Status Q7 Q6 Q5 Q3 Q2 RY/BY Byte Program in Auto Program Algorithm Q7 Toggle 0 0 1 0 0 Toggle 0 1 Toggle 0 1 1 0 0 Toggle 1 Auto Erase Algorithm Erase Suspend Read In Progress (Erase Suspended Sector) Erase Suspended Mode Erase Suspend Read (Note1) Data Data Data Data Data 1 Q7 Toggle 0 0 1 0 (Non-Erase Suspended Sector) Erase Suspend Program (Non-Erase Suspended Sector) Byte Program in Auto Program Algorithm Exceeded Program/Erase in Auto Erase Algorithm Time Limits Erase Suspended Mode Erase Suspend Program (Note2) (Note3) Q7 Toggle 1 0 1 0 0 Toggle 1 1 N/A 0 Q7 Toggle 1 1 N/A 0 (Non-Erase Suspended Sector) Notes: 1.Performing successive read operations from the erase-suspended sector will cause Q2 to toggle. 2.Performing successive read operations from any address will cause Q6 to toggle. 3.Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the Q2 bit. However, successive reads from the erase-suspended sector will cause Q2 to toggle. P/N:PM0439 REV. 0.9, AUG. 01, 1998 9 INDEX MX29F400T/B data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode(no program verify command is required). ERASE SUSPEND This command only has meaning while the state machine is executing Automatic Block Erase operation, and therefore will only be responded during Automatic Block Erase operation. However, When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to respond to the Read Memory Array, Erase Resume and program commands. DATA POLLING-Q7 The MX29F400T/B also features Data Polling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed. While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program Algorithm an attempt to read the device will produce the true data last written to Q7. The Data Polling feature is valid after the rising edge of the fourth WE pulse of the four write pulse sequences for automatic program. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend program operation is complete, the system can once again read array data within non-suspended blocks. While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is competed. Upon completion of the erase operation, the data on Q7 will read "1". The Data Polling feature is valid after the rising edge of the sixth WE pulse of six write pulse sequences for automatic chip/sector erase. ERASE RESUME This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions.Another Erase Suspend command can be written after the chip has resumed erasing. The Data Polling feature is active during Automatic Program/Erase algorithm or sector erase time-out.(see section Q3 Sector Erase Timer) SET-UP AUTOMATIC PROGRAM COMMANDS To initiate Automatic Program mode, A three-cycle command sequence is required. There are two "unlock" write cycles. These are followed by writing the Automatic Program command A0H. RY/BY:Ready/Busy The RY/By is a dedicated, open-drain output pin that indicates whether an Automatic Erase/Program algorithm is in progress or complete. The RY/BY status is valid after the rising edge of the final WE pulse in the command sequence. Since RY/BY is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to Vcc. Once the Automatic Program command is initiated, the next WE pulse causes a transition to an active programming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE pulse. The rising edge of WE also begins the programming operation. The system is not required to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.)If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. If the program opetation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating a program failure. The automatic programming operation is completed when the Table 4 shows the outputs for RY/BY. P/N:PM0439 REV. 0.9, AUG. 01, 1998 10 INDEX MX29F400T/B Q6:Toggle BIT I Q2:Toggle Bit II Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE pulse in the command sequence(prior to the program or erase operation), and during the sector time-out. The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively eraseing (that is, the Automatic Erase alorithm is in process), or whether that sector is erase-suspended. Toggle Bit I is valid after the rising edge of the final WE pulse in the command sequence. Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 4 to compare outputs for Q2 and Q6. During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, Q6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. Reading Toggle Bits Q6/ Q2 Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfuly completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. If a program address falls within a protected sector, Q6 toggles for approximately 2 us after the program command sequence is written, then returns to reading array data. Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete. Table 4 shows the outputs for Toggle Bit I on Q6. The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. P/N:PM0439 REV. 0.9, AUG. 01, 1998 11 INDEX MX29F400T/B Q5 Exceeded Timing Limits Q3 Sector Erase Timer Q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the only operating functions of the device under this condition. After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted. If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. WRITE PULSE "GLITCH" PROTECTION If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector maynot be reused, (other sectors are still functional and can be reused). Noise pulses of less than 5ns(typical) on CE or WE will not initiate a write cycle. The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used. Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. LOGICAL INHIBIT POWER SUPPLY DECOUPLING In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND. DATA PROTECTION The MX29F400T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. P/N:PM0439 REV. 0.9, AUG. 01, 1998 12 INDEX MX29F400T/B SECTOR PROTECTION WITH 12V SYSTEM POWER-UP SEQUENCE The MX29F400T/B features hardware sector protection. This feature will disable both program and erase operations for these sectors protected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 12V) A6 = VIL and CE = VIL.(see Table 2) Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated on the rising edge. Please refer to sector protect algorithm and waveform. The MX29F400T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. SECTOR PROTECTION WITHOUT 12V SYSTEM The MX29F400T/B also feature a hardware sector protection method in a system without 12V power suppply. The programming equipment do not need to supply 12 volts to protect sectors. The details are shown in sector protect algorithm and waveform. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 ( with CE and OE at VIL and WE at VIH). When A1=1, it will produce a logical "1" code at device output Q0 for a protected sector. Otherwise the device will produce 00H for the unprotected sector. In this mode, the addresses,except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer and device codes.(Read Silicon ID) CHIP UNPROTECT WITHOUT 12V SYSTEM The MX29F400T/B also feature a hardware chip unprotection method in a system without 12V power supply. The programming equipment do not need to supply 12 volts to unprotect all sectors. The details are shown in chip unprotect algorithm and waveform. It is also possible to determine if the sector is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected sector. ABSOLUTE MAXIMUM RATINGS CHIP UNPROTECT WITH 12V SYSTEM RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 & OE The MX29F400T/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode. To activate this mode, the programming equipment must force VID on control pin OE and address pin A9. The CE pins must be set at VIL. Pins A6 must be set to VIH.(see Table 2) Refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. The unprotection mechanism begins on the falling edge of the WE pulse and is terminated on the rising edge. VALUE 0oC to 70oC -65oC to 125oC -0.5V to 7.0V -0.5V to 7.0V -0.5V to 7.0V -0.5V to 13.5V NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Performing a read operation with A1=VIH, it will produce 00H at data outputs(Q0-Q7) for an unprotected sector. It is noted that all sectors are unprotected after the chip unprotect algorithm is completed. NOTICE: Specifications contained within the following tables are subject to change. P/N:PM0439 REV. 0.9, AUG. 01, 1998 13 INDEX MX29F400T/B CAPACITANCE TA = 25oC, f = 1.0 MHz SYMBOL PARAMETER CIN COUT MIN. TYP MAX. UNIT CONDITIONS Input Capacitance 8 pF VIN = 0V Output Capacitance 12 pF VOUT = 0V READ OPERATION 10% DC CHARACTERISTICS TA = 0oC TO 70oC, VCC = 5V SYMBOL PARAMETER ILI ILO ISB1 MIN. TYP MAX. UNIT CONDITIONS Input Leakage Current 1 uA VIN = GND to VCC Output Leakage Current 10 uA VOUT = GND to VCC Standby VCC current 1 mA CE = VIH 5 uA CE = VCC + 0.3V 30 mA IOUT = 0mA, f=1MHz 50 mA IOUT= 0mA, f=10MHz ISB2 ICC1 1 Operating VCC current ICC2 VIL Input Low Voltage -0.3(NOTE 1) VIH Input High Voltage 2.0 VOL Output Low Voltage VOH Output High Voltage 0.8 V VCC + 0.3 V 0.45 2.4 V IOL = 2.1mA V IOH = -400uA NOTES: 1.VIL min. = -1.0V for pulse width 50 ns. VIL min. = -2.0V for pulse width 20 ns. 2.VIH max. = VCC + 1.5V for pulse width 20 ns If VIH is over the specified maximum value, read operation cannot be guaranteed. AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V 10% 29F400T/B-70 SYMBOL PARAMETER MIN. MAX. 29F400T/B-90 MIN. MAX. 29F400T/B-12 MIN. MAX. UNIT CONDITIONS tACC Address to Output Delay 70 90 120 ns CE=OE=VIL tCE CE to Output Delay 70 90 120 ns OE=VIL tOE OE to Output Delay 40 40 50 ns CE=VIL tDF OE High to Output Float (Note1) 0 30 ns CE=VIL tOH Address to Output hold 0 ns CE=OE=VIL 20 0 0 30 0 0 NOTE: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. TEST CONDITIONS: * Input pulse levels: 0.45V/2.4V * Input rise and fall times: 10ns * Output load: 1 TTL gate + 100pF (Including scope and jig) * Reference levels for measuring timing: 0.8V, 2.0V P/N:PM0439 REV. 0.9, AUG. 01, 1998 14 INDEX MX29F400T/B READ TIMING WAVEFORMS VIH ADD Valid Addresses VIL tCE VIH CE VIL WE VIH OE VIH tACC VIL Outputs tDF tOE VIL VOH tOH HIGH Z HIGH Z DATA Valid VOL COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION DC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V 10% SYMBOL PARAMETER ICC1 (Read) Operating VCC Current MIN. TYP ICC2 MAX. UNIT CONDITIONS 30 mA IOUT=0mA, f=1MHz 50 mA IOUT=0mA, F=10MHz ICC3 (Program) 50 mA In Programming ICC4 (Erase) 50 mA In Erase mA CE=VIH, Erase Suspended ICCES VCC Erase Suspend Current 2 NOTES: 1. VIL min. = -0.6V for pulse width 20ns. 2. If VIH is over the specified maximum value, programming operation cannot be guranteed. 3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is the sum of ICCES and ICC1 or ICC2. 4. All current are in RMS unless otherwise noted. P/N:PM0439 REV. 0.9, AUG. 01, 1998 15 INDEX MX29F400T/B AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V 10% 29F400T/B-70 MAX. 29F400T/B-90 MIN. SYMBOL PARAMETER MIN. tOES OE setup time 50 50 50 ns tCWC Command programming cycle 70 90 120 ns tCEP WE programming pulse width 35 45 50 ns tCEPH1 WE programming pluse width High 20 20 20 ns tCEPH2 WE programming pluse width High 20 20 20 ns tAS Address setup time 0 0 0 ns tAH Address hold time 45 45 50 ns tDS Data setup time 30 45 50 ns tDH Data hold time 0 0 0 ns tCES CE setup time 0 0 0 ns tCESC CE setup time before command write 0 0 0 ns tDF Output disable time (Note 1) 30 MAX. 29F400T/B-12 MIN. 40 70 90 MAX. UNIT CONDITIONS 40 ns 120 ns tVA Verify access time tAETC Total erase time in auto chip erase 4(TYP.) 4(TYP.) 4(TYP.) s tAETB Total erase time in auto block erase 1(TYP.) 1(TYP.) 1(TYP.) s tAVT Total programming time in auto verify 7/14 7/14 7/14 us 10 10 ms (byte/ word program time) tET Standby time in erase 10 tBALC Block address load cycle 0.3 tBAL Block address load time 80 tCH CE Hold Time 0 0 0 ns tCS CE setup to WE going low 0 0 0 ns tVLHT Voltge Transition Time 4 4 4 us tOESP OE Setup Time to WE Active 4 4 4 us tWPP1 Write pulse width for sector protect 10 10 10 us tWPP2 Write pulse width for sector unprotect 12 12 12 ms 30 0.3 80 30 0.3 80 30 us us NOTES: 1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven. P/N:PM0439 REV. 0.9, AUG. 01, 1998 16 INDEX MX29F400T/B SWITCHING TEST CIRCUITS DEVICE UNDER 1.8K ohm +5V TEST CL 6.2K ohm DIODES=IN3064 OR EQUIVALENT CL=100pF Including jig capacitance SWITCHING TEST WAVEFORMS 2.4V 2.0V 2.0V TEST POINTS 0.8V 0.8V 0.45V INPUT OUTPUT AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are <20ns. COMMAND WRITE TIMING WAVEFORM VCC Addresses 5V VIH ADD Valid VIL tAH tAS WE VIH VIL tOES tCEPH1 tCEP tCWC CE VIH VIL tCS OE tCH VIH VIL tDS tDH VIH Data DIN VIL P/N:PM0439 REV. 0.9, AUG. 01, 1998 17 INDEX MX29F400T/B AUTOMATIC PROGRAMMING TIMING WAVEFORM One byte data is programmed. Verify in fast algorithm and additional programming by external control are not required because these operations are executed automatically by internal control circuit. Programming completion can be verified by DATA polling and toggle bit check- ing after automatic verification starts. Device outputs DATA during programming and DATA after programming on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) AUTOMATIC PROGRAMMING TIMING WAVEFORM (WORD MODE) Vcc 5V A11~A17 A0~A10 ADD Valid 2AAH 555H tAS WE ADD Valid 555H tCWC tAH tCEPH1 tCESC tAVT CE tCEP OE tDS Q0,Q1, tDH Command In tDF Command In Command In DATA Data In DATA polling Q4(Note 1) Q7 Command In Command #AAH Command In Command In Command #55H Command #A0H DATA Data In DATA tOE (Q0~Q7) Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit P/N:PM0439 REV. 0.9, AUG. 01, 1998 18 INDEX MX29F400T/B AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART (WORD MODE) START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Toggle Bit Checking Q6 not Toggled NO YES Invalid Command NO Verify Byte Ok YES NO Q5 = 1 Auto Program Completed YES Reset Auto Program Exceed Timing Limit P/N:PM0439 REV. 0.9, AUG. 01, 1998 19 INDEX MX29F400T/B AUTOMATIC CHIP ERASE TIMING WAVEFORM All data in chip are erased. External erase verification is not required because data is erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after auto- matic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) AUTOMATIC CHIP ERASE TIMING WAVEFORM (WORD MODE) Vcc 5V A11~A17 A0~A10 2AAH 555H 555H 555H tAS WE 2AAH 555H tCWC tAH tCEPH1 tCESC tAETC CE tCEP OE tDF tDS tDH Q0,Q1, Command In Command In Command In Command In Command In Command In Q4(Note 1) Q7 DATA polling Command In Command #AAH Command In Command In Command In Command In Command In Command #55H Command #80H Command #AAH Command #55H Command #10H tDPA (Q0~Q7) Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit P/N:PM0439 REV. 0.9, AUG. 01, 1998 20 INDEX MX29F400T/B AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART (WORD MODE) START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Toggle Bit Checking Q6 not Toggled NO YES Invalid Command NO DATA Polling Q7 = 1 YES NO Q5 = 1 Auto Chip Erase Completed Reset Auto Chip Erase Exceed Timing Limit P/N:PM0439 REV. 0.9, AUG. 01, 1998 21 INDEX MX29F400T/B AUTOMATIC BLOCK ERASE TIMING WAVEFORM ing after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) Block data indicated by A12 to A17 are erased. External erase verify is not required because data are erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit check- AUTOMATIC BLOCK ERASE TIMING WAVEFORM (WORD MODE) Vcc 5V Block Address 0 A12~A17 A0~A10 2AAH 555H 555H 555H Block Address N 2AAH tAS WE Block Address 1 tCWC tAH tCEPH1 tBAL tCEPH2 tCESC tAETB CE tCEP OE tDF tDS tDH Q0,Q1, Command In Command In Command In Command In Command In Command In Command In Command In Q4(Note 1) Q7 DATA polling Command In Command #AAH Command In Command In Command In Command In Command In Command In Command In Command #55H Command #80H Command #AAH Command #55H Command #30H Command #30H Command #30H (Q0~Q7) tDPA Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit P/N:PM0439 REV. 0.9, AUG. 01, 1998 22 INDEX MX29F400T/B AUTOMATIC BLOCK ERASE ALGORITHM FLOWCHART (WORD MODE) START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address Toggle Bit Checking Q6 Toggled ? NO Invalid Command YES Load Other Sector Addrss If Necessary (Load Other Sector Address) NO Last Block to Erase YES Time-out Bit Checking Q3=1 ? NO YES Toggle Bit Checking Q6 not Toggled NO YES Q5 = 1 DATA Polling Q7 = 1 Reset Auto Block Erase Completed Auto Block Erase Exceed Timing Limit P/N:PM0439 REV. 0.9, AUG. 01, 1998 23 INDEX MX29F400T/B ERASE SUSPEND/ERASE RESUME FLOWCHART START Write Data B0H NO Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or Programming End NO YES Write Data 30H Continue Erase Another Erase Suspend ? NO YES P/N:PM0439 REV. 0.9, AUG. 01, 1998 24 INDEX MX29F400T/B TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITH 12V A1 A6 12V 5V A9 tVLHT Verify 12V 5V OE tVLHT tVLHT tWPP 1 WE tOESP CE Data 01H tOE A17-A12 Sector Address TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V A1 12V 5V A9 tVLHT A6 Verify 12V 5V OE tVLHT tVLHT tWPP 2 WE tOESP CE Data 00H tOE A17-A12 Sector Address P/N:PM0439 REV. 0.9, AUG. 01, 1998 25 INDEX MX29F400T/B SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V START Set Up Sector Addr (A17,A16,A15,A14,A13,A12) PLSCNT=1 OE=VID,A9=VID,CE=VIL A6=VIL Activate WE Pulse Time Out 10us Set WE=VIH, CE=OE=VIL A9 should remain VID Read from Sector Addr=SA, A1=1 No PLSCENT=32? No Data=01H? Yes Device Failed Protect Another Yes Sector? Remove VID from A9 Write Reset Command Sector Protection Complete P/N:PM0439 REV. 0.9, AUG. 01, 1998 26 INDEX MX29F400T/B CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V START Protect All Sectors PLSCNT=1 Set OE=A9=VID CE=VIL,A6=1 Activate WE Pulse Time Out 12ms Increment PLSCENT Set OE=CE=VIL A9=VID,A1=1 Set Up First Sector Addr Read Data from Device No Data=00H? Increment Sector Addr No PLSCENT=1000? Yes Yes No Device Failed All sectors have been verified? Yes Remove VID from A9 Write Reset Command Chip Unprotect Complete * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM0439 REV. 0.9, AUG. 01, 1998 27 INDEX MX29F400T/B TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V A1 A6 5V A9 Toggle bit polling Verify 5V OE tCEP WE * See the following Note! CE Data 01H Don't care tOE A15-A12 Sector Address Note: Must issue "unlock for sector protect/unprotect" command before sector protection for a system without 12V provided. TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V A1 5V A9 A6 Toggle bit polling Verify 5V OE tCEP WE * See the following Note! CE Data 00H Don't care tOE Sector Addresss A15-A12 Note: Must issue "unlock for sector protect/unprotect" command before sector unprotection for a system without 12V provided. P/N:PM0439 REV. 0.9, AUG. 01, 1998 28 INDEX MX29F400T/B SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V START PLSCNT=1 Write "unlock for sector protect/unprotect" Command(Table1) Set Up Sector Addr (A17,A16,A15,A14,A13,A12) OE=VIH,A9=VIH CE=VIL,A6=VIL Activate WE Pulse to start Data don't care Toggle bit checking Q6 not Toggled No Yes Increment PLSCNT Set CE=OE=VIL A9=VIH Read from Sector Addr=SA, A1=1 No PLSCENT=32? No Data=01H? Yes Device Failed Protect Another Yes Sector? Write Reset Command Sector Protection Complete P/N:PM0439 REV. 0.9, AUG. 01, 1998 29 INDEX MX29F400T/B CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V START Protect All Sectors PLSCNT=1 Write "unlock for sector protect/unprotect" Command (Table 1) Set OE=A9=VIH CE=VIL,A6=1 Activate WE Pulse to start Data don't care No Toggle bit checking Q6 not Toggled Increment PLSCENT Yes Set OE=CE=VIL A9=VIH,A1=1 Set Up First Sector Addr Read Data from Device No Data=00H? Increment Sector Addr No PLSCENT=1000? Yes Yes No Device Failed All sectors have been verified? Yes Write Reset Command Chip Unprotect Complete * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM0439 REV. 0.9, AUG. 01, 1998 30 INDEX MX29F400T/B ID CODE READ TIMING WAVEFORM VCC 5V VID ADD VIH VIL A9 ADD VIH A0 VIL tACC tACC ADD A1-A8 A10-A16 CE VIH VIL VIH VIL WE VIH tCE VIL OE VIH tOE VIL tDF tOH tOH VIH DATA Q0-Q7 DATA OUT DATA OUT VIL 58H/59H C2H P/N:PM0439 REV. 0.9, AUG. 01, 1998 31 INDEX MX29F400T/B ORDERING INFORMATION PLASTIC PACKAGE (Top Boot Sector as an sample. For Bottom Boot Sector ones,MX29F400Txx will change to MX29F400Bxx) PART NO. MX29F400TMC-70 MX29F400TMC-90 MX29F400TMC-12 MX29F400TTC-70 ACCESS TIME (ns) 70 90 120 70 OPERATING CURRENT MAX.(mA) 50 50 50 50 STANDBY CURRENT MAX.(uA) 100 100 100 100 MX29F400TTC-90 90 50 100 MX29F400TTC-12 120 50 100 MX29F400TRC-70 70 50 100 MX29F400TRC-90 90 50 100 MX29F400TRC-12 120 50 100 P/N:PM0439 PACKAGE 44 Pin SOP 44 Pin SOP 44 Pin SOP 48 Pin TSOP (Normal Type) 48 Pin TSOP (Normal Type) 48 Pin TSOP (Normal Type) 48 Pin TSOP (Reverse Type) 48 Pin TSOP (Reverse Type) 48 Pin TSOP (Reverse Type) REV. 0.9, AUG. 01, 1998 32 INDEX MX29F400T/B 48-PIN PLASTIC TSOP ITEM MILLIMETERS INCHES A 20.0 .20 .787 .008 B 18.40 .10 .724 .004 C 12.20 max. .480 max. D 0.15 [Typ.] .006 [Typ.] E .80 [Typ.] .031 [Typ.] F .20 .10 .008 .004 G .30 .10 .012 .004 H .50 [Typ.] .020 [Typ.] I .45 max. .018 max. J 0 ~ .20 0 ~ .008 K 1.00 .10 .039 .004 L 1.27 max. .050 max. M .50 .020 0 ~ 5 .500 A N NOTE: B C N M K L D E F I H G J Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition. 44-PIN PLASTIC SOP ITEM MILLIMETERS INCHES A 28.70 max. 1.130 max. B 1.10 [REF] .043 [REF] C 1.27 [TP] .050 [TP] D .40 .10 [Typ.] .016 .004 [Typ.] E .010 min. .004 min. F 3.00 max. .118 max. G 2.80 .13 .110 .005 H 16.04 .30 .631 .012 I 12.60 .496 J 1.72 .068 K .15 .10 [Typ.] .006 .004 [Typ.] L .80 .20 .031 .008 44 23 1 22 H A I G J F K E NOTE: Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition. D C B P/N:PM0439 L REV. 0.9, AUG. 01, 1998 33 INDEX MX29F400T/B MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-8888 FAX:+886-3-578-8887 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-747-2309 FAX:+65-748-4090 TAIPEI OFFICE: TEL:+886-3-509-3300 FAX:+886-3-509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. 34