April 2011 Doc ID 17050 Rev 4 1/158
1
STM32F215xx
STM32F217xx
ARM-based 32-bit MCU, 150MIPs, up to 1MB Flash/128+4KB RAM, crypto,
USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
Features
■Core: ARM 32-bit Cortex™-M3 CPU with
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
performance from Flash memory, frequency up
to 120 MHz, memory protection unit,
150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1)
■Memories
– Up to 1 Mbyte of Flash memory
– 512 bytes of OTP memory
– Up to 128 + 4 Kbytes of SRAM
– Flexible static memory controller that
supports Compact Flash, SRAM, PSRAM,
NOR and NAND memories
– LCD parallel interface, 8080/6800 modes
■Clock, reset and supply management
– From 1.8 to 3.6 V application supply and
I/Os
– POR, PDR, PVD and BOR
– 4 to 26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy at 25 °C)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
■Low power
– Sleep, Stop and Standby modes
–V
BAT supply for RTC, 20 × 32 bit backup
registers, and optional 4 KB backup SRAM
■3 × 12-bit, 0.5 µs A/D converters
– up to 24 channels
– up to 6 MSPS in triple interleaved mode
■2 × 12-bit D/A converters
■General-purpose DMA
– 16-stream DMA controller with centralized
FIFOs and burst support
■Up to 17 timers
– Up to twelve 16-bit and two 32-bit timers,
up to 120 MHz, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
■Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™
■Up to 140 I/O ports with interrupt capability:
– Up to 136 fast I/Os up to 60 MHz
– Up to 138 5 V-tolerant I/Os
■Up to 15 communication interfaces
– Up to 3 × I2C interfaces (SMBus/PMBus)
– Up to 4 USARTs and 2 UARTs (7.5 Mbit/s,
ISO 7816 interface, LIN, IrDA, modem
control)
– Up to 3 SPIs (30 Mbit/s), 2 with muxed I2S
to achieve audio class accuracy via audio
PLL or external PLL
– 2 × CAN interfaces (2.0B Active)
– SDIO interface
■Advanced connectivity
– USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
– USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
– 10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
■8- to 14-bit parallel camera interface: up to
48 Mbyte/s
■Cryptographic acceleration
– Hardware acceleration for AES 128, 192,
256, Triple DES, HASH (MD5, SHA-1)
– Analog true random number generator
■CRC calculation unit, 96-bit unique ID
■Analog true random number generator
Table 1. Device summary
Reference Part number
STM32F215xx
STM32F215RG, STM32F215VG,
STM32F215ZG, STM32F215RE,
STM32F215VE, STM32F215ZE
STM32F217xx
STM32F217VG, STM32F217IG,
STM32F217ZG, STM32F217VE,
STM32F217IE, STM32F217ZE
LQFP64 (10 × 10 mm)
LQFP100 (14 × 14 mm)
LQFP144 (20 × 20 mm)
LQFP176 (24 × 24 mm)(1)
FBGA
UFBGA176
(10 × 10 mm)
www.st.com
Contents STM32F215xx, STM32F217xx
2/158 Doc ID 17050 Rev 4
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 16
2.2.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.3 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 16
2.2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 17
2.2.6 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.7 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.8 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.9 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.10 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.11 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 19
2.2.12 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.13 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.14 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.15 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.16 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.17 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.18 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 22
2.2.19 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.20 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.22 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2.23 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.24 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.25 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.26 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.27 Universal synchronous/asynchronous receiver transmitters
(UARTs/USARTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.28 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM32F215xx, STM32F217xx Contents
Doc ID 17050 Rev 4 3/158
2.2.29 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2.30 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.31 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 28
2.2.32 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.33 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 29
2.2.34 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 29
2.2.35 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2.36 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2.37 Cryptographic acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.38 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.39 ADCs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.40 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.41 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.42 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.43 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 60
5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 60
5.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 61
5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Contents STM32F215xx, STM32F217xx
4/158 Doc ID 17050 Rev 4
5.3.7 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . . 82
5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 87
5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.3.21 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.3.24 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.3.26 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 135
5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 135
5.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
A.1 Main applications versus package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
A.2 Application example with regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . 146
A.3 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 146
A.4 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 148
A.5 Complete audio player solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
STM32F215xx, STM32F217xx List of tables
Doc ID 17050 Rev 4 5/158
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F215xx and STM32F217xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 12
Table 3. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. STM32F21x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 6. Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 7. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 8. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 9. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 10. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 11. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 57
Table 12. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 60
Table 13. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 60
Table 14. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 15. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 16. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 64
Table 17. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 18. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 19. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 70
Table 20. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 70
Table 21. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 22. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 23. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 24. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 25. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 26. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 27. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 28. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 29. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 30. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 31. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 32. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 33. Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 34. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 35. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 36. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 37. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 38. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 39. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 40. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 41. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 42. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 43. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 44. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 45. Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 46. Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . . 95
List of tables STM32F215xx, STM32F217xx
6/158 Doc ID 17050 Rev 4
Table 47. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 48. SCL frequency (fPCLK1= 30 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 49. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 50. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 51. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 52. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 53. USB OTG FS electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 54. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 55. Clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 56. ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 57. Ethernet DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 58. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 59. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 60. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 61. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 62. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 63. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 64. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 65. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 66. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 117
Table 68. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 118
Table 69. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 70. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 71. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 72. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 73. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 74. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 75. Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . 131
Table 76. Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . 134
Table 77. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 78. SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 79. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 80. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data. . . . . . . . . 138
Table 81. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 139
Table 82. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 140
Table 83. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm package mechanical data . 141
Table 84. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data . 142
Table 85. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 86. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 87. Main applications versus package for STM32F20xxx microcontrollers . . . . . . . . . . . . . . 145
Table 88. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
STM32F215xx, STM32F217xx List of figures
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List of figures
Figure 1. Compatible board design: LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 2. Compatible board design: LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. Compatible board design: LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. STM32F21x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. Startup in regulator OFF: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8. STM32F21x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 9. STM32F21x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 10. STM32F21x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. STM32F21x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. STM32F21xxx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 13. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 14. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 15. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 16. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 17. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 18. Number of wait states versus fCPU and VDD range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 19. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 20. Typical current consumption vs temperature, Run mode, code with data
processing running from RAM, and peripherals ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 21. Typical current consumption vs temperature, Run mode, code with data
processing running from RAM, and peripherals OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 22. Typical current consumption vs temperature, Run mode, code with data
processing running from Flash, ART accelerator OFF, peripherals ON . . . . . . . . . . . . . . . 66
Figure 23. Typical current consumption vs temperature, Run mode, code with data
processing running from Flash, ART accelerator OFF, peripherals OFF . . . . . . . . . . . . . . 66
Figure 24. Typical current consumption vs temperature in Sleep mode,
peripherals ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 25. Typical current consumption vs temperature in Sleep mode,
peripherals OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 26. Typical current consumption vs temperature in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 27. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 28. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 29. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 30. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 31. ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 32. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 33. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 34. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 35. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 36. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 37. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 38. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 39. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 40. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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Figure 41. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 42. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 43. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 104
Figure 44. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 45. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 46. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 47. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 48. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 49. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 50. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 112
Figure 51. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 112
Figure 52. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 117
Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 118
Figure 55. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 56. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 57. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 58. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 59. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 60. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 61. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 127
Figure 62. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 128
Figure 63. PC Card/CompactFlash controller waveforms for attribute memory read
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 64. PC Card/CompactFlash controller waveforms for attribute memory write
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 65. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 130
Figure 66. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 131
Figure 67. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 68. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 69. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 134
Figure 70. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 134
Figure 71. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 72. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 73. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 138
Figure 74. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 75. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 139
Figure 76. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 77. LQFP144, 20 x 20 mm, 144-pin low-profile quad
flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 78. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 79. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline . . . . . . . . 141
Figure 80. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline . 142
Figure 81. Regulator OFF/internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 82. USB OTG FS peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 83. USB OTG FS host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 84. OTG FS connection dual-role with internal PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 85. USB OTG HS peripheral-only connection in FS mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 86. USB OTG HS host-only connection in FS mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 87. OTG HS connection dual-role with external PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 88. Complete audio player solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 89. Complete audio player solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
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Figure 90. Audio player solution using PLL, PLLI2S, USB and 1 crystal. . . . . . . . . . . . . . . . . . . . . . 151
Figure 91. Audio PLL (PLLI2S) providing accurate I2S clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 92. Master clock (MCK) used to drive the external audio DAC. . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 93. Master clock (MCK) not used to drive the external audio DAC. . . . . . . . . . . . . . . . . . . . . 152
Introduction STM32F215xx, STM32F217xx
10/158 Doc ID 17050 Rev 4
1 Introduction
This datasheet provides the description of the STM32F215xx and STM32F217xx lines of
microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please
refer to Section 2.1: Full compatibility throughout the family.
The STM32F215xx and STM32F217xx datasheet should be read in conjunction with the
STM32F20x/STM32F21x reference manual.
For information on programming, erasing and protection of the internal Flash memory,
please refer to the STM32F20x/STM32F21x Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
STM32F215xx, STM32F217xx Description
Doc ID 17050 Rev 4 11/158
2 Description
The STM32F215xx and STM32F217xx family is based on the high-performance ARM®
Cortex™-M3 32-bit RISC core operating at a frequency of up to 120 MHz. The family
incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to
128 Kbytes of system SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of
enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit
multi-AHB bus matrix.
The devices also feature an adaptive real-time memory accelerator (ART Accelerator™)
which allows to achieve a performance equivalent to 0 wait state program execution from
Flash memory at a CPU frequency up to 120 MHz. This performance has been validated
using the CoreMark benchmark.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers.
a true number random generator (RNG). They also feature standard and advanced
communication interfaces. New advanced peripherals include an SDIO, an enhanced
flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins
and more), a cryptographic acceleration cell, and a camera interface for CMOS sensors.
The devices also feature standard peripherals.
●Up to three I2Cs
●Three SPIs, two I2Ss. To achieve audio class accuracy, the I2S peripherals can be
clocked via a dedicated internal audio PLL or via an external PLL to allow
synchronization.
●4 USARTs and 2 UARTs
●An USB OTG full-speed and a USB OTG full-speed with high-speed capability (with the
ULPI),
●Two C A N s
●An SDIO interface
●Ethernet and the camera interface available on STM32F217xx devices only.
The STM32F215xx and STM32F217xx family operates in the –40 to +105 °C temperature
range from a 1.8 V to 3.6 V power supply. A comprehensive set of power-saving mode
allows the design of low-power applications.
The STM32F215xx and STM32F217xx family offers devices in four packages ranging from
64 pins to 176 pins. The set of included peripherals changes with the device chosen.
These features make the STM32F215xx and STM32F217xx microcontroller family suitable
for a wide range of applications:
●Motor drive and application control
●Medical equipment
●Industrial applications: PLC, inverters, circuit breakers
●Printers, and scanners
●Alarm systems, video intercom, and HVAC
●Home audio appliances
Figure 4 shows the general block diagram of the device family.
STM32F215xx, STM32F217xx Description
Doc ID 17050 Rev 4 12/158
Table 2. STM32F215xx and STM32F217xx: features and peripheral counts
Peripherals STM32F215Rx STM32F215Vx STM32F215Zx STM32F217Vx STM32F217Zx STM32F217Ix
Flash memory in Kbytes 512 1024 512 1024 512 1024 512 1024 512 1024 512 1024
SRAM in Kbytes
System 128(112+16)
Backup 4 4 4 4 4 4
FSMC memory controller No Ye s
Ethernet No Ye s
Timers
General-purpose 10
Advanced-control 2
Basic 2
Random number generator Ye s
Communication
interfaces
SPI / (I2S) 3 (2)
I2C 3
USART
UART
4
2
USB OTG FS No 1
USB OTG HS 1
CAN 2
Camera interface No Ye s
Encryption Ye s
GPIOs 51 82 114 82 114 140
12-bit ADC
Number of channels
3
16 16 24 16 24 24
12-bit DAC
Number of channels
Ye s
2
Maximum CPU frequency 120 MHz
Operating voltage 1.8 V to 3.6 V
Operating temperatures
Ambient temperatures: –40 to +85 °C /–40 to +105 °C
Junction temperature: –40 to + 125 °C
Package LQFP64 LQFP100 LQFP144 LQFP100 LQFP144 UFBGA176
LQFP176
STM32F215xx, STM32F217xx Description
Doc ID 17050 Rev 4 13/158
2.1 Full compatibility throughout the family
The STM32F215xx and STM32F217xx constitute the STM32F21x family whose members
are fully pin-to-pin, software and feature compatible, allowing the user to try different
memory densities and peripherals for a greater degree of freedom during the development
cycle.
The STM32F215xx and STM32F217xx devices maintain a close compatibility with the
whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The
STM32F215xx and STM32F217xx, however, are not drop-in replacements for the
STM32F10xxx devices: the two families do not have the same power scheme, and so their
power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F21x
family remains simple as only a few pins are impacted.
Figure 1 compatible board design between the STM32F21x and the STM32F10xxx family.
Figure 1. Compatible board design: LQFP144
1. RFU = reserved for future use.
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Description STM32F215xx, STM32F217xx
14/158 Doc ID 17050 Rev 4
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STM32F215xx, STM32F217xx Description
Doc ID 17050 Rev 4 15/158
2.2 Device overview
Figure 4. STM32F21x block diagram
1. The timers connected to APB2 are clocked from TIMxCLK up to 120 MHz, while the timers connected to APB1 are clocked
from TIMxCLK up to 60 MHz.
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Description STM32F215xx, STM32F217xx
16/158 Doc ID 17050 Rev 4
2.2.1 ARM® Cortex™-M3 core with embedded Flash and SRAM
The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded
systems. It was developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced response to interrupts.
The ARM Cortex-M3 32-bit RISC processor features exceptional code-efficiency, delivering
the high-performance expected from an ARM core in the memory size usually associated
with 8- and 16-bit devices.
With its embedded ARM core, the STM32F215xx and STM32F217xx family is compatible
with all ARM tools and software.
Figure 1 shows the general block diagram of the STM32F21x family.
2.2.2 Memory protection unit
The memory protection unit (MPU) is used to separate the processing of tasks from the data
protection. The MPU can manage up to 8 protection areas that can all be further divided up
into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes
of addressable memory.
The memory protection unit is especially helpful for applications where some critical or
certified code has to be protected against the misbehavior of other tasks. It is usually
managed by an RTOS (real-time operating system). If a program accesses a memory
location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS
environment, the kernel can dynamically update the MPU area setting, based on the
process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
2.2.3 Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
standard ARM® Cortex™-M3 processors. It balances the inherent performance advantage
of the ARM Cortex-M3 over Flash memory technologies, which normally requires the
processor to wait for the Flash memory at higher operating frequencies.
To release the processor full 150 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 120 MHz.
2.2.4 Embedded Flash memory
The STM32F21x devices embed a 128-bit wide Flash memory of 128 Kbytes, 256 Kbytes,
512 Kbytes, 768 Kbytes or 1 Mbytes available for storing programs and data.
The devices also feature 512 bytes of OTP memory that can be used to store critical user
data such as Ethernet MAC addresses or cryptographic keys.
STM32F215xx, STM32F217xx Description
Doc ID 17050 Rev 4 17/158
2.2.5 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
2.2.6 True random number generator (RNG)
All STM32F2xxx products embed a true RNG that delivers 32-bit random numbers
produced by an integrated analog circuit.
2.2.7 Embedded SRAM
All STM32F21x products embed up to 128 Kbytes of system SRAM accessed (read/write) at
CPU clock speed with 0 wait states, plus 4 Kbytes of backup SRAM.
2.2.8 Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB
HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a
seamless and efficient operation even when several high-speed peripherals work
simultaneously.
Figure 5. Multi-AHB matrix
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Description STM32F215xx, STM32F217xx
18/158 Doc ID 17050 Rev 4
2.2.9 DMA
The flexible 16-stream general-purpose DMAs (8 streams for DMA1 and 8 streams for
DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to-
peripheral transfers. They share some centralized FIFOs for APB/AHB peripherals, support
burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB)
and performance.
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals:
●SPI and I2S
●I2C
●USART and UART
●General-purpose, basic and advanced-control timers TIMx
●DAC
●SDIO
●Cryptographic acceleration
●Camera interface (DCMI)
●ADC.
2.2.10 FSMC (flexible static memory controller)
The FSMC is embedded in the STM32F215xx and STM32F217xx family. It has four Chip
Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM,
NOR Flash and NAND Flash.
Functionality overview:
●Write FIFO
●Code execution from external memory except for NAND Flash and PC Card
●The targeted frequency, fCLK, is equal to HCLK/2, so external access is at 60 MHz
when HCLK is at 120 MHz and external access is at 30 MHz when HCLK is at 60 MHz
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
STM32F215xx, STM32F217xx Description
Doc ID 17050 Rev 4 19/158
2.2.11 Nested vectored interrupt controller (NVIC)
The STM32F215xx and STM32F217xx embed a nested vectored interrupt controller able to
handle up to 87 maskable interrupt channels (not including the 16 interrupt lines of the
Cortex™-M3) and 16 priority levels.
●Closely coupled NVIC gives low-latency interrupt processing
●Interrupt entry vector table address passed directly to the core
●Closely coupled NVIC core interface
●Allows early processing of interrupts
●Processing of late arriving, higher-priority interrupts
●Support tail chaining
●Processor state automatically saved
●Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
2.2.12 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected
to the 16 external interrupt lines.
2.2.13 Clocks and startup
System clock selection is performed on startup, however, the 16 MHz internal RC oscillator
is selected as the default CPU clock on reset. An external 4-26 MHz clock can be selected,
in which case it is monitored for failure. If failure is detected, the system automatically
switches back to the internal RC oscillator. A software interrupt is generated if enabled.
Similarly, full interrupt management of the PLL clock entry is available when necessary (for
example if an indirectly used external oscillator fails).
The advanced clock controller clocks the core and all peripherals using a single crystal or
oscillator. In particular, the ethernet and USB OTG FS peripherals can be clocked by the
system clock.
Several prescalers and PLLs allow the configuration of the two AHB buses, the high-speed
APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two
AHB buses is 120 MHz and the maximum frequency the high-speed APB domains is
60 MHz. The maximum allowed frequency of the low-speed APB domain is 30 MHz.
In order to achieve audio class performance, a specific crystal can be used. In this case, the
I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz.
Description STM32F215xx, STM32F217xx
20/158 Doc ID 17050 Rev 4
2.2.14 Boot modes
At startup, boot pins are used to select one out of three boot options:
●Boot from user Flash
●Boot from system memory
●Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB15), USB
OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade).
2.2.15 Power supply schemes
●VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
●VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,
RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
●VBAT = 1.65 to 3.6 V: power supply for RTC, external clock, 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Refer to Figure 16: Power supply scheme for more details.
2.2.16 Power supply supervisor
The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, BOR is always active, and
ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the
option byte loading process starts, either to confirm or modify default thresholds, or to
disable BOR permanently. Three BOR thresholds are available through option bytes.
The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or
VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher
than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
2.2.17 Voltage regulator
The regulator has four operating modes:
●Regulator ON
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
●Regulator OFF
– Regulator OFF/internal reset ON
Regulator ON
The regulator ON modes are activated by default on LQFP packages. On UFBGA176
package, they are activated by connecting REGOFF to VSS.
STM32F215xx, STM32F217xx Description
Doc ID 17050 Rev 4 21/158
VDD minimum value is 1.8 V.
There are three regulator ON modes:
●MR is used in nominal regulation mode (Run)
●LPR is used in Stop mode
●Power-down is used in Standby mode:
The regulator output is in high impedance: the kernel circuitry is powered down,
inducing zero consumption (but the contents of the registers and SRAM are lost).
Regulator OFF
●Regulator OFF/internal reset ON
On UFBGA176 package, REGOFF must be connected to VDD.
The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage
source through VCAP_1 and VCAP_2 pins, in addition to VDD.
The following conditions must be respected:
–V
DD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
– If the time for VCAP_1 and VCAP_2 to reach 1.08 V is faster than the time for VDD to
reach 1.8 V, then PA0 should be connected to the NRST pin (see Figure 6).
Otherwise, PA0 should be asserted low externally during POR until VDD reaches
1.8 V (see Figure 7).
In this mode, PA0 cannot be used as a GPIO pin since it allows to reset the part of the
1.2 V logic which is not reset by the NRST pin, when the internal voltage regulator in
OFF.
Figure 6. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization
1. This figure is valid both whatever the internal reset mode (ON or OFF).
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Description STM32F215xx, STM32F217xx
22/158 Doc ID 17050 Rev 4
Figure 7. Startup in regulator OFF: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization
2.2.18 Real-time clock (RTC), backup SRAM and backup registers
The backup domain of the STM32F215xx and STM32F217xx includes:
●The real-time clock (RTC)
●4 Kbytes of backup SRAM
●20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-coded
decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC provides a programmable alarm and programmable
periodic interrupts with wakeup from Stop and Standby modes.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The backup SRAM size is 4 Kbytes and can be enabled by software. When the backup RAM
is enabled the power consumption in Standby or VBAT mode is slightly higher (see
Section 2.2.19: Low-power modes).
The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. Backup registers are not reset by a system, a power reset,
or when the device wakes up from the Standby mode (see Section 2.2.19: Low-power
modes).
The RTC, backup RAM and backup registers are supplied through a switch that takes power
from either the VDD supply when present or the VBAT pin.
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STM32F215xx, STM32F217xx Description
Doc ID 17050 Rev 4 23/158
2.2.19 Low-power modes
The STM32F215xx and STM32F217xx support three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
●Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
●Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from the Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup.
●Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event
occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped when the device
enters the Stop or Standby mode.
2.2.20 VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery or an
external supercapacitor.
VBAT operation is activated when VDD is not present.
Note: When the microcontroller is supplied from VBAT
, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
Description STM32F215xx, STM32F217xx
24/158 Doc ID 17050 Rev 4
2.2.21 Timers and watchdogs
The STM32F215xx and STM32F217xx devices include two advanced-control timers, eight
general-purpose timers, two basic timers and two watchdog timers.
Ta bl e 3 compares the features of the advanced-control, general-purpose and basic timers.
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
●Input capture
●Output compare
●PWM generation (edge- or center-aligned modes)
●One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
Table 3. Timer feature comparison
Timer type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
output
Max
interface
clock
Max
timer
clock
Advanced-
control
TIM1,
TIM8 16-bit
Up,
Down,
Up/down
Any integer
between 1
and 65536
Ye s 4 Ye s 6 0 M H z 120
MHz
General
purpose
TIM2,
TIM5 32-bit
Up,
Down,
Up/down
Any integer
between 1
and 65536
Ye s 4 N o 3 0 M H z 60
MHz
TIM3,
TIM4 16-bit
Up,
Down,
Up/down
Any integer
between 1
and 65536
Ye s 4 N o 3 0 M H z 60
MHz
Basic TIM6,
TIM7 16-bit Up
Any integer
between 1
and 65536
Ye s 0 N o 3 0 M H z 60
MHz
General
purpose
TIM9 16-bit Up
Any integer
between 1
and 65536
No 2 No 60 MHz 120
MHz
TIM10,
TIM11 16-bit Up
Any integer
between 1
and 65536
No 1 No 60 MHz 120
MHz
TIM12 16-bit Up
Any integer
between 1
and 65536
No 2 No 30 MHz 60
MHz
TIM13,
TIM14 16-bit Up
Any integer
between 1
and 65536
No 1 No 30 MHz 60
MHz
STM32F215xx, STM32F217xx Description
Doc ID 17050 Rev 4 25/158
The TIM1 and TIM8 counters can be frozen in debug mode. Many of the advanced-control
timer features are shared with those of the standard TIMx timers which have the same
architecture. The advanced-control timer can therefore work together with the TIMx timers
via the Timer Link feature for synchronization or event chaining.
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F21x devices
(see Ta b l e 3 for differences).
●TIM2, TIM3, TIM4, TIM5
The STM32F21x include 4 full-featured general-purpose timers. TIM2 and TIM5 are
32-bit timers, and TIM3 and TIM4 are 16-bit timers. The TIM2 and TIM5 timers are
based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and
TIM4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler.
They all feature 4 independent channels for input capture/output compare, PWM or
one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on
the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
The counters of TIM2, TIM3, TIM4, TIM5 can be frozen in debug mode. Any of these
general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
●TIM10, TIM11 and TIM9
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10 and TIM11 feature one independent channel, whereas TIM9 has two
independent channels for input capture/output compare, PWM or one-pulse mode
output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured
general-purpose timers. They can also be used as simple time bases.
●TIM12, TIM13 and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13 and TIM14 feature one independent channel, whereas TIM12 has two
independent channels for input capture/output compare, PWM or one-pulse mode
output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured
general-purpose timers.
They can also be used as simple time bases.
2.2.22 Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
Description STM32F215xx, STM32F217xx
26/158 Doc ID 17050 Rev 4
2.2.23 Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
The counter can be frozen in debug mode.
2.2.24 Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
2.2.25 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
●A 24-bit downcounter
●Autoreload capability
●Maskable system interrupt generation when the counter reaches 0
●Programmable clock source
2.2.26 I²C bus
Up to three I²C bus interfaces can operate in multimaster and slave modes. They can
support the Standard- and Fast-modes. They support the 7/10-bit addressing mode and the
7-bit dual addressing mode (as slave). A hardware CRC generation/verification is
embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
2.2.27 Universal synchronous/asynchronous receiver transmitters
(UARTs/USARTs)
The STM32F215xx and STM32F217xx embed four universal synchronous/asynchronous
receiver transmitters (USART1, USART2, USART3 and USART6) and two universal
asynchronous receiver transmitters (UART4 and UART5).
These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
communicate at speeds of up to 7.5 Mbit/s. The other available interfaces communicate at
up to 3.75 Mbit/s.
USART1, USART2, USART3 and USART6 also provide hardware management of the CTS
and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication
capability. All interfaces can be served by the DMA controller.
STM32F215xx, STM32F217xx Description
Doc ID 17050 Rev 4 27/158
2.2.28 Serial peripheral interface (SPI)
The STM32F21x feature up to three SPIs in slave and master modes in full-duplex and
simplex communication modes. SPI1 can communicate at up to 30 Mbits/s, SPI2 and SPI3
can communicate at up to 15 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies
and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification
supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.
2.2.29 Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be
operated in master or slave mode, and can be configured to operate with a 16-/32-bit
resolution as input or output channels. Audio sampling frequencies from 8 kHz up to
192 kHz are supported. When either or both of the I2S interfaces is/are configured in master
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency.
Table 4. USART feature comparison
USART
name
Standard
features
Modem
(RTS/CTS) LIN SPI
master irDA Smartcard
(ISO 7816)
Max. baud rate
in Mbit/s
(oversampling
by 16)
Max. baud rate
in Mbit/s
(oversampling
by 8)
APB
mapping
USART1 X X X X X X 1.87 7.5
APB2
(max.
60 MHz)
USART2 X X X X X X 1.87 3.75
APB1
(max.
30 MHz)
USART3 X X X X X X 1.87 3.75
APB1
(max.
30 MHz)
UART4 X - X - X - 1.87 3.75
APB1
(max.
30 MHz)
UART5 X - X - X - 3.75 3.75
APB1
(max.
30 MHz)
USART6 X X X X X X 3.75 7.5
APB2
(max.
60 MHz)
Description STM32F215xx, STM32F217xx
28/158 Doc ID 17050 Rev 4
2.2.30 SDIO
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with the
SD Memory Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol
Rev1.1.
2.2.31 Ethernet MAC interface with dedicated DMA and IEEE 1588 support
Peripheral available only on the STM32F217xx devices.
The STM32F217xx devices provide an IEEE-802.3-2002-compliant media access controller
(MAC) for ethernet LAN communications through an industry-standard medium-
independent interface (MII) or a reduced medium-independent interface (RMII). The
STM32F217xx requires an external physical interface device (PHY) to connect to the
physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F217xx MII
port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz
(MII) or 50 MHz (RMII) output from the STM32F217xx.
The STM32F217xx includes the following features:
●Supports 10 and 100 Mbit/s rates
●Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors (see the STM32F20x and STM32F21x reference manual for
details)
●Tagged MAC frame support (VLAN support)
●Half-duplex (CSMA/CD) and full-duplex operation
●MAC control sublayer (control frames) support
●32-bit CRC generation and removal
●Several address filtering modes for physical and multicast address (multicast and group
addresses)
●32-bit status code for each transmitted or received frame
●Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive
FIFO are both 2 Kbytes, that is 4 Kbytes in total
●Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
●Triggers interrupt when system time becomes greater than target time
STM32F215xx, STM32F217xx Description
Doc ID 17050 Rev 4 29/158
2.2.32 Controller area network (CAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). The 256 bytes of SRAM which are allocated for each CAN are not shared
with any other peripheral.
2.2.33 Universal serial bus on-the-go full-speed (OTG_FS)
The STM32F215xx and STM32F217xx embed an USB OTG full-speed device/host/OTG
peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the
USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable
endpoint setting and supports suspend/resume. The USB OTG full-speed controller
requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE
oscillator. The major features are:
●Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
●Supports the session request protocol (SRP) and host negotiation protocol (HNP)
●4 bidirectional endpoints
●8 host channels with periodic OUT support
●HNP/SNP/IP inside (no need for any external resistor)
●For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
●Internal FS OTG PHY support
●External FS OTG PHY support through an I2C connection
2.2.34 Universal serial bus on-the-go high-speed (OTG_HS)
The STM32F215xx and STM32F217xx devices embed a USB OTG high-speed (up to
480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and
high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and
features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using
the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
1.0 specification. It has software-configurable endpoint setting and supports
Description STM32F215xx, STM32F217xx
30/158 Doc ID 17050 Rev 4
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The major features are:
●Combined Rx and Tx FIFO size of 1024× 35 bits with dynamic FIFO sizing
●Supports the session request protocol (SRP) and host negotiation protocol (HNP)
●6 bidirectional endpoints
●12 host channels with periodic OUT support
●Internal FS OTG PHY support
●External FS OTG PHY support through an I2C connection
●External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
●Internal USB DMA
●HNP/SNP/IP inside (no need for any external resistor)
●For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
2.2.35 Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I2S application. It allows to
achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I2S sample rate change without
disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 kHz to 192 kHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S
flow with an external PLL (or Codec output).
2.2.36 Digital camera interface (DCMI)
The camera interface is not available in STM32F215xx devices.
STM32F217xx products embed a camera interface that can connect with camera modules
and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The
camera interface can sustain up to 27 Mbyte/s at 27 MHz or 48 Mbyte/s at 48 MHz. It
features:
●Programmable polarity for the input pixel clock and synchronization signals
●Parallel data communication can be 8-, 10-, 12- or 14-bit
●Supports 8-bit progressive video monochrome or raw Bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
●Supports continuous mode or snapshot (a single frame) mode
●Capability to automatically crop the image
STM32F215xx, STM32F217xx Description
Doc ID 17050 Rev 4 31/158
2.2.37 Cryptographic acceleration
The STM32F215xx and STM32F217xx devices embed a cryptographic accelerator. This
cryprographic accelerator provides a set of hardware acceleration for the advanced
cryptographic algorithms usually needed to provide confidentiality, authentication, data
integrity and non repudiation when exchanging messages with a peer.
●These algorithms consists of:
Encryption/Decryption
– DES/TDES (data encryption standard/triple data encryption standard): ECB
(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,
128- or 192-bit key
– AES (advanced encryption standard): ECB, CBC and CTR (counter mode)
chaining algorithms, 128, 192 or 256-bit key
Universal hash
– SHA-1 (secure hash algorithm)
–MD5
●It also provides a true random number generator that deliver 32-bit random numbers
produced by an integrated analog circuit.
2.2.38 GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O alternate function configuration can be locked if needed by following a specific
sequence in order to avoid spurious writing to the I/Os registers.
To provide fast I/O handling, the GPIOs are on the fast AHB1 bus with a clock up to
120 MHz that leads to a maximum I/O toggling speed of 60 MHz.
2.2.39 ADCs (analog-to-digital converters)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
●Simultaneous sample and hold
●Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
The events generated by the timers TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 can be
internally connected to the ADC start trigger and injection trigger, respectively, to allow the
application to synchronize A/D conversion and timers.
Description STM32F215xx, STM32F217xx
32/158 Doc ID 17050 Rev 4
2.2.40 DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The design structure is composed of integrated resistor
strings and an amplifier in inverting configuration.
This dual digital Interface supports the following features:
●two DAC converters: one for each output channel
●8-bit or 12-bit monotonic output
●left or right data alignment in 12-bit mode
●synchronized update capability
●noise-wave generation
●triangular-wave generation
●dual DAC channel independent or simultaneous conversions
●DMA capability for each channel
●external triggers for conversion
●input voltage reference VREF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
2.2.41 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.8 and 3.6 V. The temperature sensor is internally connected
to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a
digital value.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
2.2.42 Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
2.2.43 Embedded Trace Macrocell™
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F21x through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
STM32F215xx, STM32F217xx Pinouts and pin description
Doc ID 17050 Rev 4 33/158
3 Pinouts and pin description
Figure 8. STM32F21x LQFP64 pinout
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Pinouts and pin description STM32F215xx, STM32F217xx
34/158 Doc ID 17050 Rev 4
Figure 9. STM32F21x LQFP100 pinout
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STM32F215xx, STM32F217xx Pinouts and pin description
Doc ID 17050 Rev 4 35/158
Figure 10. STM32F21x LQFP144 pinout
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Pinouts and pin description STM32F215xx, STM32F217xx
36/158 Doc ID 17050 Rev 4
Figure 11. STM32F21x LQFP176 pinout
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STM32F215xx, STM32F217xx Pinouts and pin description
Doc ID 17050 Rev 4 37/158
Figure 12. STM32F21xxx UFBGA176 ballout
1. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected.
2. Top view.
1 2 3 9 10 11 12 13 14 15
A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13
B PE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12
CVBATPI7PI6PI5 RFU
VDD_3 VDD_11 VDD_10 VDD_15 PG9 PD5 PD1 PI3 PI2 PA11
DPC13-
TAMP1
PI8-
TAMP2 PI9 PI4 BOOT0 VSS_11 VSS_10 VSS_15 PD4 PD3 PD2 PH15 PI1 PA10
EPC14-
OSC32_IN PF0 PI10 PI11 PH13 PH14 PI0 PA9
FPC15-
OSC32_OUT
VSS_13 VDD_13 PH2 VSS VSS VSS VSS VSS VSS_2 VCAP2 PC9 PA8
GPH0-
OSC_IN VSS_5 VDD_5 PH3 VSS VSS VSS VSS VSS VSS_9 VDD_2 PC8 PC7
HPH1-
OSC_OUT PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS_14 VDD_9 PG8 PC6
J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD_14 VDD_8 PG7 PG6
K PF7 PF6 PF5 VDD_4 VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3
L PF10 PF9 PF8 REGOFF PH11 PH10 PD15 PG2
M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS_6 VSS_7 VCAP1 PH6 PH8 PH9 PD14 PD13
NVREF-PA1
PA0-
WKUP PA4 PC4 PF13 PG0 VDD_6 VDD_7 VDD_1 PE13 PH7 PD12 PD11 PD10
P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8
R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15
AIB
VSS
435678
Table 5. STM32F21x pin and ball definitions
Pins
Pin name
Type(1)
I / O Level(2)
Main
function(3)
(after reset)
Alternate functions Other
functions
LQFP64
LQFP100
LQFP144
LQFP176
UFBGA176
- 1 1 1 A2 PE2 I/O FT PE2 TRACECLK/ FSMC_A23 /
ETH_MII_TXD3
- 2 2 2 A1 PE3 I/O FT PE3 TRACED0/FSMC_A19
- 3 3 3 B1 PE4 I/O FT PE4 TRACED1/FSMC_A20 /
DCMI_D4
- 4 4 4 B2 PE5 I/O FT PE5 TRACED2 / FSMC_A21 /
TIM9_CH1 / DCMI_D6
- 5 5 5 B3 PE6 I/O FT PE6 TRACED3 / FSMC_A22 /
TIM9_CH2 / DCMI_D7
1666C1 V
BAT SV
BAT
---7D2 PI8
(4) I/O FT PI8(5) RTC_AF2
2778D1 PC13
(4) I/O FT PC13(5) RTC_AF1
3889E1PC14
(4)-OSC32_IN(6) I/O FT PC14(5) OSC32_IN
Pinouts and pin description STM32F215xx, STM32F217xx
38/158 Doc ID 17050 Rev 4
49910F1 PC15(4)-
OSC32_OUT(6) I/O FT PC15(5) OSC32_OUT
- - - 11 D3 PI9 I/O FT PI9 CAN1_RX
- - - 12 E3 PI10 I/O FT PI10 ETH_MII_RX_ER
- - - 13 E4 PI11 I/O FT PI11 OTG_HS_ULPI_DIR
---14F2 V
SS_13 SV
SS_13
---15F3 V
DD_13 SV
DD_13
- - 10 16 E2 PF0 I/O FT PF0 FSMC_A0 / I2C2_SDA
- - 11 17 H3 PF1 I/O FT PF1 FSMC_A1 / I2C2_SCL
- - 12 18 H2 PF2 I/O FT PF2 FSMC_A2 / I2C2_SMBA
- - 13 19 J2 PF3(6) I/O FT PF3 FSMC_A3 ADC3_IN9
- - 14 20 J3 PF4(6) I/O FT PF4 FSMC_A4 ADC3_IN14
--1521K3 PF5
(6) I/O FT PF5 FSMC_A5 ADC3_IN15
-101622G2 V
SS_5 SV
SS_5
-111723G3 V
DD_5 SV
DD_5
--1824K2 PF6
(6) I/O FT PF6 TIM10_CH1 / FSMC_NIORD ADC3_IN4
--1925K1 PF7
(6) I/O FT PF7 TIM11_CH1/FSMC_NREG ADC3_IN5
- - 20 26 L3 PF8(6) I/O FT PF8 TIM13_CH1 /
FSMC_NIOWR ADC3_IN6
- - 21 27 L2 PF9(6) I/O FT PF9 TIM14_CH1 / FSMC_CD ADC3_IN7
- - 22 28 L1 PF10(6) I/O FT PF10 FSMC_INTR ADC3_IN8
5122329G1 PH0
(6)-OSC_IN I/O FT PH0 OSC_IN
6132430H1 PH1
(6)-OSC_OUT I/O FT PH1 OSC_OUT
7 14 25 31 J1 NRST I/O NRST
8152632M2 PC0
(6) I/O FT PC0 OTG_HS_ULPI_STP ADC123_
IN10
9162733M3 PC1
(6) I/O FT PC1 ETH_MDC ADC123_
IN11
10 17 28 34 M4 PC2(6) I/O FT PC2
SPI2_MISO /
OTG_HS_ULPI_DIR /
ETH_MII_TXD2
ADC123_
IN12
11 18 29 35 M5 PC3(6) I/O FT PC3
SPI2_MOSI / I2S2_SD /
OTG_HS_ULPI_NXT /
ETH_MII_TX_CLK
ADC123_
IN13
-193036 - V
DD_12 SV
DD_12
Table 5. STM32F21x pin and ball definitions (continued)
Pins
Pin name
Type(1)
I / O Level(2)
Main
function(3)
(after reset)
Alternate functions Other
functions
LQFP64
LQFP100
LQFP144
LQFP176
UFBGA176
STM32F215xx, STM32F217xx Pinouts and pin description
Doc ID 17050 Rev 4 39/158
12 20 31 37 M1 VSSA SV
SSA
----N1 V
REF- SV
REF-
-213238P1 V
REF+ SV
REF+
13 22 33 39 R1 VDDA SV
DDA
14 23 34 40 N3 PA0(7)-WKUP(6) I/O FT PA0-WKUP
USART2_CTS/ UART4_TX/
ETH_MII_CRS /
TIM2_CH1_ETR/
TIM5_CH1 / TIM8_ETR
ADC123_CH0/
WKUP
15 24 35 41 N2 PA1(6) I/O FT PA1
USART2_RTS / UART4_RX/
ETH_RMII_REF_CLK /
ETH_MII_RX_CLK /
TIM5_CH2 / TIM2_CH2
ADC123_IN1
16 25 36 42 P2 PA2(6) I/O FT PA2
USART2_TX/TIM5_CH3 /
TIM9_CH1 / TIM2_CH3 /
ETH_MDIO
ADC123_IN2
- - - 43 F4 PH2 I/O FT PH2 ETH_MII_CRS
- - - 44 G4 PH3 I/O FT PH3 ETH_MII_COL
---45H4 PH4 I/OFT PH4 I2C2_SCL /
OTG_HS_ULPI_NXT
- - - 46 J4 PH5 I/O FT PH5 I2C2_SDA
17 26 37 47 R2 PA3(6) I/O FT PA3
USART2_RX/TIM5_CH4 /
TIM9_CH2 / TIM2_CH4 /
OTG_HS_ULPI_D0 /
ETH_MII_COL
ADC123_IN3
18 27 38 48 - VSS_4 SV
SS_4
L4 REGOFF I/O REGOFF
19 28 39 49 K4 VDD_4 SV
DD_4
20 29 40 50 N4 PA4(6) I/O TT PA4
SPI1_NSS / SPI3_NSS /
USART2_CK /
DCMI_HSYNC /
OTG_HS_SOF/ I2S3_WS
ADC12_IN4
/DAC1_OUT
21 30 41 51 P4 PA5(6) I/O TT PA5
SPI1_SCK/
OTG_HS_ULPI_CK / /
TIM2_CH1_ETR/
TIM8_CHIN
ADC12_IN5
/DAC2_OUT
22 31 42 52 P3 PA6(6) I/O FT PA6
SPI1_MISO /
TIM8_BKIN/TIM13_CH1 /
DCMI_PIXCLK / TIM3_CH1 /
TIM1_BKIN
ADC12_IN6
Table 5. STM32F21x pin and ball definitions (continued)
Pins
Pin name
Type(1)
I / O Level(2)
Main
function(3)
(after reset)
Alternate functions Other
functions
LQFP64
LQFP100
LQFP144
LQFP176
UFBGA176
Pinouts and pin description STM32F215xx, STM32F217xx
40/158 Doc ID 17050 Rev 4
23 32 43 53 R3 PA7(6) I/O FT PA7
SPI1_MOSI/ TIM8_CH1N /
TIM14_CH1
TIM3_CH2/
ETH_MII_RX_DV /
TIM1_CH1N /
RMII_CRS_DV
ADC12_IN7
24 33 44 54 N5 PC4(6) I/O FT PC4 ETH_RMII_RX_D0 /
ETH_MII_RX_D0 ADC12_IN14
25 34 45 55 P5 PC5(6) I/O FT PC5 ETH_RMII_RX_D1 /
ETH_MII_RX_D1 ADC12_IN15
26 35 46 56 R5 PB0(6) I/O FT PB0
TIM3_CH3 / TIM8_CH2N/
OTG_HS_ULPI_D1/
ETH_MII_RXD2 /
TIM1_CH2N
ADC12_IN8
27 36 47 57 R4 PB1(6) I/O FT PB1
TIM3_CH4 / TIM8_CH3N/
OTG_HS_ULPI_D2/
ETH_MII_RXD3 /
OTG_HS_INTN /
TIM1_CH3N
ADC12_IN9
28 37 48 58 M6 PB2 I/O FT PB2-BOOT1
- - 49 59 R6 PF11 I/O FT PF11 DCMI_12
- - 50 60 P6 PF12 I/O FT PF12 FSMC_A6
--5161M8 V
SS_6 SV
SS_6
--5262N8 V
DD_6 SV
DD_6
- - 53 63 N6 PF13 I/O FT PF13 FSMC_A7
- - 54 64 R7 PF14 I/O FT PF14 FSMC_A8
- - 55 65 P7 PF15 I/O FT PF15 FSMC_A9
- - 56 66 N7 PG0 I/O FT PG0 FSMC_A10
- - 57 67 M7 PG1 I/O FT PG1 FSMC_A11
- 38 58 68 R8 PE7 I/O FT PE7 FSMC_D4/TIM1_ETR
- 39 59 69 P8 PE8 I/O FT PE8 FSMC_D5/TIM1_CH1N
- 40 60 70 P9 PE9 I/O FT PE9 FSMC_D6/TIM1_CH1
--6171M9 V
SS_7 SV
SS_7
--6272N9 V
DD_7 SV
DD_7
- 41 63 73 R9 PE10 I/O FT PE10 FSMC_D7/TIM1_CH2N
- 42 64 74 P10 PE11 I/O FT PE11 FSMC_D8/TIM1_CH2
- 43 65 75 R10 PE12 I/O FT PE12 FSMC_D9/TIM1_CH3N
Table 5. STM32F21x pin and ball definitions (continued)
Pins
Pin name
Type(1)
I / O Level(2)
Main
function(3)
(after reset)
Alternate functions Other
functions
LQFP64
LQFP100
LQFP144
LQFP176
UFBGA176
STM32F215xx, STM32F217xx Pinouts and pin description
Doc ID 17050 Rev 4 41/158
- 44 66 76 N11 PE13 I/O FT PE13 FSMC_D10/TIM1_CH3
- 45 67 77 P11 PE14 I/O FT PE14 FSMC_D11/TIM1_CH4
- 46 68 78 R11 PE15 I/O FT PE15 FSMC_D12/TIM1_BKIN
29 47 69 79 R12 PB10 I/O FT PB10
SPI2_SCK/ I2S2_SCK/
I2C2_SCL / USART3_TX /
OTG_HS_ULPI_D3 /
ETH_MII_RX_ER /
OTG_HS_SCL / TIM2_CH3
30 48 70 80 R13 PB11 I/O FT PB11
I2C2_SDA/USART3_RX/
OTG_HS_ULPI_D4 /
ETH_RMII_TX_EN/
ETH_MII_TX_EN /
OTG_HS_SDA / TIM2_CH4
31 49 71 81 M10 VCAP_1 SV
CAP_1
32 50 72 82 N10 VDD_1 SV
DD_1
---83M11 PH6 I/OFT PH6 I2C2_SMBA / TIM12_CH1 /
ETH_MII_RXD2
- - - 84 N12 PH7 I/O FT PH7 I2C3_SCL / ETH_MII_RXD3
- - - 85 M12 PH8 I/O FT PH8 I2C3_SDA / DCMI_HSYNC
---86M13 PH9 I/OFT PH9 I2C3_SMBA / TIM12_CH2/
DCMI_D0
- - - 87 L13 PH10 I/O FT PH10 TIM5_CH1_ETR / DCMI_D1
- - - 88 L12 PH11 I/O FT PH11 TIM5_CH2 / DCMI_D2
- - - 89 K12 PH12 I/O FT PH12 TIM5_CH3 / DCMI_D3
---90H12 V
SS_14 SV
SS_14
---91J12 V
DD_14 SV
DD_14
33 51 73 92 P12 PB12 I/O FT PB12
SPI2_NSS/I2S2_WS/
I2C2_SMBA/
USART3_CK/ TIM1_BKIN /
CAN2_RX /
OTG_HS_ULPI_D5/
ETH_RMII_TXD0 /
ETH_MII_TXD0/
OTG_HS_ID
34 52 74 93 P13 PB13 I/O FT PB13
SPI2_SCK / I2S2_SCK /
USART3_CTS/
TIM1_CH1N /CAN2_TX /
OTG_HS_ULPI_D6 /
ETH_RMII_TXD1 /
ETH_MII_TXD1
OTG_HS_
VBUS
Table 5. STM32F21x pin and ball definitions (continued)
Pins
Pin name
Type(1)
I / O Level(2)
Main
function(3)
(after reset)
Alternate functions Other
functions
LQFP64
LQFP100
LQFP144
LQFP176
UFBGA176
Pinouts and pin description STM32F215xx, STM32F217xx
42/158 Doc ID 17050 Rev 4
35 53 75 94 R14 PB14 I/O FT PB14
SPI2_MISO/ TIM1_CH2N /
TIM12_CH1 / OTG_HS_DM
USART3_RTS/ TIM8_CH2N
36 54 76 95 R15 PB15 I/O FT PB15
SPI2_MOSI / I2S2_SD /
TIM1_CH3N / TIM8_CH3N /
TIM12_CH2 / OTG_HS_DP /
RTC_50Hz
- 55 77 96 P15 PD8 I/O FT PD8 FSMC_D13 / USART3_TX
- 56 78 97 P14 PD9 I/O FT PD9 FSMC_D14 / USART3_RX
- 57 79 98 N15 PD10 I/O FT PD10 FSMC_D15 / USART3_CK
- 58 80 99 N14 PD11 I/O FT PD11 FSMC_A16/USART3_CTS
- 59 81 100 N13 PD12 I/O FT PD12 FSMC_A17/TIM4_CH1 /
USART3_RTS
- 60 82 101 M15 PD13 I/O FT PD13 FSMC_A18/TIM4_CH2
- - 83 102 - VSS_8 SV
SS_8
- - 84 103 J13 VDD_8 SV
DD_8
- 61 85 104 M14 PD14 I/O FT PD14 FSMC_D0/TIM4_CH3
- 62 86 105 L14 PD15 I/O FT PD15 FSMC_D1/TIM4_CH4
- - 87 106 L15 PG2 I/O FT PG2 FSMC_A12
- - 88 107 K15 PG3 I/O FT PG3 FSMC_A13
- - 89 108 K14 PG4 I/O FT PG4 FSMC_A14
- - 90 109 K13 PG5 I/O FT PG5 FSMC_A15
- - 91 110 J15 PG6 I/O FT PG6 FSMC_INT2
- - 92 111 J14 PG7 I/O FT PG7 FSMC_INT3 /USART6_CK
- - 93 112 H14 PG8 I/O FT PG8 USART6_RTS /
ETH_PPS_OUT
- - 94 113 G12 VSS_9 SV
SS_9
- - 95 114 H13 VDD_9 SV
DD_9
37 63 96 115 H15 PC6 I/O FT PC6
SPI2_MCK /
TIM8_CH1/SDIO_D6 /
USART6_TX /
DCMI_D0/TIM3_CH1
38 64 97 116 G15 PC7 I/O FT PC7
SPI3_MCK /
TIM8_CH2/SDIO_D7 /
USART6_RX /
DCMI_D1/TIM3_CH2
Table 5. STM32F21x pin and ball definitions (continued)
Pins
Pin name
Type(1)
I / O Level(2)
Main
function(3)
(after reset)
Alternate functions Other
functions
LQFP64
LQFP100
LQFP144
LQFP176
UFBGA176
STM32F215xx, STM32F217xx Pinouts and pin description
Doc ID 17050 Rev 4 43/158
39 65 98 117 G14 PC8 I/O FT PC8
TIM8_CH3/SDIO_D0
/TIM3_CH3/ USART6_CK /
DCMI_D2
40 66 99 118 F14 PC9 I/O FT PC9
I2S2_CKIN/ I2S3_CKIN/
MCO2 /
TIM8_CH4/SDIO_D1 /
/I2C3_SDA / DCMI_D3 /
TIM3_CH4
41 67 100 119 F15 PA8 I/O FT PA8
MCO1 / USART1_CK/
TIM1_CH1/ I2C3_SCL/
OTG_FS_SOF
42 68 101 120 E15 PA9 I/O FT PA9 USART1_TX/ TIM1_CH2 /
I2C3_SMBA / DCMI_D0
OTG_FS_
VBUS
43 69 102 121 D15 PA10 I/O FT PA10 USART1_RX/ TIM1_CH3/
OTG_FS_ID/DCMI_D1
44 70 103 122 C15 PA11 I/O FT PA11 USART1_CTS / CAN1_RX /
TIM1_CH4 / OTG_FS_DM
45 71 104 123 B15 PA12 I/O FT PA12 USART1_RTS / CAN1_TX/
TIM1_ETR/ OTG_FS_DP
46 72 105 124 A15 PA13 I/O FT JTMS-SWDIO JTMS-SWDIO
47 73 106 125 F13 VCAP_2 SV
CAP_2
- 74 107 126 F12 VSS_2 SV
SS_2
48 75 108 127 G13 VDD_2 SV
DD_2
- - - 128 E12 PH13 I/O FT PH13 TIM8_CH1N / CAN1_TX
- - - 129 E13 PH14 I/O FT PH14 TIM8_CH2N / DCMI_D4
- - - 130 D13 PH15 I/O FT PH15 TIM8_CH3N / DCMI_D11
- - - 131 E14 PI0 I/O FT PI0 TIM5_CH4 / SPI2_NSS /
I2S2_WS / DCMI_D13
- - - 132 D14 PI1 I/O FT PI1 SPI2_SCK / I2S2_SCK /
DCMI_D8
- - - 133 C14 PI2 I/O FT PI2 TIM8_CH4 /SPI2_MISO /
DCMI_D9
- - - 134 C13 PI3 I/O FT PI3 TIM8_ETR / SPI2_MOSI /
I2S2_SD / DCMI_D10
- - - 135 D9 VSS_15 SV
SS_15
- - - 136 C9 VDD_15 SV
DD_15
49 76 109 137 A14 PA14 I/O FT JTCK-SWCLK JTCK-SWCLK
Table 5. STM32F21x pin and ball definitions (continued)
Pins
Pin name
Type(1)
I / O Level(2)
Main
function(3)
(after reset)
Alternate functions Other
functions
LQFP64
LQFP100
LQFP144
LQFP176
UFBGA176
Pinouts and pin description STM32F215xx, STM32F217xx
44/158 Doc ID 17050 Rev 4
50 77 110 138 A13 PA15 I/O FT JTDI
JTDI/ SPI3_NSS/
I2S3_WS/TIM2_CH1_ETR /
SPI1_NSS
51 78 111 139 B14 PC10 I/O FT PC10
SPI3_SCK / I2S3_SCK /
UART4_TX / SDIO_D2 /
DCMI_D8 / USART3_TX
52 79 112 140 B13 PC11 I/O FT PC11
UART4_RX/ SPI3_MISO /
SDIO_D3 /
DCMI_D4/USART3_RX
53 80 113 141 A12 PC12 I/O FT PC12
UART5_TX/SDIO_CK /
DCMI_D9 / SPI3_MOSI /
I2S3_SD / USART3_CK
- 81 114 142 B12 PD0 I/O FT PD0 FSMC_D2/CAN1_RX
- 82 115 143 C12 PD1 I/O FT PD1 FSMC_D3 / CAN1_TX
54 83 116 144 D12 PD2 I/O FT PD2 TIM3_ETR/UART5_RX
SDIO_CMD / DCMI_D11
- 84 117 145 D11 PD3 I/O FT PD3 FSMC_CLK/USART2_CTS
- 85 118 146 D10 PD4 I/O FT PD4 FSMC_NOE/USART2_RTS
- 86 119 147 C11 PD5 I/O FT PD5 FSMC_NWE/USART2_TX
- - 120 148 D8 VSS_10 SV
SS_10
- - 121 149 C8 VDD_10 SV
DD_10
- 87 122 150 B11 PD6 I/O FT PD6 FSMC_NWAIT/USART2_RX
- 88 123 151 A11 PD7 I/O FT PD7 USART2_CK/FSMC_NE1/F
SMC_NCE2
- - 124 152 C10 PG9 I/O FT PG9 USART6_RX /
FSMC_NE2/FSMC_NCE3
- - 125 153 B10 PG10 I/O FT PG10 FSMC_NCE4_1/
FSMC_NE3
- - 126 154 B9 PG11 I/O FT PG11 FSMC_NCE4_2 /
ETH_MII_TX_EN
- - 127 155 B8 PG12 I/O FT PG12 FSMC_NE4 / USART6_RTS
- - 128 156 A8 PG13 I/O FT PG13
FSMC_A24 / USART6_CTS
/ETH_MII_TXD0/ETH_RMII_
TXD0
- - 129 157 A7 PG14 I/O FT PG14
FSMC_A25 / USART6_TX
/ETH_MII_TXD1/ETH_RMII_
TXD1
- - 130 158 D7 VSS_11 SV
SS_11
Table 5. STM32F21x pin and ball definitions (continued)
Pins
Pin name
Type(1)
I / O Level(2)
Main
function(3)
(after reset)
Alternate functions Other
functions
LQFP64
LQFP100
LQFP144
LQFP176
UFBGA176
STM32F215xx, STM32F217xx Pinouts and pin description
Doc ID 17050 Rev 4 45/158
- - 131 159 C7 VDD_11 SV
DD_11
- - 132 160 B7 PG15 I/O FT PG15 USART6_CTS / DCMI_D13
55 89 133 161 A10 PB3 I/O FT JTDO/
TRACESWO
JTDO/ TRACESWO/
SPI3_SCK / I2S3_SCK /
TIM2_CH2 / SPI1_SCK
56 90 134 162 A9 PB4 I/O FT NJTRST NJTRST/ SPI3_MISO /
TIM3_CH1 / SPI1_MISO
57 91 135 163 A6 PB5 I/O FT PB5
I2C1_SMBA/ CAN2_RX /
OTG_HS_ULPI_D7 /
ETH_PPS_OUT/TIM3_CH2 /
SPI1_MOSI/ SPI3_MOSI /
DCMI_D10 / I2S3_SD
58 92 136 164 B6 PB6 I/O FT PB6
I2C1_SCL/ TIM4_CH1 /
CAN2_TX /OTG_FS_INTN /
DCMI_D5/USART1_TX
59 93 137 165 B5 PB7 I/O FT PB7
I2C1_SDA / FSMC_NL(8) /
DCMI_VSYNC /
USART1_RX/ TIM4_CH2
60 94 138 166 D6 BOOT0 I BOOT0 VPP
61 95 139 167 A5 PB8 I/O FT PB8
TIM4_CH3/SDIO_D4/
TIM10_CH1 / DCMI_D6 /
OTG_FS_SCL/
ETH_MII_TXD3 / I2C1_SCL/
CAN1_RX
62 96 140 168 B4 PB9 I/O FT PB9
SPI2_NSS/ I2S2_WS/
TIM4_CH4/ TIM11_CH1/
OTG_FS_SDA/ SDIO_D5 /
DCMI_D7 / I2C1_SDA /
CAN1_TX
- 97 141 169 A4 PE0 I/O FT PE0 TIM4_ETR / FSMC_NBL0 /
DCMI_D2
- 98 142 170 A3 PE1 I/O FT PE1 FSMC_NBL1 / DCMI_D3
----D5 V
SS SV
SS
63 - - - - VSS_3 SV
SS_3
- 99 143 171 C6 RFU(9)
64 100 144 172 C5 VDD_3 SV
DD_3
- - - 173 D4 PI4 I/O FT PI4 TIM8_BKIN / DCMI_D5
- - - 174 C4 PI5 I/O FT PI5 TIM8_CH1 / DCMI_VSYNC
- - - 175 C3 PI6 I/O FT PI6 TIM8_CH2 / DCMI_D6
Table 5. STM32F21x pin and ball definitions (continued)
Pins
Pin name
Type(1)
I / O Level(2)
Main
function(3)
(after reset)
Alternate functions Other
functions
LQFP64
LQFP100
LQFP144
LQFP176
UFBGA176
Pinouts and pin description STM32F215xx, STM32F217xx
46/158 Doc ID 17050 Rev 4
- - - 176 C2 PI7 I/O FT PI7 TIM8_CH3 / DCMI_D7
1. I = input, O = output, S = supply, HiZ = high impedance.
2. FT = 5 V tolerant; TT = 3.6 V tolerant.
3. Function availability depends on the chosen device.
4. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a
maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED).
5. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F20x and STM32F21x reference manual, available from the STMicroelectronics
website: www.st.com.
6. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
7. If the device is delivered in an UFBGA176 package and if the REGOFF pin is set to VDD (Regulator OFF), then PA0 is used
as an internal Reset (active low).
8. FSMC_NL pin is also named FSMC_NADV on memory devices.
9. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected.
Table 5. STM32F21x pin and ball definitions (continued)
Pins
Pin name
Type(1)
I / O Level(2)
Main
function(3)
(after reset)
Alternate functions Other
functions
LQFP64
LQFP100
LQFP144
LQFP176
UFBGA176
Pinouts and pin description STM32F215xx, STM32F217xx
47/158 Doc ID 17050 Rev 4
Table 6. Alternate function mapping
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
AF014 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 UART4/5/
USART6
CAN1/CAN2/
TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/
OTG_FS DCMI
PA 0 - W K U P TIM2_CH1
TIM2_ETR TIM 5_CH1 TIM8_ETR USART2_CTS UART4_TX ETH_MII_CRS EVENTOUT
PA1 TIM2_CH2 TIM5_CH2 USART2_RTS UART4_RX ETH_MII _RX_CLK
ETH_RMII _REF_CLK EVENTOUT
PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX ETH_MDIO EVENTOUT
PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX OTG_HS_ULPI_D0 ETH _MII_COL EVENTOUT
PA 4 SPI1_NSS SPI3_NSS
I2S3_WS USART2_CK OTG_HS_SOF DCMI_HSYNC EVENTOUT
PA 5 TIM2_CH1
TIM2_ETR TIM8_CH1N SPI1_SCK OTG_HS_ULPI_CK EVENTOUT
PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN SPI1_MISO TIM13_CH1 DCMI_PIXCK EVENTOUT
PA7 TIM1_CH1N TIM3_CH2 TIM8_CH1N SPI1_MOSI TIM14_CH1 ETH_MII _RX_DV
ETH_RMII _CRS_DV EVENTOUT
PA8 MCO1 TIM1_CH1 I2C3_SCL USART1_CK OTG_FS_SOF EVENTOUT
PA9 TIM1_CH2 I2C3_SMBA USART1_TX DCMI_D0 EVENTOUT
PA10 TIM1_CH3 USART1_RX OTG_FS_ID DCMI_D1 EVENTOUT
PA11 TIM1_CH4 USART1_CTS CAN1_RX OTG_FS_DM EVENTOUT
PA12 TIM1_ETR USART1_RTS CAN1_TX OTG_FS_DP EVENTOUT
PA 1 3 J T M S - S W D I O EVENTOUT
PA14 JTCK-SWCLK EVENTOUT
PA 1 5 J T D I TIM 2_CH1
TIM 2_ETR SPI1_NSS SPI3_NSS
I2S3_WS EVENTOUT
PB0 TIM1_CH2N TIM3_CH3 TIM8_CH2N OTG_HS_ULPI_D1 ETH _MII_RXD2 EVENTOUT
PB1 TIM1_CH3N TIM3_CH4 TIM8_CH3N OTG_HS_ULPI_D2 ETH _MII_RXD3 OTG_HS_INTN EVENTOUT
PB2 EVENTOUT
PB3 JTDO/
TRACESWO
TIM2_CH2 SPI1_SCK
SPI3_SCK
I2S3_SCK EVENTOUT
PB4 JTRST TIM3_CH1 SPI1_MISO SPI3_MISO EVENTOUT
PB5 TIM3_CH2 I2C1_SMBA SPI1_MOSI
SPI3_MOSI
I2S3_SD CAN2_RX OTG_HS_ULPI_D7 ETH _PPS_OUT DCMI_D10 EVENTOUT
PB6 TIM4_CH1 I2C1_SCL USART1_TX CAN2_TX OTG_FS_INTN DCMI_D5 EVENTOUT
PB7 TIM4_CH2 I2C1_SDA USART1_RX FSMC_NL DCMI_VSYNC EVENTOUT
PB8 TIM4_CH3 TIM10_CH1 I2C1_SCL CAN1_RX OTG_FS_SCL ETH _MII_TXD3 SDIO_D4 DCMI_D6 EVENTOUT
PB9 TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS
I2S2_WS CAN1_TX OTG_FS_SDA SDIO_D5 DCMI_D7 EVENTOUT
PB10 TIM2_CH3 I2C2_SCL
SPI2_SCK
I2S2_SCK USART3_TX OTG_HS_ULPI_D3 ETH_ MII_RX_ER OTG_HS_SCL EVENTOUT
PB11 TIM2_CH4 I2C2_SDA USART3_RX OTG_HS_ULPI_D4
ETH _MII_TX_EN
ETH _RMII_TX_EN OTG_HS_SDA EVENTOUT
PB12 TIM1_BKIN I2C2_SMBA SPI2_NSS
I2S2_WS USART3_CK CAN2_RX OTG_HS_ULPI_D5
ETH _MII_TXD0
ETH _RMII_TXD0 OTG_HS_ID EVENTOUT
PB13 TIM1_CH1N SPI2_SCK
I2S2_SCK USART3_CTS CAN2_TX OTG_HS_ULPI_D6
ETH _MII_TXD1
ETH _RMII_TXD1 EVENTOUT
PB14 TIM1_CH2N TIM8_CH2N SPI2_MISO USART3_RTS TIM12_CH1 OTG_HS_DM EVENTOUT
STM32F215xx, STM32F217xx Pinouts and pin description
Doc ID 17050 Rev 4 48/158
PB15 RTC_50Hz TIM1_CH3N TIM8_CH3N SPI2_MOSI
I2S2_SD TIM12_CH2 OTG_HS_DP EVENTOUT
PC0 OTG_HS_ULPI_STP EVENTOUT
PC1 ETH_MDC EVENTOUT
PC2 SPI2_MISO OTG_HS_ULPI_DIR ETH _MII_TXD2 EVENTOUT
PC3 SPI2_MOSI OTG_HS_ULPI_NXT ETH _MII_TX_CLK EVENTOUT
PC4 ETH_MII_RXD0
ETH_RMII_RXD0 EVENTOUT
PC5 ETH _MII_RXD1
ETH _RMII_RXD1 EVENTOUT
PC6 TIM3_CH1 TIM8_CH1 I2S2_MCK USART6_TX SDIO_D6 DCMI_D0 EVENTOUT
PC7 TIM3_CH2 TIM8_CH2 I2S3_SCK USART6_RX SDIO_D7 DCMI_D1 EVENTOUT
PC8 TIM3_CH3 TIM8_CH3 USART6_CK SDIO_D0 DCMI_D2 EVENTOUT
PC9 MCO2 TIM3_CH4 TIM8_CH4 I2C3_SDA I2S2_CKIN I2S3_CKIN SDIO_D1 DCMI_D3 EVENTOUT
PC10 SPI3_SCK
I2S3_SCK USART3_TX UART4_TX SDIO_D2 DCMI_D8 EVENTOUT
PC11 SPI3_MISO USART3_RX UART4_RX SDIO_D3 DCMI_D4 EVENTOUT
PC12 SPI3_MOSI
I2S3_SD USART3_CK UART5_TX SDIO_CK DCMI_D9 EVENTOUT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 CAN1_RX FSMC_D2 EVENTOUT
PD1 CAN1_TX FSMC_D3 EVENTOUT
PD2 TIM3_ETR UART5_RX SDIO_CMD DCMI_D11 EVENTOUT
PD3 USART2_CTS FSMC_CLK EVENTOUT
PD4 USART2_RTS FSMC_NOE EVENTOUT
PD5 USART2_TX FSMC_NWE EVENTOUT
PD6 USART2_RX FSMC_NWAIT EVENTOUT
PD7 USART2_CK FSMC_NE1 EVENTOUT
PD8 USART3_TX FSMC_D13 EVENTOUT
PD9 USART3_RX FSMC_D14 EVENTOUT
PD10 USART3_CK FSMC_D15 EVENTOUT
PD11 USART3_CTS FSMC_A16 EVENTOUT
PD12 TIM4_CH1 USART3_RTS FSMC_A17 EVENTOUT
PD13 TIM4_CH2 FSMC_A18 EVENTOUT
PD14 TIM4_CH3 FSMC_D0 EVENTOUT
Table 6. Alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
AF014 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 UART4/5/
USART6
CAN1/CAN2/
TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/
OTG_FS DCMI
Pinouts and pin description STM32F215xx, STM32F217xx
49/158 Doc ID 17050 Rev 4
PD15 TIM4_CH4 FSMC_D1 EVENTOUT
PE0 TIM4_ETR FSMC_NBL0 DCMI_D2 EVENTOUT
PE1 FSMC_BLN1 DCMI_D3 EVENTOUT
PE2 TRACECLK ETH _MII_TXD3 FSMC_A23 EVENTOUT
PE3 TRACED0 FSMC_A19 EVENTOUT
PE4 TRACED1 FSMC_A20 DCMI_D4 EVENTOUT
PE5 TRACED2 TIM9_CH1 FSMC_A21 DCMI_D6 EVENTOUT
PE6 TRACED3 TIM9_CH2 FSMC_A22 DCMI_D7 EVENTOUT
PE7 TIM1_ETR FSMC_D4 EVENTOUT
PE8 TIM1_CH1N FSMC_D5 EVENTOUT
PE9 TIM1_CH1 FSMC_D6 EVENTOUT
PE10 TIM1_CH2N FSMC_D7 EVENTOUT
PE11 TIM1_CH2 FSMC_D8 EVENTOUT
PE12 TIM1_CH3N FSMC_D9 EVENTOUT
PE13 TIM1_CH3 FSMC_D10 EVENTOUT
PE14 TIM1_CH4 FSMC_D11 EVENTOUT
PE15 TIM1_BKIN FSMC_D12 EVENTOUT
PF0 I2C2_SDA FSMC_A0 EVENTOUT
PF1 I2C2_SCL FSMC_A1 EVENTOUT
PF2 I2C2_SMBA FSMC_A2 EVENTOUT
PF3 FSMC_A3 EVENTOUT
PF4 FSMC_A4 EVENTOUT
PF5 FSMC_A5 EVENTOUT
PF6 TIM10_CH1 FSMC_NIORD EVENTOUT
PF7 TIM11_CH1 FSMC_NREG EVENTOUT
PF8 TIM13_CH1 FSMC_NIOWR EVENTOUT
PF9 TIM14_CH1 FSMC_CD EVENTOUT
PF10 FSMC_INTR EVENTOUT
PF11 DCMI_D12 EVENTOUT
PF12 FSMC_A6 EVENTOUT
PF13 FSMC_A7 EVENTOUT
PF14 FSMC_A8 EVENTOUT
PF15 FSMC_A9 EVENTOUT
Table 6. Alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
AF014 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 UART4/5/
USART6
CAN1/CAN2/
TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/
OTG_FS DCMI
STM32F215xx, STM32F217xx Pinouts and pin description
Doc ID 17050 Rev 4 50/158
PG0 FSMC_A10 EVENTOUT
PG1 FSMC_A11 EVENTOUT
PG2 FSMC_A12 EVENTOUT
PG3 FSMC_A13 EVENTOUT
PG4 FSMC_A14 EVENTOUT
PG5 FSMC_A15 EVENTOUT
PG6 FSMC_INT2 EVENTOUT
PG7 USART6_CK FSMC_INT3 EVENTOUT
PG8 USART6_RTS ETH _PPS_OUT EVENTOUT
PG9 USART6_RX FSMC_NE2 EVENTOUT
PG10 FSMC_NCE4_1 EVENTOUT
PG11 ETH _MII_TX_EN
ETH _RMII_TX_EN FSMC_NCE4_2 EVENTOUT
PG12 USART6_RTS FSMC_NE4 EVENTOUT
PG13 UART6_CTS ETH _MII_TXD0
ETH _RMII_TXD0 FSMC_A24 EVENTOUT
PG14 USART6_TX ETH _MII_TXD1
ETH _RMII_TXD1 FSMC_A25 EVENTOUT
PG15 USART6_CTS DCMI_D13 EVENTOUT
PH0 - OSC_IN
PH1 - OSC_OUT
PH2 ETH _MII_CRS EVENTOUT
PH3 ETH _MII_COL EVENTOUT
PH4 I2C2_SCL OTG_HS_ULPI_NXT EVENTOUT
PH5 I2C2_SDA EVENTOUT
PH6 I2C2_SMBA TIM12_CH1 ETH _MII_RXD2 EVENTOUT
PH7 I2C3_SCL ETH _MII_RXD3 EVENTOUT
PH8 I2C3_SDA DCMI_HSYNC EVENTOUT
PH9 I2C3_SMBA TIM12_CH2 DCMI_D0 EVENTOUT
PH10 TIM5_CH1TIM5_ETR DCMI_D1 EVENTOUT
PH11 TIM5_CH2 DCMI_D2 EVENTOUT
PH12 TIM5_CH3 DCMI_D3 EVENTOUT
PH13 TIM8_CH1N CAN1_TX EVENTOUT
PH14 TIM8_CH2N DCMI_D4 EVENTOUT
PH15 TIM8_CH3N DCMI_D11 EVENTOUT
Table 6. Alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
AF014 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 UART4/5/
USART6
CAN1/CAN2/
TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/
OTG_FS DCMI
Pinouts and pin description STM32F215xx, STM32F217xx
51/158 Doc ID 17050 Rev 4
PI0 TIM5_CH4 SPI2_NSS
I2S2_WS DCMI_D13 EVENTOUT
PI1 SPI2_SCK
I2S2_SCK DCMI_D8 EVENTOUT
PI2 TIM8_CH4 SPI2_MISO DCMI_D9 EVENTOUT
PI3 TIM8_ETR SPI2_MOSI
I2S2_SD DCMI_D10 EVENTOUT
PI4 TIM8_BKIN DCMI_D5 EVENTOUT
PI5 TIM8_CH1 DCMI_VSYNC EVENTOUT
PI6 TIM8_CH2 DCMI_D6 EVENTOUT
PI7 TIM8_CH3 DCMI_D7 EVENTOUT
PI8
PI9 CAN1_RX EVENTOUT
PI10 ETH _MII_RX_ER EVENTOUT
PI11 OTG_HS_ULPI_DIR EVENTOUT
Table 6. Alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
AF014 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 UART4/5/
USART6
CAN1/CAN2/
TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/
OTG_FS DCMI
Memory mapping STM32F215xx, STM32F217xx
52/158 Doc ID 17050 Rev 4
4 Memory mapping
The memory map is shown in Figure 13.
Figure 13. Memory map
512-Mbyte
block 7
Cortex-M3's
internal
peripherals
512-Mbyte
block 6
Not used
512-Mbyte
block 5
FSMC registers
512-Mbyte
block 4
FSMC bank 3
& bank4
512-Mbyte
block 3
FSMC bank1
& bank2
512-Mbyte
block 2
Peripherals
512-Mbyte
block 1
SRAM
0x0000 0000
0x1FFF FFFF
0x2000 0000
0x3FFF FFFF
0x4000 0000
0x5FFF FFFF
0x6000 0000
0x7FFF FFFF
0x8000 0000
0x9FFF FFFF
0xA000 0000
0xBFFF FFFF
0xC000 0000
0xDFFF FFFF
0xE000 0000
0xFFFF FFFF
512-Mbyte
block 0
Code
Flash
0x0810 0000 - 0x0FFF FFFF
0x1FFF 0000 - 0x1FFF 7A0F
0x1FFF C000 - 0x1FFF C007
0x0800 0000
-
0x080F FFFF
0x0001 C000 - 0x07FF FFFF
0x0000 0000 - 0x000F FFFF
System memory
Reserved
Reserved
Aliased to Flash, system
memory or SRAM depending
on the BOOT pins
SRAM (16 KB aliased
by bit-banding)
Reserved
0x2000 0000 - 0x2001 BFFF
0x2001 C000 - 0x2001 FFFF
0x2002 0000 - 0x3FFF FFFF
TIM2
TIM3
0x4000 0000 - 0x4000 03FF
TIM4
TIM5
TIM6
TIM7
Reserved
0x4000 0400 - 0x4000 07FF
0x4000 0800 - 0x4000 0BFF
0x4000 0C00 - 0x4000 0FFF
0x4000 1000 - 0x4000 13FF
0x4000 2000 - 0x4000 23FF
0x4000 2400 - 0x4000 27FF
RTC & BKP registers0x4000 2800 - 0x4000 2BFF
WWDG 0x4000 2C00 - 0x4000 2FFF
IWDG 0x4000 3000 - 0x4000 33FF
Reserved 0x4000 3400 - 0x4000 37FF
SPI2/I2S20x4000 3800 - 0x4000 3BFF
SPI3/I2S3 0x4000 3C00 - 0x4000 3FFF
Reserved
0x4000 4000 - 0x4000 43FF
USART2 0x4000 4400 - 0x4000 47FF
0x4000 4800 - 0x4000 4BFF
USART3
UART4 0x4000 4C00 - 0x4000 4FFF
UART5 0x4000 5000 - 0x4000 53FF
I2C1 0x4000 5400 - 0x4000 57FF
I2C2 0x4000 5800 - 0x4000 5BFF
Reserved
0x4000 6C00 - 0x4000 6FFF
0x4000 7000 - 0x4000 73FF
PWR
0x4000 7400 - 0x4000 77FF
DAC1/DAC2
0x4000 7800 - 0x4000 FFFF
TIM1 / PWM1 0x4001 0000 - 0x4001 03FF
TIM8 / PWM2 0x4001 0400 - 0x4001 07FF
Por t A
USART1 0x4001 1000 - 0x4001 13FF
0x4001 1400 - 0x4001 17FF
Por t B
0x4001 1800 - 0x4001 1FFF
Por t C
0x4001 2000 - 0x4001 23FF
Por t D
0x4001 2400 - 0x4001 27FF
Por t E
0x4001 2800 - 0x4001 2BFF
Por t F
0x4001 2C00 - 0x4001 2FFF
Por t G
0x4001 3000 - 0x4001 33FF
Reserved 0x4001 3400 - 0x4001 37FF
0x4001 3800 - 0x4001 3BFF
0x4001 4000 - 0x4001 43FF
0x4001 4400 - 0x4001 47FF
USART6
0x4001 4800 - 0x4001 4BFF
Reserved
0x4002 000 - 0x4002 03FF
0x4002 0C00 - 0x4002 0FFF
0x4002 1000 - 0x4002 13FF
0x4002 1400 - 0x4002 17FF
Reset clock controller (RCC)
0x4002 1800 - 0x4002 1BFF
Por t H 0x4002 1C00 - 0x4002 1FFF
Flash interface
0x4002 2000 - 0x4002 23FF
Reserved 0x4002 2400 - 0x4002 2FFF
CRC 0x4002 3000 - 0x4002 33FF
Reserved 0x5006 0C00 - 0x5FFF FFFF
FSMC bank1 NOR/PSRAM 1 0x6000 0000 - 0x63FF FFFF
FSMC bank1 NOR/PSRAM 2 0x6400 0000 - 0x67FF FFFF
FSMC bank1 NOR/PSRAM 30x6800 0000 - 0x6BFF FFFF
FSMC bank1 NOR/PSRAM 4 0x6C00 0000 - 0x6FFF FFFF
FSMC bank2 NAND (NAND1) 0x7000 0000 - 0x7FFF FFFF
FSMC bank3 NAND (NAND2) 0x8000 0000 - 0x8FFF FFFF
FSMC bank4 PC Card 0x9000 0000 - 0x9FFF FFFF
FSMC control register 0xA000 0000 - 0xA000 0FFF
Reserved 0xA000 1000 - 0xBFFF FFFF
ai15989
Option Bytes
TIM10
SYSCFG
0x4002 0400 - 0x4002 07FF
0x4002 0800 - 0x4002 0BFF
SDIO
Reserved
Reserved 0x4001 4C00 - 0x4001 FFFF
EXTI 0x4001 3C00 - 0x4001 3FFF
Reserved
BxCAN2
0x4000 6000 - 0x4000 63FF
0x4000 6400 - 0x4000 67FF
0x4000 6800 - 0x4000 6BFF
0x5006 0800 - 0x5006 0FFF
RNG
0x5006 0400 - 0x5006 07FF
HASH
0x5006 0000 - 0x5006 03FF
CRYP
0x5005 0400 - 0x5005 0FFF
Reserved
0x5005 0000 - 0x5005 03FF
DCMI
0x5004 0000 - 0x5004 0FFF
Reserved
0x5000 0000 - 0x5003 FFFF
USB OTG FS
0x4002 9400 - 0x4FFF FFFF
Reserved
0x4004 0000 - 0x4007 FFFF
USB OTG HS
Reserved 0x4002 9400 - 0x4003 FFFF
0x4002 8000 - 0x4002 93FF
ETHERNET
Reserved 0x4002 6800 - 0x4002 7FFF
0x4002 6400 - 0x4002 67FF
0x4002 6000 - 0x4002 63FF
DMA2
DMA1
Reserved 0x4002 5000 - 0x4002 5FFF
0x4002 4000 - 0x4002 4FFF
BKPSRAM
0x4002 3C00 - 0x4002 3FFF
0x4002 3800 - 0x4002 3BFF
Reserved 0x4002 3400 - 0x4002 37FF
Por t I
TIM11
TIM9
SPI1
ADC1 - ADC2 - ADC3
Reserved
BxCAN1
0x4000 5C00 - 0x4000 5FFF
I2C3
Reserved
TIM12
TIM13
TIM14
0x4000 1C00 - 0x4000 1FFF
0x4000 1800 - 0x4000 1BFF
0x4000 1400 - 0x4000 17FF
SRAM (112 KB aliased
by bit-banding)
Reserved
0x1FFF C008 - 0x1FFF FFFF
0x1FFF 7A10 - 0x1FFF 7FFF
Reserved
Reserved
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 53/158
5 Electrical characteristics
5.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
5.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
1.8 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
5.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 14.
5.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 15.
Figure 14. Pin loading conditions Figure 15. Pin input voltage
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Electrical characteristics STM32F215xx, STM32F217xx
54/158 Doc ID 17050 Rev 4
5.1.6 Power supply scheme
Figure 16. Power supply scheme
1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These
capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the
PCB to ensure the good functionality of the device.
2. To connect REGOFF pin, refer to Section 2.2.17: Voltage regulator.
3. The two 2.2 µF ceramic capacitors should not be connected when the voltage regulator is OFF.
4. The 4.7 µF ceramic capacitor must be connected to one of the VDDx pin.
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STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 55/158
5.1.7 Current consumption measurement
Figure 17. Current consumption measurement scheme
5.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics,
Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
ai14126
VBAT
VDD
VDDA
IDD_VBAT
IDD
Table 7. Voltage characteristics
Symbol Ratings Min Max Unit
VDD–VSS External main supply voltage (including VDDA, VDD)(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
–0.3 4.0
V
VIN
Input voltage on five-volt tolerant pin(2)
2. VIN maximum value must always be respected. Refer to Table 8 for the values of the maximum allowed
injected current.
VSS–0.3 VDD+0.4
Input voltage on any other pin VSS–0.3 4.0
|ΔVDDx| Variations between different VDD power pins - 50 mV
|VSSX − VSS| Variations between all the different ground pins - 50
VESD(HBM) Electrostatic discharge voltage (human body model)
see Section 5.3.14:
Absolute maximum
ratings (electrical
sensitivity)
Electrical characteristics STM32F215xx, STM32F217xx
56/158 Doc ID 17050 Rev 4
5.3 Operating conditions
5.3.1 General operating conditions
Table 8. Current characteristics
Symbol Ratings Max. Unit
IVDD Total current into VDD power lines (source)(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
120
mA
IVSS Total current out of VSS ground lines (sink)(1) 120
IIO
Output current sunk by any I/O and control pin 25
Output current source by any I/Os and control pin 25
IINJ(PIN) (2)
2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.20: 12-bit ADC
characteristics.
Injected current on five-volt tolerant I/O(3)
3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 7 for the values of the maximum allowed input voltage.
–5/+0
Injected current on any other pin(4)
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 7 for the values of the maximum allowed input voltage.
±5
ΣIINJ(PIN)(4) Total injected current (sum of all I/O and control pins)(5)
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
±25
Table 9. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C
TJMaximum junction temperature 125 °C
Table 10. General operating conditions
Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency 0 120
MHzfPCLK1 Internal APB1 clock frequency 0 30
fPCLK2 Internal APB2 clock frequency 0 60
VDD Standard operating voltage 1.8 3.6 V
VDDA(1)
Analog operating voltage
(ADC limited to 1 M samples) Must be the same potential as VDD(2)
1.8 3.6
V
Analog operating voltage
(ADC limited to 2 M samples) 2.4 3.6
VBAT Backup operating voltage 1.65 3.6 V
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 57/158
VCAP1 Internal core voltage to be supplied
externally in REGOFF mode 1.1 1.3 V
VCAP2
CEXT Capacitance of external capacitor(3) -2.2µF
ESR ESR of external capacitor(3) 0.1 2 Ω
PD
Power dissipation at TA = 85 °C for
suffix 6 or TA = 105 °C for suffix 7(4)
LQFP64 - 444
mW
LQFP100 - 434
LQFP144 - 500
LQFP176 - 526
UFBGA176 - 513
TA
Ambient temperature for 6 suffix
version
Maximum power dissipation –40 85 °C
Low power dissipation(5) –40 105
Ambient temperature for 7 suffix
version
Maximum power dissipation –40 105 °C
Low power dissipation(5) –40 125
TJ Junction temperature range 6 suffix version –40 105 °C
7 suffix version –40 125
1. When the ADC is used, refer to Table 61: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and power-down operation.
3. This parameter range must be respected for the full application range, taking into account the physical capacitor
characteristics and tolerance.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
5. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.
Table 10. General operating conditions (continued)
Symbol Parameter Conditions Min Max Unit
Table 11. Limitations depending on the operating power supply range
Operating
power
supply
range
ADC
operation
Maximum
Flash
memory
access
frequency
(fFlashmax)
Number of wait
states at
maximum CPU
frequency
(fCPUmax=
120 MHz)(1)
I/O operation
FSMC
controller
operation
Possible
Flash
memory
operations
VDD =1.8 to
2.1 V
Conversion
time up to
1 Msps
16 MHz with
no Flash
memory wait
state
7(2)
– Degraded
speed
performance
– No I/O
compensation
up to 30 MHz
8-bit erase
and program
operations
only
VDD = 2.1 to
2.4 V
Conversion
time up to
1 Msps
18 MHz with
no Flash
memory wait
state
6(2)
– Degraded
speed
performance
– No I/O
compensation
up to 30 MHz
16-bit erase
and program
operations
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VDD = 2.4 to
2.7 V
Conversion
time up to
2Msps
24 MHz with
no Flash
memory wait
state
4(2)
– Degraded
speed
performance
– I/O
compensation
works
up to 48 MHz
16-bit erase
and program
operations
VDD = 2.7 to
3.6 V(3)
Conversion
time up to
2Msps
30 MHz with
no Flash
memory wait
state
3(2)
– Full-speed
operation
– I/O
compensation
works
–up to
60 MHz
when VDD =
3.0 to 3.6 V
–up to
48 MHz
when VDD =
2.7 to 3.0 V
32-bit erase
and program
operations
1. The number of wait states can be reduced by reducing the CPU frequency (see Figure 18).
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state
program execution.
3. The voltage range for OTG USB FS can drop down to 2.7 V. However it is degraded between 2.7 and 3 V.
Table 11. Limitations depending on the operating power supply range
Operating
power
supply
range
ADC
operation
Maximum
Flash
memory
access
frequency
(fFlashmax)
Number of wait
states at
maximum CPU
frequency
(fCPUmax=
120 MHz)(1)
I/O operation
FSMC
controller
operation
Possible
Flash
memory
operations
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Figure 18. Number of wait states versus fCPU and VDD range
5.3.2 VCAP1/VCAP2 external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP1/VCAP2 pins. CEXT is specified in Ta b l e 1 0 .
Figure 19. External capacitor CEXT
1. Legend: ESR is the equivalent series resistance.
AIB
0
1
2
3
4
5
6
7
8
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
88
92
96
100
104
108
112
116
120
Number of Wait states
Fcpu (MHz)
Wait states vs Fcpu and VDD range
1.8 to 2.1V
2.1 to 2.4V
2.4 to 2.7V
2.7 to 3.6V
MS19044V1
ESR
RLeak
C
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5.3.3 Operating conditions at power-up / power-down (regulator ON)
Subject to general operating conditions for TA.
Table 12. Operating conditions at power-up / power-down (regulator ON)
5.3.4 Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for TA.
Table 13. Operating conditions at power-up / power-down (regulator OFF)
Symbol Parameter Min Max Unit
tVDD
VDD rise time rate 20 ∞
µs/V
VDD fall time rate 20 ∞
Symbol Parameter Conditions Min Max Unit
tVDD
VDD rise time rate Power-up 20 ∞
µs/V
VDD fall time rate Power-down 20 ∞
tVCAP
VCAP_1 and VCAP_2 rise
time rate Power-up 20 ∞
VCAP_1 and VCAP_2 fall
time rate Power-down 20 ∞
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5.3.5 Embedded reset and power control block characteristics
The parameters given in Ta b l e 1 4 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Ta b le 1 0 .
Table 14. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
VPVD
Programmable voltage
detector level selection
PLS[2:0]=000 (rising
edge) 2.09 2.14 2.19 V
PLS[2:0]=000 (falling
edge) 1.98 2.04 2.08 V
PLS[2:0]=001 (rising
edge) 2.23 2.30 2.37 V
PLS[2:0]=001 (falling
edge) 2.13 2.19 2.25 V
PLS[2:0]=010 (rising
edge) 2.39 2.45 2.51 V
PLS[2:0]=010 (falling
edge) 2.29 2.35 2.39 V
PLS[2:0]=011 (rising
edge) 2.54 2.60 2.65 V
PLS[2:0]=011 (falling
edge) 2.44 2.51 2.56 V
PLS[2:0]=100 (rising
edge) 2.70 2.76 2.82 V
PLS[2:0]=100 (falling
edge) 2.59 2.66 2.71 V
PLS[2:0]=101 (rising
edge) 2.86 2.93 2.99 V
PLS[2:0]=101 (falling
edge) 2.65 2.84 3.02 V
PLS[2:0]=110 (rising
edge) 2.96 3.03 3.10 V
PLS[2:0]=110 (falling
edge) 2.85 2.93 2.99 V
PLS[2:0]=111 (rising
edge) 3.07 3.14 3.21 V
PLS[2:0]=111 (falling
edge) 2.95 3.03 3.09 V
VPVDhyst(2) PVD hysteresis - 100 - mV
VPOR/PDR
Power-on/power-down
reset threshold
Falling edge TBD(1) 1.70 TBD V
Rising edge TBD 1.74 TBD V
VPDRhyst(2) PDR hysteresis - 40 - mV
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5.3.6 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 17: Current consumption
measurement scheme.
All Run mode current consumption measurements given in this section are performed using
CoreMark code.
VBOR1
Brownout level 1
threshold
Falling edge 2.13 2.19 2.24 V
Rising edge 2.23 2.29 2.33 V
VBOR2
Brownout level 2
threshold
Falling edge 2.44 2.50 2.56 V
Rising edge 2.53 2.59 2.63 V
VBOR3
Brownout level 3
threshold
Falling edge 2.75 2.83 2.88 V
Rising edge 2.85 2.92 2.97
VBORhyst(2) BOR hysteresis - 100 - mV
TRSTTEMPO(2)(3) Reset temporization 0.5 1.5 3.0 ms
IRUSH(2)
InRush current on
voltage regulator
power-on (POR or
wakeup from Standby)
- 160 200 mA
ERUSH(2)
InRush energy on
voltage regulator
power-on (POR or
wakeup from Standby)
VDD = 1.8 V, TA = 105 °C,
IRUSH = 171 mA for 31 µs --5.4µC
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.
3. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant
when first instruction is read by the user application code.
Table 14. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
STM32F215xx, STM32F217xx Electrical characteristics
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Typical and maximum current consumption
The MCU is placed under the following conditions:
●At startup, all I/O pins are configured as analog inputs by firmware.
●All peripherals are disabled except if it is explicitly mentioned.
●The Flash memory access time is adjusted to fHCLK frequency (0 wait state from 0 to
30 MHz, 1 wait state from 30 to 60 MHz, 2 wait states from 60 to 90 MHz and 3 wait
states from 90 to 120 MHz).
●When the peripherals are enabled HCLK is the system clock, fPCLK1 = fHCLK/4, and
fPCLK2 = fHCLK/2, except is explicitly mentioned.
●The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature
(TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Table 15. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled)
Symbol Parameter Conditions fHCLK
Typ Max(1)
Unit
TA = 25 °C TA = 85 °C TA = 105 °C
IDD
Supply current
in Run mode
External clock(2), all
peripherals enabled(3)
120 MHz 61 81 93
mA
90 MHz 48 68 80
60 MHz 33 53 65
30 MHz 18 38 50
25 MHz 14 34 46
16 MHz(4) 10 30 42
8 MHz 6 26 38
4 MHz 4 24 36
2 MHz 3 23 35
External clock(3), all
peripherals disabled
120 MHz 33 54 66
90 MHz 27 47 59
60 MHz 19 39 51
30 MHz 11 31 43
25 MHz 8 28 41
16 MHz(4) 62638
8 MHz 4 24 36
4 MHz 3 23 35
2 MHz 2 23 34
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz.
3. When the ADC is on (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for
the analog part.
4. In this case HCLK = system clock/2.
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Table 16. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled) or RAM (1)
Symbol Parameter Conditions fHCLK
Typ Max(2)
Unit
TA =
25 °C
TA =
85 °C
TA =
105 °C
IDD
Supply current in
Run mode
External clock(3), all
peripherals enabled(4)
120 MHz 49 63 72
mA
90 MHz 38 51 61
60 MHz 26 39 49
30 MHz 14 27 37
25 MHz 11 24 34
16 MHz(5) 82130
8 MHz 5 17 27
4 MHz 3 16 26
2 MHz 2 15 25
External clock(3), all
peripherals disabled
120 MHz 21 34 44
90 MHz 17 30 40
60 MHz 12 25 35
30 MHz 7 20 30
25 MHz 5 18 28
16 MHz(5) 4.0 17.0 27.0
8 MHz 2.5 15.5 25.5
4 MHz 2.0 14.7 24.8
2 MHz 1.6 14.5 24.6
1. Code and data processing running from SRAM1 using boot pins.
2. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
3. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz.
4. When the ADC is on (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for
the analog part.
5. In this case HCLK = system clock/2.
STM32F215xx, STM32F217xx Electrical characteristics
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Figure 20. Typical current consumption vs temperature, Run mode, code with data
processing running from RAM, and peripherals ON
Figure 21. Typical current consumption vs temperature, Run mode, code with data
processing running from RAM, and peripherals OFF
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Figure 22. Typical current consumption vs temperature, Run mode, code with data
processing running from Flash, ART accelerator OFF, peripherals ON
Figure 23. Typical current consumption vs temperature, Run mode, code with data
processing running from Flash, ART accelerator OFF, peripherals OFF
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STM32F215xx, STM32F217xx Electrical characteristics
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Table 17. Typical and maximum current consumption in Sleep mode
Symbol Parameter Conditions fHCLK
Typ Max(1)
Unit
TA = 25 °C TA = 85 °C TA =
105 °C
IDD
Supply current in
Sleep mode
External clock(2),
all peripherals enabled(3)
120 MHz 38 51 61
mA
90 MHz 30 43 53
60 MHz 20 33 43
30 MHz 11 25 35
25 MHz 8 21 31
16 MHz 6 19 29
8 MHz 3.6 17.0 27.0
4 MHz 2.4 15.4 25.3
2 MHz 1.9 14.9 24.7
External clock(2), all
peripherals disabled
120 MHz 8 21 31
90 MHz 7 20 30
60 MHz 5 18 28
30 MHz 3.5 16.0 26.0
25 MHz 2.5 16.0 25.0
16 MHz 2.1 15.1 25.0
8 MHz 1.7 15.0 25.0
4 MHz 1.5 14.6 24.6
2 MHz 1.4 14.2 24.3
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz.
3. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is on (ADON bit is set in the ADC_CR2 register).
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Figure 24. Typical current consumption vs temperature in Sleep mode,
peripherals ON
Figure 25. Typical current consumption vs temperature in Sleep mode,
peripherals OFF
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STM32F215xx, STM32F217xx Electrical characteristics
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Figure 26. Typical current consumption vs temperature in Stop mode
1. All typical and maximum values from table 18 and figure 26 will be reduced over time by up to 50% as part
of ST continuous improvement of test procedures. New versions of the datasheet will be released to reflect
these changes
Table 18. Typical and maximum current consumptions in Stop mode(1)
Symbol Parameter Conditions
Typ Max
Unit
TA = 25 °C TA = 85 °C TA =
105 °C
IDD_STOP
Supply current
in Stop mode
with main
regulator in
Run mode
Flash in Stop mode, low-speed and high-speed
internal RC oscillators and high-speed oscillator
OFF (no independent watchdog)
0.55 11.00 20.00
mA
Flash in Deep power down mode, low-speed
and high-speed internal RC oscillators and
high-speed oscillator OFF (no independent
watchdog)
0.50 11.00 20.00
Supply current
in Stop mode
with main
regulator in
Low Power
mode
Flash in Stop mode, low-speed and high-speed
internal RC oscillators and high-speed oscillator
OFF (no independent watchdog)
0.35 8.00 15.00
Flash in Deep power down mode, low-speed
and high-speed internal RC oscillators and
high-speed oscillator OFF (no independent
watchdog)
0.30 8.00 15.00
1. All typical and maximum values will be further reduced by up to 50% as part of ST continuous improvement of test
procedures. New versions of the datasheet will be released to reflect these changes.
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On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Ta b l e 2 1 . The MCU is placed
under the following conditions:
●At startup, all I/O pins are configured as analog inputs by firmware.
●All peripherals are disabled unless otherwise mentioned
●The given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with one peripheral clocked on (with only the clock applied)
●The code is running from Flash memory and the Flash memory access time is equal to
3 wait states at 120 MHz
●Prefetch and Cache ON
●When the peripherals are enabled, HCLK = 120MHz, fPCLK1 = fHCLK/4, and
fPCLK2 =f
HCLK/2
●The typical values are obtained for VDD = 3.3 V and TA= 25 °C, unless otherwise
specified.
Table 19. Typical and maximum current consumptions in Standby mode
Symbol Parameter Conditions
Typ Max
Unit
TA = 25 °C TA = 85 °C TA = 105 °C
VDD =
1.8 V
VDD=
2.4 V
VDD =
3.3 V VDD = 3.6 V
IDD_STBY
Supply current
in Standby
mode
Backup SRAM ON, RTC ON 4.8 5.2 5.8 15.1(1) 25.8(1)
µA
Backup SRAM OFF, RTC ON 4.2 4.5 5.1 12.4(1) 20.5(1)
Backup SRAM ON, RTC OFF 2.3 2.5 3.2 12.5(1) 24.8(1)
Backup SRAM OFF, RTC OFF 1.6 1.8 2.5 9.8(1) 19.2(1)
1. Based on characterization, not tested in production.
Table 20. Typical and maximum current consumptions in VBAT mode
Symbol Parameter Conditions
Typ Max
Unit
TA = 25 °C TA = 85 °C TA =
105 °C
VDD =
1.8 V
VDD=
2.4 V
VDD =
3.3 V VDD = 3.6 V
IDD_VBAT
Backup
domain supply
current
Backup SRAM ON, RTC ON 3.2 3.4 3.7 12(1) 19(1)
µA
Backup SRAM OFF, low-speed
oscillator and RTC ON 2.6 2.7 3.0 8(1) 10(1)
Backup SRAM ON, RTC OFF 0.7 0.7 0.8 9(1) 16(1)
Backup SRAM OFF, RTC OFF 0.1 0.1 0.1 5(1) 7(1)
1. Based on characterization, not tested in production.
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Table 21. Peripheral current consumption(1)
Peripheral(2) Typical consumption at 25 °C Unit
AHB1
GPIO A 0.45
mA
GPIO B 0.43
GPIO C 0.46
GPIO D 0.44
GPIO E 0.44
GPIO F 0.42
GPIO G 0.44
GPIO H 0.42
GPIO I 0.43
OTG_HS + ULPI 3.64
CRC 1.17
BKPSRAM 0.21
DMA1 2.76
DMA2 2.85
ETH_MAC +
ETH_MAC_TX
ETH_MAC_RX
ETH_MAC_PTP
2.99
AHB2 OTG_FS 3.16
DCMI 0.60
AHB3 FSMC 1.74
AHB2 CRYPTO TBD mA
HASH TBD
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APB1
TIM2 0.61
mA
TIM3 0.49
TIM4 0.54
TIM5 0.62
TIM6 0.20
TIM7 0.20
TIM12 0.36
TIM13 0.28
TIM14 0.25
USART2 0.25
USART3 0.25
UART4 0.25
UART5 0.26
I2C1 0.25
I2C2 0.25
I2C3 0.25
SPI2 0.20/0.10
SPI3 0.18/0.09
CAN1 0.31
CAN2 0.30
DAC channel 1(3) 1.11
DAC channel 1(4) 1.11
PWR 0.15
WWDG 0.15
Table 21. Peripheral current consumption(1) (continued)
Peripheral(2) Typical consumption at 25 °C Unit
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5.3.7 Wakeup time from low-power mode
The wakeup times given in Ta bl e 2 2 is measured on a wakeup phase with a 16 MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
●Stop or Standby mode: the clock source is the RC oscillator
●Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Ta b l e 1 0 .
APB2
SDIO 0.69
mA
TIM1 1.06
TIM8 1.03
TIM9 0.58
TIM10 0.37
TIM11 0.39
ADC1(5) 2.13
ADC2(5) 2.04
ADC3(5) 2.12
SPI1 1.20
USART1 0.38
USART6 0.37
1. TBD stands for “to be defined”.
2. External clock is 25 MHz (HSE oscillator with 25 MHz crystal) and PLL is on.
3. EN1 bit is set in DAC_CR register.
4. EN2 bit is set in DAC_CR register.
5. fADC = fPCLK2/2, ADON bit set in ADC_CR2 register.
Table 21. Peripheral current consumption(1) (continued)
Peripheral(2) Typical consumption at 25 °C Unit
Table 22. Low-power mode wakeup timings
Symbol Parameter Min(1) Typ(1) Max(1) Unit
tWUSLEEP(2) Wakeup from Sleep mode - 1 - µs
tWUSTOP(2)
Wakeup from Stop mode (regulator in Run mode) - 13 -
µs
Wakeup from Stop mode (regulator in low power mode) - 17 40
Wakeup from Stop mode (regulator in low power mode
and Flash memory in Deep power down mode) -110-
tWUSTDBY(2)(3) Wakeup from Standby mode 260 375 480 µs
1. Based on characterization, not tested in production.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
3. tWUSTDBY minimum and maximum values are given at 105 °C and –45 °C, respectively.
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5.3.8 External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Tabl e 2 3 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Ta b l e 1 0 .
Low-speed external user clock generated from an external source
The characteristics given in Tabl e 2 4 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Ta b l e 1 0 .
Table 23. High-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fHSE_ext
External user clock source
frequency(1) 1826MHz
VHSEH OSC_IN input pin high level voltage 0.7VDD -V
DD V
VHSEL OSC_IN input pin low level voltage VSS -0.3V
DD
tw(HSE)
tw(HSE)
OSC_IN high or low time(1)
1. Guaranteed by design, not tested in production.
5--
ns
tr(HSE)
tf(HSE)
OSC_IN rise or fall time(1) --20
Cin(HSE) OSC_IN input capacitance(1) -5-pF
DuCy(HSE) Duty cycle 45 - 55 %
ILOSC_IN Input leakage current VSS ≤VIN ≤VDD --±1µA
Table 24. Low-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fLSE_ext
User External clock source
frequency(1)
1. Guaranteed by design, not tested in production.
- 32.768 1000 kHz
VLSEH
OSC32_IN input pin high level
voltage 0.7VDD -V
DD
V
VLSEL
OSC32_IN input pin low level
voltage VSS -0.3V
DD
tw(LSE)
tf(LSE)
OSC32_IN high or low time(1) 450 - -
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1) --50
Cin(LSE) OSC32_IN input capacitance(1) -5-pF
DuCy(LSE) Duty cycle 30 - 70 %
ILOSC32_IN Input leakage current VSS ≤VIN ≤VDD --±1µA
STM32F215xx, STM32F217xx Electrical characteristics
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Figure 27. High-speed external clock source AC timing diagram
Figure 28. Low-speed external clock source AC timing diagram
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Ta b l e 2 5 . In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
ai17528
OSC_IN
External
STM32F
clock source
VHSEH
tf(HSE) tW(HSE)
IL
90%
10%
THSE
t
tr(HSE) tW(HSE)
fHSE_ext
VHSEL
ai17529
OSC32_IN
External
STM32F
clock source
VLSEH
tf(LSE) tW(LSE)
IL
90%
10%
TLSE
t
tr(LSE) tW(LSE)
fLSE_ext
VLSEL
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For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 29). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
Figure 29. Typical application with an 8 MHz crystal
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Ta b l e 2 6 . In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 25. HSE 4-26 MHz oscillator characteristics(1) (2)
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit
fOSC_IN Oscillator frequency 4 - 26 MHz
RFFeedback resistor - 200 - kΩ
C
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
RS = 30 Ω -15-pF
i2HSE driving current VDD = 3.3 V, VIN =V
SS
with 30 pF load --1mA
gmOscillator transconductance Startup 5 - - mA/V
tSU(HSE(4)
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
Startup time VDD is stabilized - 2 - ms
ai17530
OSC_OUT
OSC_IN fHSE
CL1
RF
STM32F
8 MHz
resonator
Resonator with
integrated capacitors
Bias
controlled
gain
REXT(1)
CL2
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 77/158
Note: For CL1 and CL2 it is recommended to use high-quality external ceramic capacitors in the
5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see
Figure 30). CL1 and CL2, are usually the same size. The crystal manufacturer typically
specifies a load capacitance which is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where
Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL
≤
7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF,
then CL1 = CL2 = 8 pF.
Figure 30. Typical application with a 32.768 kHz crystal
Table 26. LSE oscillator characteristics (fLSE = 32.768 kHz) (1)
1. Based on characterization, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit
RFFeedback resistor - 18.4 - MΩ
C(2)
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details
RS = 30 kΩ- - 15 pF
I2LSE driving current VDD = 3.3 V, VIN = VSS --3.5µA
gmOscillator Transconductance 7 - - µA/V
tSU(LSE)(4)
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer
startup time VDD is stabilized - 2 - s
ai17531
OSC32_OUT
OSC32_IN fLSE
CL1
RF
STM32F
32.768 kHz
resonator
Resonator with
integrated capacitors
Bias
controlled
gain
CL2
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5.3.9 Internal clock source characteristics
The parameters given in Ta b l e 2 7 and Ta bl e 2 8 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Ta bl e 1 0 .
High-speed internal (HSI) RC oscillator
Figure 31. ACCHSI versus temperature
Table 27. HSI oscillator characteristics (1)
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fHSI Frequency - 16 - MHz
ACCHSI
Accuracy of the HSI
oscillator
User-trimmed with the RCC_CR
register(2)
2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the
ST website www.st.com.
--1%
Factory-
calibrated
TA = –40 to 105 °C –8 - 4.5 %
TA = –10 to 85 °C –4 - 4 %
TA = 25 °C –1 - 1 %
tsu(HSI)(3)
3. Guaranteed by design, not tested in production.
HSI oscillator
startup time -2.24µs
IDD(HSI)
HSI oscillator
power consumption -6080µA
-36
-8
-6
-4
-2
0
2
4
6
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
N
ormalized deviation (%
)
T
emperature (°
C)
max
avg
min
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 79/158
Low-speed internal (LSI) RC oscillator
Figure 32. ACCLSI versus temperature
5.3.10 PLL characteristics
The parameters given in Ta b l e 2 9 and Ta bl e 3 0 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Ta b le 1 0 .
Table 28. LSI oscillator characteristics (1)
1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Min Typ Max Unit
fLSI(2)
2. Based on characterization, not tested in production.
Frequency 17 32 47 kHz
tsu(LSI)(3)
3. Guaranteed by design, not tested in production.
LSI oscillator startup time - 15 40 µs
IDD(LSI)(3) LSI oscillator power consumption - 0.4 0.6 µA
-36
.ORMALIZEDDEVIATI ON
4E M P E R AT U R E #
MAX
AVG
MIN
Table 29. Main PLL characteristics
Symbol Parameter Conditions Min Typ Max Unit
fPLL_IN PLL input clock(1) 0.95
(2) 12.10
(2) MHz
fPLL_OUT PLL multiplier output clock 24 - 120 MHz
fPLL48_OUT
48 MHz PLL multiplier output
clock --48MHz
fVCO_OUT PLL VCO output 192 - 432 MHz
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tLOCK PLL lock time VCO freq = 192 MHz 75 - 200 µs
VCO freq = 432 MHz 100 - 300
Jitter(3)
Cycle-to-cycle jitter
System clock
120 MHz
RMS - 25 -
ps
peak
to
peak
-±150 -
Period Jitter
RMS - 15 -
peak
to
peak
-±200 -
Main clock output (MCO) for
Ethernet
Cycle to cycle at 50 MHz
on 1000 samples -32-
Main clock output (MCO) for
OTG FS
Cycle to cycle at 25 MHz
on 1000 samples -40-
Bit Time CAN jitter Cycle to cycle at 1 MHz
on 1000 samples -330-
IDD(PLL)(4) PLL power consumption on VDD VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45 -0.40
0.75 mA
IDDA(PLL)(4) PLL power consumption on
VDDA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55 -0.40
0.85 mA
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design, not tested in production.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Based on characterization, not tested in production.
Table 29. Main PLL characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 30. PLLI2S (audio PLL) characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fPLLI2S_IN PLLI2S input clock(2) 0.95(3) 12.1
(3) MHz
fPLLI2S_OUT PLLI2S multiplier output clock - - 216 MHz
fVCO_OUT PLLI2S VCO output 192 - 432 MHz
tLOCK PLLI2S lock time VCO freq = 192 MHz 75 - 200 µs
VCO freq = 432 MHz 100 - 300
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Doc ID 17050 Rev 4 81/158
Jitter(4)
Cycle-to-cycle jitter
System clock
120 MHz
RMS - 25 -
ps
peak
to
peak
-±150 -
Period Jitter
RMS - 15 -
peak
to
peak
-±200 -
Clock output on MCO pin (for
Ethernet applications) 50 MHz - TBD -
Clock output on MCO pin (for
OTG FS applications) 25 MHz - TBD -
Jitter(5)
Master I2S clock jitter
Cycle to cycle at
12,343 MHz on
48KHz period,
N=432, P=4, R=5
RMS - 90 -
peak
to
peak
- ±280 - ps
Average frequency of
12,343 MHz
N=432, P=4, R=5
on 256 samples
TBD - TBD ps
WS I2S clock jitter Cycle to cycle at 48 KHz
on 1000 samples -400-ps
IDD(PLLI2S)(6) PLLI2S power consumption on
VDD
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45 -0.40
0.75 mA
IDDA(PLLI2S)(6) PLLI2S power consumption on
VDDA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55 -0.40
0.85 mA
1. TBD stands for “to be defined”.
2. Take care of using the appropriate division factor M to have the specified PLL input clock values.
3. Guaranteed by design, not tested in production.
4. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
5. Value given with main PLL running.
6. Based on characterization, not tested in production.
Table 30. PLLI2S (audio PLL) characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
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82/158 Doc ID 17050 Rev 4
5.3.11 PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 37: EMI characteristics). It is available only on the main PLL.
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
Figure 33 and Figure 34 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is fPLL_OUT nominal.
Tmode is the modulation period.
md is the modulation depth.
Table 31. SSCG parameters constraint
Symbol Parameter Min Typ Max(1) Unit
fMod Modulation frequency - - 10 KHz
md Peak modulation depth 0.5 - 2 dec
MODEPER * INCSTEP - - 215−1dec
1. Guaranteed by design, not tested in production.
MODEPER round fPLL_IN 4f
Mod
×()⁄[]=
INCSTEP round 215 1–()md fVCO_OUT
××()100 5×MODEPER×()⁄[]=
mdquantized% MODEPER INCSTEP×100×5×()215 1–()fVCO_OUT
×()⁄=
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 83/158
Figure 33. PLL output clock waveforms in center spread mode
Figure 34. PLL output clock waveforms in down spread mode
5.3.12 Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
&REQUENCY0,,?/54
4IME
&
TMODE TMODE
MD
AI
MD
&REQUENCY0,,?/54
4IME
&
TMODE TMODE
MD
AI
Table 32. Flash memory characteristics(1)
1. TBD stands for “to be defined”.
Symbol Parameter Conditions Min Max Unit
IDD Supply current
Read mode
fHCLK = 120 MHz with 3 wait states,
VDD = 3.3 V
-100mA
Write / Erase modes
fHCLK = 120 MHz, VDD = 3.3 V -TBDmA
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Table 33. Flash memory programming(1)
1. TBD stands for “to be defined”.
Symbol Parameter Conditions Min(2) Typ Max(2)
2. Based on characterization, not tested in production.
Unit
tprog Word programming time Program/erase parallelism
(PSIZE) = x 8/16/32 -16100
(3)
3. The maximum programming time is measured after 100K erase operations.
µs
tERASE16KB Sector (16 KB) erase time
Program/erase parallelism
(PSIZE) = x 8 - 400 800
ms
Program/erase parallelism
(PSIZE) = x 16 - 300 600
Program/erase parallelism
(PSIZE) = x 32 - 250 500
tERASE64KB Sector (64 KB) erase time
Program/erase parallelism
(PSIZE) = x 8 - 1200 2400
ms
Program/erase parallelism
(PSIZE) = x 16 - 700 1400
Program/erase parallelism
(PSIZE) = x 32 - 550 1100
tERASE128KB Sector (128 KB) erase time
Program/erase parallelism
(PSIZE) = x 8 -24
s
Program/erase parallelism
(PSIZE) = x 16 -1.32.6
Program/erase parallelism
(PSIZE) = x 32 -12
tME Mass erase time
Program/erase parallelism
(PSIZE) = x 8 -16TBD
s
Program/erase parallelism
(PSIZE) = x 16 -11TBD
Program/erase parallelism
(PSIZE) = x 32 -8TBD
Vprog Programming voltage
32-bit program operation 2.7 - 3.6 V
16-bit program operation 2.1 - 3.6 V
8-bit program operation 1.8 - 3.6 V
STM32F215xx, STM32F217xx Electrical characteristics
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Table 35. Flash memory endurance and data retention
5.3.13 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
●FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
Table 34. Flash memory programming with VPP(1)
1. TBD stands for “to be defined”.
Symbol Parameter Conditions Min(2) Typ Max(2)
2. Guaranteed by design, not tested in production.
Unit
tprog Double word programming
TA = 0 to +40 °C
- 16 100(3)
3. The maximum programming time is measured after 100K erase operations.
µs
tERASE16KB Sector (16 KB) erase time - TBD -
tERASE64KB Sector (64 KB) erase time - TBD -
tERASE128KB Sector (128 KB) erase time - TBD -
tME Mass erase time - 6.8 -
Vprog Programming voltage 2.7 - 3.6 V
VPP VPP voltage range 7 - 9 V
IPP
Minimum current sunk on
the VPP pin 10 - - mA
tVPP(4)
4. VPP should only be connected during programming/erasing.
Cumulative time during
which VPP is applied - - 1 hour
Symbol Parameter Conditions
Value
Unit
Min(1)
1. Based on characterization, not tested in production.
NEND Endurance TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions) 10 kcycles
tRET Data retention
1 kcycle(2) at TA = 85 °C
2. Cycling performed over the whole temperature range.
30
Years1 kcycle(2) at TA = 105 °C 10
10 kcycles(2) at TA = 55 °C 20
Electrical characteristics STM32F215xx, STM32F217xx
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A device reset allows normal operations to be resumed.
The test results are given in Tab l e 3 6 . They are based on the EMS levels and classes
defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●Corrupted program counter
●Unexpected reset
●Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC® code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 36. EMS characteristics
Symbol Parameter Conditions Level/
Class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VDD = 3.3 V, LQFP100, TA = +25 °C,
fHCLK = 75 MHz, conforms to
IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP100, TA = +25 °C,
fHCLK = 75 MHz, conforms to
IEC 61000-4-2
4A
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5.3.14 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●A supply overvoltage is applied to each power supply pin
●A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 37. EMI characteristics(1)
Symbol Parameter Conditions Monitored
frequency band
Max vs. [fHSE/fHCLK]
Unit
8/48 MHz 8/72 MHz
SEMI Peak level
VDD = 3.3 V, TA = 25 °C,
120 MHz, code running
from Flash with prefetch
and cache enabled
0.1 to 30 MHz TBD TBD
dBµV30 to 130 MHz TBD TBD
130 MHz to 1GHz TBD TBD
SAE EMI Level 4 4 -
VDD = 3.3 V, TA = 25 °C,
120 MHz, code running
from Flash with prefetch
and cache enabled, and
PLL spread spectrum
enabled
TBD TBD dBµV
1. TBD stands for “to be defined”.
Table 38. ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum
value(1) Unit
VESD(HBM)
Electrostatic discharge
voltage (human body
model)
TA = +25 °C conforming to JESD22-A114 2 2000(2)
V
VESD(CDM)
Electrostatic discharge
voltage (charge device
model)
TA = +25 °C conforming to JESD22-C101 II 500
1. Based on characterization results, not tested in production.
2. On VBAT pin, VESD(HBM) is limited to 1000 V.
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5.3.15 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of spec current injection on adjacent pins or other functional failure (for
example reset, oscillator frequency deviation).
The test results are given in Tab l e 4 0 .
Table 39. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II level A
Table 40. I/O current injection susceptibility
Symbol Description
Functional susceptibility
Unit
Negative
injection
Positive
injection
IINJ
Injected current on all FT pins –5 +0 mA
Injected current on any other pin –5 +5
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5.3.16 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Ta b l e 4 1 are derived from tests
performed under the conditions summarized in Ta b l e 1 0 . All I/Os are CMOS and TTL
compliant.
Table 41. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL Input low level voltage
TTL ports
2.7 V ≤VDD ≤ 3.6 V
VSS–0.3 - 0.8
V
VIH(1) TT(2) I/O input high level voltage 2.0 - VDD+0.3
FT(3) I/O input high level voltage 2.0 - 5.5
VIL Input low level voltage
CMOS ports
1.8 V ≤VDD ≤ 3.6 V
VSS–0.3 - 0.3VDD
VIH(1)
TT I/O input high level voltage
0.7VDD
-3.6
(4)
FT I/O input high level voltage
-5.2
(4)
CMOS ports
2.0 V ≤VDD ≤ 3.6 V
-5.5
(4)
Vhys
I/O Schmitt trigger voltage hysteresis(5) -200-
mV
IO FT Schmitt trigger voltage
hysteresis(5) 5% VDD(4) - -
Ilkg
I/O input leakage current (6) VSS ≤VIN ≤ VDD --±1µA
I/O FT input leakage current (6) VIN = 5V - - 3
RPU
Weak pull-up equivalent
resistor(7)
All pins
except for
PA10 and
PB12 VIN = VSS
30 40 50
kΩ
PA10 and
PB12 81115
RPD
Weak pull-down
equivalent resistor
All pins
except for
PA10 and
PB12 VIN = VDD
30 40 50
PA10 and
PB12 81115
CIO(8) I/O pin capacitance 5 pF
1. If VIH maximum value cannot be respected, the injection current must be limited externally to IINJ(PIN) maximum value.
2. TT = 3.6 V tolerant.
3. FT = 5 V tolerant.
4. With a minimum of 100 mV.
5. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
6. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.
7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
8. Guaranteed by design, not tested in production.
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All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters.
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source ±20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
●The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Ta b le 8 ).
●The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Ta b l e 8 ).
Output voltage levels
Unless otherwise specified, the parameters given in Ta b l e 4 2 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Ta bl e 1 0 . All I/Os are CMOS and TTL compliant.
Table 42. Output voltage characteristics(1)
1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited
amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed
should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current
source (e.g. to drive an LED).
Symbol Parameter Conditions Min Max Unit
VOL(2)
2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
Output low level voltage for an I/O pin
when 8 pins are sunk at same time TTL port
IIO = +8 mA
2.7 V < VDD < 3.6 V
-0.4
V
VOH(3)
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
Output high level voltage for an I/O pin
when 8 pins are sourced at same time VDD–0.4 -
VOL (2) Output low level voltage for an I/O pin
when 8 pins are sunk at same time CMOS port
IIO =+ 8mA
2.7 V < VDD < 3.6 V
-0.4
V
VOH (3) Output high level voltage for an I/O pin
when 8 pins are sourced at same time 2.4 -
VOL(2)(4)
4. Based on characterization data, not tested in production.
Output low level voltage for an I/O pin
when 8 pins are sunk at same time IIO = +20 mA
2.7 V < VDD < 3.6 V
-1.3
V
VOH(3)(4) Output high level voltage for an I/O pin
when 8 pins are sourced at same time VDD–1.3 -
VOL(2)(4) Output low level voltage for an I/O pin
when 8 pins are sunk at same time IIO = +6 mA
2 V < VDD < 2.7 V
-0.4
V
VOH(3)(4) Output high level voltage for an I/O pin
when 8 pins are sourced at same time VDD–0.4 -
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 91/158
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 35 and
Ta bl e 4 3 , respectively.
Unless otherwise specified, the parameters given in Ta b l e 4 3 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Ta b l e 1 0 .
Table 43. I/O AC characteristics(1)(2)
OSPEEDRy
[1:0] bit
value(1)
Symbol Parameter Conditions Min Typ Max Unit
00
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDD > 2.70 V - - 2
MHz
CL = 50 pF, VDD > 1.8 V - - 2
CL = 10 pF, VDD > 2.70 V - - TBD
CL = 10 pF, VDD > 1.8 V - - TBD
tf(IO)out
Output high to low level fall
time CL = 50 pF, VDD = 1.8 V to
3.6 V
--TBD
ns
tr(IO)out
Output low to high level rise
time --TBD
01
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDD > 2.70 V - - 25
MHz
CL = 50 pF, VDD > 1.8 V - - 12.5(4)
CL = 10 pF, VDD > 2.70 V - - 50(4)
CL = 10 pF, VDD > 1.8 V - - TBD
tf(IO)out
Output high to low level fall
time
CL = 50 pF, VDD < 2.7 V - - TBD
ns
CL = 10 pF, VDD > 2.7 V - - TBD
tr(IO)out
Output low to high level rise
time
CL = 50 pF, VDD < 2.7 V - - TBD
CL = 10 pF, VDD > 2.7 V - - TBD
10
fmax(IO)out Maximum frequency(3)
CL = 40 pF, VDD > 2.70 V - - 50(4)
MHz
CL = 40 pF, VDD > 1.8 V - - 25
CL = 10 pF, VDD > 2.70 V - - 100(4)
CL = 10 pF, VDD > 1.8 V - - TBD
tf(IO)out
Output high to low level fall
time
CL = 50 pF, 2.4 < VDD < 2.7 V - - TBD
nsCL = 10 pF, VDD > 2.7 V - - TBD
tr(IO)out
Output low to high level rise
time
CL = 50 pF, 2.4 < VDD < 2.7 V - - TBD
CL = 10 pF, VDD > 2.7 V - - TBD
Electrical characteristics STM32F215xx, STM32F217xx
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Figure 35. I/O AC characteristics definition
11
Fmax(IO)out Maximum frequency(3)
CL = 30 pF, VDD > 2.70 V - - 100(4)
MHz
CL = 30 pF, VDD > 1.8 V - - 50(4)
CL = 10 pF, VDD > 2.70 V - - 200(4)
CL = 10 pF, VDD > 1.8 V - - TBD
tf(IO)out
Output high to low level fall
time
CL = 20 pF, 2.4 < VDD < 2.7 V - - TBD
ns
CL = 10 pF, VDD > 2.7 V - - TBD
tr(IO)out
Output low to high level rise
time
CL = 20 pF, 2.4 < VDD < 2.7 V - - TBD
CL = 10 pF, VDD > 2.7 V - - TBD
-t
EXTIpw
Pulse width of external signals
detected by the EXTI
controller
10 - - ns
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F20/21xxx reference manual for a
description of the GPIOx_SPEEDR GPIO port output speed register.
2. TBD stands for “to be defined”.
3. The maximum frequency is defined in Figure 35.
4. For maximum frequencies above 50 MHz, the compensation cell should be used.
Table 43. I/O AC characteristics(1)(2) (continued)
OSPEEDRy
[1:0] bit
value(1)
Symbol Parameter Conditions Min Typ Max Unit
ai14131
10%
90%
50%
tr(IO)out
OUTPUT
EXTERNAL
ON 50pF
Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%)
10 %
50%
90%
when loaded by 50pF
T
tr(IO)out
STM32F215xx, STM32F217xx Electrical characteristics
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5.3.17 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Ta b l e 4 1 ).
Unless otherwise specified, the parameters given in Ta b l e 4 4 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Ta b l e 1 0 .
Figure 36. Recommended NRST pin protection
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 44. Otherwise the reset is not taken into account by the device.
Table 44. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL(NRST)(1)
1. Guaranteed by design, not tested in production.
NRST Input low level voltage –0.5 - 0.8 V
VIH(NRST)(1) NRST Input high level voltage 2 - VDD+0.5
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis - 200 - mV
RPU Weak pull-up equivalent resistor(2)
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
VIN = VSS 30 40 50 kΩ
VF(NRST)(1) NRST Input filtered pulse - - 100 ns
VNF(NRST)(1) NRST Input not filtered pulse VDD > 2.7 V 300 - - ns
TNRST_OUT Generated reset pulse duration Internal
Reset source 20 - - µs
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Electrical characteristics STM32F215xx, STM32F217xx
94/158 Doc ID 17050 Rev 4
5.3.18 TIM timer characteristics
The parameters given in Ta b l e 4 5 and Ta b l e 4 6 are guaranteed by design.
Refer to Section 5.3.16: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 45. Characteristics of TIMx connected to the APB1 domain(1)
1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers.
Symbol Parameter Conditions Min Max Unit
tres(TIM) Timer resolution time
AHB/APB1
prescaler distinct
from 1, fTIMxCLK =
60 MHz
1-
tTIMxCLK
16.7 - ns
AHB/APB1
prescaler = 1,
fTIMxCLK = 30 MHz
1-
tTIMxCLK
33.3 - ns
fEXT Timer external clock
frequency on CH1 to CH4
fTIMxCLK = 60 MHz
APB1= 30 MHz
0fTIMxCLK/2 MHz
030MHz
ResTIM Timer resolution - 16/32 bit
tCOUNTER
16-bit counter clock period
when internal clock is
selected
1 65536 tTIMxCLK
0.0167 1092 µs
32-bit counter clock period
when internal clock is
selected
1-
tTIMxCLK
0.0167 71582788 µs
tMAX_COUNT Maximum possible count - 65536 × 65536 tTIMxCLK
-71.6 s
STM32F215xx, STM32F217xx Electrical characteristics
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5.3.19 Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Ta b l e 4 7 are derived from tests
performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage
conditions summarized in Ta b l e 1 0 .
The STM32F21x and STM32F215xx I2C interface meets the requirements of the standard
I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present.
The I2C characteristics are described in Ta b l e 4 7 . Refer also to Section 5.3.16: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 46. Characteristics of TIMx connected to the APB2 domain(1)
1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers.
Symbol Parameter Conditions Min Max Unit
tres(TIM) Timer resolution time
AHB/APB2
prescaler distinct
from 1, fTIMxCLK =
120 MHz
1-
tTIMxCLK
8.3 - ns
AHB/APB2
prescaler = 1,
fTIMxCLK = 60 MHz
1-
tTIMxCLK
16.7 - ns
fEXT Timer external clock
frequency on CH1 to CH4
fTIMxCLK = 120 MHz
APB2 = 60 MHz
0fTIMxCLK/2 MHz
060MHz
ResTIM Timer resolution - 16 bit
tCOUNTER
16-bit counter clock period
when internal clock is
selected
1 65536 tTIMxCLK
0.0083 546 µs
tMAX_COUNT Maximum possible count - 65536 × 65536 tTIMxCLK
- 35.79 s
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Table 47. I2C characteristics
Symbol Parameter
Standard mode I2C(1)
1. Guaranteed by design, not tested in production.
Fast mode I2C(1)(2)
2. fPCLK1 must be higher than 4 MHz to achieve the fast mode I2C frequency. It must be higher than 4 MHz to
achieve the maximum fast mode I2C frequency.
Unit
Min Max Min Max
tw(SCLL) SCL clock low time 4.7 - 1.3 - µs
tw(SCLH) SCL clock high time 4.0 - 0.6 -
tsu(SDA) SDA setup time 250 - 100 -
ns
th(SDA) SDA data hold time 0(3)
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
-0
(4)
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time - 1000 20 + 0.1Cb300
tf(SDA)
tf(SCL)
SDA and SCL fall time - 300 - 300
th(STA) Start condition hold time 4.0 - 0.6 -
µs
tsu(STA)
Repeated Start condition
setup time 4.7 - 0.6 -
tsu(STO) Stop condition setup time 4.0 - 0.6 - μs
tw(STO:STA)
Stop to Start condition time
(bus free) 4.7 - 1.3 - μs
Cb
Capacitive load for each bus
line - 400 - 400 pF
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 97/158
Figure 37. I2C bus AC waveforms and measurement circuit
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 48. SCL frequency (fPCLK1= 30 MHz.,VDD = 3.3 V)(1)(2)
1. RP = External pull-up resistance, fSCL = I2C speed,
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external
components used to design the application.
fSCL (kHz)
I2C_CCR value
RP = 4.7 kΩ
400 0x8019
300 0x8021
200 0x8032
100 0x0096
50 0x012C
20 0x02EE
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Electrical characteristics STM32F215xx, STM32F217xx
98/158 Doc ID 17050 Rev 4
I2S - SPI interface characteristics
Unless otherwise specified, the parameters given in Ta b l e 4 9 for SPI or in Ta b le 5 0 for I2S
are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Ta bl e 1 0 .
Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 49. SPI characteristics(1)(2)
1. Remapped SPI1 characteristics to be determined.
2. TBD stands for “to be defined”.
Symbol Parameter Conditions Min Max Unit
fSCK
1/tc(SCK)
SPI clock frequency Master mode - 30 MHz
Slave mode - 30
tr(SCL)
tf(SCL)
SPI clock rise and fall
time Capacitive load: C = 30 pF - 8 ns
DuCy(SCK) SPI slave input clock
duty cycle Slave mode 30 70 %
tsu(NSS)(3)
3. Based on characterization, not tested in production.
NSS setup time Slave mode 4 tPCLK -
ns
th(NSS)(3) NSS hold time Slave mode 2 tPCLK -
tw(SCLH)(3)
tw(SCLL)(3) SCK high and low time Master mode, fPCLK = 30 MHz,
presc = 4 TBD TBD
tsu(MI) (3)
tsu(SI)(3) Data input setup time Master mode 5 -
Slave mode 5 -
th(MI) (3)
th(SI)(3) Data input hold time Master mode 5 -
Slave mode 4 -
ta(SO)(3)(4)
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access
time Slave mode, fPCLK = 20 MHz 0 3 tPCLK
tdis(SO)(3)(5)
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable
time Slave mode 2 10
tv(SO) (3)(1) Data output valid time Slave mode (after enable edge) - 25
tv(MO)(3)(1) Data output valid time Master mode (after enable edge) - 5
th(SO)(3)
Data output hold time Slave mode (after enable edge) 15 -
th(MO)(3) Master mode (after enable edge) 2 -
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 99/158
Figure 38. SPI timing diagram - slave mode and CPHA = 0
Figure 39. SPI timing diagram - slave mode and CPHA = 1(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
ai14134c
SCK Input
CPHA= 0
MOSI
INPUT
MISO
OUT P UT
CPHA= 0
MS B O U T
MSB IN
BI T6 O U T
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
NSS input
tSU(NSS)
tc(SCK)
th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK)
tdis(SO)
tsu(SI)
th(SI)
ai14135
SCK Input
CPHA=1
MOSI
INPUT
MISO
OUT P UT
CPHA=1
MS B O U T
MSB IN
BI T6 O U T
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
tSU(NSS) tc(SCK) th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK)
tdis(SO)
tsu(SI) th(SI)
NSS input
Electrical characteristics STM32F215xx, STM32F217xx
100/158 Doc ID 17050 Rev 4
Figure 40. SPI timing diagram - master mode(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
ai14136
SCK Input
CPHA= 0
MOSI
OUTUT
MISO
INP UT
CPHA= 0
MS BIN
M SB OUT
BI T6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
B IT1 OUT
NSS input
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(MI)
High
SCK Input
CPHA=1
CPHA=1
CPOL=0
CPOL=1
tsu(MI)
tv(MO) th(MO)
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 101/158
Table 50. I2S characteristics(1)
1. TBD stands for “to be defined”.
Symbol Parameter Conditions Min Max Unit
fCK
1/tc(CK)
I2S clock frequency Master TBD TBD MHz
Slave 0 TBD
tr(CK)
tf(CK)
I2S clock rise and fall time capacitive load
CL= 50 pF - TBD
ns
tv(WS) (2)
2. Based on design simulation and/or characterization results, not tested in production.
WS valid time Master TBD -
th(WS) (2) WS hold time Master TBD -
tsu(WS) (2) WS setup time Slave TBD -
th(WS) (2) WS hold time Slave TBD -
tw(CKH) (2)
tw(CKL) (2) CK high and low time Master fPCLK= TBD,
presc = TBD TBD -
tsu(SD_MR) (2)
tsu(SD_SR) (2) Data input setup time Master receiver
Slave receiver
TBD
TBD -
th(SD_MR)(2)(3)
th(SD_SR) (2)(3)
3. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.
Data input hold time Master receiver
Slave receiver
TBD
TBD -
th(SD_MR) (2)
th(SD_SR) (2) Data input hold time Master fPCLK = TBD
Slave fPCLK = TBD
TBD
TBD -
tv(SD_ST) (2)(3) Data output valid time
Slave transmitter
(after enable edge) - TBD
fPCLK = TBD - TBD
th(SD_ST) (2) Data output hold time Slave transmitter
(after enable edge) TBD -
tv(SD_MT) (2)(3) Data output valid time
Master transmitter
(after enable edge) - TBD
fPCLK = TBD TBD TBD
th(SD_MT) (2) Data output hold time Master transmitter
(after enable edge) TBD -
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Figure 41. I2S slave timing diagram (Philips protocol)(1)
1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 42. I2S master timing diagram (Philips protocol)(1)
1. Based on characterization, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
CK Input
CPOL = 0
CPOL = 1
tc(CK)
WS input
SDtransmit
SDreceive
tw(CKH) tw(CKL)
tsu(WS)tv(SD_ST) th(SD_ST)
th(WS)
tsu(SD_SR) th(SD_SR)
MSB receive Bitn receive LSB receive
MSB transmit Bitn transmit LSB transmit
ai14881b
LSB receive(2)
LSB transmit(2)
CK output
CPOL = 0
CPOL = 1
tc(CK)
WS output
SDreceive
SDtransmit
tw(CKH)
tw(CKL)
tsu(SD_MR)
tv(SD_MT) th(SD_MT)
th(WS)
th(SD_MR)
MSB receive Bitn receive LSB receive
MSB transmit Bitn transmit LSB transmit
ai14884b
tf(CK) tr(CK)
tv(WS)
LSB receive
(2)
LSB transmit
(2)
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 103/158
USB OTG FS characteristics
The USB OTG interface is USB-IF certified (Full-Speed). This interface is present in both
the USB OTG HS and USB OTG FS controllers.
Table 51. USB OTG FS startup time
Symbol Parameter Max Unit
tSTARTUP(1)
1. Guaranteed by design, not tested in production.
USB OTG FS transceiver startup time 1 µs
Table 52. USB OTG FS DC electrical characteristics
Symbol Parameter Conditions Min.(1)
1. All the voltages are measured from the local ground potential.
Typ. Max.(1) Unit
Input
levels
VDD
USB OTG FS operating
voltage 3.0(2)
2. The STM32F21x and STM32F215xx USB OTG FS functionality is ensured down to 2.7 V but not the full
USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
-3.6V
VDI(3)
3. Guaranteed by design, not tested in production.
Differential input sensitivity I(USB_FS_DP/DM,
USB_HS_DP/DM) 0.2 - -
VVCM(3) Differential common mode
range Includes VDI range 0.8 - 2.5
VSE(3) Single ended receiver
threshold 1.3 - 2.0
Output
levels
VOL Static output level low RL of 1.5 kΩ to 3.6 V(4)
4. RL is the load connected on the USB OTG FS drivers
--0.3
V
VOH Static output level high RL of 15 kΩ to VSS(4) 2.8 - 3.6
RPD
PA11, PA12, PB14, PB15
(USB_FS_DP/DM,
USB_HS_DP/DM) VIN = VDD
17 21 24
kΩ
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
0.65 1.1 2.0
RPU
PA12, PB15 (USB_FS_DP,
USB_HS_DP) VIN = VSS 1.5 1.8 2.1
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
VIN = VSS 0.25 0.37 0.55
Electrical characteristics STM32F215xx, STM32F217xx
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Figure 43. USB OTG FS timings: definition of data signal rise and fall time
USB HS characteristics
Ta bl e 5 4 shows the USB HS operating voltage.
Table 53. USB OTG FS electrical characteristics(1)
1. Guaranteed by design, not tested in production.
Driver characteristics
Symbol Parameter Conditions Min Max Unit
trRise time(2)
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
CL = 50 pF 420ns
tfFall time(2) CL = 50 pF 4 20 ns
trfm Rise/ fall time matching tr/tf90 110 %
VCRS Output signal crossover voltage 1.3 2.0 V
Table 54. USB HS DC electrical characteristics
Symbol Parameter Min.(1)
1. All the voltages are measured from the local ground potential.
Max.(1) Unit
Input level VDD Ethernet operating voltage 2.7 3.6 V
Table 55. Clock timing parameters
Parameter(1)
1. Guaranteed by design, not tested in production.
Symbol Min Nominal Max Unit
Frequency (first transition) 8-bit ±10% FSTART_8BIT 54 60 66 MHz
Frequency (steady state) ±500 ppm FSTEADY 59.97 60 60.03 MHz
Duty cycle (first transition) 8-bit ±10% DSTART_8BIT 40 50 60 %
Duty cycle (steady state) ±500 ppm DSTEADY 49.975 50 50.025 %
Time to reach the steady state frequency and
duty cycle after the first transition TSTEADY --1.4ms
Clock startup time after the
de-assertion of SuspendM
Peripheral TSTART_DEV --5.6
ms
Host TSTART_HOST ---
PHY preparation time after the first transition
of the input clock TPREP ---µs
ai14137
tf
Differen tial
data lines
VSS
V
CR S
tr
Crossover
points
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 105/158
Figure 44. ULPI timing diagram
Ethernet characteristics
Ta bl e 5 7 shows the Ethernet operating voltage.
Ta bl e 5 8 gives the list of Ethernet MAC signals for the SMI (station management interface)
and Figure 45 shows the corresponding timing diagram.
Table 56. ULPI timing
Parameter Symbol
Value(1)
1. VDD = 2.7 V to 3.6 V and TA = –40 to 85 °C.
Unit
Min. Max.
Output clock
Setup time (control in) tSC, tSD -6.0ns
Hold time (control in) tHC, tHD 0.0 - ns
Output delay (control out) tDC, tDD -9.0ns
Input clock
(optional)
Setup time (control in) tSC, tSD -3.0ns
Hold time (control in) tHC, tHD 1.5 - ns
Output delay (control out) tDC, tDD -6.0ns
Table 57. Ethernet DC electrical characteristics
Symbol Parameter Min.(1)
1. All the voltages are measured from the local ground potential.
Max.(1) Unit
Input level VDD Ethernet operating voltage 2.7 3.6 V
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Electrical characteristics STM32F215xx, STM32F217xx
106/158 Doc ID 17050 Rev 4
Figure 45. Ethernet SMI timing diagram
Ta bl e 5 9 gives the list of Ethernet MAC signals for the RMII and Figure 46 shows the
corresponding timing diagram.
Figure 46. Ethernet RMII timing diagram
Table 58. Dynamics characteristics: Ethernet MAC signals for SMI(1)
1. TBD stands for “to be defined”.
Symbol Rating Min Typ Max Unit
tMDC MDC cycle time (1.71 MHz, AHB = 72 MHz) TBD TBD TBD ns
td(MDIO) MDIO write data valid time TBD TBD TBD ns
tsu(MDIO) Read data setup time TBD TBD TBD ns
th(MDIO) Read data hold time TBD TBD TBD ns
Table 59. Dynamics characteristics: Ethernet MAC signals for RMII(1)
1. TBD stands for “to be defined”.
Symbol Rating Min Typ Max Unit
tsu(RXD) Receive data setup time TBD TBD TBD ns
tih(RXD) Receive data hold time TBD TBD TBD ns
tsu(CRS) Carrier sense set-up time TBD TBD TBD ns
tih(CRS) Carrier sense hold time TBD TBD TBD ns
td(TXEN) Transmit enable valid delay time 0 9.6 21.9 ns
td(TXD) Transmit data valid delay time 0 9.9 21 ns
ETH_MDC
ETH_MDIO(O)
ETH_MDIO(I)
t
MDC
t
d(MDIO)
t
su(MDIO)
t
h(MDIO)
ai15666c
RMII_REF_CLK
RMII_TX_EN
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRS_DV
td(TXEN)
td(TXD)
tsu(RXD)
tsu(CRS)
tih(RXD)
tih(CRS)
ai15667
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 107/158
Ta bl e 6 0 gives the list of Ethernet MAC signals for MII and Figure 46 shows the
corresponding timing diagram.
Figure 47. Ethernet MII timing diagram
CAN (controller area network) interface
Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (CANTX and CANRX).
Table 60. Dynamics characteristics: Ethernet MAC signals for MII(1)
1. TBD stands for “to be defined”.
Symbol Rating Min Typ Max Unit
tsu(RXD) Receive data setup time TBD TBD TBD ns
tih(RXD) Receive data hold time TBD TBD TBD ns
tsu(DV) Data valid setup time TBD TBD TBD ns
tih(DV) Data valid hold time TBD TBD TBD ns
tsu(ER) Error setup time TBD TBD TBD ns
tih(ER) Error hold time TBD TBD TBD ns
td(TXEN) Transmit enable valid delay time 13.4 15.5 17.7 ns
td(TXD) Transmit data valid delay time 12.9 16.1 19.4 ns
MII_RX_CLK
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
t
d(TXEN)
t
d(TXD)
t
su(RXD)
t
su(ER)
t
su(DV)
t
ih(RXD)
t
ih(ER)
t
ih(DV)
ai15668
MII_TX_CLK
MII_TX_EN
MII_TXD[3:0]
Electrical characteristics STM32F215xx, STM32F217xx
108/158 Doc ID 17050 Rev 4
5.3.20 12-bit ADC characteristics
Unless otherwise specified, the parameters given in Ta b l e 6 1 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Ta b l e 1 0 .
Table 61. ADC characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VDDA Power supply 1.8 - 3.6 V
VREF+ Positive reference voltage 1.8(2) -V
DDA V
fADC ADC clock frequency VDDA = 1.8 to 2.4 V 0.6 - 15 MHz
VDDA = 2.4 to 3.6 V 0.6 - 30 MHz
fTRIG(3) External trigger frequency fADC = 30 MHz - - 823 kHz
--171/f
ADC
VAIN Conversion voltage range(4) 0 (VSSA or VREF-
tied to ground) -V
REF+ V
RAIN(3) External input impedance See Equation 1 for
details --50kΩ
RADC(3)(5) Sampling switch resistance 1.5 - 6 kΩ
CADC(3) Internal sample and hold
capacitor 4-TBDpF
tlat(3) Injection trigger conversion
latency
fADC = 30 MHz - - 0.100 µs
--3
(6) 1/fADC
tlatr(3) Regular trigger conversion latency fADC = 30 MHz - - 0.067 µs
--2
(6) 1/fADC
tS(3) Sampling time fADC = 30 MHz 0.100 - 16 µs
3 - 480 1/fADC
tSTAB(3) Power-up time - 2 3 µs
tCONV(3) Total conversion time (including
sampling time)
fADC = 30 MHz
12-bit resolution 0.5 - 16.40 µs
fADC = 30 MHz
10-bit resolution 0.43 - 16.34 µs
fADC = 30 MHz
8-bit resolution 0.37 - 16.27 µs
fADC = 30 MHz
6-bit resolution 0.3 - 16.20 µs
9 to 492 (tS for sampling +n-bit resolution for successive
approximation) 1/fADC
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 109/158
Equation 1: RAIN max formula
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
fS(3) Sampling rate
(fADC = 30 MHz)
12-bit resolution
Single ADC --2Msps
12-bit resolution
Interleave Dual ADC
mode
--4Msps
12-bit resolution
Interleave Triple ADC
mode
--6Msps
IVREF+(3) ADC VREF DC current
consumption in conversion mode
fADC = 30 MHz
3 sampling time
12-bit resolution
- 300 500 µA
fADC = 30 MHz
480 sampling time
12-bit resolution
--TBDµA
IDDA(3) ADC VDDA DC current
consumption in conversion mode
fADC = 30 MHz
3 sampling time
12-bit resolution
-1.61.8
mA
fADC = 30 MHz
480 sampling time
12-bit resolution
--TBD
1. TBD stands for “to be defined”.
2. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V.
3. Based on characterization, not tested in production.
4. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
5. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V.
6. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 61.
Table 61. ADC characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
RAIN
k0.5–()
fADC CADC 2N2+
()ln××
-------------------------------------------------------------- RADC
–=
Electrical characteristics STM32F215xx, STM32F217xx
110/158 Doc ID 17050 Rev 4
a
Note: ADC accuracy vs. negative injection current: Injecting a negative current on any of the
standard (non-robust) analog input pins should be avoided as this significantly reduces the
accuracy of the conversion being performed on another analog input. It is recommended to
add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 5.3.16 does not affect the ADC accuracy.
Figure 48. ADC accuracy characteristics
1. Example of an actual transfer curve.
2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Table 62. ADC accuracy (1)
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
Symbol Parameter Test conditions Typ Max(2)
2. Based on characterization, not tested in production.
Unit
ET Total unadjusted error
fPCLK2 = 60 MHz,
fADC = 30 MHz, RAIN < 10 kΩ,
VDDA = 1.8 to 3.6 V
±2 ±5
LSB
EO Offset error ±1.5 ±2.5
EG Gain error ±1.5 ±3
ED Differential linearity error ±1 ±2
EL Integral linearity error ±1.5 ±3
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STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 111/158
Figure 49. Typical connection diagram using the ADC
1. Refer to Ta b l e 6 1 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
ai17534
STM32F
VDD
AINx
IL±1 µA
0.6 V
VT
RAIN(1)
Cparasitic
VAIN
0.6 V
VT
RADC(1)
C
ADC(1)
12-bit
converter
Sample and hold ADC
converter
Electrical characteristics STM32F215xx, STM32F217xx
112/158 Doc ID 17050 Rev 4
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 50 or Figure 51,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 50. Power supply and reference decoupling (VREF+ not connected to VDDA)
1. VREF+ and VREF– inputs are available only on 100-pin packages.
Figure 51. Power supply and reference decoupling (VREF+ connected to VDDA)
1. VREF+ and VREF– inputs are available only on 100-pin packages.
VREF+
STM32F
VDDA
VSSA/V REF-
1 µF // 10 nF
1 µF // 10 nF
ai17535
(See note 1)
(See note 1)
VREF+/VDDA
STM32F
1 µF // 10 nF
VREF–/VSSA
ai17536
(See note 1)
(See note 1)
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 113/158
5.3.21 DAC electrical characteristics
Table 63. DAC characteristics
Symbol Parameter Min Typ Max Unit Comments
VDDA Analog supply voltage 1.8 - 3.6 V
VREF+ Reference supply voltage 1.8 - 3.6 V VREF+ ≤ VDDA
VSSA Ground 0 - 0 V
RLOAD(1) Resistive load with buffer ON 5 - - kΩ
RO(1) Impedance output with buffer
OFF -- 15 kΩ
When the buffer is OFF, the
Minimum resistive load between
DAC_OUT and VSS to have a 1%
accuracy is 1.5 MΩ
CLOAD(1) Capacitive load - - 50 pF
Maximum capacitive load at
DAC_OUT pin (when the buffer is
ON).
DAC_OUT
min(1)
Lower DAC_OUT voltage
with buffer ON 0.2 - - V
It gives the maximum output
excursion of the DAC.
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ =
3.6 V and (0x1C7) to (0xE38) at
VREF+ = 1.8 V
DAC_OUT
max(1)
Higher DAC_OUT voltage
with buffer ON --V
DDA – 0.2 V
DAC_OUT
min(1)
Lower DAC_OUT voltage
with buffer OFF -0.5 - mV
It gives the maximum output
excursion of the DAC.
DAC_OUT
max(1)
Higher DAC_OUT voltage
with buffer OFF --V
REF+ – 1LSB V
IVREF+(2)
DAC DC VREF current
consumption in quiescent
mode (Standby mode)
- 170 240
µA
With no load, worst code (0x800)
at VREF+ = 3.6 V in terms of DC
consumption on the inputs
-50 75
With no load, worst code (0xF1C)
at VREF+ = 3.6 V in terms of DC
consumption on the inputs
IDDA(2)
DAC DC VDDA current
consumption in quiescent
mode (Standby mode)
- 280 380 µA With no load, middle code (0x800)
on the inputs
- 475 625 µA
With no load, worst code (0xF1C)
at VREF+ = 3.6 V in terms of DC
consumption on the inputs
DNL(2)
Differential non linearity
Difference between two
consecutive code-1LSB)
-- ±0.5 LSB
Given for the DAC in 10-bit
configuration.
-- ±2 LSB
Given for the DAC in 12-bit
configuration.
Electrical characteristics STM32F215xx, STM32F217xx
114/158 Doc ID 17050 Rev 4
INL(2)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
-- ±1 LSB
Given for the DAC in 10-bit
configuration.
-- ±4 LSB
Given for the DAC in 12-bit
configuration.
Offset(2)
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
VREF+/2)
-- ±10 mV
Given for the DAC in 12-bit
configuration
-- ±3 LSB
Given for the DAC in 10-bit at
VREF+ = 3.6 V
-- ±12LSB
Given for the DAC in 12-bit at
VREF+ = 3.6 V
Gain
error(2) Gain error - - ±0.5 % Given for the DAC in 12-bit
configuration
tSETTLING(2)
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±4LSB
-3 6 µs
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
THD(2) Total Harmonic Distortion
Buffer ON -- - dB
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
Update
rate(1)
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
-- 1 MS/s
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
tWAKEUP(2)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
-6.5 10 µs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
input code between lowest and
highest possible ones.
PSRR+ (1)
Power supply rejection ratio
(to VDDA) (static DC
measurement)
- –67 –40 dB No RLOAD, CLOAD = 50 pF
1. Guaranteed by design, not tested in production.
2. Guaranteed by characterization, not tested in production.
Table 63. DAC characteristics (continued)
Symbol Parameter Min Typ Max Unit Comments
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 115/158
Figure 52. 12-bit buffered /non-buffered DAC
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
5.3.22 Temperature sensor characteristics
5.3.23 VBAT monitoring characteristics
RLOAD
CLOAD
Buffered/Non-buffered DAC
DACx_OUT
Buffer(1)
12-bit
digital to
analog
converter
ai17157
Table 64. TS characteristics
Symbol Parameter Min Typ Max Unit
TL(1)
1. Based on characterization, not tested in production.
VSENSE linearity with temperature - ±1±2°C
Avg_Slope(1) Average slope - 2.5 mV/°C
V25(1) Voltage at 25 °C - 0.76 V
tSTART(2)
2. Guaranteed by design, not tested in production.
Startup time - 6 10 µs
TS_temp(3)(2)
3. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when reading the
temperature
1°C accuracy
16 - - µs
Table 65. VBAT monitoring characteristics(1)
1. TBD stands for “to be defined”.
Symbol Parameter Min Typ Max Unit
R Resistor bridge for VBAT -50-KΩ
QRatio on VBAT measurement - 2 -
Er(2)
2. Guaranteed by design, not tested in production.
Error on Q –1 - +1 %
TS_vbat(3)(2)
3. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when reading the VBAT
1mV accuracy TBD(1) --µs
Electrical characteristics STM32F215xx, STM32F217xx
116/158 Doc ID 17050 Rev 4
5.3.24 Embedded reference voltage
The parameters given in Ta b l e 6 6 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Ta b le 1 0 .
5.3.25 FSMC characteristics
Asynchronous waveforms and timings
Figure 53 through Figure 56 represent asynchronous waveforms and Ta bl e 6 7 through
Ta bl e 7 0 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
●AddressSetupTime = 0
●AddressHoldTime = 1
●DataSetupTime = 1
Table 66. Embedded internal reference voltage
Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.18 1.21 1.24 V
TS_vrefint(1)
1. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when
reading the internal reference
voltage
16 - - µs
VRERINT_s
(2)
2. Guaranteed by design, not tested in production.
Internal reference voltage
spread over the temperature
range
VDD = 3 V - 3 5 mV
TCoeff(2) Temperature coefficient - 30 50 ppm/°C
tSTART(2) Startup time - 6 10 µs
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 117/158
Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) (2)
1. CL = 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
tw(NE) FSMC_NE low time 5THCLK – 1.5 5THCLK + 2 ns
tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 0.5 1.5 ns
tw(NOE) FSMC_NOE low time 5THCLK – 1.5 5THCLK + 1.5 ns
th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time –1.5 ns
tv(A_NE) FSMC_NEx low to FSMC_A valid 7 ns
th(A_NOE) Address hold time after FSMC_NOE high 0.1 ns
tv(BL_NE) FSMC_NEx low to FSMC_BL valid 0 ns
th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 ns
tsu(Data_NE) Data to FSMC_NEx high setup time 2THCLK + 25 ns
tsu(Data_NOE) Data to FSMC_NOEx high setup time 2THCLK + 25 ns
th(Data_NOE) Data hold time after FSMC_NOE high 0 ns
th(Data_NE) Data hold time after FSMC_NEx high 0 ns
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 5 ns
tw(NADV) FSMC_NADV low time THCLK + 1.5 ns
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Electrical characteristics STM32F215xx, STM32F217xx
118/158 Doc ID 17050 Rev 4
Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 68. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)
1. CL = 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
tw(NE) FSMC_NE low time 3THCLK – 1 3THCLK + 2 ns
tv(NWE_NE) FSMC_NEx low to FSMC_NWE low THCLK – 0.5 THCLK + 1.5 ns
tw(NWE) FSMC_NWE low time THCLK – 0.5 THCLK + 1.5 ns
th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK ns
tv(A_NE) FSMC_NEx low to FSMC_A valid 7.5 ns
th(A_NWE) Address hold time after FSMC_NWE high THCLK ns
tv(BL_NE) FSMC_NEx low to FSMC_BL valid 1.5 ns
th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK – 0.5 ns
tv(Data_NE) FSMC_NEx low to Data valid THCLK + 7 ns
th(Data_NWE) Data hold time after FSMC_NWE high THCLK ns
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 5.5 ns
tw(NADV) FSMC_NADV low time THCLK + 1.5 ns
NBL
Data
FSMC_NEx
FSMC_NBL[1:0]
FSMC_D[15:0]
t
v(BL_NE)
th(Data_NWE)
FSMC_NOE
Address
FSMC_A[25:0]
t
v(A_NE)
tw(NWE)
FSMC_NWE
tv(NWE_NE) th(NE_NWE)
th(A_NWE)
th(BL_NWE)
tv(Data_NE)
tw(NE)
ai14990
FSMC_NADV(1)
tv(NADV_NE)
tw(NADV)
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 119/158
Figure 55. Asynchronous multiplexed PSRAM/NOR read waveforms
Table 69. Asynchronous multiplexed PSRAM/NOR read timings(1)(2)
1. CL = 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
tw(NE) FSMC_NE low time 7THCLK – 2 7THCLK + 2 ns
tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 3THCLK – 0.5 3THCLK + 1.5 ns
tw(NOE) FSMC_NOE low time 4THCLK – 1 4THCLK + 2 ns
th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time –1 ns
tv(A_NE) FSMC_NEx low to FSMC_A valid 0 ns
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 3 5 ns
tw(NADV) FSMC_NADV low time THCLK –1.5 THCLK + 1.5 ns
th(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC_NADV high THCLK ns
th(A_NOE) Address hold time after FSMC_NOE high THCLK ns
th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 ns
tv(BL_NE) FSMC_NEx low to FSMC_BL valid 0 ns
tsu(Data_NE) Data to FSMC_NEx high setup time 2THCLK + 24 ns
tsu(Data_NOE) Data to FSMC_NOE high setup time 2THCLK + 25 ns
th(Data_NE) Data hold time after FSMC_NEx high 0 ns
th(Data_NOE) Data hold time after FSMC_NOE high 0 ns
NBL
Data
FSMC_NBL[1:0]
FSMC_AD[15:0]
t
v(BL_NE)
th(Data_NE)
Address
FSMC_A[25:16]
t
v(A_NE)
FSMC_NWE
tv(A_NE)
ai14892b
Address
FSMC_NADV
tv(NADV_NE)
tw(NADV)
tsu(Data_NE)
t
h(AD_NADV)
FSMC_NE
FSMC_NOE
tw(NE)
tw(NOE)
tv(NOE_NE) th(NE_NOE)
th(A_NOE)
th(BL_NOE)
tsu(Data_NOE) th(Data_NOE)
Electrical characteristics STM32F215xx, STM32F217xx
120/158 Doc ID 17050 Rev 4
Figure 56. Asynchronous multiplexed PSRAM/NOR write waveforms
Table 70. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)
1. CL = 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
tw(NE) FSMC_NE low time 5THCLK – 1 5THCLK + 2 ns
tv(NWE_NE) FSMC_NEx low to FSMC_NWE low 2THCLK 2THCLK + 1 ns
tw(NWE) FSMC_NWE low time 2THCLK – 1 2THCLK + 2 ns
th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK – 1 ns
tv(A_NE) FSMC_NEx low to FSMC_A valid 7 ns
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 3 5 ns
tw(NADV) FSMC_NADV low time THCLK – 1 THCLK + 1 ns
th(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC_NADV high THCLK – 3 ns
th(A_NWE) Address hold time after FSMC_NWE high 4THCLK ns
tv(BL_NE) FSMC_NEx low to FSMC_BL valid 1.6 ns
th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK – 1.5 ns
tv(Data_NADV) FSMC_NADV high to Data valid THCLK + 1.5 ns
th(Data_NWE) Data hold time after FSMC_NWE high THCLK – 5 ns
NBL
Data
FSMC_NEx
FSMC_NBL[1:0]
FSMC_AD[15:0]
t
v(BL_NE)
th(Data_NWE)
FSMC_NOE
Address
FSMC_A[25:16]
t
v(A_NE)
tw(NWE)
FSMC_NWE
tv(NWE_NE) th(NE_NWE)
th(A_NWE)
th(BL_NWE)
tv(A_NE)
tw(NE)
ai14891B
Address
FSMC_NADV
tv(NADV_NE)
tw(NADV)
tv(Data_NADV)
t
h(AD_NADV)
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 121/158
Synchronous waveforms and timings
Figure 57 through Figure 60 represent synchronous waveforms and Ta bl e 7 2 through
Ta bl e 7 4 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
●BurstAccessMode = FSMC_BurstAccessMode_Enable;
●MemoryType = FSMC_MemoryType_CRAM;
●WriteBurst = FSMC_WriteBurst_Enable;
●CLKDivision = 1; (0 is not supported, see the STM32F20xxx/21xxx reference manual)
●DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
Figure 57. Synchronous multiplexed NOR/PSRAM read timings
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Electrical characteristics STM32F215xx, STM32F217xx
122/158 Doc ID 17050 Rev 4
Table 71. Synchronous multiplexed NOR/PSRAM read timings(1)(2)
1. CL = 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
tw(CLK) FSMC_CLK period 16.6 ns
td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) 1.5 ns
td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) THCLK + 2 ns
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low 4 ns
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 ns
td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) 0 ns
td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) THCLK + 2 ns
td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low THCLK +1 ns
td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high THCLK + 0.5 ns
td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid 12 ns
td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 ns
tsu(ADV-CLKH)
FSMC_A/D[15:0] valid data before FSMC_CLK
high 6 ns
th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high THCLK – 10 ns
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high 8 ns
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 ns
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 123/158
Figure 58. Synchronous multiplexed PSRAM write timings
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Electrical characteristics STM32F215xx, STM32F217xx
124/158 Doc ID 17050 Rev 4
Table 72. Synchronous multiplexed PSRAM write timings(1)(2)
1. CL = 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
tw(CLK) FSMC_CLK period 16.6 ns
td(CLKL-NExL) FSMC_CLK low to FSMC_Nex low (x = 0...2) 2 ns
td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) THCLK + 2 ns
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low 4 ns
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 ns
td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) 0 ns
td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) TCK + 2 ns
td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low 1 ns
td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high THCLK +1 ns
td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid 12 ns
td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 3 ns
td(CLKL-Data) FSMC_A/D[15:0] valid after FSMC_CLK low 6 ns
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high 7 ns
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 ns
td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1 ns
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 125/158
Figure 59. Synchronous non-multiplexed NOR/PSRAM read timings
Table 73. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2)
1. CL = 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
tw(CLK) FSMC_CLK period 16.6 ns
td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) 1.5 ns
td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) THCLK + 2 ns
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low 4 ns
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 ns
td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 0...25) 0 ns
td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 0...25) THCLK + 4 ns
td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low THCLK + 1.5 ns
td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high THCLK + 1.5 ns
tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 6.5 ns
th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 7 ns
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_SMCLK high 7 ns
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 ns
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Electrical characteristics STM32F215xx, STM32F217xx
126/158 Doc ID 17050 Rev 4
Figure 60. Synchronous non-multiplexed PSRAM write timings
Table 74. Synchronous non-multiplexed PSRAM write timings(1)(2)
1. CL = 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
tw(CLK) FSMC_CLK period 16.6 ns
td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) 2 ns
td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) THCLK + 2 ns
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low 4 ns
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 ns
td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) 0 ns
td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) TCK + 2 ns
td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low 1 ns
td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high THCLK + 1 ns
td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low 6 ns
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high 7 ns
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 ns
td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1 ns
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STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 127/158
PC Card/CompactFlash controller waveforms and timings
Figure 61 through Figure 66 represent synchronous waveforms and Ta bl e 7 5 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
●COM.FSMC_SetupTime = 0x04;
●COM.FSMC_WaitSetupTime = 0x07;
●COM.FSMC_HoldSetupTime = 0x04;
●COM.FSMC_HiZSetupTime = 0x00;
●ATT.FSMC_SetupTime = 0x04;
●ATT.FSMC_WaitSetupTime = 0x07;
●ATT.FSMC_HoldSetupTime = 0x04;
●ATT.FSMC_HiZSetupTime = 0x00;
●IO.FSMC_SetupTime = 0x04;
●IO.FSMC_WaitSetupTime = 0x07;
●IO.FSMC_HoldSetupTime = 0x04;
●IO.FSMC_HiZSetupTime = 0x00;
●TCLRSetupTime = 0;
●TARSetupTime = 0;
Figure 61. PC Card/CompactFlash controller waveforms for common memory read
access
1. FSMC_NCE4_2 remains high (inactive during 8-bit access.
FSMC_NWE
tw(NOE)
FSMC_N
OE
FSMC_D[15:0]
FSMC_A[10:0]
FSMC_NCE4_2
(1)
FSMC_NCE4_1
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
td(NCE4_1-NOE)
tsu(D-NOE) th(NOE-D)
tv(NCEx-A)
td(NREG-NCEx)
td(NIORD-NCEx)
th(NCEx-AI)
th(NCEx-NREG)
th(NCEx-NIORD)
th(NCEx-
NIOWR
)
ai14895b
Electrical characteristics STM32F215xx, STM32F217xx
128/158 Doc ID 17050 Rev 4
Figure 62. PC Card/CompactFlash controller waveforms for common memory write
access
td(NCE4_1-NWE) tw(NWE)
th(NWE-D)
tv(NCE4_1-A)
td(NREG-NCE4_1)
td(NIORD-NCE4_1)
th(NCE4_1-AI)
MEMxHIZ =1
tv(NWE-D)
th(NCE4_1-NREG)
th(NCE4_1-NIORD)
th(NCE4_1-NIOWR)
ai14896b
FSMC_NWE
FSMC_N
OE
FSMC_D[15:0]
FSMC_A[10:0]
FSMC_NCE4_1
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
td(NWE-NCE4_1)
td(D-NWE)
FSMC_NCE4_2 High
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 129/158
Figure 63. PC Card/CompactFlash controller waveforms for attribute memory read
access
1. Only data bits 0...7 are read (bits 8...15 are disregarded).
td(NCE4_1-NOE) tw(NOE)
tsu(D-NOE) th(NOE-D)
tv(NCE4_1-A) th(NCE4_1-AI)
td(NREG-NCE4_1) th(NCE4_1-NREG)
ai14897b
FSMC_NWE
FSMC_NOE
FSMC_D[15:0](1)
FSMC_A[10:0]
FSMC_NCE4_2
FSMC_NCE4_1
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
td(NOE-NCE4_1)
High
Electrical characteristics STM32F215xx, STM32F217xx
130/158 Doc ID 17050 Rev 4
Figure 64. PC Card/CompactFlash controller waveforms for attribute memory write
access
1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z).
Figure 65. PC Card/CompactFlash controller waveforms for I/O space read access
tw(NWE)
tv(NCE4_1-A)
td(NREG-NCE4_1)
th(NCE4_1-AI)
th(NCE4_1-NREG)
tv(NWE-D)
ai14898b
FSMC_NWE
FSMC_NOE
FSMC_D[7:0](1)
FSMC_A[10:0]
FSMC_NCE4_2
FSMC_NCE4_1
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
td(NWE-NCE4_1)
High
td(NCE4_1-NWE)
td(NIORD-NCE4_1) tw(NIORD)
tsu(D-NIORD) td(NIORD-D)
tv(NCEx-A) th(NCE4_1-AI)
ai14899B
FSMC_NWE
FSMC_NOE
FSMC_D[15:0]
FSMC_A[10:0]
FSMC_NCE4_2
FSMC_NCE4_1
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 131/158
Figure 66. PC Card/CompactFlash controller waveforms for I/O space write access
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Table 75. Switching characteristics for PC Card/CF read and write cycles(1)(2)
Symbol Parameter Min Max Unit
tv(NCEx-A)
tv(NCE4_1-A)
FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid (y =
0...10) FSMC_NCE4_1 low (x = 4_1/4_2) to FSMC_Ay valid
(y = 0...10)
0 ns
th(NCEx-AI)
th(NCE4_1-AI)
FSMC_NCEx high (x = 4_1/4_2) to FSMC_Ax invalid (x =
0...10) FSMC_NCE4_1 high (x = 4_1/4_2) to FSMC_Ax
invalid (x = 0...10)
2.5 ns
td(NREG-NCEx)
td(NREG-NCE4_1)
FSMC_NCEx low to FSMC_NREG valid FSMC_NCE4_1
low to FSMC_NREG valid 5 ns
th(NCEx-NREG)
th(NCE4_1-NREG)
FSMC_NCEx high to FSMC_NREG invalid FSMC_NCE4_1
high to FSMC_NREG invalid THCLK + 3 ns
td(NCE4_1-NOE) FSMC_NCE4_1 low to FSMC_NOE low 5THCLK + 2 ns
tw(NOE) FSMC_NOE low width 8THCLK –1.5 8THCLK + 1 ns
td(NOE-NCE4_1 FSMC_NOE high to FSMC_NCE4_1 high 5THCLK + 2 ns
tsu(D-NOE) FSMC_D[15:0] valid data before FSMC_NOE high 25 ns
th(NOE-D) FSMC_D[15:0] valid data after FSMC_NOE high 15 ns
tw(NWE) FSMC_NWE low width 8THCLK – 1 8THCLK + 2 ns
td(NWE-NCE4_1) FSMC_NWE high to FSMC_NCE4_1 high 5THCLK + 2 ns
td(NCE4_1-NWE) FSMC_NCE4_1 low to FSMC_NWE low 5THCLK + 1.5 ns
tv(NWE-D) FSMC_NWE low to FSMC_D[15:0] valid 0 ns
th(NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 11THCLK ns
td(D-NWE) FSMC_D[15:0] valid before FSMC_NWE high 13THCLK ns
Electrical characteristics STM32F215xx, STM32F217xx
132/158 Doc ID 17050 Rev 4
NAND controller waveforms and timings
Figure 67 through Figure 70 represent synchronous waveforms and Ta bl e 7 6 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
●COM.FSMC_SetupTime = 0x01;
●COM.FSMC_WaitSetupTime = 0x03;
●COM.FSMC_HoldSetupTime = 0x02;
●COM.FSMC_HiZSetupTime = 0x01;
●ATT.FSMC_SetupTime = 0x01;
●ATT.FSMC_WaitSetupTime = 0x03;
●ATT.FSMC_HoldSetupTime = 0x02;
●ATT.FSMC_HiZSetupTime = 0x01;
●Bank = FSMC_Bank_NAND;
●MemoryDataWidth = FSMC_MemoryDataWidth_16b;
●ECC = FSMC_ECC_Enable;
●ECCPageSize = FSMC_ECCPageSize_512Bytes;
●TCLRSetupTime = 0;
●TARSetupTime = 0;
tw(NIOWR) FSMC_NIOWR low width 8THCLK + 3 ns
tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid 5THCLK +1 ns
th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid 11THCLK ns
td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid 5THCLK+3ns ns
th(NCEx-NIOWR)
th(NCE4_1-NIOWR)
FSMC_NCEx high to FSMC_NIOWR invalid
FSMC_NCE4_1 high to FSMC_NIOWR invalid 5THCLK – 5 ns
td(NIORD-NCEx)
td(NIORD-NCE4_1)
FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1
low to FSMC_NIORD valid 5THCLK + 2.5 ns
th(NCEx-NIORD)
th(NCE4_1-NIORD)
FSMC_NCEx high to FSMC_NIORD invalid
FSMC_NCE4_1 high to FSMC_NIORD invalid 5THCLK – 5 ns
tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high 4.5 ns
td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high 9 ns
tw(NIORD) FSMC_NIORD low width 8THCLK + 2 ns
1. CL = 15 pF.
2. Based on characterization, not tested in production.
Table 75. Switching characteristics for PC Card/CF read and write cycles(1)(2) (continued)
Symbol Parameter Min Max Unit
STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 133/158
Figure 67. NAND controller waveforms for read access
Figure 68. NAND controller waveforms for write access
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Electrical characteristics STM32F215xx, STM32F217xx
134/158 Doc ID 17050 Rev 4
Figure 69. NAND controller waveforms for common memory read access
Figure 70. NAND controller waveforms for common memory write access
Table 76. Switching characteristics for NAND Flash read and write cycles(1)
Symbol Parameter Min Max Unit
td(D-NWE)(2) FSMC_D[15:0] valid before FSMC_NWE high 6THCLK + 12 ns
tw(NOE)(2) FSMC_NOE low width 4THCLK – 1.5 4THCLK + 1.5 ns
tsu(D-NOE)(2) FSMC_D[15:0] valid data before FSMC_NOE
high 25 ns
th(NOE-D)(2) FSMC_D[15:0] valid data after FSMC_NOE high 7 ns
tw(NWE)(2) FSMC_NWE low width 4THCLK – 1 4THCLK + 2.5 ns
tv(NWE-D)(2) FSMC_NWE low to FSMC_D[15:0] valid 0 ns
th(NWE-D)(2) FSMC_NWE high to FSMC_D[15:0] invalid 10THCLK + 4 ns
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STM32F215xx, STM32F217xx Electrical characteristics
Doc ID 17050 Rev 4 135/158
5.3.26 Camera interface (DCMI) timing specifications
5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in Ta b l e 7 8 are derived from tests
performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions
summarized in Ta b l e 1 0 .
Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (D[7:0], CMD, CK).
Figure 71. SDIO high-speed mode
td(ALE-NWE)(3) FSMC_ALE valid before FSMC_NWE low 3THCLK + 1.5 ns
th(NWE-ALE)(3) FSMC_NWE high to FSMC_ALE invalid 3THCLK + 4.5 ns
td(ALE-NOE)(3) FSMC_ALE valid before FSMC_NOE low 3THCLK + 2 ns
th(NOE-ALE)(3) FSMC_NWE high to FSMC_ALE invalid 3THCLK + 4.5 ns
1. CL = 15 pF.
2. Based on characterization, not tested in production.
3. Guaranteed by design, not tested in production.
Table 76. Switching characteristics for NAND Flash read and write cycles(1)
Symbol Parameter Min Max Unit
Table 77. DCMI characteristics
Symbol Parameter Conditions Min Max Unit
Frequency ratio
DCMI_PIXCLK/fHCLK
DCMI_PIXCLK=
48 MHz 2.5
tW(CKH)
CK
D, CMD
(output)
D, CMD
(input)
tC
tW(CKL)
tOV tOH
tISU tIH
tftr
ai14887
Electrical characteristics STM32F215xx, STM32F217xx
136/158 Doc ID 17050 Rev 4
Figure 72. SD default mode
5.3.28 RTC characteristics
Table 78. SD / MMC characteristics
Symbol Parameter Conditions Min Max Unit
fPP Clock frequency in data transfer
mode CL ≤ 30 pF 0 48 MHz
- SDIO_CK/fPCLK2 frequency ratio - - 8/3 -
tW(CKL) Clock low time, fPP = 16 MHz CL ≤ 30 pF 32
ns
tW(CKH) Clock high time, fPP = 16 MHz CL ≤ 30 pF 31
trClock rise time CL ≤ 30 pF 3.5
tfClock fall time CL ≤ 30 pF 5
CMD, D inputs (referenced to CK)
tISU Input setup time CL ≤ 30 pF 2
ns
tIH Input hold time CL ≤ 30 pF 0
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV Output valid time CL ≤ 30 pF 6
ns
tOH Output hold time CL ≤ 30 pF 0.3
CMD, D outputs (referenced to CK) in SD default mode(1)
1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output.
tOVD Output valid default time CL ≤ 30 pF 7
ns
tOHD Output hold default time CL ≤ 30 pF 0.5
CK
D, CMD
(output)
tOVD tOHD
ai14888
Table 79. RTC characteristics
Symbol Parameter Conditions Min Max Unit
-fPCLK1/RTCCLK frequency
ratio
Any read/write
operation from/to an
RTC register
4--
STM32F215xx, STM32F217xx Package characteristics
Doc ID 17050 Rev 4 137/158
6 Package characteristics
6.1 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Package characteristics STM32F215xx, STM32F217xx
138/158 Doc ID 17050 Rev 4
Figure 73. LQFP64 – 10 x 10 mm 64 pin low-profile
quad flat package outline(1) Figure 74. Recommended footprint(1)(2)
1. Drawing is not to scale.
2. Dimensions are in millimeters.
A
A2
A1
c
L1
L
EE1
D
D1
e
b
ai14398b
48
3249
64 17
116
1.2
0.3
33
10.3
12.7
10.3
0.5
7.8
12.7
ai14909
Table 80. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 0.200 0.0035 0.0079
D 12.000 0.4724
D1 10.000 0.3937
E 12.000 0.4724
E1 10.000 0.3937
e 0.500 0.0197
θ0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
NNumber of pins
64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
STM32F215xx, STM32F217xx Package characteristics
Doc ID 17050 Rev 4 139/158
Figure 75. LQFP100, 14 x 14 mm 100-pin low-profile
quad flat package outline(1) Figure 76. Recommended footprint(1)(2)
1. Drawing is not to scale.
2. Dimensions are in millimeters.
D
D1
D3
75 51
50
76
100 26
125
E3 E1 E
e
b
Pin 1
identification
SEATING PLANE
GAGE PLANE
C
A
A2
A1
Cccc
0.25 mm
0.10 inch
L
L1
k
C
1L_ME
75 51
5076 0.5
0.3
16.7 14.3
100 26
12.3
25
1.2
16.7
1
ai14906
Table 81. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 0.200 0.0035 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 12.000 0.4724
E 15.80v 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
E3 12.000 0.4724
e 0.500 0.0197
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
k 0°3.5°7° 0°3.5°7°
ccc 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Package characteristics STM32F215xx, STM32F217xx
140/158 Doc ID 17050 Rev 4
Figure 77. LQFP144, 20 x 20 mm, 144-pin low-profile quad
flat package outline(1) Figure 78. Recommended
footprint(1)(2)
1. Drawing is not to scale.
2. Dimensions are in millimeters.
D1
D3
D
E1
E3
E
e
Pin 1
identification
73
72
37
36
109
144
108
1
AA2A1 bc
A1 L
L1
k
Seating plane
C
ccc C
0.25 mm
gage plane
ME_1A
0.5
0.35
19.9
17.85
22.6
1.35
22.6
19.9
a
136
37
72
73108
109
144
Table 82. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 0.200 0.0035 0.0079
D 21.800 22.000 22.200 0.8583 0.8661 0.874
D1 19.800 20.000 20.200 0.7795 0.7874 0.7953
D3 17.500 0.689
E 21.800 22.000 22.200 0.8583 0.8661 0.8740
E1 19.800 20.000 20.200 0.7795 0.7874 0.7953
E3 17.500 0.6890
e 0.500 0.0197
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
k 0°3.5°7° 0°3.5°7°
ccc 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
STM32F215xx, STM32F217xx Package characteristics
Doc ID 17050 Rev 4 141/158
Figure 79. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline
1. Drawing is not to scale.
ccc C
Seating plane
C
AA2
A1 c
0.25 mm
gauge plane
HD
D
A1
L
L1
k
89
88
EHE
45
44
e
1
176
Pin 1
identification
b
133
132
1T_ME
ZD
ZE
Table 83. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.450 0.0531 0.0571
b 0.170 0.270 0.0067 0.0106
c 0.090 0.200 0.0035 0.0079
D 23.900 24.100 0.9409 0.9488
E 23.900 24.100 0.9409 0.9488
e 0.500 0.0197
HD 25.900 26.100 1.0197 1.0276
HE 25.900 26.100 1.0197 1.0276
L(2) 0.450 0.750 0.0177 0.0295
L1 1.000 0.0394
ZD 1.250 0.0492
ZE 1.250 0.0492
k0° 7°0° 7°
ccc 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. L dimension is measured at gauge plane at 0.25 mm above the seating plane.
Package characteristics STM32F215xx, STM32F217xx
142/158 Doc ID 17050 Rev 4
Figure 80. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline
1. Drawing is not to scale.
Seating plane
C
A2
A4
A3
Cddd
A1
A
A
B
eF
D
F
E
e
R
eee MCAB
Cfff
(176 balls)Øb
M
Ø
ØA0E7_ME
Ball A1
A
15 1
Table 84. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A 0.460 0.530 0.610 0.0181 0.0209 0.0240
A1 0.050 0.080 0.110 0.002 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 0.130 0.0051
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.300 0.350 0.400 0.0118 0.0138 0.0157
D 9.950 10.000 10.050 0.3740 0.3937 0.3957
E 9.950 10.000 10.050 0.3740 0.3937 0.3957
e 0.600 0.650 0.700 0.0236 0.0256 0.0276
F 0.400 0.450 0.500 0.0157 0.0177 0.0197
ddd 0.120 0.0047
eee 0.150 0.0059
fff 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
STM32F215xx, STM32F217xx Package characteristics
Doc ID 17050 Rev 4 143/158
6.2 Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
●TA max is the maximum ambient temperature in °C,
●ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
●PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
●PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
Table 85. Package thermal characteristics
Symbol Parameter Value Unit
ΘJA
Thermal resistance junction-ambient
LQFP 64 - 10 × 10 mm / 0.5 mm pitch 45
°C/W
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch 46
Thermal resistance junction-ambient
LQFP144 - 20 × 20 mm / 0.5 mm pitch 40
Thermal resistance junction-ambient
LQFP176 - 24 × 24 mm / 0.5 mm pitch 38
Thermal resistance junction-ambient
UFBGA176 - 10× 10 mm / 0.5 mm pitch 39
Part numbering STM32F215xx, STM32F217xx
144/158 Doc ID 17050 Rev 4
7 Part numbering
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Table 86. Ordering information scheme
Example: STM32 F 215 R E T 6 xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
215 = STM32F21x, connectivity, USB OTG FS/HS,
cryptographic acceleration
217= STM32F21x, connectivity, USB OTG FS/HS,
camera interface, cryptographic acceleration, Ethernet
Pin count
R = 64 pins
V = 100 pins
Z = 144 pins
I = 176 pins
Flash memory size
E = 512 Kbytes of Flash memory
G = 1024 Kbytes of Flash memory
Package
T = LQFP
H = UFBGA
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Options
xxx = programmed parts
TR = tape and reel
STM32F215xx, STM32F217xx Application block diagrams
Doc ID 17050 Rev 4 145/158
Appendix A Application block diagrams
A.1 Main applications versus package
Ta bl e 8 7 gives examples of configurations for each package.
Table 87. Main applications versus package for STM32F20xxx microcontrollers(1)
64 pins 100 pins 144 pins 176 pins
Config
1
Config
2
Config
3
Config
1
Config
2
Config
3
Config
4
Config
1
Config
2
Config
3
Config
4
Config
1
Config
2
USB 1
OTG
FS XXXXXX - X - X - X -
FS XXXXXXXXXXXX -
USB 2
HS
ULPI ---X---XX--XX
OTGFS---X---XX--XX
FS - - - XXXXXXXXXX
Ethernet
MII -----XX--XXXX
RMII----XXXXXXXXX
SPI/I2S2
SPI/I2S3 - X - - XXXXXXXXX
SDIO SDIO
SDIO
or
DCMI
SDIO
or
DCMI
-
SDIO
or
DCMI
SDIO
or
DCMI
SDIO
or
DCMI
X
SDIO
or
DCMI
X
SDIO
or
DCMI
XXX
DCMI
8-bit
Data - X X XXX
10-bit
Data - X X XXX
12-bit
Data - X X XXX
14-bit
Data --------X-XXX
FSMC
NOR/
RAM
Muxed
- - - XXXXXXXXXX
NOR/
RAM - - - XXXXXX
NAND - - - X X X*22 X*19 XX*
19 X*22 X*19 X*22 X*22
CF -------XXXXXX
CAN - XX - XXX - - XX - X
1. X*y: FSMC address limited to “y”.
Application block diagrams STM32F215xx, STM32F217xx
146/158 Doc ID 17050 Rev 4
A.2 Application example with regulator OFF
Figure 81. Regulator OFF/internal reset ON
1. This mode is available only on UFBGA176.
A.3 USB OTG full speed (FS) interface solutions
Figure 82. USB OTG FS peripheral-only connection
2%'/&&
6#!0?
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6#!0?
0! .234
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6
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6
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STM32F215xx, STM32F217xx Application block diagrams
Doc ID 17050 Rev 4 147/158
Figure 83. USB OTG FS host-only connection
1. STMPS2141STR/STULPI01B needed only if the application has to support a VBUS powered device. A
basic power switch can be used if 5 V are available on the application board.
Figure 84. OTG FS connection dual-role with internal PHY
1. External voltage regulator only needed when building a VBUS powered device.
2. STMPS2141STR/STULPI01B needed only if the application has to support a VBUS powered device. A
basic power switch can be used if 5 V are available on the application board.
3. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance
thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
34-&XX
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Application block diagrams STM32F215xx, STM32F217xx
148/158 Doc ID 17050 Rev 4
A.4 USB OTG high speed (HS) interface solutions
Figure 85. USB OTG HS peripheral-only connection in FS mode
Figure 86. USB OTG HS host-only connection in FS mode
1. STMPS2141STR/STULPI01B needed only if the application has to support a VBUS powered device. A
basic power switch can be used if 5 V are available on the application board.
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STM32F215xx, STM32F217xx Application block diagrams
Doc ID 17050 Rev 4 149/158
Figure 87. OTG HS connection dual-role with external PHY
1. It is possible to use MCO1 or MCO2 to save a crystal. It is however not mandatory to clock the STM32F21x
with a 24 or 26 MHz crystal when using USB HS. The above figure only shows an example of a possible
connection.
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-#/OR-#/
OR-(Z84
0,, 84
8)
AIB
#ASEOFAN3-3#
WHICHREQUIRED-(Z
Application block diagrams STM32F215xx, STM32F217xx
150/158 Doc ID 17050 Rev 4
A.5 Complete audio player solutions
Two solutions are offered, illustrated in Figure 88 and Figure 89.
Figure 88 shows storage media to audio DAC/amplifier streaming using a software Codec.
This solution implements an audio crystal to provide audio class I2S accuracy on the master
clock (0.5% error maximum, see the Serial peripheral interface section in the reference
manual for details).
Figure 88. Complete audio player solution 1
Figure 89 shows storage media to audio Codec/amplifier streaming with SOF
synchronization of input/output audio streaming using a hardware Codec.
Figure 89. Complete audio player solution 2
1. SOF = start of frame.
Cortex-M3 core
up to 120 MHz
OTG
(host
mode) +
PHY
SPI
SPI
GPIO
I2S
XTAL
25 MHz
or 14.7456 MHz
USB
Mass-storage
device
MMC/
SDCard
LCD
touch
screen
Control
buttons
DAC +
Audio
ampli
File
System
Program memory
Audio
CODEC
User
application
ai16039b
Cortex-M3 core
up to 120 MHz
OTG
+
PHY
SPI
SPI/
FSMC
GPIO
I2S
USB
Mass-storage
device
MMC/
SDCard
LCD
touch
screen
Control
buttons
Audio
ampli
File
System
Program memory
Audio PLL
+DAC
User
application
ai16040b
SOF
SOF synchronization of input/output
audio streaming
XTAL
25 MHz
or 14.7456 MHz
STM32F215xx, STM32F217xx Application block diagrams
Doc ID 17050 Rev 4 151/158
Figure 90. Audio player solution using PLL, PLLI2S, USB and 1 crystal
Figure 91. Audio PLL (PLLI2S) providing accurate I2S clock
/4'
-(Z
0(9
84!,
-(Z
OR-(Z
AIB
)3
ACCURACY
$!#
!UDIO
AMPLI
-#,+OUT
3#,+
-#/
-#/
0,,)3
X.
0,,
X.
/3#
$IV
BY-
$IV
BY0
$IV
BY1
UPTO
-(Z
#ORTEX-CORE
UPTO-(Z
$IV
BY2
-#,+
IN
-#/02%
-#/02%
I2S CTL
I2S_MCK = 256 × F
SAUDIO
11.2896 MHz for 44.1 kHz
12.2880 MHz for 48.0 kHz
I2S_MCK
PLLI2S
/M
M=1,2,3,..,64
1 MHz 192 to 432 MHz
N=192,194,..,432
I2SCOM_CK
PhaseC
VCO
/N
/R
CLKIN
Phase lock detector
R=2,3,4,5,6,7 I2SD=2,3,4.. 129
ai16041b
Application block diagrams STM32F215xx, STM32F217xx
152/158 Doc ID 17050 Rev 4
Figure 92. Master clock (MCK) used to drive the external audio DAC
1. I2S_SCK is the I2S serial clock to the external audio DAC (not to be confused with I2S_CK).
Figure 93. Master clock (MCK) not used to drive the external audio DAC
1. I2S_SCK is the I2S serial clock to the external audio DAC (not to be confused with I2S_CK).
I2S_CK
I2S controller
I2S_MCK = 256 × F
SAUDIO
= 11.2896 MHz for F
SAUDIO
= 44.1 kHz
= 12.2880 MHz for F
SAUDIO
= 48.0 kHz
/(2 x 16)/8
/I2SD
F
SAUDIO
I2S_SCK
(1)
= I2S_MCK/8 for 16-bit stereo
for 16-bit stereo
/(2 x 32)/4
for 32-bit stereo
F
SAUDIO
2,3,4,..,129
= I2S_MCK/4 for 32-bit stereo
ai16042
I2SCOM_CK
I2S controller
/(2 x 16)
/I2SD
F
SAUDIO
I2S_SCK
(1)
for 16-bit stereo
/(2 x 32)
for 32-bit stereo
F
SAUDIO
ai16042
STM32F215xx, STM32F217xx Revision history
Doc ID 17050 Rev 4 153/158
Revision history
Table 88. Document revision history
Date Revision Changes
02-Feb-2010 1 Initial release.
13-Jul-2010 2
Updated datasheet status to PRELIMINARY DATA.
Renamed high-speed SRAM, system SRAM.
Added UFBGA176 package, and note 1 related to LQFP176 package
in Ta b l e 2 , Figure 11, and Ta b l e 8 6 .
Added information on ART accelerator and audio PLL (PLLI2S).
Added Table 4: USART feature comparison.
Several updates on Table 5: STM32F21x pin and ball definitions and
Table 6: Alternate function mapping. ADC, DAC, oscillator, RTC_AF,
WKUP and VBUS signals removed from alternate functions and
moved to the “other functions” column in Table 5: STM32F21x pin and
ball definitions.
TRACESWO added in Figure 4: STM32F21x block diagram, Ta bl e 5 :
STM32F21x pin and ball definitions, and Table 6: Alternate function
mapping.
XTAL oscillator frequency updated on cover page, in Figure 4:
STM32F21x block diagram and in Section 2.2.12: External
interrupt/event controller (EXTI).
Updated list of peripherals used for boot mode in Section 2.2.14: Boot
modes.
Added Regulator bypass mode in Section 2.2.17: Voltage regulator,
and Section 5.3.4: Operating conditions at power-up / power-down
(regulator OFF).
Updated Section 2.2.18: Real-time clock (RTC), backup SRAM and
backup registers.
Added Note Note: in Section 2.2.19: Low-power modes.
Added SPI TI protocol in Section 2.2.28: Serial peripheral interface
(SPI).
Updated Section 2.2.33: Universal serial bus on-the-go full-speed
(OTG_FS), and Section 2.2.34: Universal serial bus on-the-go high-
speed (OTG_HS).
Added Section 5: Electrical characteristics, and Section 6.2: Thermal
characteristics.
Updated Table 83: LQFP176 - Low profile quad flat package 24 × 24 ×
1.4 mm package mechanical data and Figure 79: LQFP176 - Low
profile quad flat package 24 × 24 × 1.4 mm, package outline.
Added Table 87: Main applications versus package for STM32F20xxx
microcontrollers in A.1: Main applications versus package. Updated
figures in Appendix A.3: USB OTG full speed (FS) interface solutions
and A.4: USB OTG high speed (HS) interface solutions. Updated
Figure 90: Audio player solution using PLL, PLLI2S, USB and 1 crystal
and Figure 91: Audio PLL (PLLI2S) providing accurate I2S clock.
Added random number generation feature. Added trademark for ART
accelerator and updated Section 2.2.3: Adaptive real-time memory
accelerator (ART Accelerator™).
Revision history STM32F215xx, STM32F217xx
154/158 Doc ID 17050 Rev 4
25-Nov-2010 3
Added WLCSP66 (64+2) package. Added note 1 related to LQFP176
on cover page.
Update I/Os in Section : Features.
Updated Table 5: Multi-AHB matrix.
Added case of BOR inactivation using IRROFF on WLCSP devices in
Section 2.2.16: Power supply supervisor.
Reworked Section 2.2.17: Voltage regulator to clarify regulator off
modes. Added Section 2.2.20: VBAT operation.
Modified VDD_3 pin in Table 5: STM32F21x pin and ball definitions, and
added note related to the FSMC_NL pin.
Renamed BYPASS-REG REGOFF, and add IRROFF pin.
Changed VSS_SA to VSS, and VDD_SA pin reserved for future use.
Updated maximum HSE crystal frequency to 26 MHz.
USART4/5 renamed UART4/5. USART4 pins renamed UART4 in
Table 5: STM32F21x pin and ball definitions. Updated LIN and IrDA
features for UART4/5 in Table 4: USART feature comparison.
Section 5.2: Absolute maximum ratings: Updated VIN minimum and
maximum values and note for non-five-volt tolerant pins in Ta bl e 7 :
Voltage characteristics. Updated IINJ(PIN) maximum values and related
notes in Table 8: Current characteristics.
Updated VDDA minimum value in Table 10: General operating
conditions.
Added Note 2 and updated Maximum CPU frequency in Ta bl e 1 1:
Limitations depending on the operating power supply range; and
added Figure 18: Number of wait states versus fCPU and VDD range.
Renamed Brownout Low, medium and High reset thresholds,
Renamed VBORL/VBORM/VBORH, VBOR1/VBOR2/VBOR3 in Table 14:
Embedded reset and power control block characteristics.
Changed fLSI typical value in Table 28: LSI oscillator characteristics.
Added Figure 32: ACCLSI versus temperature.
Changed fOSC_IN maximum value in Table 25: HSE 4-26 MHz oscillator
characteristics.
Changed fPLL_IN maximum value in Table 29: Main PLL characteristics,
and updated jitter parameters in Table 30: PLLI2S (audio PLL)
characteristics.
Section 5.3.16: I/O port characteristics: updated VIH and VIL in
Table 41: I/O static characteristics.
Added Note 1 below Table 42: Output voltage characteristics.
Updated RPD and RPU parameter description in Table 52: USB OTG
FS DC electrical characteristics.
Updated VREF+ minimum value in Table 61: ADC characteristics.
Updated Table 66: Embedded internal reference voltage.
Removed Ethernet and USB2 for 64-pin devices in Ta ble 8 7 : M a i n
applications versus package for STM32F20xxx microcontrollers.
Added A.2: Application example with regulator OFF, removed “OTG
FS connection with external PHY” figure, updated Figure 83,
Figure 84, and Figure 86 to add STULPI01B.
Table 88. Document revision history (continued)
Date Revision Changes
STM32F215xx, STM32F217xx Revision history
Doc ID 17050 Rev 4 155/158
22-Apr-2011 4
Changed datasheet status to “Full Datasheet”.
APB1 frequency changed form 36 MHz to 30 MHz.
Introduced concept of SRAM1 and SRAM2.
LQFP176 now in production.
Removed WLCSP64+2 package.
Updated Figure 1: Compatible board design: LQFP144 and Figure 2:
Compatible board design: LQFP100.
Added camera interface for STM32F217Vx devices in Ta bl e 2 :
STM32F215xx and STM32F217xx: features and peripheral counts.
Removed 16 MHz internal RC oscillator accuracy in Section 2.2.13:
Clocks and startup.
Updated Section 2.2.17: Voltage regulator.
Modified I2S sampling frequency range in Section 2.2.13: Clocks
and startup, Section 2.2.29: Inter-integrated sound (I2S), and
Section 2.2.35: Audio PLL (PLLI2S).
Updated Section 2.2.18: Real-time clock (RTC), backup SRAM and
backup registers and description of TIM2 and TIM5 in Section :
General-purpose timers (TIMx).
Modified maximum baud rate (oversampling by 16) for USART1 in
Table 4: USART feature comparison.
Updated note related to RFU pin below Figure 9: STM32F21x
LQFP100 pinout, Figure 10: STM32F21x LQFP144 pinout, Figure 11:
STM32F21x LQFP176 pinout, Figure 12: STM32F21xxx UFBGA176
ballout, and Table 5: STM32F21x pin and ball definitions.
Added RTC_50Hz as PB15 alternate function, and TT (3.6 V tolerant
I/O) in Table 5: STM32F21x pin and ball definitions and Tab l e 6 :
Alternate function mapping.
PA15 added in Table 5: STM32F21x pin and ball definitions.
In Table 5: STM32F21x pin and ball definitions, changed I2S2_CK and
I2S3_CK to I2S2_SCK and I2S3_SCK, respectively.
Removed
ETH _RMII_TX_CLK for PC3/AF11 in
Table 6: Alternate
function mapping.
Updated Table 7: Voltage characteristics and Table 8: Current
characteristics.
TSTG updated to –65 to +150 in Table 9: Thermal characteristics.
Added CEXT and ESR in Table 10: General operating conditions as
well as Section 5.3.2: VCAP1/VCAP2 external capacitor.
Modified Note 3 in Table 11: Limitations depending on the operating
power supply range.
Updated Table 12: Operating conditions at power-up / power-down
(regulator ON), and Table 13: Operating conditions at power-up /
power-down (regulator OFF).
Added OSC_OUT pin in Figure 14: Pin loading conditions. and
Figure 15: Pin input voltage.
Updated notes below Figure 14: Pin loading conditions.
Updated VPVD, VBOR1, VBOR2, VBOR3, TRSTTEMPO typical value, and
IRUSH, added ERUSH and Note 3 in Table 14: Embedded reset and
power control block characteristics.
Table 88. Document revision history (continued)
Date Revision Changes
Revision history STM32F215xx, STM32F217xx
156/158 Doc ID 17050 Rev 4
22-Apr-2011 4
(continued)
Updated Typical and maximum current consumption conditions, as
well as Table 15: Typical and maximum current consumption in Run
mode, code with data processing running from Flash memory (ART
accelerator disabled) and Table 16: Typical and maximum current
consumption in Run mode, code with data processing running from
Flash memory (ART accelerator enabled) or RAM. Added Figure 20,
Figure 21, Figure 22, and Figure 23.
Updated Table 17: Typical and maximum current consumption in Sleep
mode, and added Figure 24 and Figure 25.
Updated Table 19: Typical and maximum current consumptions in
Standby mode and Table 20: Typical and maximum current
consumptions in VBAT mode.
Updated Table 18: Typical and maximum current consumptions in Stop
mode. Added Figure 26: Typical current consumption vs temperature
in Stop mode.
Updated Table 19: Typical and maximum current consumptions in
Standby mode and Table 20: Typical and maximum current
consumptions in VBAT mode.
Updated On-chip peripheral current consumption conditions and
Table 21: Peripheral current consumption.
Updated tWUSTDBY and tWUSTOP
, and added Note 3 in Table 22: Low-
power mode wakeup timings.
Maximum fHSE_ext and minimum tw(HSE) values updated in Ta bl e 23:
High-speed external user clock characteristics.
Updated C and gm in Table 25: HSE 4-26 MHz oscillator
characteristics. Updated RF
, I2, gm, and tsu(LSE) in Table 26: LSE
oscillator characteristics (fLSE = 32.768 kHz).
Added Note 3 and updated ACCHSI, IDD(HSI) and tsu(HSI) in Table 27:
HSI oscillator characteristics. Added Figure 31: ACCHSI versus
temperature
Updated fLSI, tsu(LSI) and IDD(LSI) in Table 28: LSI oscillator
characteristics.
Table 29: Main PLL characteristics: removed note 1, updated tLOCK,
jitter, IDD(PLL) and IDDA(PLL) , added Note 2 for fPLL_IN minimum and
maximum values.
Table 30: PLLI2S (audio PLL) characteristics: removed note 1, updated
tLOCK, jitter, IDD(PLLI2S) and IDDA(PLLI2S) , added Note 3 for fPLLI2S_IN
minimum and maximum values.
Added Note 1 in Table 31: SSCG parameters constraint.
Updated Table 32: Flash memory characteristics. Modified Ta ble 3 3 :
Flash memory programming and added Note 2 for tprog. Updated tprog
and added Note 2 in Table 34: Flash memory programming with VPP.
Modified Figure 36: Recommended NRST pin protection.
Updated Table 37: EMI characteristics and EMI monitoring conditions
in Section : Electromagnetic Interference (EMI).
Added Note 2 related to VESD(HBM)in Table 38: ESD absolute
maximum ratings.
Added Section 5.3.15: I/O current injection characteristics.
Updated Table 41: I/O static characteristics. Modified maximum
frequency values and conditions in Table 43: I/O AC characteristics.
Table 88. Document revision history (continued)
Date Revision Changes
STM32F215xx, STM32F217xx Revision history
Doc ID 17050 Rev 4 157/158
22-Apr-2011 4
(continued)
Updated tres(TIM) in Table 45: Characteristics of TIMx connected to the
APB1 domain. Modified tres(TIM) and fEXT Table 46: Characteristics of
TIMx connected to the APB2 domain.
Changed tw(SCKH) to tw(SCLH), tw(SCKL) to tw(SCLL), tr(SCK) to tr(SCL), and
tf(SCK) to tf(SCL) in Table 47: I2C characteristics and Figure 37: I2C bus
AC waveforms and measurement circuit.
Added Table 52: USB OTG FS DC electrical characteristics and
updated Table 53: USB OTG FS electrical characteristics.
Updated VDD minimum value in Table 57: Ethernet DC electrical
characteristics.
Updated Table 61: ADC characteristics and RAIN equation.
Updated RAIN equation. Updated Table 63: DAC characteristics.
Updated tSTART in Table 64: TS characteristics.
Updated Table 66: Embedded internal reference voltage.
Modified FSMC_NOE waveform in Figure 53: Asynchronous non-
multiplexed SRAM/PSRAM/NOR read waveforms. Shifted end of
FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK
period, changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL-
AIV), td(CLKH-NOEH) to td(CLKL-NOEH), and td(CLKH-NWEH) to td(CLKL-
NWEH), and updated data latency from 1 to 0 in Figure 57:
Synchronous multiplexed NOR/PSRAM read timings, Figure 58:
Synchronous multiplexed PSRAM write timings, Figure 59:
Synchronous non-multiplexed NOR/PSRAM read timings, and
Figure 60: Synchronous non-multiplexed PSRAM write timings,
Changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL-AIV),
td(CLKH-NOEH) to td(CLKL-NOEH), td(CLKH-NWEH) to td(CLKL-NWEH), and
modified tw(CLK) minimum value in Ta b l e 7 1 , Ta b l e 7 2 , Ta b l e 7 3 , and
Ta bl e 7 4 .
Updated R typical value in Table 65: VBAT monitoring
characteristics.Updated note 2 in Ta b l e 6 7 , Ta bl e 6 8 , Ta bl e 6 9 ,
Ta bl e 7 0 , Ta b l e 7 1 , Ta ble 72, Ta bl e 7 3 , and Ta bl e 7 4 .
Modified th(NIOWR-D) in Figure 66: PC Card/CompactFlash controller
waveforms for I/O space write access.
Modified FSMC_NCEx signal in Figure 67: NAND controller
waveforms for read access, Figure 68: NAND controller waveforms for
write access, Figure 69: NAND controller waveforms for common
memory read access, and Figure 70: NAND controller waveforms for
common memory write access.
Specified Full speed (FS) mode for Figure 85: USB OTG HS
peripheral-only connection in FS mode and Figure 86: USB OTG HS
host-only connection in FS mode.
Table 88. Document revision history (continued)
Date Revision Changes
STM32F215xx, STM32F217xx
158/158 Doc ID 17050 Rev 4
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