DESCRIPTION
The 38C1 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 38C1 group has the LCD drive control circuit, an 8-channel A-
D converter, and serial I/O as additional functions.
The various microcomputers in the 38C1 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
FEATURES
•Basic machine-language instructions....................................... 71
•The minimum instruction execution time............................ 0.5 µs
(at 8 MHz oscillation frequency)
•Memory size
ROM ................................................................ 1 6 K t o 2 4 K bytes
RAM ................................................................... 384 to 512 bytes
•Programmable input/output ports (Ports P2–P6) ..................... 30
•Segment output pin/Input port (Port P0) ....................................... 8
•Software pull-up/pull-down resistor....................... Ports P0, P2–P6
•Interrupts .................................................. 13 sources, 13 vectors
(includes key input interrupt)
•Timers ........................................................... 8-bit ✕ 3, 16-bit ✕ 2
•Serial I/O ...................................... 8-bit ✕ 1 (Clock-synchronous)
•A-D converter .................................................. 8-bit ✕ 8 channels
(It can be used in the low-speed mode.)
•LCD drive control circuit
Bias ............................................................................1/1, 1/2, 1/3
Duty ................................................................ Static, 1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output......................................................................... 25
•Main clock generating circuit ...................................................... 1
(connect to external ceramic resonator or built-in ring oscillator)
•Sub clock generating circuit........................................................ 1
(connect to external quartz-crystal oscillator)
•Power source voltage
In high-speed mode (f(XIN) ≤ 8.0 MHz) ..................... 4.0 to 5.5 V
In middle-speed mode (Mask ROM version: f(XIN) ≤ 6.0 MHz)
.................................................................................... 1.8 to 5.5 V
In middle-speed mode (One Time PROM version: f(X
IN
) ≤ 6.0 MHz)
.................................................................................... 2.2 to 5.5 V
In low-speed mode (Mask ROM version) .................. 1.8 to 5.5 V
In low-speed mode (One Time PROM version) ........ 2.2 to 5.5 V
•Power dissipation (Mask ROM version)
In high-speed mode (frequency divided by 2)...........Typ. 15 mW
(VCC = 5 V, f(XIN) = 8 MHz , Ta = 25 °C)
In low-speed mode......................................................Typ. 18 µW
(VCC = 2.5 V, f(XIN) = stop , f(XCIN) = 32 kHz , Ta = 25 °C)
•Operating temperature range ...................................– 2 0 t o 85°C
APPLICATIONS
Household appliances, consumer electronics, etc.
38C1 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
2
Fig. 1 Pin configuration of M38C1XMX-XXXFP/HP
PIN CONFIGURATION (TOP VIEW)
Outline 64P6U-A/64P6Q-A
P
34(
L
E
D4)
/
(
K
W4)
6
1
3
2
3
1
3
0
2
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2
7
2
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25
2
4
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1
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2
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51/
I
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T1
P
56/
S
CLK
P
55/
S
OUT
P
54/
S
IN
P
53/
C
N
T
R1
4
9
5
0
5
1
5
2
5
3
6
2
64
12345
20
1
9
1
8
1
7
5
5
5
6
5
7
5
8
59
60
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32/
(
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30/(LED0)/(KW0)
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2
VL
1
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04/
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06/
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G8
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G9
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0
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G1
2
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G1
3
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G1
4
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G1
5
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1
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N
63
P
27/
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63
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8394041424
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64
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P
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7
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23/
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P
21/
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8
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22/
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P
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AN3/ADKEY3
P
64
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6
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P
33(
L
E
D3)
/
(
K
W3)
P
01/
S
E
G
1
P
03/
S
E
G3
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
3
FUNCTIONAL BLOCK DIAGRAM
Fig. 2 Functional block diagram
I
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φ
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
4
PIN DESCRIPTION
Table 1 Pin description
FunctionPin Name Function except a port function
• Apply voltage of power source to VCC, and 0 V to VSS.
(As for VCC, refer to the recommended operating condition)
• Connect to Vss.
• Reset input pin for active “L”.
• Input and output pins for the main clock generating circuit.
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
A feedback resistor is built-in.
• Input 0 ≤ VL1 ≤ VL2 < VL3 voltage.
• LCD common output pins.
• 8-bit input port.
• CMOS compatible input level.
•
1, 2, 4 or 8-bit input and 8-bit pull-down can be programmed.
• LCD segment output pin.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• 1-bit input/output and pull-down can be programmed.
• 5-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• 1-bit input/output and pull-up can be programmed.
• Analog input pins for A-D converter.
When these pins are used as ADKEY pins, the input
voltage of ADKEY pin which is input “L” level is A-D
converted automatically.
• 4-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• 1-bit input/output and pull-up can be programmed.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• 1-bit input/output and pull-up can be programmed.
• 5-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• 1-bit input/output and pull-up can be programmed.
Power source
CNVSS
Reset input
Clock input
VCC, VSS
CNVSS
RESET
XIN
XOUT
VL1–VL3
COM
0
–COM
3
P00/SEG0–
P07/SEG7
SEG
8
–/SEG
16
P20/SEG17–
P27/SEG24
P3
0
(LED)/KW
0
–
P3
4
(LED)/KW
4
AN
0
/ADKEY
0
–
AN3/ADKEY3
P44/AN4–
P47/AN7
P50/INT0,
P51/INT1
P52/CNTR0
P53/CNTR1
P54/SIN
P55/SOUT
P56/SCLK
P57/SRDY
P60/XCIN
P61/XCOUT
P62/TOUT
P63/φOUT
P64
Clock output
LCD power source
Common output
Input port P0
Segment output pin
I/O port P2
I/O port P3
Analog input
I/O port P4
I/O port P5
I/O port P6
• LCD segment output pins
• LCD segment output pins
• Key input (key-on wake-up) interrupt
input pins
• ADKEY input pins
• Analog input pins for A-D converter
• Interrupt input pins
• Timer X, timer Y function pins
• Serial I/O function pins
• Sub-clock generating circuit I/O pins
(Oscillator is connected.
External clock cannot be input directly.)
Timer 2 output pin
System clock φ output
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
5
PART NUMBERING
Fig. 3 Part numbering
M
3
8
C
1
3M6
-
X
X
XF
P
P
r
o
d
u
c
t
R
O
M
/
P
R
O
M
s
i
z
e
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
: 4096
b
ytes
: 8192 byt es
: 12288 byt es
: 16384 byt es
: 20480 byt es
: 24576 byt es
: 28672 byt es
: 32768 byt es
: 36864 byt es
: 40960 byt es
: 45056 byt es
: 49152 byt es
: 53248 byt es
: 57344 byt es
: 61440 byt es
T
h
e
f
i
r
s
t
1
2
8
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.
P
a
c
k
a
g
e
t
y
p
e
F
P
H
P: 64P6U-A pac kage
: 64P6Q-A package
ROM
num
b
er
Omitted in One Time PROM version.
M
emory type
M: Ma sk RO M v ersion
E: One Tim e PROM version
R
A
M
s
i
z
e
0
1
2
3
4
5
6
7
8
9
: 192
b
ytes
: 256 byte s
: 384 byte s
: 512 byte s
: 640 byte s
: 768 byte s
: 896 byte s
: 1024 byt es
: 1536 byt es
: 2048 byt es
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
6
GROUP EXPANSION
Mitsubishi plans to expand the 38C1 group as follows.
Memory Type
Support for Mask ROM version, One Time PROM version.
Memory Size
ROM/PROM size ............................................... 16 K to 2 4 K bytes
RAM size .............................................................. 384 to 512 bytes
Packages
64P6Q-A .................................... 0.5 mm-pitch plastic molded QFP
64P6U-A .................................... 0.8 mm-pitch plastic molded QFP
Fig. 4 Memory expansion plan
Currently products are listed below.
Table 2. List of products As of May. 2002
Remarks
Mask ROM version
One Time PROM version (shipped in blank)
Package
64P6U-A
64P6Q-A
64P6U-A
64P6Q-A
64P6U-A
64P6Q-A
Product
M38C12M4-XXXFP
M38C12M4-XXXHP
M38C13M6-XXXFP
M38C13M6-XXXHP
M38C13E6FP
M38C13E6HP
RAM size (bytes)
384
16384
(16256)
24576
(24446)
ROM size (bytes)
ROM size for User in ( )
512
32K
2
8
K
2
4
K
20K
1
6
K
12K
8K
4K
2
5
63
8
45
1
2 640 7
6
8 896 1024
1
9
2
48K
R
O
M
s
i
z
e
(
b
y
t
e
s
)
R
A
M
s
i
z
e
(
b
y
t
e
s
)
Products under development or planning :the development schedule and specification may be revised without notice.
M38C13M6/E6
M38C12M4
U
n
d
e
r
d
e
v
e
l
o
p
m
e
n
t
Under development
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
7
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 38C1 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0” , the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with pro-
gram when the user needs them during interrupts or subroutine
calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
Fig. 5 740 Family CPU register structure
A Accumulator
b7
b7
b7
b7 b0
b7b15 b0
b7 b0
b0
b0
b0
X Index register X
Y Index register Y
S Stack pointer
PCLProgram counterPCH
N V T B D I Z C Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
8
Table 3 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Fig. 6 Register push and pop at interrupt generation and subroutine call
Note: Condition for acceptance of an interrupt Interrupt enable flag is “1”
E
x
e
c
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e
J
S
R
On-going Routin
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M (S) (PCH)
(
S
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S
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M
(
S
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P
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S
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(
S
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(
S
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(
S
)
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(
S
)
(
S
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(
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(S)
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(S)
(S) + 1
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r
r
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p
t
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e
r
v
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R
o
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n
e
POP conten ts of
processor status
register from stack
M (S) (PCH)
(S)
(S) – 1
M (S) (PCL)
(S)
(S) – 1
(PCL)M (S)
(S)
(S) + 1
(S)
(S) + 1
(PCH)M (S)
POP return
address
from stack
I Flag is set from “0” to “1”
Fetch the jump vector
Push return address
on stack
Push contents of processor
status register on stack
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
(Note)
Interrupt disable flag is “0”
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
9
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
• Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arith-
metic logic unit (ALU) immediately after an arithmetic operation.
It can also be changed by a shift or rotate instruction.
• Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
• Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt gener-
ated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
• Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed
when this flag is “0”; decimal arithmetic is executed when it is
“1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
• Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was gen-
erated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
• Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed be-
tween accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled be-
tween memory locations.
• Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location op-
erated on by the BIT instruction is stored in the overflow flag.
• Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7
of the memory location operated on by the BIT instruction is
stored in the negative flag.
Table 4 Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
C flag
SEC
CLC
Z flag
–
–
I flag
SEI
CLI
D flag
SED
CLD
B flag
–
–
T flag
SET
CLT
V flag
–
CLV
N flag
–
–
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
10
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
After system is released from reset, the ring oscillator mode is se-
lected, and the XIN–XOUT oscillation and the XCIN–XCOUT
oscillation are stopped.
Fig. 7 Structure of CPU mode register
N
ot ava
il
a
bl
e
P
roc essor mo
d
e
bi
ts
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Main clock selection bit
0 : XIN input signal (XIN–XOUT oscillating)
1 : Bui lt - in ring os cillat or
(in t ernal system clock: only frequency divided by 8 is valid.)
Port Xc switch bit
0 : I/O po rt fun c tion (Oscillati on stop)
1 : XCIN–XCOUT osc illating function
XIN–XOUT oscil lati on st op bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
(th is bit is invalid when ring oscillato r is s ele c ted. )
0 : f(XIN)/2 (high-speed mode)
1 : f(XIN)/8 (middle-speed mode)
Internal system clock selection bit
0 : Main clock selected (middle-/high-speed, ring oscillator mode)
1 : XCIN–XCOUT selected (low-speed mode)
CPU
mo
d
e reg
i
ster
(
C
P
U
M
:
a
d
d
r
e
s
s
0
0
3
B
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
6
8
1
6
)
b
7
b
0
Fig. 8 Switching method of CPU mode register
N
Y
A
f
t
e
r
r
e
l
e
a
s
i
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g
r
e
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i
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t
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b
i
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4
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C
P
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S
w
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a
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c
t
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b
i
t
s
(
b
i
t
6
o
f
C
P
U
M
)
M
a
i
n
r
o
u
t
i
n
e
Start with a built -in r ing oscill ator.
Initial value of CPUM is 6816.
As for the details of condition for
transi tion among each mode,
refer to the state transition of system clock.
O
s
c
i
l
l
a
t
o
r
s
t
a
r
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a
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m
c
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k
(
b
i
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3
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y
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t
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b
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.
S
e
l
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c
t
i
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t
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r
n
a
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s
y
s
t
e
m
c
l
o
c
k
.
D
o
n
o
t
c
h
a
n
g
e
b
i
t
3
a
n
d
b
i
t
7
,
o
r
b
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6
a
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d
b
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7
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a
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a
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.
S
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c
t
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a
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d
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r
a
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.
S
w
i
t
c
h
t
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-
s
p
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m
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e
,
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f
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c
e
s
s
a
r
y
.
When the low-, middle- or high-speed mode is used after the XIN–
XOUT oscillation and the XCIN–XCOUT oscillation are enabled, wait
in the ring oscillator mode until oscillation stabilizes, and then,
switch the operation mode.
When the middle- and high-speed mode are not used (XIN-XOUT
oscillation and external clock input are not performed), connect
XIN to VCC through a resistor.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
11
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac-
cess to this area with only 2 bytes is possible in the special page
addressing mode.
Fig. 9 Memory map diagram
1
9
2
2
5
6
3
8
4
5
1
2
6
4
0
7
6
8
8
9
6
1
0
2
4
1
5
3
6
2
0
4
8
00
FF
16
013F
16
01BF
16
023F
16
02BF
16
033F
16
03BF
16
043F
16
063F
16
083F
16
R
A
M
a
r
e
a
R
A
M
s
i
z
e
(
b
y
t
e
s
)
A
d
d
r
e
s
s
X
X
X
X
1
6
4
0
9
6
8
1
9
2
1
2
2
8
8
1
6
3
8
4
2
0
4
8
0
2
4
5
7
6
2
8
6
7
2
3
2
7
6
8
3
6
8
6
4
4
0
9
6
0
4
5
0
5
6
4
9
1
5
2
5
3
2
4
8
5
7
3
4
4
6
1
4
4
0
F
0
0
0
1
6
E
0
0
0
1
6
D
0
0
0
1
6
C
0
0
0
1
6
B
0
0
0
1
6
A
0
0
0
1
6
9
0
0
0
1
6
8
0
0
0
1
6
7
0
0
0
1
6
6
0
0
0
1
6
5
0
0
0
1
6
4
0
0
0
1
6
3
0
0
0
1
6
2
0
0
0
1
6
1
0
0
0
1
6
F
0
8
0
1
6
E
0
8
0
1
6
D
0
8
0
1
6
C
0
8
0
1
6
B
0
8
0
1
6
A
0
8
0
1
6
9
0
8
0
1
6
8
0
8
0
1
6
7
0
8
0
1
6
6
0
8
0
1
6
5
0
8
0
1
6
4
0
8
0
1
6
3
0
8
0
1
6
2
0
8
0
1
6
1
0
8
0
1
6
ROM
area
ROM
s
i
ze
(bytes)
A
d
d
r
e
s
s
Y
Y
Y
Y
1
6
A
d
d
r
e
s
s
Z
Z
Z
Z
1
6
0100
16
0000
16
0040
16
0440
16
FF
00
16
FFDC
16
F
F
F
E
1
6
FFFF
16
XXXX
16
YYYY
16
ZZZZ
16
RAM
R
O
M
R
eserve
d
area
S
F
R
a
r
e
a
N
ot use
d
(N
ote
)
I
n
t
e
r
r
u
p
t
v
e
c
t
o
r
a
r
e
a
R
eserve
d
ROM
area
(128 bytes )
Z
e
r
o
p
a
g
e
S
p
e
c
i
a
l
p
a
g
e
R
e
s
e
r
v
e
d
R
O
M
a
r
e
a
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
12
Fig. 10 Memory map of special function register (SFR)
0
0
0
01
60
0
2
01
6
0
0
0
11
60
0
2
11
6
0
0
0
21
60
0
2
21
6
0
0
0
31
60
0
2
31
6
0
0
0
41
60
0
2
41
6
0
0
0
51
60
0
2
51
6
0
0
0
61
60
0
2
61
6
0
0
0
71
60
0
2
71
6
0
0
0
81
60
0
2
81
6
0
0
0
91
60
0
2
91
6
0
0
0
A1
60
0
2
A1
6
φ output con trol registe r
0
0
0
B1
60
0
2
B1
6
0
0
0
C1
60
0
2
C1
6
T
e
m
p
o
r
a
r
y
d
a
t
a
r
e
g
i
s
t
e
r
1
(
T
D
0
)
000D16 002D16
Temporary data r egister 2 (TD 1)
0
0
0
E1
60
0
2
E1
6
T
e
m
p
o
r
a
r
y
d
a
t
a
r
e
g
i
s
t
e
r
3
(
T
D
2
)
0
0
0
F1
60
0
2
F1
6
R
R
F
r
e
g
i
s
t
e
r
(
R
R
F
)
001016
LCD dis play regis ter 0(LCD
0
)
003016
0
0
1
11
6
LCD dis play regis ter 1(LCD
1
)
0
0
3
11
6
0
0
1
21
60
0
3
21
6
001316 003316
0
0
1
41
60
0
3
41
6
001516 003516
0
0
1
61
60
0
3
61
6
0
0
1
71
60
0
3
71
6
001816 003816
0
0
1
91
60
0
3
91
6
0
0
1
A1
60
0
3
A1
6
001B16 003B16
0
0
1
C1
60
0
3
C1
6
0
0
1
D1
60
0
3
D1
6
0
0
1
E1
60
0
3
E1
6
0
0
1
F1
60
0
3
F1
6
L
C
D
d
i
s
p
l
a
y
r
e
g
i
s
t
e
r
2
(
L
C
D
2
)
L
C
D
d
i
s
p
l
a
y
r
e
g
i
s
t
e
r
3
(
L
C
D
3
)
L
C
D
d
i
s
p
l
a
y
r
e
g
i
s
t
e
r
4
(
L
C
D
4
)
L
C
D
d
i
s
p
l
a
y
r
e
g
i
s
t
e
r
5
(
L
C
D
5
)
L
C
D
d
i
s
p
l
a
y
r
e
g
i
s
t
e
r
6
(
L
C
D
6
)
L
C
D
d
i
s
p
l
a
y
r
e
g
i
s
t
e
r
7
(
L
C
D
7
)
LCD dis play regis ter 8(LCD
8
)
LCD dis play regis ter 9(LCD
9
)
LCD dis play regis ter 10(LCD
10
)
LCD dis play regis ter 11(LCD
11
)
LCD dis play regis ter 12(LCD
12
)
P
o
r
t
P
0
(
P
0
)
Port P2 (P2)
P
o
r
t
P
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
2
D
)
P
o
r
t
P
3
(
P
3
)
P
o
r
t
P
4
,
A
D
K
E
Y
p
i
n
s
e
l
e
c
t
i
o
n
(
P
4
)
P
o
r
t
P
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
4
D
)
P
o
r
t
P
5
(
P
5
)
P
o
r
t
P
5
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
5
D
)
P
o
r
t
P
6
(
P
6
)
P
o
r
t
P
6
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
6
D
)
Interrupt control register 2(ICON2)
Timer 3 (T3)
Timer X mode register (TXM)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Int er r upt request re gis t er 1( IREQ1)
Int er r upt request re gis t er 2( IREQ2)
Interrupt control register 1(ICON1)
Timer X (low) (TXL)
Timer Y (low) (TYL)
Timer 1 (T1)
Timer 2 (T2)
Timer X (high) (TXH)
Timer Y (high) (TYH)
Timer Y mode register (TYM)
Timer 123 mode regis t er ( T123M)
Seg m ent output ena ble register (SEG)
LCD m ode register (LM)
A-D control register (ADCON)
A-D conversio n r egis ter (AD)
Port P 3 dir ection register (P3D)
S
e
r
i
a
l
I
/
O
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
I
O
C
O
N
)
S
e
r
i
a
l
I
/
O
r
e
g
i
s
t
e
r
(
S
I
O
)
PULL register
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
13
I/O PORTS
Direction Registers (Ports P2–P6)
The I/O ports (P2–P6) have direction registers which determine
the input/output direction of each individual pin.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
Pull-up/Pull-down Control
By setting the PULL register (address 003316), I/O ports can con-
trol pull-up/pull-down (pins also used as segment output pin: pull-
down, other pins: pull-up). Pull-up/pull-down of pins are performed
by setting the PULL register to “1”.
However, the contents of PULL register does not affect ports pro-
grammed as the output ports.
Input port P0 and I/O port P2 are pulled-down in the initial state.
Also, the pull-down setting is invalid for pins set to segment output
with the segment output enable register (address 003816).
Fig. 11 Structure of PULL register
b7 b
0P
U
L
L
r
e
g
i
s
t
e
r
(
P
U
L
L
:
a
d
d
r
e
s
s
0
0
3
31
6,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
71
6)
P20–P23 pull-down
P24–P27 pull-down Note
P30–P34 pull-up
P44–P47 pull-up
P50–P53 pull-up
P54–P57 pull-up
P60–P64 pull-up
Note: These ports are invalid when selecting SEG.
P00–P07 pull-down
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
14
Fig. No.
Related SFRs
Input/OutputName
Pin Non-Port Function
I/O Format
Table 5 List of I/O port function
COM
0
–COM
3
P00/SEG0–
P07/SEG7
SEG
8
–/SEG
16
P20/SEG17–
P27/SEG24
P3
0
(LED)/KW
0
–
P3
4
(LED)/KW
4
AN
0
/ADKEY
0
–
AN3/ADKEY3
P44/AN4–
P47/AN7
P50/INT0,
P51/INT1
P52/CNTR0
P53/CNTR1
P54/SIN
P55/SOUT
P56/SCLK
P57/SRDY
P60/XCIN
P61/XCOUT
P62/TOUT
P63/φOUT
P64
Common
Input Port P0
Segment
I/O Port P2
I/O Port P3
A-D
conversion
input
I/O Port P4
I/O Port P5
I/O port P6
Output
Input,
individual bits
Output
Input/output
individual bits
Input/output
individual bits
Input
Input/output
individual bits
Input/output
individual bits
Input/output
individual bits
LCD common output
CMOS compatible
input level
CMOS 3-state output
LCD segment output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
Analog input
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS compatible
input level
CMOS 3-state output
LCD segment output
LCD segment output
Key input (key-on wake-up)
interrupt input
ADKEY input
A-D conversion input
Interrupt input
T imer X function input/output
Timer Y function input
Serial I/O function output
Sub-clock generating
circuit input/output
Timer 2 output
φ clock output
LCD mode register
PULL register
Segment output enable register
LCD0–LCD3
LCD mode register
LCD4–LCD8
PULL register
Segment output enable register
LCD8–LCD12
PULL register
Interrupt control register
A-D control register
P4 data latch
(ADKEY selected)
PULL register
A-D control register
PULL register
Interrupt edge selection register
PULL register
Timer X mode register
PULL register
Timer Y mode register
PULL register
Serial I/O control register
PULL register
CPU mode register
PULL register
Timer X mode register
PULL register
φ output control register
PULL register
(16)
(1)
(17)
(2)
(3)
(15)
(4)
(3)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(18)
Notes 1: For details of how to use double function ports as function I/O ports,refer to the applicable sections.
2: When an input level is at an intermediate potential,a current will flow from VCC to VSS through the input-stage gate.
Especially, power source current may increase during execution of the STP and WIT instructions.
Fix the unused input pins to “H” or “L” through a resistor.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
15
Fig. 12 Port block diagram (1)
(
2
)
P
o
r
t
P
2
Segment output enabl e bit
P
u
l
l
-
d
o
w
n
c
o
n
t
r
o
l
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
Data bus Port latch
V
L2
/V
L3
V
L1
/V
SS
(
1
)
P
o
r
t
P
0
D
a
t
a
b
u
s
V
L
2
/
V
L
3
V
L1
/V
SS
(
3
)
P
o
r
t
P
3
0
–
P
3
4
,
P
5
0
,
P
5
1
Key input (key-on wakeup) interrup t input
INT
0
, INT
1
interrupt input
D
a
t
a
b
u
sPort latch
P
u
l
l
-
u
p
c
o
n
t
r
o
l
(
4
)
P
o
r
t
P
4
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
A
-
D
c
o
n
v
e
r
s
i
o
n
i
n
p
u
t
Data bus Port latch
Pull-up control
(
5
)
P
o
r
t
P
5
2
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
Timer output
CNTR
0
interrupt input
P
u
l
l
-
u
p
c
o
n
t
r
o
l
T
i
m
e
r
X
o
p
e
r
a
t
i
o
n
m
o
d
e
b
i
t
(
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
s
e
l
e
c
t
e
d
)
(
6
)
P
o
r
t
P
5
3
Data bus
Direction
register
P
o
r
t
l
a
t
c
h
P
u
l
l
-
u
p
c
o
n
t
r
o
l
CNTR
1
interrupt input
P
u
l
l
-
d
o
w
n
c
o
n
t
r
o
l
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Direction
register
Direction
register
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
16
Fig. 13 Port block diagram (2)
S
e
r
i
a
l
I
/
O
t
r
a
n
s
m
i
t
e
n
d
s
i
g
n
a
l
S
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
P
5
5
/
SO
U
T
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
Synchronous clock
selection bit S
e
r
i
a
l
I
/
O
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
SR
D
Y
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
(
1
1
)
P
o
r
t
P
6
0
D
a
t
a
b
u
s
Port Xc switch bit
Port latch
O
s
c
i
l
l
a
t
o
r
P
o
r
t
P
6
0
P
o
r
t
X
c
s
w
i
t
c
h
b
i
t
(
1
2
)
P
o
r
t
P
6
1
D
a
t
a
b
u
s
P
o
r
t
X
c
s
w
i
t
c
h
b
i
t
P
o
r
t
l
a
t
c
h
S
u
b
-
c
l
o
c
k
g
e
n
e
r
a
t
i
n
g
c
i
r
c
u
i
t
i
n
p
u
t
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
rDirection
register
P
o
r
t
s
e
l
e
c
t
i
o
n
•
P
u
l
l
-
u
p
c
o
n
t
r
o
lPort selection • Pull-up control
(8)Port P5
5
D
a
t
a
b
u
s
Serial I/O output
P
o
r
t
l
a
t
c
h
(9)Port P5
6
D
a
t
a
b
u
s
Serial I/O clock output
S
e
r
i
a
l
I
/
O
c
l
o
c
k
i
n
p
u
t
P
o
r
t
l
a
t
c
h
(10)Port P5
7
Data bus
Serial I/O ready output
Port latch
(
7
)
P
o
r
t
P
5
4
D
a
t
a
b
u
s
S
e
r
i
a
l
I
/
O
i
n
p
u
t
P
o
r
t
l
a
t
c
h
P
u
l
l
-
u
p
c
o
n
t
r
o
l
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
rD
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Direction
register
Direction
register
P
u
l
l
-
u
p
c
o
n
t
r
o
l
Pull-up control Pull-up control
Serial I/O port selection bit
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
17
Fig. 14 Port block diagram (3)
(13)Port P62
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
T
O
U
T
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
T
i
m
e
r
o
u
t
p
u
t
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
u
l
l
-
u
p
c
o
n
t
r
o
l
(
1
6
)
C
O
M0–
C
O
M3
V
L3
V
L2
V
L1
(
1
7
)
S
E
G8–
S
E
G1
6
V
L
2
/
V
L
3
V
L
1
/
V
S
S
(
1
4
)
P
o
r
t
P
63
φ
φ
output control bit
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
Direction register
P
u
l
l
-
u
p
c
o
n
t
r
o
l
(15)AN0/ADKEY0–AN3/ADKEY3
A
-
D
c
o
n
v
e
r
s
i
o
n
i
n
p
u
t
A
D
K
E
Y
s
e
l
e
c
t
i
o
n
b
i
t
A
D
K
E
Y
e
n
a
b
l
e
b
i
t
A
n
a
l
o
g
i
n
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
(18)Port P64
Data bus P
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Pull-up control
The gate input signal of each
transistor is controlled by the LCD
duty ratio and the bias value.
The voltage applied to the sources of P-
channel and N-channel transistor s is the
controlled voltage by the bias value.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
18
INTERRUPTS
Interrupts occur by thirteen sources: five external, seven internal,
and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the corre-
sponding interrupt request and enable bits are “1” and the inter-
rupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
■ Notes on Interrupts
When the active edge of an external interrupt (INT0 , INT1, CNTR0
or CNTR1) is set or an interrupt source where several interrupt
source is assigned to the same vector address is switched, the
corresponding interrupt request bit may also be set. Therefore,
take following sequence:
(1) Disable the interrupt.
(2) Set the interrupt edge selection register (Timer X control regis-
ter for CNTR0, Timer Y mode register for CNTR1).
(3) Clear the set interrupt request bit to “0.”
(4) Enable the interrupt.
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Table 6 Interrupt vector addresses and priority
Remarks
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At timer 2 underflow
At completion of serial I/O data
transmission or reception
At falling of conjunction of input
level for port P3 (at input mode)
At completion of A-D conversion
At BRK instruction execution
Interrupt Source LowHigh
Priority V ector Addresses (Note 1)
Reset (Note 2)
INT0
INT1
Timer X
Timer Y
Timer 1
Timer 3
CNTR0
CNTR1
Timer 2
Serial I/O
Key input
(Key-on wake-up)
A-D conversion
BRK instruction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
FFFD16
FFFB16
FFF916
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE316
FFE116
FFDF16
FFDD16
FFFC16
FFFA16
FFF816
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE216
FFE016
FFDE16
FFDC16
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(valid at falling)
Valid when A-D interrupt is selected
Non-maskable software interrupt
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
19
Fig. 15 Interrupt control
Fig. 16 Structure of interrupt-related registers
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
g
(
I
)
B
R
K
i
n
s
t
r
u
c
t
i
o
n
R
e
s
e
t
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
7
b
0
I
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
I
N
T
0
i
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
I
N
T
1
i
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
(
I
N
T
E
D
G
E
:
a
d
d
r
e
s
s
0
0
3
A
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
0
1
6
)
I
nterrupt request reg
i
ster 1
INT
0
i
nterrupt request
bi
t
INT
1
interrupt request bit
Not used (retu rn “0” when read)
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 3 interrupt request bit
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
INT
0
i
nterrupt ena
bl
e
bi
t
INT
1
interrupt enable bit
Not used (Do not w rite “1” to these bits.)
Timer X interrupt enable bit
Timer Y i nter rup t enable bit
Timer 1 i nter ru pt ena bl e bi t
Timer 3 i nter ru pt ena bl e bi t
0
:
N
o
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
1
:
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
(IREQ
1 : a
dd
ress 003
C
16
,
i
n
i
t
i
a
l
va
l
ue: 00
16
)
(
I
C
O
N
1
:
a
d
d
r
e
s
s
0
0
3
E
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
0
1
6
)
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
2
C
N
T
R
0
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
C
N
T
R
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
S
e
r
i
a
l
I
/
O
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
K
e
y
i
n
p
u
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
A
D
c
o
n
v
e
r
s
i
o
n
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
(IREQ
2 : a
dd
ress 003
D
16
,
i
n
i
t
i
a
l
va
l
ue: 00
16
)
I
nter r upt c ontro
l
reg
i
ster 2
CNTR
0
i
nterrupt ena
bl
e
bi
t
CNTR
1
interrupt enable bit
Timer 2 interrupt enable bit
Not used (Do not w rite “1” to this bit)
Seria l I/O interr up t enabl e bit
Key input interrupt ena ble bit
AD conversion interrupt enable bit
Not used (Do not w rite “1” to this bit)
0 :
I
nterrupts
di
sa
bl
e
d
1 : Interrupts enabled
(ICON
2 : a
dd
ress 003
F
16
,
i
n
i
t
i
a
l
va
l
ue: 00
16
)
0 :
F
a
lli
ng e
d
ge act
i
ve
1 : Risin g edge ac ti ve
b
7
b
0
b
7
b
0
b
7
b
0
b
7
b
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
20
Key Input Interrupt (Key-on Wake Up)
A Key-on wake up interrupt request is generated by applying “L”
level voltage to any pin of port P3 that have been set to input
mode. In other words, it is generated when AND of input level
goes from “1” to “0”. An example of using a key input interrupt is
shown in Figure 17, where an interrupt request is generated by
pressing one of the keys consisted as an active-low key matrix
which inputs to ports P30–P33.
Fig. 17 Connection example when using key input control register, key input interrupt and port P3 block diagram
P
o
r
t
P
3
0
l
a
t
c
h
Port P3
0
direction register = “0”
Port P3
1
latch
Port P3
1
direction register = “0”
Port P3
2
latch
Port P3
2
direction register = “0”
P
o
r
t
P
3
3
l
a
t
c
h
Port P3
3
direction register = “0”
P
o
r
t
P
3
4
l
a
t
c
h
Port P3
4
direction register = “1”
P
3
0
i
n
p
u
t
P3
1
input
P
3
2
i
n
p
u
t
P
3
3
i
n
p
u
t
P
3
4
o
u
t
p
u
t
PULL register
Bit 3 = “1”
Port P3
input r ead circuit
Port PXx
“L” level output
K
e
y
i
n
p
u
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
P-cha nnel transistor f or pull-up
CMOS out put buffer
✽ ✽✽
✽ ✽✽
✽ ✽✽
✽ ✽✽
✽ ✽✽
✽ ✽
✽
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
21
TIMERS
The 38C1 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0”, an
underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
Read and write operation on 16-bit timer must be performed for
both high- and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct
operation when reading during the write operation, or when writing
during the read operation.
Fig. 18 Timer block diagram
"1"
P53/CNTR1"0"
"10"
"00","01","11"
P
52/
C
N
T
R0
Q
QT
S
P52 direction register
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
P
52
l
a
t
c
h
"0"
"
1
"
"
0
"
"1" "10"
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
C
N
T
R0
e
d
g
e
s
w
i
t
c
h
b
i
t
Q
Q
T
S
"0"
P62 direction register P62 latch
"0"
"1"
TO
U
T
o
u
t
p
u
t
e
d
g
e
s
w
i
t
c
h
b
i
t
"0"
"
1
"
TOUT output
control bit
"
1
"
P
62/
TO
U
T
f
(
XC
I
N)
"0"
"1"
TO
U
T
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
φS
O
U
R
C
E/
1
6
"
1
1
"
φS
O
U
R
C
E/
1
6
"
1
"
"0"
Count sour c e selection bit (Note 1)
φS
O
U
R
C
E
φSOURCE/16
φSOURCE/16
f
(
XI
N)
/
1
6
(
N
o
t
e
2
)
T
i
m
e
r
1
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
N
o
t
e
1
)
C
N
T
R
1
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
Timer Y stop
control bit
Falling edge detection Period
measurement mode
Timer Y
interrupt
request
P
u
l
s
e
w
i
d
t
h
H
L
c
o
n
t
i
n
u
o
u
s
l
y
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
Rising edge detection
Timer Y
operating
mode bits
(Note 1)
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
Timer X stop
control bit Timer X write
control bit
Timer X operat-
ing mode bits
“00”,“01”,“11”
CNTR0 active
edge swi tch bit
Timer 2 write
control bit
T
i
m
e
r
3
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
N
o
t
e
1
)
Timer 2
interrupt
request
Timer 3
interrupt
request
Timer 2 count source
selection bit
(Note 1)
Timer 1
interrupt
request
D
a
t
a
b
u
s
Timer Y (low) (8) Timer Y (high) (8)
T
i
m
e
r
3
l
a
t
c
h
(
8
)
Timer 3 (8)
Timer 1 latch (8)
T
i
m
e
r
1
(
8
)
Timer 2 latch (8)
Timer 2 (8)
T
i
m
e
r
X
(
l
o
w
)
(
8
)Timer X (high) (8)
T
i
m
e
r
X
(
l
o
w
)
l
a
t
c
h
(
8
)Timer X (high) latch (8)
T
i
m
e
r
Y
(
l
o
w
)
l
a
t
c
h
(
8
)T
i
m
e
r
Y
(
h
i
g
h
)
l
a
t
c
h
(
8
)
Timer Y operating mode bits
“00”,“01”,“10”
CNTR0
interrupt
request
C
N
T
R1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
φS
O
U
R
C
E:
r
e
p
r
e
s
e
n
t
s
t
h
e
s
u
p
p
l
y
s
o
u
r
c
e
o
f
i
n
t
e
r
n
a
l
c
l
o
c
k
φ.
I
t
i
s
t
h
e
o
s
c
i
l
l
a
t
i
o
n
f
r
e
q
u
e
n
c
y
o
f
XI
N
i
n
p
u
t
i
n
t
h
e
m
i
d
d
l
e
-
a
n
d
h
i
g
h
-
s
p
e
e
d
m
o
d
e
,
b
u
i
l
t
-
i
n
r
i
n
g
o
s
c
i
l
l
a
t
o
r
i
n
t
h
e
r
i
n
g
o
s
c
i
l
l
a
t
o
r
m
o
d
e
,
a
n
d
s
u
b
-
c
l
o
c
k
i
n
t
h
e
l
o
w
-
s
p
e
e
d
m
o
d
e
.
N
o
t
e
s
1
:
I
n
t
e
r
n
a
l
c
l
o
c
k
i
n
t
h
e
l
o
w
-
s
p
e
e
d
m
o
d
e
i
s
t
h
e
s
u
b
-
c
l
o
c
k
o
s
c
i
l
l
a
t
i
o
n
/
2
.
I
n
t
e
r
n
a
l
c
l
o
c
k
i
n
t
h
e
r
i
n
g
o
s
c
i
l
l
a
t
o
r
m
o
d
e
i
s
t
h
e
i
n
t
e
r
n
a
l
r
i
n
g
o
s
c
i
l
l
a
t
o
r
o
s
c
i
l
l
a
t
i
o
n
/
8
.
E
x
c
e
p
t
C
N
T
R
i
n
p
u
t
,
t
i
m
e
r
1
a
n
d
t
i
m
e
r
3
c
o
u
n
t
s
o
u
r
c
e
s
,
t
h
e
c
l
o
c
k
e
x
c
e
p
t
s
y
s
t
e
m
c
l
o
c
k
c
a
n
n
o
t
b
e
u
s
e
d
a
s
t
h
e
c
o
u
n
t
s
o
u
r
c
e
.
2
: φS
O
U
R
C
E
c
a
n
b
e
s
e
l
e
c
t
e
d
a
s
t
h
e
t
i
m
e
r
X
c
o
u
n
t
s
o
u
r
c
e
o
n
l
y
i
n
t
h
e
p
u
l
s
e
o
u
t
p
u
t
m
o
d
e
.
W
r
i
t
e
“
0
”
t
o
t
h
e
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
e
x
c
e
p
t
i
n
t
h
e
p
u
l
s
e
o
u
t
p
u
t
m
o
d
e
.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
22
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write and the real time port by
setting the timer X mode register.
(1) Timer mode
The timer counts the followings;
• f(XIN) (input frequency to XIN pin) divided by 16 in middle-, or
high-speed mode
• f(XCIN) (sub-clock oscillation frequency) divided by 16 in low-
speed mode
• f(XROSC) (built-in ring oscillator oscillation frequency) divided by
16 in ring oscillator mode
(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR0
pin is inverted and f(XIN), f(ROSC) or f(XCIN) can be selected for
the count source. Except for them, the operation in pulse output
mode is the same as in timer mode. When using a timer in this
mode, set the corresponding port P52 direction register to output
mode.
(3) Event counter mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P52 direction register to input mode.
(4) Pulse width measurement mode
The count source is f(XIN)/16 in the middle-, or high-speed mode,
f(ROSC)/16 in ring oscillator mode, and f(XCIN)/16 in the low-speed
mode. If CNTR0 active edge switch bit is “0”, the timer counts
while the input signal of CNTR0 pin is at “H”. If it is “1”, the timer
counts while the input signal of CNTR0 pin is at “L”. When using a
timer in this mode, set the corresponding port P52 direction regis-
ter to input mode.
Fig. 19 Structure of timer X mode register
T
i
m
e
r
X
m
o
d
e
r
e
g
i
s
t
e
r
(
T
X
M
:
a
d
d
r
e
s
s
0
0
2
71
6,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
01
6)
T
i
m
e
r
X
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
0
:
W
r
i
t
e
v
a
l
u
e
i
n
l
a
t
c
h
a
n
d
t
i
m
e
r
1
:
W
r
i
t
e
v
a
l
u
e
i
n
l
a
t
c
h
o
n
l
y
C
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
N
o
t
e
)
0
:
φ
S
O
U
R
C
E
/
1
6
1
:
φ
S
O
U
R
C
E
(
t
h
i
s
c
a
n
b
e
u
s
e
d
o
n
l
y
i
n
p
u
l
s
e
o
u
t
p
u
t
m
o
d
e
.
)
N
o
t
u
s
e
d
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
e
s
e
b
i
t
s
.
)
T
i
m
e
r
X
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
b
5
b
4
00
:
T
i
m
e
r
m
o
d
e
01
:
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
10
:
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
11
:
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
C
N
T
R0
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
0
:
C
o
u
n
t
a
t
r
i
s
i
n
g
e
d
g
e
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
S
t
a
r
t
f
r
o
m
“
H
”
o
u
t
p
u
t
i
n
p
u
l
s
e
o
u
t
p
u
t
m
o
d
e
M
e
a
s
u
r
e
“
H
”
p
u
l
s
e
w
i
d
t
h
i
n
p
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
F
a
l
l
i
n
g
e
d
g
e
a
c
t
i
v
e
f
o
r
i
n
t
e
r
r
u
p
t
1
:
C
o
u
n
t
a
t
f
a
l
l
i
n
g
e
d
g
e
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
S
t
a
r
t
f
r
o
m
“
L
”
o
u
t
p
u
t
i
n
p
u
l
s
e
o
u
t
p
u
t
m
o
d
e
M
e
a
s
u
r
e
“
L
”
p
u
l
s
e
w
i
d
t
h
i
n
p
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
R
i
s
i
n
g
e
d
g
e
a
c
t
i
v
e
f
o
r
i
n
t
e
r
r
u
p
t
T
i
m
e
r
X
s
t
o
p
c
o
n
t
r
o
l
b
i
t
0
:
C
o
u
n
t
s
t
a
r
t
1
:
C
o
u
n
t
s
t
o
p
b
7
b
0
N
o
t
e
: φS
O
U
R
C
E
r
e
p
r
e
s
e
n
t
s
t
h
e
o
s
c
i
l
l
a
t
i
o
n
f
r
e
q
u
e
n
c
y
o
f
X
I
N
i
n
p
u
t
i
n
t
h
e
m
i
d
d
l
e
-
a
n
d
h
i
g
h
-
s
p
e
e
d
m
o
d
e
,
b
u
i
l
t
-
i
n
r
i
n
g
o
s
c
i
l
l
a
t
o
r
i
n
t
h
e
r
i
n
g
o
s
c
i
l
l
a
t
o
r
m
o
d
e
,
a
n
d
s
u
b
-
c
l
o
c
k
i
n
t
h
e
l
o
w
-
s
p
e
e
d
m
o
d
e
.
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
e
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
e
x
c
e
p
t
t
h
e
p
u
l
s
e
o
u
t
p
u
t
m
o
d
e
.
●Timer X Write Control
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
If the value is written in latch only, when the value is written in
latch at the timer underflow, the value is loaded in the timer X and
the latch at the same time. Also, unexpected value may be set in
the high-order counter when the writing in high-order latch and the
underflow of timer X are performed at the same timing.
■Note on CNTR
0
interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
■Note on count source selection bit
Except the pulse output mode, write “0” to the count source selec-
tion bit.
When the timer X count source selection bit is set to “1”, as for the
recommended operating condition of the main clock input fre-
quency f(XIN), the rating value at the high-speed mode is applied.
■Note on interrupt in pulse output mode
When the count source selection bit is “1” in the pulse output
mode, the timing when the timer X interrupt request occurs may
be early or lately for one instruction cycle.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
23
T imer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
(1) Timer mode
The timer counts the followings;
• f(XIN)/16 in middle-, or high-speed mode
• f(XCIN)/16 in low-speed mode
• f(XROSC) divided by 16 in ring oscillator mode
(2) Period measurement mode
CNTR1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Ex-
cept for the above-mentioned, the operation in period measure-
ment mode is the same as in timer mode.
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
The rising/falling timing of CNTR1 pin input signal is found by
CNTR1 interrupt. When using a timer in this mode, set the corre-
sponding port P53 direction register to input mode.
(3) Event counter mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P53 direction register to input mode.
(4) Pulse width HL continuously measure-
ment mode
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the corresponding port P53 direction register to input mode.
■Note on CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR1 interrupt request is generated at both rising and
falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
Fig. 20 Structure of timer Y mode register
Ti
mer
Y
mo
d
e reg
i
ster
(TYM : address 002816, initial val ue: 0016)
b
7
b
0
N
ot use
d
(
returns “0” w
h
en rea
d)
(Do not writ e “1” to these bits.)
Ti me r Y opera t ing mo de bits
b5 b4
0 0 : Timer mode
0 1 : Per iod m easurement m ode
1 0 : Event cou nter mode
1 1 : Pulse width HL continuously
measurement mode
CNTR1 active edge sw it ch bit
0 : Count at rising edge in event counter mode
Mea s ur e the f all i ng edg e t o fal lin g edge
period in period measurement mode
Falling edge active for CNTR1 interrupt
1 : Count at falli ng edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge ac ti ve for CN TR1 int errupt
Ti mer Y stop con trol b i t
0 : Count star t
1 : Count stop
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
24
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected by a change of the count source. How-
ever, because changing the count source may cause an inadvert-
ent count down of the timer. Therefore, rewrite the value of timer
whenever the count source is changed.
●Timer 2 Write Control
If the timer 2 write control bit is “0”, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
If the timer 2 write control bit is “1”, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
●Timer 2 Output Control
When the timer 2 (TOUT) is output enabled, an inversion signal
from pin TOUT is output each time timer 2 underflows.
In this case, set the port P62 shared with the port TOUT to the out-
put mode.
■Note on Timer 1 to Timer 3
When the count source of timers 1 to 3 is changed, the timer
counting value may be changed large because a thin pulse is gen-
erated in count input of timer. If timer 1 output is selected as the
count source of timer 2 or timer 3, when timer 1 is written, the
counting value of timer 2 or timer 3 may be changed large be-
cause a thin pulse is generated in timer 1 output.
Therefore, set the value of timer in the order of timer 1, timer 2
and timer 3 after the count source selection of timer 1 to 3.
Fig. 21 Structure of timer 123 mode register
T
O
U
T
o
u
t
p
u
t
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
0
:
S
t
a
r
t
a
t
“
H
”
o
u
t
p
u
t
1
:
S
t
a
r
t
a
t
“
L
”
o
u
t
p
u
t
T
O
U
T
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
0
:
T
O
U
T
o
u
t
p
u
t
d
i
s
a
b
l
e
d
1
:
T
O
U
T
o
u
t
p
u
t
e
n
a
b
l
e
d
T
i
m
e
r
2
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
0
:
W
r
i
t
e
d
a
t
a
i
n
l
a
t
c
h
a
n
d
c
o
u
n
t
e
r
1
:
W
r
i
t
e
d
a
t
a
i
n
l
a
t
c
h
o
n
l
y
T
i
m
e
r
2
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
N
o
t
e
)
0
:
T
i
m
e
r
1
o
u
t
p
u
t
1
:
φ
S
O
U
R
C
E
/
1
6
T
i
m
e
r
3
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
T
i
m
e
r
1
o
u
t
p
u
t
1
:
f
(
X
I
N
)
/
1
6
T
i
m
e
r
1
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
N
o
t
e
)
0
:
φ
S
O
U
R
C
E
/
1
6
1
:
f
(
X
C
I
N
)
N
o
t
u
s
e
d
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
e
s
e
b
i
t
s
.
)
T
i
m
e
r
1
2
3
m
o
d
e
r
e
g
i
s
t
e
r
(
T
1
2
3
M
:
a
d
d
r
e
s
s
0
0
2
9
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
0
1
6
)
N
ote: φ
SOURCE
represents t
h
e osc
ill
at
i
on
f
requency o
f
X
IN
input in th e middle- and hi gh-speed mode,
built-in ring oscillator in the r ing oscillator mo de ,
and sub-clock in the low-speed mode.
b
7
b
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
25
Serial I/O
The serial I/O function can be used only for clock synchronous se-
rial I/O.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. When the internal clock is used, transfer
is started by a write signal to the serial I/O register.
[Serial I/O Control Register (SIOCON)] 001D16
The serial I/O control register contains 8 bits which control various
serial I/O functions.
■ Notes on Serial I/O
Write data to the serial I/O register only when the SCLK pin is “H”.
Fig. 22 Structure of serial I/O control register
Fig. 23 Block diagram of serial I/O function
S
e
r
i
a
l
I
/
O
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
I
O
C
O
N
:
a
d
d
r
e
s
s
0
0
1
D
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e:
0
0
1
6
)
b7
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
b
i
t
s
0
0
0
:
f
(
X
I
N
)
/
8
0
0
1
:
f
(
X
I
N
)
/
1
6
0
1
0
:
f
(
X
I
N
)
/
3
2
0
1
1
:
f
(
X
I
N
)
/
6
4
1
0
0
:
1
0
1
:
1
1
0
:
f
(
X
I
N
)
/
1
2
8
1
1
1
:
f
(
X
I
N
)
/
2
5
6
S
e
r
i
a
l
I
/
O
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
0
:
I
/
O
p
o
r
t
1
:
S
O
U
T
,
S
C
L
K
s
i
g
n
a
l
o
u
t
p
u
t
P
5
5
/
S
O
U
T
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
0
:
C
M
O
S
o
u
t
p
u
t
(
i
n
o
u
t
p
u
t
m
o
d
e
)
1
:
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
(
i
n
o
u
t
p
u
t
m
o
d
e
)
T
r
a
n
s
f
e
r
d
i
r
e
c
t
i
o
n
s
e
l
e
c
t
i
o
n
b
i
t
0
:
L
S
B
f
i
r
s
t
1
:
M
S
B
f
i
r
s
t
S
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
0
:
E
x
t
e
r
n
a
l
c
l
o
c
k
1
:
I
n
t
e
r
n
a
l
c
l
o
c
k
S
R
D
Y
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
0
:
I
/
O
p
o
r
t
P
5
7
1
:
S
R
D
Y
s
i
g
n
a
l
o
u
t
p
u
t
b0
b
2
b
1
b
0
D
o
n
o
t
s
e
t
N
o
t
e
: φ
S
O
U
R
C
E
r
e
p
r
e
s
e
n
t
s
t
h
e
o
s
c
i
l
l
a
t
i
o
n
f
r
e
q
u
e
n
c
y
o
f
X
I
N
i
n
p
u
t
i
n
t
h
e
m
i
d
d
l
e
-
a
n
d
h
i
g
h
-
s
p
e
e
d
m
o
d
e
,
b
u
i
l
t
-
i
n
r
i
n
g
o
s
c
i
l
l
a
t
o
r
i
n
t
h
e
r
i
n
g
o
s
c
i
l
l
a
t
o
r
m
o
d
e
,
a
n
d
s
u
b
-
c
l
o
c
k
i
n
t
h
e
l
o
w
-
s
p
e
e
d
m
o
d
e
.
"
1
"
"
0
"
"
0
"
"
1
"
"
0
"
"
1
"
S
C
L
K
1
/
8
1
/
1
6
1
/
3
2
1
/
6
4
1
/
1
2
8
1
/
2
5
6
P
54/
SI
N
P
56/
SC
L
K
P
55/
SO
U
T
P
57/
SR
D
Y
(
N
o
t
e
)
φS
O
U
R
C
E
D
a
t
a
b
u
s
S
e
r
i
a
l
I
/
O
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Serial I/O port s elec tion bit
S
e
r
i
a
l
I
/
O
c
o
u
n
t
e
r
(
3
)
S
e
r
i
a
l
I
/
O
r
e
g
i
s
t
e
r
(
8
)
S
y
n
c
h
r
o
n
o
u
s
c
i
r
c
u
i
t
S
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
E
x
t
e
r
n
a
l
c
l
o
c
k
Internal synchronous
clock select bits
D
i
v
i
d
e
r
P
5
6
l
a
t
c
h
P
5
5
l
a
t
c
h
N
o
t
e
:
I
t
i
s
s
e
l
e
c
t
e
d
b
y
t
h
e
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
,
t
h
e
SR
D
Y
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
,
a
n
d
t
h
e
s
e
r
i
a
l
I
/
O
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
.
P
5
7
l
a
t
c
h
(
N
o
t
e
)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
26
Fig. 24 Timing of serial I/O function
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
T
r
a
n
s
f
e
r
c
l
o
c
k
(
N
o
t
e
1
)
S
e
r
i
a
l
I
/
O
o
u
t
p
u
t
SO
U
T
S
e
r
i
a
l
I
/
O
i
n
p
u
t
SI
N
S
e
r
i
a
l
I
/
O
r
e
g
i
s
t
e
r
w
r
i
t
e
s
i
g
n
a
l
(Note 2)
Serial I/O interrupt r equest bit set
1
:
W
h
e
n
t
h
e
i
n
t
e
r
n
a
l
c
l
o
c
k
i
s
s
e
l
e
c
t
e
d
a
s
t
h
e
t
r
a
n
s
f
e
r
c
l
o
c
k
,
t
h
e
d
i
v
i
d
e
r
a
t
i
o
c
a
n
b
e
s
e
l
e
c
t
e
d
b
y
s
e
t
t
i
n
g
b
i
t
s
0
t
o
2
o
f
t
h
e
s
e
r
i
a
l
I
/
O
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
.
2
:
W
h
e
n
t
h
e
i
n
t
e
r
n
a
l
c
l
o
c
k
i
s
s
e
l
e
c
t
e
d
a
s
t
h
e
t
r
a
n
s
f
e
r
c
l
o
c
k
,
t
h
e
SO
U
T
p
i
n
g
o
e
s
t
o
h
i
g
h
i
m
p
e
d
a
n
c
e
a
f
t
e
r
t
r
a
n
s
f
e
r
c
o
m
p
l
e
t
i
o
n
.
W
h
e
n
t
h
e
e
x
t
e
r
n
a
l
c
l
o
c
k
i
s
s
e
l
e
c
t
e
d
a
s
t
h
e
t
r
a
n
s
f
e
r
c
l
o
c
k
,
a
c
o
n
t
e
n
t
o
f
t
h
e
s
e
r
i
a
l
I
/
O
s
h
i
f
t
r
e
g
i
s
t
e
r
i
s
c
o
n
t
i
n
u
e
d
t
o
s
h
i
f
t
d
u
r
i
n
g
i
n
p
u
t
t
i
n
g
a
t
r
a
n
s
f
e
r
c
l
o
c
k
.
T
h
e
SO
U
T
p
i
n
d
o
e
s
n
o
t
g
o
t
o
h
i
g
h
i
m
p
e
d
a
n
c
e
a
f
t
e
r
t
r
a
n
s
f
e
r
c
o
m
p
l
e
t
i
o
n
.
N
o
t
e
s
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
27
A-D CONVERTER
The functional blocks of the A-D converter are described below.
● A-D Converter
The conversion method of this A-D converter is the 8-bit resolution
successive comparison method. This A-D converter has the
ADKEY function for A-D conversion of “L” level analog input to
ADKEY pin automatically.
[A-D Conversion Register (AD)] 003516
The A-D conversion register is a read-only register that contains
the result of an A-D conversion. When reading this register during
an A-D conversion, the previous conversion result is read.
After power on or system is released from reset, the value is unde-
fined.
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 signals
the completion of an A-D conversion. The value of this bit remains
at “0” during an A-D conversion, then changes to “1” when the A-
D conversion is completed. Writing “0” to this bit starts the A-D
conversion. Bit 4 enables the ADKEY function. Writing “1” to this
bit enables the ADKEY function. When this function is set to be
valid, the analog input pin selection bits are invalid. Also, when the
bit 4 is “1”, do not write “0” to bit 3 by program.
Resistor ladder
The resistor ladder divides the voltage between VCC and VSS by
256, and outputs the comparison voltages to the comparator.
Channel Selector
The channel selector selects one of the input ports AN7–AN0.
Comparator and Control Circuit
The comparator and control circuit compare an analog input volt-
age with the comparison voltage and store the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
The comparator is constructed linked to a capacitor. The conver-
sion accuracy may be low because the charge is lost if the conver-
sion speed is not enough.
Accordingly, set f(XIN) to at least 500kHz during A-D conversion in
the middle- or high-speed mode.
Also, do not execute the STP and WIT instructions during the A-D
conversion.
In the low-speed mode, since the A-D conversion is executed by
the built-in self-oscillation circuit, the minimum value of f(XIN) fre-
quency is not limited.
Fig. 26 A-D converter block diagram
Fig. 25 Structure of A-D control register
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
D
C
O
N
:
a
d
d
r
e
s
s
0
0
3
41
6,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
81
6)
A
D
c
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
i
o
n
b
i
t
0
:
C
o
n
v
e
r
s
i
o
n
i
n
p
r
o
g
r
e
s
s
1
:
C
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
e
d
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
s
0
0
0
:
A
N0
0
0
1
:
A
N1
0
1
0
:
A
N2
0
1
1
:
A
N3
1
0
0
:
A
N4
1
0
1
:
A
N5
1
1
0
:
A
N6
1
1
1
:
A
N7
A
D
K
E
Y
e
n
a
b
l
e
b
i
t
(
N
o
t
e
)
0
:
D
i
s
a
b
l
e
d
1
:
E
n
a
b
l
e
d
b
7
b
0
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
e
s
e
b
i
t
s
.
)
N
o
t
e
:
W
h
e
n
t
h
e
A
D
K
E
Y
e
n
a
b
l
e
b
i
t
i
s
“
1
”
,
a
n
a
l
o
g
i
n
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
i
s
i
n
v
a
l
i
d
.
D
o
n
o
t
e
x
e
c
u
t
e
t
h
e
A
-
D
c
o
n
v
e
r
s
i
o
n
w
h
i
l
e
A
D
K
E
Y
i
s
e
n
a
b
l
e
d
.
E
v
e
n
i
f
A
D
K
E
Y
i
s
e
n
a
b
l
e
d
,
v
a
l
u
e
s
o
f
b
i
t
s
0
t
o
2
o
f
A
D
C
O
N
a
r
e
n
o
t
a
f
f
e
c
t
e
d
.
V
SS
b
7b0
3
A
N0/
A
D
K
E
Y0
A
N1/
A
D
K
E
Y1
AN2/ADKEY2
A
N3/
A
D
K
E
Y3
P
44/
A
N4
P
45/
A
N5
P
46/
A
N6
P
47/
A
N7
8
A
D
K
E
Y
c
o
n
t
r
o
l
c
i
r
c
u
i
t
Comparator
A-D control circuit A-D interrupt request
D
a
t
a
b
u
s
A-D control register
A
-
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
R
e
s
i
s
t
o
r
l
a
d
d
e
r
C
h
a
n
n
e
l
s
e
l
e
c
t
o
r
V
CC
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
28
Fig. 27 Structure of ADKEY pin selection bits
b
7b
0
P
4
d
a
t
a
r
e
g
i
s
t
e
r
(
A
d
d
r
e
s
s
0
0
0
8
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
0
1
6
)
P4
N
o
t
e
;
A
D
K
E
Y
p
i
n
i
s
s
e
l
e
c
t
e
d
b
y
p
o
r
t
P
4
d
a
t
a
r
e
g
i
s
t
e
r
.
T
h
e
p
r
i
o
r
i
t
y
o
f
A
D
K
E
Y
0
–
A
D
K
E
Y
3
i
s
a
s
f
o
l
l
o
w
s
;
A
D
K
E
Y
0
>
A
D
K
E
Y
1
>
A
D
K
E
Y
2
>
A
D
K
E
Y
3
A
D
K
E
Y
0
s
e
l
e
c
t
i
o
n
b
i
t
0
:
I
n
v
a
l
i
d
1
:
V
a
l
i
d
A
D
K
E
Y
1
s
e
l
e
c
t
i
o
n
b
i
t
0
:
I
n
v
a
l
i
d
1
:
V
a
l
i
d
A
D
K
E
Y
2
s
e
l
e
c
t
i
o
n
b
i
t
0
:
I
n
v
a
l
i
d
1
:
V
a
l
i
d
A
D
K
E
Y
3
s
e
l
e
c
t
i
o
n
b
i
t
0
:
I
n
v
a
l
i
d
1
:
V
a
l
i
d
P
4
4
–
P
4
7
d
a
t
a
l
a
t
c
h
ADKEY Control Circuit
The ADKEY function is the function for A-D conversion of the “L”
level analog input voltage input to the ADKEY pin automatically.
This function can be used also in the state of STP and WIT.
• ADKEY Selection
Two or more ADKEY pins can be selected by the low-order 4 bits
of P4 data register.
If “L” level input to an ADKEY pin is detected, other bits are set to
“0” and only the corresponding ADKEY selection bit is set to “1”.
As a result, the pin with “L” level input can be recognized.
• ADKEY Enable
The ADKEY function is enabled by writing “1” to the ADKEY en-
able bit. Surely, in order to enable ADKEY functin, set “1” to the
ADKEY enable bit, after selecting the ADKEY pin.
ADKEY becomes disabled automatically after the A-D conversion
end by the ADKEY function. When the ADKEY enable bit of the A-
D control register is “1”, the analog input pin selection bits become
invalid. Please do not write “0” in the AD conversion completion bit
by the program during ADKEY enabled state.
[ADKEY Control Circuit]
The pins which performs A-D conversion is selected with the rank-
ing of ADKEY0, ADKEY1, ADKEY2, and ADKEY3 when there is
an “L” level input simultaneously to two or more valid ADKEY pins.
In order to obtain a more exact conversion result, by the A-D con-
version with ADKEY, execute the following;
➀ set the input to the ADKEY pin into a steep falling waveform,
➁ stabilize the input voltage within 8 clock cycle (1 µs at f(XIN) =
8MHz) after the input voltage is under VIL, and
➂ maintain the input voltage until the completion of the A-D con-
version.
The threshold voltage with an actual ADKEY pin is the voltage be-
tween VIH-VIL.
In order not to make ADKEY operation perform superfluously in a
noise etc., in the state of the waiting for an input, set the voltage of
an ADKEY pin to VIH (0.9VCC) or more.
When the following operations are performed, the A-D conversion
operation cannot be guaranteed.
• When the CPU mode register is operated during A-D conversion
operation,
• When the AD conversion control register is operated during A-D
conversion operation,
• When STP or WIT instructin is executed during A-D conversion
operation,
• When the ADKEY pin selection bit is operated during A-D con-
version operation at selecting ADKEY function, and
• Return operation by reset, STOP or WIT under A-D conversion
operation at selecting ADKEY function is performed.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
29
Definition of A-D converter accuracy
The A-D conversion accuracy is defined below (refer to Figure 28).
• Relative accuracy
➀ Zero transition voltage (V0T)
This means an analog input voltage when the actual A-D con-
version output data changes from “0” to “1.”
➁ Full-scale transition voltage (VFST)
This means an analog input voltage when the actual A-D con-
version output data changes from “255” to ”254.”
➂ Linearity error
This means a deviation from the line between V0T and VFST of a
converted value between V0T and VFST.
➃ Differential non-linearity error
This means a deviation from the input potential difference re-
quired to change a converter value between V0T and VFST by 1
LSB at the relative accuracy.
• Absolute accuracy
This means a deviation from the ideal characteristics between 0 to
V
REF
(V
CC
in 38C1 Group) of actual A-D conversion characteristics.
V
REF
(V
CC
)
V
254
V
n
V
1
V
0
V
n+1
n
+
1
n
2
5
4
255
1
0
b
a
c
O
u
t
p
u
t
d
a
t
a
Differential non-linearity error =
Linearity error =
[LSB]
c
a
b–a
a
[
L
S
B
]
Actual A-D conversion
characteristics
a
:
1
L
S
B
b
y
r
e
l
a
t
i
v
e
a
c
c
u
r
a
c
y
b
:
V
n
+
1
–
V
n
c
:
D
i
f
f
e
r
e
n
c
e
b
e
t
w
e
e
n
i
d
e
a
l
V
n
a
n
d
a
c
t
u
a
l
V
n
Zero transition voltage (V
0T
)Analog voltage
Full-scale transition voltage (V
FST
)
Ideal line of A-D conversion
between V
0
–V
254
Fig. 28 Definition of A-D conversion accuracy
VFST–V0T
254
VREF*
256
Vn: Analog input voltage when the output data changes from “n” to
“n+1” (n = 0 to 254)
• 1LSB at relative accuracy →(V)
• 1LSB at absolute accuracy →(V)
* VREF = VCC in the 38C1 Group.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
30
LCD DRIVE CONTROL CIRCUIT
The 38C1 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
•LCD display register
•Segment output enable register
•LCD mode register
•Selector
•Timing controller
•Common driver
•Segment driver
•Bias control circuit
A maximum of 25 segment output pins and 4 common output pins
can be used.
Up to 100 pixels can be controlled for LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register,
Fig. 29 Structure of segment output enable register and LCD mode register
the segment output enable register and the LCD display register,
the LCD drive control circuit starts reading the display data auto-
matically, performs the bias control and the duty ratio control, and
displays the data on the LCD panel.
Table 7. Maximum number of display pixels at each duty ratio
Maximum number of display pixel
25 dots
or 8 segment LCD 3 digits
50 dots
or 8 segment LCD 6 digits
75 dots
or 8 segment LCD 9 digits
100 dots
or 8 segment LCD 12 digits
Duty ratio
1
2
3
4
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
0
b
3
b
2
b
1
b
0
0
0
0
0:
S
E
G8–
S
E
G1
6
E
n
a
b
l
e
d
0
0
0
1:
S
E
G4–
S
E
G1
6
E
n
a
b
l
e
d
0
0
1
0:
S
E
G2–
S
E
G1
6
E
n
a
b
l
e
d
0
0
1
1:
S
E
G1–
S
E
G1
6
E
n
a
b
l
e
d
0
1
✕
✕:
S
E
G0–
S
E
G1
6
E
n
a
b
l
e
d
1
0
0
0:
S
E
G0–
S
E
G1
7
E
n
a
b
l
e
d
1
0
0
1:
S
E
G0–
S
E
G1
8
E
n
a
b
l
e
d
1
0
1
0:
S
E
G0–
S
E
G1
9
E
n
a
b
l
e
d
1
0
1
1:
S
E
G0–
S
E
G2
0
E
n
a
b
l
e
d
1
1
0
0:
S
E
G0–
S
E
G2
1
E
n
a
b
l
e
d
1
1
0
1:
S
E
G0–
S
E
G2
2
E
n
a
b
l
e
d
1
1
1
0:
S
E
G0–
S
E
G2
3
E
n
a
b
l
e
d
1
1
1
1:
S
E
G0–
S
E
G2
4
E
n
a
b
l
e
d
N
o
t
u
s
e
d
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
e
s
e
b
i
t
s
)
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
r
e
g
i
s
t
e
r
(
S
E
G
:
a
d
d
r
e
s
s
0
0
3
81
6,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
01
6)
b
7
b
0
L
C
D
m
o
d
e
r
e
g
i
s
t
e
r
(
L
M
:
a
d
d
r
e
s
s
0
0
3
91
6,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
01
6)
D
uty rat
i
o se
l
ect
i
on
bi
ts
b1b0
0 0 : 1 duty (static)
0 1 : 2 duty
1 0 : 3 duty
1 1 : 4 duty
Bias control bit (Note 2)
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Not used
(Do not writ e “1” to this bit.)
LCD circuit divider division ratio selection bits
b6b5
0 0 : Clock input
0 1 : 2 division of Clock input
1 0 : 4 division of Clock input
1 1 : 8 division of Clock input
LCDCK c ount so urce selectio n bit (Note 3)
0 : f(XCIN)/32
1 : φSOURCE/8192
N
otes 1:
S
et t
h
e
di
rect
i
on reg
i
ster o
f
t
h
e port w
hi
c
h
i
s a
l
so use
d
as t
h
e segment output ena
bl
e
d
p
i
n to “1”.
2: When “1 duty” is selected by the duty ratio selection bit, set the bias control bit to “1”.
3: LCDCK i s a clock for a LCD timing controll er.
φSOURCE represent s the oscillation frequenc y of XIN input in the middle- and high-speed mode,
built-i n ring oscil lato r i n the ring osc illator m ode, and s ub-clock i n the l ow-s peed m ode.
b
7
b
0
(N
ote 1
)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
31
Fig. 30 Block diagram of LCD controller/driver
f
(
X
C
I
N
)
/
3
2
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
V
S
S
V
L
1
V
L
2
V
L
3
P
0
3
/
S
E
G
3
P
0
2
/
S
E
G
2
P
0
1
/
S
E
G
1
P
0
0
/
S
E
G
0
"
1
"
"
0
"
L
C
D
C
K
2
2
D
a
t
a
b
u
s
T
i
m
i
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c
o
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r
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r
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C
D
d
i
v
i
d
e
r
A
d
d
r
e
s
s
0
0
1
1
1
6
A
d
d
r
e
s
s
0
0
1
0
1
6
L
C
D
C
K
c
o
u
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u
r
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i
a
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u
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o
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r
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i
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o
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C
D
d
i
s
p
l
a
y
r
e
g
i
s
t
e
r
S
e
g
m
e
n
t
d
r
i
v
e
r
S
e
g
m
e
n
t
d
r
i
v
e
r
S
e
g
m
e
n
t
d
r
i
v
e
r
S
e
g
m
e
n
t
d
r
i
v
e
r
S
e
l
e
c
t
o
r
S
e
l
e
c
t
o
r
S
e
l
e
c
t
o
r
S
e
l
e
c
t
o
r
S
e
l
e
c
t
o
r
φ
s
o
u
r
c
e
/
8
1
9
2
N
o
t
e
:
A
c
c
o
r
d
i
n
g
t
o
t
h
e
o
p
e
r
a
t
i
o
n
m
o
d
e
,
φ
s
o
u
r
c
e
i
n
d
i
c
a
t
e
s
t
h
e
o
s
c
i
l
l
a
t
i
o
n
f
r
e
q
u
e
n
c
y
s
h
o
w
n
b
e
l
o
w
;
•
I
n
m
i
d
d
l
e
-
o
r
h
i
g
h
-
s
p
e
e
d
m
o
d
e
:
X
I
N
i
n
p
u
t
,
•
I
n
r
i
n
g
o
s
c
i
l
l
a
t
o
r
m
o
d
e
:
b
u
i
l
t
-
i
n
r
i
n
g
o
s
c
i
l
l
a
t
o
r
,
a
n
d
•
I
n
l
o
w
-
s
p
e
e
d
m
o
d
e
:
o
s
c
i
l
l
a
t
i
o
n
f
r
e
q
u
e
n
c
y
o
f
s
u
b
-
c
l
o
c
k
.
S
E
G
1
6
P
2
6
/
S
E
G
2
3
P
2
7
/
S
E
G
2
4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
32
Fig. 31 Example of circuit at each bias
Table 8. Bias control and applied voltage to VL1–VL3
Bias value
1/3 bias
1/2 bias
1/1 bias
(static)
Voltage value
VL3=VLCD
VL2=2/3 VLCD
VL1=1/3 VLCD
VL3=VLCD
VL2=VL1=1/2 VLCD
VL3=VLCD
VL2=VL1=1/2 VSS
Note : VLCD is the maximum value of supplied voltage for the
LCD panel.
Bias Control and Applied Voltage to LCD
Power Input Pins
To the LCD power input pins (VL1–VL3), apply the voltage shown
in Table 8 according to the bias value.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by
duty ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
When the LCD enable bit is “0”, the output of COM0–COM3 is “L”
level. Table 9. Duty ratio control and common pins used
Duty
ratio
1
2
3
4
Common pins used
Notes 1: Set COM1, COM2 and COM3 to be open.
2: Set COM2 and COM3 to be open.
3: Set COM3 to be open.
Bit 1
0
0
1
1
Bit 0
0
1
0
1
COM0 (Note 1)
COM0, COM1 (Note 2)
COM0–COM2 (Note 3)
COM0–COM3
Duty ratio selection bits
R4
R5
R4 = R5
R
1
R
2
R3
R
1
=
R
2
=
R
3
VL
3
VL2
VL1
VL3
VL
2
VL
1
VL3
VL
2
VL
1
1/3 bias 1/1 bias (static)
Contrast control
1
/
2
b
i
a
s
Contrast control
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
33
(frequency of count source for LCDCK)
(divider division ratio for LCD)
f(LCDCK)=
f(LCDCK)
duty ratio
Frame frequency=
Fig. 32 LCD display register map
LCD Display register
Address 001016 to 001C16 is the LCD display register. When “1”
are written to these addresses, the corresponding segments of the
LCD display panel are turned on.
LCD Drive Timing
The LCDCK timing frequency (LCD drive timing) is generated in-
ternally and the frame frequency can be determined with the fol-
lowing equation;
COM3 C
O
M
2C
O
M
1COM0C
O
M
3COM2C
O
M
1COM0
0
0
1
C
1
6
0018
16
0
0
1
9
1
6
0
0
1
A
1
6
0
0
1
B
1
6
0
0
1
4
1
6
0015
16
0016
16
0017
16
0
0
1
0
1
6
0011
16
0012
16
0013
16
43
–
SEG
11
S
E
G
1
S
E
G
2
1
S
E
G
2
3
SEG
13
SEG
15
SEG
17
S
E
G
1
9
SEG
3
SEG
5
SEG
7
S
E
G
9
S
E
G
0
SEG
10
SEG
12
SEG
14
SEG
16
S
E
G
1
8
S
E
G
2
0
S
E
G
2
2
S
E
G
2
4
SEG
2
SEG
4
SEG
6
S
E
G
8
0
Bits
Address 765 21
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
34
Fig. 33 LCD drive waveform (1/2 bias, 1/1 bias)
V
L3
V
L2
=V
L1
V
SS
V
L3
V
SS
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
SEG
0
C
O
M
3
C
O
M
2
C
O
M
1
C
O
M
0
COM
3
C
O
M
2
C
O
M
1
COM
0
V
L3
V
L2
=V
L1
V
SS
V
L3
V
SS
C
O
M
0
C
O
M
1
C
O
M
2
SEG
0
C
O
M
0
C
O
M
2
C
O
M
1
C
O
M
0
C
O
M
2
C
O
M
1
C
O
M
0
C
O
M
2
C
O
M
0
C
O
M
1
S
E
G
0
V
L
3
V
L
2
=
V
L
1
V
S
S
V
L
3
V
S
S
C
O
M
1
C
O
M
0
COM
1
COM
0
C
O
M
1
COM
0
COM
1
COM
0
C
O
M
0
S
E
G
0
V
L
3
V
L
2
=
V
L
1
=
V
S
S
V
L
3
V
S
S
I
n
t
e
r
n
a
l
l
o
g
i
c
L
C
D
C
K
t
i
m
i
n
g
1
/
4
d
u
t
yVoltage level
O
F
FO
NO
F
FO
N
1
/
3
d
u
t
y
O
F
FO
NONO
F
FONOFF
1
/
2
d
u
t
y
O
F
FON O
F
FO
NO
F
FON OFFO
N
1
/
1
d
u
t
y
(
1
/
1
b
i
a
s
)
O
F
FO
N
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
35
Fig. 34 LCD drive waveform (1/3 bias)
VL3
VS
S
C
O
M0
C
O
M1
C
O
M2
C
O
M3
S
E
G0
COM3C
O
M2COM1COM0C
O
M3C
O
M2COM1C
O
M0
C
O
M0
C
O
M1
C
O
M2
S
E
G0
C
O
M0
C
O
M1
S
E
G0
VL
3
VL
2
VS
S
VL
1
VL
3
VL
2
VS
S
VL
1
VL
3
VSS
VL
3
VL
2
VS
S
VL
1
VL
3
VS
S
COM0C
O
M2COM1COM0COM2COM1COM0COM2
COM1C
O
M0COM1COM0COM1C
O
M0C
O
M1COM0
I
n
t
e
r
n
a
l
l
o
g
i
c
L
C
D
C
K
t
i
m
i
n
g
1/4 duty Voltage level
O
F
FON OFFON
1/3 duty
OFFO
NO
NO
F
FONO
F
F
1/2 duty
OFFO
NOFF
O
NO
F
FON O
F
FO
N
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
36
Fig. 35 Structure of clock output control register
OTHER FUNCTION REGISTERS
● φ clock output function
The internal clock φ can be output from port P63 by setting the φ
output control register.
At φ clock output, set “1” to the bit 3 of the port P6 direction regis-
ter.
b
7b
0φ outpu t control regis ter
(CKOUT: address 002A
16
, init ial value: 00
16
)
φ outpu t control bit
00:
01:
10:
11:
P
o
r
t
f
u
n
c
t
i
o
n
φ
fr
e
q
u
e
n
c
y
s
i
g
n
a
l
o
u
t
p
u
t
X
C
I
N
f
r
e
q
u
e
n
c
y
s
i
g
n
a
l
o
u
t
p
u
t
N
o
t
a
v
a
i
l
a
b
l
e
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
i
s
b
i
t
)
b7 b0
DB
0
data stor ed
DB
1
data stor ed
DB
2
data stor ed
DB
3
data stor ed
DB
4
data stor ed
DB
5
data stor ed
DB
6
data stor ed
DB
7
data stor ed
b
7b0
RRF register
(RRFR: address 002F
16
, initial value: 00
16
)
D
B
4
d
a
t
a
s
t
o
r
e
d
D
B
5
d
a
t
a
s
t
o
r
e
d
D
B
6
d
a
t
a
s
t
o
r
e
d
D
B
7
d
a
t
a
s
t
o
r
e
d
D
B
0
d
a
t
a
s
t
o
r
e
d
D
B
1
d
a
t
a
s
t
o
r
e
d
D
B
2
d
a
t
a
s
t
o
r
e
d
D
B
3
d
a
t
a
s
t
o
r
e
d
Temporary data reg is ters 0, 1, 2
(TD
0
, TD
1
, TD
2
: address 002C
16
, 002D
16
, 002 E
16
,
initial value: 00
16
)
● Temporary data register
The temporary data register (addresses 002C16 to 002E16) is the
8-bit register and does not have the control function. It can be
used to store data temporarily. It is initialized after reset.
● RRF register
The RRF register (address 002F16) is the 8-bit register and does
not have the control function.
As for the value written in this register, high-order 4 bits and low-
order 4 bits interchange.
It is initialized after reset.
Fig. 36 Structure of temporary data register, RRF register
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
37
Fig. 37 Example of reset circuit
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between VCC(min.) and
5.5 V), reset is released. After the reset is completed, the program
starts from the address contained in address FFFD16 (high-order
byte) and address FFFC16 (low-order byte). Make sure that the re-
set input voltage is less than 0.2 VCC for VCC of VCC (min.).
Fig. 38 Reset Sequence
P
o
w
e
r
o
n
P
o
w
e
r
s
o
u
r
c
e
v
o
l
t
a
g
e
Rese t in put
voltage
P
o
w
e
r
s
o
u
r
c
e
v
o
l
t
a
g
e
d
e
t
e
c
t
i
o
n
c
i
r
c
u
i
t
0.2 V
CC
0
V
0
V
V
C
C
R
E
S
E
T
V
C
C
R
E
S
E
T
N
o
t
e
:
R
e
s
e
t
r
e
l
e
a
s
e
v
o
l
t
a
g
e
V
C
C
=
3
.
0
V
(Note)
R
E
S
E
T
S
Y
N
C
φ
ROSC
F
F
F
C FFFD ADH, ADL
ADL
????
ADH
R
O
S
C
:
a
b
o
u
t
3
5
c
l
o
c
k
c
y
c
l
e
s
Notes 1 : f(ROSC) and
φ
are in the relationship : f(ROSC) = 8•f(
φ
)
2 : A question mark (?) indicates an undefined status that depends on the previous status.
Reset address from vector table
Internal
reset
Address
D
a
t
a
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
38
Fig. 39 Internal state of microcomputer immediately after reset
N
ote:
Th
e con t en ts o
f
a
ll
ot
h
er reg
i
sters an
d
RAM
are un
d
e
fi
ne
d
a
f
ter
reset, so they must b e initia lized b y software.
✕ : Undefined
R
e
g
i
s
t
e
r
c
o
n
t
e
n
t
s
Add
res
s
0
0
0
51
6
0
0
0
71
6
0
0
0
91
6
0
0
0
B
1
6
0
0
0
D
1
6
0
0
1
D
1
6
0
0
2
01
6
0
0
2
11
6
0
0
2
21
6
0
0
2
31
6
002416
002516
0
0
2
61
6
002716
002816
0
0
2
91
6
0
0
2
A
1
6
0
0
2
C
1
6
0
0
2
D
1
6
0
0
2
E
1
6
0
0
2
F
1
6
0
0
3
31
6
0
0
3
41
6
0
0
3
81
6
0
0
3
91
6
0
0
3
A
1
6
003
B
16
0
0
3
C
1
6
003
D
16
(
P
S
)
(
P
C
H
)
(PC
L
)
(
1
0
)
(
11
)
(
1
2
)
(
1
3
)
(
1
4
)
(
15
)
(
16
)
(
17
)
(
18
)
(
1
9
)
(
2
0
)
(
2
1
)
(
2
2
)
(
2
3
)
(
2
4
)
(
2
5
)
(
2
6
)
(
2
7
)
(
2
8
)
(
29
)
(
1
)
(
2
)
(
3
)
(
4
)
(
5
)
(
6
)
(
7
)
(
8
)
(
9
)
T
i
m
e
r
Y
(
l
o
w
)
P
o
r
t
P
5
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
P
6
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
T
i
m
e
r
Y
(
h
i
g
h
)
S
e
r
i
a
l
I
/
O
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
T
i
m
e
r
X
(
h
i
g
h
)
T
i
m
e
r
X
(
l
o
w
)
T
i
m
e
r
X
m
o
d
e
r
e
g
i
s
t
e
r
Timer Y mode register
T
i
m
e
r
1
2
3
m
o
d
e
r
e
g
i
s
t
e
r
A-D c ontro l r egiste r
Segm ent out put enable regis ter
L
C
D
m
o
d
e
r
e
g
i
s
t
e
r
I
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
1
Interrupt request registe r 2
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
Interrupt control register 2
P
r
o
c
e
s
s
o
r
s
t
a
t
u
s
r
e
g
i
s
t
e
r
Program c ounter
P
o
r
t
P
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
P
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Timer 1
T
i
m
e
r
2
T
i
m
e
r
3
✕1✕✕✕✕✕✕
0
01
6
6816
0016
0716
0
81
6
0
01
6
0
01
6
0
01
6
F
F
1
6
101
6
F
F
1
6
F
F
1
6
F
F
1
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
F
F
1
6
F
F
1
6
0016
C
o
n
t
e
n
t
s
o
f
a
d
d
r
e
s
s
F
F
F
D
1
6
C
o
n
t
e
n
t
s
o
f
a
d
d
r
e
s
s
F
F
F
C
1
6
T
e
m
p
o
r
a
r
y
d
a
t
a
r
e
g
i
s
t
e
r
1
φ output control register
T
e
m
p
o
r
a
r
y
d
a
t
a
r
e
g
i
s
t
e
r
0
0
01
6
0016
0016
0
01
6
0016
(
30
)
(
3
1
)
(
32
)
(
3
3
)
0016
0016
0016
0016
Tem porary data r egis ter 2
R
R
F
r
e
g
i
s
t
e
r
PULL register
003
E
16
0
0
3
F
1
6
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
39
CLOCK GENERATING CIRCUIT
The oscillation circuit of 38C1 group can be formed by connecting
an oscillator, capacitor and resistor between XIN and XOUT (XCIN
and XCOUT). To supply a clock signal externally, input it to the XIN
pin and make the XOUT pin open. The clocks that are externally
generated cannot be directly input to XCIN. Use the circuit con-
stants in accordance with the oscillator manufacturer's recom-
mended values. No external resistor is needed between XIN and
XOUT since a feed-back resistor exists on-chip. However, a 10 MΩ
external feed-back resistor is needed between XCIN and XCOUT.
Immediately after reset is released, only the built-in ring oscillator
starts oscillating, XIN -XOUT oscillation stops oscillating, and XCIN
and XCOUT pins function as I/O ports.
Operation mode
(1) Ring oscillator mode
The internal clock φ is the built-in ring oscillator oscillation divided
by 8.
(2) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8.
(3)High-speed mode
The internal clock φ is half the frequency of XIN.
(4) Low-speed mode
The internal clock φ is half the frequency of XCIN.
After reset release and when system returns from the stop mode,
the ring oscillator mode is selected.
Refer to the clock state transition diagram for the setting of transi-
tion to each mode.
The XIN–XOUT oscillation is controlled by the bit 5 of CPUM, and
the sub-clock oscillation is controlled by the bit 4 of CPUM. When
the mode is switched to the ring oscillator mode, set the bit 3 of
CPUM to “1”.
In the ring oscillator mode, the oscillation by the oscillator can be
stopped. In the low-speed mode, the power consumption can be
reduced by stopping the XIN–XOUT oscillation.
When the mode is switched from the ring oscillator mode to the
low-speed mode, the built-in ring oscillator is stopped.
Set enough time for oscillation to stabilize by programming to re-
start the stopped oscillation and switch the operation mode. Also,
set enough time for oscillation to stabilize by programming to
switch the timer count source .
Note: If you switch the mode between ring oscillator mode,
middle/high-speed mode and low-speed mode, stabilize
both XIN and XCIN oscillations. Especially be careful imme-
diately after power-on and at returning from stop mode. Re-
fer to the clock state transition diagram for the setting of
transition to each mode. Set the frequency in the condition
that f(XIN) > 3•f(XCIN).
When the middle- and high-speed mode are not used (XIN-
XOUT oscillation and external clock input are not
performed), connect XIN to VCC through a resistor.
Fig. 40 Oscillator circuit
Fig. 41 External clock input circuit
Oscillation Control
(1) Stop mode
Set the timer 1 interrupt enable bit to disabled (“0”) before execut-
ing the STP instruction. If the STP instruction is executed, the in-
ternal clock φ stops at an “H” level, and main clock, ring oscillator
and sub-clock oscillators stop.
In this time, “0116” is set to timer 1 and the ring oscillator is con-
nected forcibly for the system clock and the timer 1 count source.
Also, the bits of the timer 123 mode register except bit 4 are
cleared to “0”.
When an external interrupt is received, the clock oscillated before
stop mode and the ring oscillator start oscillating.
However, bit 3 of CPUM is set to “1” forcibly and system returns to
the ring oscillator mode.
Tthe internal clock φ is supplied to the CPU after timer 1
underflows. However, when the system clock is switched from the
ring oscillator to main clock and sub-clock, generate the wait time
enough for oscillation stabilizing by program.
(2) Wait mode
If the WIT instruction is executed, only the internal clock φ stops at
an “H” level. The states of main clock, ring oscillator and sub-clock
are the same as the state before the executing the WIT instruction
and the oscillation does not stop. Since the internal clock φ re-
starts when an interrupt is received, the instruction is executed im-
mediately.
X
C
I
N
C
IN
C
OUT
C
C
I
N
C
COUT
R
fR
d
X
O
U
T
X
I
N
X
C
O
U
T
E
x
t
e
r
n
a
l
o
s
c
i
l
l
a
t
i
o
n
c
i
r
c
u
i
t
O
p
e
n
V
C
C
V
S
S
C
C
I
N
R
fR
d
C
C
O
U
T
X
C
I
N
X
OUT
X
I
N
X
C
O
U
T
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
40
Fig. 42 Clock generating circuit block diagram
S
R
Q
XI
N-
XO
U
T
o
s
c
i
l
l
a
t
i
o
n
s
t
o
p
b
i
t
C
P
U
M
B
I
T
5
X
I
N
X
O
U
T
X
C
O
U
T
X
C
I
N
Port Xc switch bit
CPUM BIT4
“
0
”
“
1
”M
a
i
n
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
C
P
U
M
B
I
T
3
Ring oscillator
1
/
21/4 1
/
2
M
a
i
n
c
l
o
c
k
d
i
v
i
s
i
o
n
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
C
P
U
M
B
I
T
6
Main clock
selection bit
CPUM BIT3
S
R
Q
Timer 1
S
R
Q
WIT instruction
T
i
m
i
n
g
φ
(
I
n
t
e
r
n
a
l
c
l
o
c
k
)
STP instruction
Interrupt request
Reset
Timer 1 count
source selection bit
T123M BIT 5
Internal system
clock selection bit
CPUM BIT7
N
o
t
e
:
W
h
e
n
X
c
o
s
c
i
l
l
a
t
i
o
n
i
s
s
e
l
e
c
t
e
d
f
o
r
i
n
t
e
r
n
a
l
s
y
s
t
e
m
c
l
o
c
k
,
s
e
t
t
h
e
p
o
r
t
X
c
s
w
i
t
c
h
b
i
t
t
o
“
1
”
.
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
g
I
S
T
P
i
n
s
t
r
u
c
t
i
o
n
I
n
t
e
r
n
a
l
s
y
s
t
e
m
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
(
N
o
t
e
)
C
P
U
M
B
I
T
7
“0”
“
1
”
“1”“0”
“
1
”
“0”
“0”
“1”
“
0
”
“
1
”“
0
”
“
1
”
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
41
Fig. 43 State transitions of system clock
R
e
s
e
t
r
e
l
e
a
s
e
X
IN
stop
X
CIN
stop
φ=f(ROSC)/8
CM7=0
CM6=1 (Note 5)
CM5=1
CM4=0
CM3=1
X
IN
stop
X
CIN
oscillation
φ=f(ROSC)/8
CM7=0
CM6=1 (Note 5)
CM5=1
CM4=1
CM3=1
X
I
N
o
s
c
i
l
l
a
t
i
o
n
X
C
I
N
s
t
o
p
φ=
f
(
R
O
S
C
)
/
8
C
M7=
0
C
M6=
1
(
N
o
t
e
5
)
C
M5=
0
C
M4=
0
C
M3=
1
X
I
N
o
s
c
i
l
l
a
t
i
o
n
X
C
I
N
o
s
c
i
l
l
a
t
i
o
n
φ=f(ROSC)/8
CM7=0
CM6=1(Note 5)
CM5=0
CM4=1
CM3=1
C
M4
C
M4
C
M4
C
M5
C
M5C
M5
X
I
N
s
t
o
p
X
C
I
N
o
s
c
i
l
l
a
t
i
o
n
φ=
1
6
k
H
z
C
M7=
1
C
M6=
1
C
M5=
1
C
M4=
1
C
M3=
*
(
N
o
t
e
9
)
X
I
N
o
s
c
i
l
l
a
t
i
o
n
X
C
I
N
o
s
c
i
l
l
a
t
i
o
n
φ=
1
6
k
H
z
C
M7=
1
C
M6=
0
(
N
o
t
e
5
)
C
M5=
0
C
M4=
1
C
M3=
*
(
N
o
t
e
9
)
CM6
C
M6
C
M5CM5
X
IN
oscillation
X
CIN
stop
φ=
1
M
H
z
C
M7=
0
C
M6=
1
C
M5=
0
C
M4=
0
C
M3=
0
X
IN
oscillation
X
CIN
oscillation
φ=1MHz
CM7=0
CM6=1
CM5=0
CM4=1
CM3=0
C
M4
X
I
N
o
s
c
i
l
l
a
t
i
o
n
X
C
I
N
s
t
o
p
φ=
4
M
H
z
C
M7=
0
C
M6=
0
(
N
o
t
e
5
)
C
M5=
0
C
M4=
0
C
M3=
0
X
I
N
o
s
c
i
l
l
a
t
i
o
n
X
C
I
N
o
s
c
i
l
l
a
t
i
o
n
φ=4MHz
CM7=0
CM6=0 (Note 5)
CM5=0
CM4=1
CM3=0
CM4
C
M7
CM7C
M7
X
I
N
o
s
c
i
l
l
a
t
i
o
n
X
C
I
N
o
s
c
i
l
l
a
t
i
o
n
φ=
1
6
k
H
z
C
M7=
1
C
M6=
1
C
M5=
0
C
M4=
1
C
M3=
*
(
N
o
t
e
9
)
R
i
n
g
o
s
c
i
l
l
a
t
o
r
m
o
d
eL
o
w
-
s
p
e
e
d
m
o
d
e
Middle-speed mode
High-speed mode
C
M3
b7 b
3
C
M3
C
M6CM6
C
M7
N
o
t
e
s
1
: S
w
i
t
c
h
t
h
e
m
o
d
e
b
y
t
h
e
a
r
r
o
w
s
s
h
o
w
n
b
e
t
w
e
e
n
t
h
e
m
o
d
e
b
l
o
c
k
s
.
T
h
e
a
l
l
m
o
d
e
s
c
a
n
b
e
s
w
i
t
c
h
e
d
t
o
t
h
e
s
t
o
p
m
o
d
e
o
r
t
h
e
w
a
i
t
m
o
d
e
.
2
:
T
i
m
e
r
a
n
d
L
C
D
o
p
e
r
a
t
e
i
n
t
h
e
w
a
i
t
m
o
d
e
.
S
y
s
t
e
m
i
s
r
e
t
u
r
n
e
d
t
o
t
h
e
s
o
u
r
c
e
m
o
d
e
w
h
e
n
t
h
e
w
a
i
t
m
o
d
e
i
s
e
n
d
e
d
.
3
:
C
M
4
,
C
M
5
a
n
d
C
M
6
a
r
e
r
e
t
a
i
n
e
d
i
n
t
h
e
s
t
o
p
m
o
d
e
.
S
y
s
t
e
m
i
s
r
e
t
u
r
n
e
d
t
o
t
h
e
r
i
n
g
o
s
c
i
l
l
a
t
o
r
m
o
d
e
(
C
M
3
=
1
,
C
M
7
=
0
)
.
4
:
W
h
e
n
t
h
e
s
t
o
p
m
o
d
e
i
s
e
n
d
e
d
,
s
e
t
t
h
e
o
s
c
i
l
l
a
t
i
o
n
s
t
a
b
i
l
i
z
i
n
g
w
a
i
t
t
i
m
e
i
n
t
h
e
r
i
n
g
o
s
c
i
l
l
a
t
o
r
m
o
d
e
.
5
:
W
h
e
n
t
h
e
s
t
o
p
m
o
d
e
i
s
e
n
d
e
d
,
s
e
t
t
h
e
i
n
i
t
i
a
l
v
a
l
u
e
t
o
C
M
6
(
C
M
6
=
1
)
.
6
:
E
x
e
c
u
t
e
t
h
e
t
r
a
n
s
i
t
i
o
n
a
f
t
e
r
t
h
e
o
s
c
i
l
l
a
t
i
o
n
u
s
e
d
i
n
t
h
e
d
e
s
t
i
n
a
t
i
o
n
m
o
d
e
i
s
s
t
a
b
i
l
i
z
e
d
.
7
:
W
h
e
n
s
y
s
t
e
m
g
o
e
s
t
o
r
i
n
g
o
s
c
i
l
l
a
t
o
r
m
o
d
e
,
t
h
e
o
s
c
i
l
l
a
t
i
o
n
s
t
a
b
i
l
i
z
i
n
g
w
a
i
t
t
i
m
e
i
s
n
o
t
n
e
e
d
e
d
.
8
:
D
o
n
o
t
g
o
t
o
t
h
e
h
i
g
h
-
s
p
e
e
d
m
o
d
e
f
r
o
m
t
h
e
r
i
n
g
o
s
c
i
l
l
a
t
o
r
m
o
d
e
.
9
:
W
r
i
t
e
t
h
e
p
r
o
p
e
r
v
a
l
u
e
s
f
o
r
d
e
s
t
i
n
a
t
i
o
n
m
o
d
e
b
e
f
o
r
e
h
a
n
d
.
1
0
:
T
h
e
e
x
a
m
p
l
e
a
s
s
u
m
e
s
t
h
a
t
8
M
H
z
i
s
b
e
i
n
g
a
p
p
l
i
e
d
t
o
t
h
e
X
I
N
p
i
n
a
n
d
3
2
k
H
z
t
o
t
h
e
X
C
I
N
p
i
n
.
f
(
R
O
S
C
)
i
n
d
i
c
a
t
e
s
t
h
e
o
s
c
i
l
l
a
t
i
o
n
f
r
e
q
u
e
n
c
y
o
f
r
i
n
g
o
s
c
i
l
l
a
t
o
r
.
Main clock selection bit
0: X
IN
input signal
1: Ring oscillator
Port Xc switch bit
0: I/O port function (Oscillation stop)
1: X
CIN
, X
COUT
function
X
IN
–X
OUT
oscillation stop bit
0: Oscillating
1: Stopped
Main clock division ratio selection bit
0: f(X
IN
)/2 (high-speed mode)
1: f(X
IN
)/8 (middle-speed mode)
Internal system clock selection bit
0: Main clock selected
(middle-/high-speed and ring oscillator mode)
1: X
CIN
–X
COUT
selected
(low-speed mode)
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
(
C
P
U
M
:
a
d
d
r
e
s
s
0
0
3
B
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
6
8
1
6
)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
42
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.
Interrupt
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt re-
quest register, execute at least one instruction before performing a
BBC or BBS instruction.
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D) to
“1”, then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
•The data transfer instruction (LDA, etc.)
•The operation instruction when the index X mode flag (T) is “1”
•The addressing mode which uses the value of a direction regis-
ter as an index
•The bit-test instruction (BBC or BBS, etc.) to a direction register
•The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit en-
able bit, the receive enable bit, and the SRDY output enable bit to
“1”.
In serial I/O, the SOUT pin goes to high impedance state after
transmission is completed.
A-D Converter
The comparator is constructed linked to a capacitor. The conver-
sion accuracy may be low because the charge is lost if the conver-
sion speed is not enough.
Accordingly, set f(XIN) to at least 500kHz during A-D conversion in
the middle- or high-speed mode.
Also, do not execute the STP or WIT instruction during an A-D
conversion.
In the low-speed mode, since the A-D conversion is executed by
the built-in self-oscillation circuit, the minimum value of f(XIN) fre-
quency is not limited.
Instruction Execution Time
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
43
NOTES ON USE
VL3 pin
When LCD drive control circuit is not used, connect VL3 to VCC.
Countermeasures against noise
(1) Shortest wiring length
➀ Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin
as short as possible. Especially, connect a capacitor across the
RESET pin and the VSS pin with the shortest possible wiring
(within 20mm).
● Reason
The width of a pulse input into the RESET pin is determined by
the timing necessary conditions. If noise having a shorter pulse
width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is com-
pletely initialized. This may cause a program runaway.
Fig. 45 Wiring for clock I/O pins
(2) Connection of bypass capacitor across VSS line and VCC line
In order to stabilize the system operation and avoid the latch-up,
connect an approximately 0.1
µ
F bypass capacitor across the VSS
line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC pin
at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin
with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS
line and VCC line.
• Connect the power source wiring via a bypass capacitor to the
VSS pin and the VCC pin.
Fig. 44 Wiring for the RESET pin
➁ Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins
as short as possible.
• Make the length of wiring (within 20 mm) across the grounding
lead of a capacitor which is connected to an oscillator and the
VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS
patterns.
● Reason
If noise enters clock I/O pins, clock waveforms may be de-
formed. This may cause a program failure or program runaway.
Also, if a potential difference is caused by the noise between
the VSS level of a microcomputer and the VSS level of an oscil-
lator, the correct clock will not be input in the microcomputer.
Fig. 46 Bypass capacitor across the VSS line and the VCC line
RESET
Reset
circuit
Noise
VSSVSS
Reset
circuit
VSS
RESET
VSS
N.G.
O.K.
Noise
X
IN
X
OUT
V
SS
X
IN
X
OUT
V
SS
N.G. O.K.
V
SS
V
CC
AA
AA
AA
AA
AA
AA
V
SS
V
CC
AA
AA
AA
AA
AA
AA
AA
AA
AA
N.G. O.K.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
44
(3) Oscillator concerns
In order to obtain the stabilized operation clock on the user system
and its condition, contact the oscillator manufacturer and select
the oscillator and oscillation circuit constants. Be careful espe-
cially when range of voltage or/and temperature is wide.
Also, take care to prevent an oscillator that generates clocks for a
microcomputer operation from being affected by other signals.
➀ Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as
possible from signal lines where a current larger than the toler-
ance of current value flows.
● Reason
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When a
large current flows through those signal lines, strong noise oc-
curs because of mutual inductance.
➁ Installing oscillator away from signal lines where potential levels
change frequently
Install an oscillator and a connecting pattern of an oscillator
away from signal lines where potential levels change frequently.
Also, do not cross such signal lines over the clock lines or the
signal lines which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as
the CNTR pin signal line) may affect other lines at signal rising
edge or falling edge. If such lines cross over a clock line, clock
waveforms may be deformed, which causes a microcomputer
failure or a program runaway.
➀ Keeping oscillator away from large current signal lines
➁ Installing oscillator away from signal lines where potential
levels change frequently Fig. 48 Wiring for the VPP pin of One Time PROM
Fig. 47 Wiring for a large current signal line/
Wiring of signal
lines where potential levels change frequently
XI
N
XO
U
T
VS
S
M
M
i
c
r
o
c
o
m
p
u
t
e
r
Mutual inductance
Large
current
GND
X
I
N
X
O
U
T
V
S
S
C
N
T
R
D
o
n
o
t
c
r
o
s
s
N.G.
(4) Analog input
The analog input pin is connected to the capacitor of a voltage
comparator. Accordingly, sufficient accuracy may not be obtained
by the charge/discharge current at the time of A-D conversion
when the analog signal source of high-impedance is connected to
an analog input pin. In order to obtain the A-D conversion result
stabilized more, please lower the impedance of an analog signal
source, or add the smoothing capacitor to an analog input pin.
(5) Difference of memory type and size
When Mask ROM and PROM version and memory size differ in
one group, actual values such as an electrical characteristics, A-D
conversion accuracy, and the amount of -proof of noise incorrect
operation may differ from the ideal values.
When these products are used switching, perform system evalua-
tion for each product of every after confirming product
specification.
(6) Wiring to VPP pin of One Time PROM version
Connect an approximately 5 kΩ resistor to the VPP pin the shortest
possible in series and also to the VSS pin.
Note: Even when a circuit which included an approximately 5 kΩ
resistor is used in the Mask ROM version, the microcom-
puter operates correctly.
● Reason
The VPP pin of the One Time PROM version is the power source
input pin for the built-in PROM. When programming in the built-in
PROM, the impedance of the VPP pin is low to allow the electric
current for writing flow into the built-in PROM. Because of this,
noise can enter easily. If noise enters the VPP pin, abnormal in-
struction codes or data are read from the built-in PROM, which
may cause a program runaway.
C
N
V
S
S
/
V
P
P
V
SS
About 5kΩ
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
45
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
1.Mask ROM Order Confirmation Form✽
2.Mark Specification Form✽
3.Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
✽For the mask ROM confirmation and the mark specifications, re-
fer to the “Mitsubishi MCU Technical Information” Homepage
(http://www.infomicom.maec.co.jp/indexe.htm).
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version
(M38C13E6FP/HP) can be read or programmed with a general-
purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
Table 10. Programming adapter
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 49 is recommended to verify programming.
Fig. 49 Programming and testing of One Time PROM version
Package
M38C13E6FP
M38C13E6HP
Name of Programming Adapter
PCA7438F-64A
PCA7438H-64A
P
r
o
g
r
a
m
m
i
n
g
w
i
t
h
P
R
O
M
p
r
o
g
r
a
m
m
e
r
Screening (Caution)
(150°C for 40 hours)
V
e
r
i
f
i
c
a
t
i
o
n
w
i
t
h
P
R
O
M
p
r
o
g
r
a
m
m
e
r
Functional check in
target device
Th e scree ni ng tem per ature is far hi ghe
r
than the storage temperature. Neve
r
expose to 150 °C exceeding 100 hours.
Caution :
46
38C1 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Table 11 Absolute maximum ratings
Parameter
Power source voltage
Input voltage P00–P07, P20–P27, P30–P34,
P44–P47, P50–P57, P60–P64
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage RESET, XIN
Input voltage AN0–AN3
Input voltage CNVSS (Mask ROM version)
Input voltage CNVSS (One Time PROM version)
Output voltage P20–P27
Output voltage P30–P34, P44–P47, P50–P57, P60–P64
Output voltage SEG0–SEG24
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
Symbol
VCC
VI
VI
VI
VI
VI
VI
VI
VI
VO
VO
VO
VO
Pd
Topr
Tstg
Conditions
All voltages are based on Vss.
Output transistors are cut off.
At output port
At segment output
Ta = 25°C
Ratings
–0.3 to 6.5
–0.3 to VCC+0.3
–0.3 to VL2
VL1 to VL3
VL2 to 6.5
–0.3 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to 13
–0.3 to VCC+0.3
–0.3 to VL3+0.3
–0.3 to VCC+0.3
–0.3 to VL3+0.3
–0.3 to VCC+0.3
300
–20 to 85
–40 to 125
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mW
°C
°C
47
38C1 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Recommended Operating Conditions
Table 12 Recommended operating conditions
(Vcc = 1.8 to 5.5 V (One Time PROM version: 2.2 to 5.5 V), Ta = –20 to 85°C, unless otherwise noted)
Power source voltage High-speed mode f(XIN) ≤ 8 MHz
(Note 1) f(XIN) ≤ 6 MHz
Mask ROM version High-speed mode f(XIN) ≤ 4 MHz
Middle-speed mode f(XIN) ≤ 8 MHz
f(XIN) ≤ 6 MHz
Low-speed, ring oscillator operation mode
One Time PROM version High-speed mode f(XIN) ≤ 4 MHz
Middle-speed mode f(XIN) ≤ 8 MHz
f(XIN) ≤ 6 MHz
Low-speed, ring oscillator operation mode
When oscillation starts Mask ROM version
(Note 2) One Time PROM version
Power source voltage
LCD power source voltage
Analog input voltage AN0–AN7
“H” input voltage
P0
0
–P0
7
, P2
0
–P2
7
, P4
4
–P4
7
, P5
5
, P5
7
, P6
2
–P6
4
“H” input voltage P60, P61 (CM4=0)
“H” input voltage P30–P34, P50–P54, P56
“H” input voltage RESET
“H” input voltage XIN
“L” input voltage
P0
0
–P0
7
, P2
0
–P2
7
, P4
4
–P4
7
, P5
5
, P5
7
, P6
2
–P6
4
“L” input voltage P60, P61 (CM4=0)
“L” input voltage P30–P34, P50–P54, P56
“L” input voltage RESET
“L” input voltage XIN
VCC
VSS
CNVSS
VL3
VIA
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
Limits
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Parameter Min.
4.0
3.0
2.0
2.0
1.8
1.8
2.5
2.5
2.2
2.2
2.2
2.5
2.5
VSS
0.7VCC
0.7VCC
0.8VCC
0.8VCC
0.8VCC
0
0
0
0
0
Typ.
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
0
0
Max.
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
0.2VCC
VCC
VCC
VCC
VCC
VCC
VCC
0.3VCC
0.3VCC
0.2VCC
0.2VCC
0.2VCC
Symbol Unit
Notes 1: When the A-D converter is used, refer to the recommended operating condition for A-D conversion.
2: Oscillation start voltage and oscillation start time depend on the oscillator, the circuit constant and temperature.
Especially, be careful that an oscillation start of the high-frequency oscillator may be difficult at low-voltage.
Until the oscillation is stabilized, wait in the ring oscillator mode.
48
38C1 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
“H” total peak output current (Note 1)
P20–P27, P30–P34
“H” total peak output current (Note 1)
P44–P47, P50–P57, P60–P64
“L” total peak output current (Note 1)
P20–P27, P30–P34
“L” total peak output current (Note 1)
P44–P47, P50–P57, P60–P64
“H” total average output current (Note 1)
P20–P27, P30–P34
“H” total average output current (Note 1)
P44–P47, P50–P57, P60–P64
“L” total average output current (Note 1)
P20–P27, P30–P34
“L” total average output current (Note 1)
P44–P47, P50–P57, P60–P64
“H” peak output current (Note 2)
P20–P27
“H” peak output current (Note 2)
P30–P34
“H” peak output current (Note 2)
P44–P47, P50–P57, P60–P64
“L” peak output current (Note 2)
P20–P27
“L” peak output current (Note 2)
P30–P34
“L” peak output current (Note 2)
P44–P47, P50–P57, P60–P64
“H” average output current (Note 3)
P20–P27
“H” average output current (Note 3)
P30–P34
“H” average output current (Note 3)
P44–P47, P50–P57, P60–P64
“L” average output current (Note 3)
P20–P27
“L” average output current (Note 3)
P30–P34
“L” average output current (Note 3)
P44–P47, P50–P57, P60–P64
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
IOH(peak)
IOL(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
IOL(avg)
Limits
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Parameter Min. Typ. Max.
Symbol Unit
–40
–60
80
60
–20
–30
40
30
–2
–5
–5
5
30
10
–1.0
–2.5
–2.5
2.5
15
5
Table 13 Recommended operating conditions
(Vcc = 1.8 to 5.5 V (One Time PROM version: 2.2 to 5.5 V), Ta = –20 to 85°C, unless otherwise noted)
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over
100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is average value measured over 100 ms.
49
38C1 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 14 Recommended operating conditions
(Vcc = 1.8 to 5.5 V (One Time PROM version: 2.2 to 5.5 V), Ta = –20 to 85°C, unless otherwise noted)
Timer X and Timer Y
Input frequency (duty cycle 50%)
Main clock input frequency
(duty cycle 50%)
(Note 1)
Sub-clock input oscillation
frequency (Note 2) (Note 4)
(duty cycle 50%)
f(CNTR0)
f(CNTR1)
f(XIN)
f(XCIN)
Limits
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
Parameter Min. Typ.
32.768
Max.
4.0
VCC
5✕VCC–8
2✕VCC–3
10✕VCC–19
3
8.0
2✕VCC
4✕VCC–6
8.0
6.0
80
Symbol Unit
(4.0 V ≤ VCC ≤ 5.5 V)
(Mask ROM version: 2.0V ≤ VCC ≤ 4.0 V)
(One T ime PROM version: 3.0 V ≤ VCC ≤ 4.0 V)
(Mask ROM version: VCC ≤ 2.0 V)
(One T ime PROM version: 2.5 V ≤ VCC ≤ 3.0 V)
(One Time PROM version: VCC ≤ 2.5 V)
High-speed mode (4.0 V < VCC ≤ 5.5 V)
High-speed mode
(Mask ROM version: 2.0V ≤ VCC ≤ 4.0 V)
(One T ime PROM version: 3.0 V ≤ VCC ≤ 4.0 V)
High-speed mode
(One T ime PROM version: 2.5 V ≤ VCC ≤ 3.0 V)
Middle-speed mode (Note 3) (Note 4)
(Mask ROM version: 2.0 V ≤ VCC ≤ 5.5 V)
(One T ime PROM version: 2.5 V ≤ VCC ≤ 5.5 V)
Middle-speed mode (Note 3) (Note 4)
Notes 1: When the A-D converter is used, refer to the recommended operating condition for A-D conversion.
2: When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
3: When the timer X count source selection bit is set to “1”, as for the recommended operating condition of the main clock input frequency f(XIN), the rating
value at the high-speed mode is applied.
4: Oscillation start voltage and oscillation start time depend on the oscillator, the circuit constant and temperature.
Especially, be careful that an oscillation start of the high-frequency oscillator may be difficult at low-voltage.
Until the oscillation is stabilized, wait in the ring oscillator mode.
Condition
50
38C1 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
IOH = –1.0 mA
IOH = –0.2 mA
VCC = 1.8 to 5.5 V (Note)
IOH = –2.5 mA
IOH = –0.5 mA
VCC = 1.8 to 5.5 V (Note)
IOL = 2.5 mA
IOL = 0.5 mA
VCC = 1.8 to 5.5 V (Note)
IOL = 5 mA
IOL = 1 mA
VCC = 1.8 to 5.5 V (Note)
IOL = 15 mA
IOL = 3 mA
VCC = 1.8 to 5.5 V (Note)
VI = VCC
VI = VSS
Pull-down “OFF”
VCC = 5.0 V, VI = VCC
Pull-down “ON”
VCC = 3.0 V, VI = VCC
Pull-down “ON”
VI = VCC
VI = VCC
VI = VSS
VI = VSS
Pull-up “OFF”
VCC = 5.0 V, VI = VSS
Pull-up “ON”
VCC = 3.0 V, VI = VSS
Pull-up “ON”
VI = VSS
VI = VSS
At clock stop
At clock stop
VCC = 5.0 V, Ta = 25 °C
“H” output voltage
P20–P27
“H” output voltage
P30–P34, P44–P47, P50–P57, P60–P64
“L” output voltage
P20–P27
“L” output voltage
P44–P47, P50–P57, P60–P64
“L” output voltage
P30–P34
Hysteresis
INT0, INT1, CNTR0, CNTR1, P30–P34
Hysteresis SCLK, SIN
Hysteresis RESET
“H” input current
P30–P34, P44–P47,
P50–P57, P60–P64
“H” input current P00–P07, P20–P27
“H” input current RESET, AN0–AN3
“H” input current XIN
“L” input current P00–P07, P20–P27
“L” input current
P30–P34, P44–P47,
P50–P57, P60–P64
“L” input current RESET, CNVSS, AN0–AN3
“L” input current XIN
RAM hold voltage (Mask ROM version)
RAM hold voltage (One Time PROM version)
Ring oscillator oscillation frequency
Limits
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
V
V
kHz
Parameter Min.
VCC–2.0
VCC–0.8
VCC–2.0
VCC–0.8
60
25
–60
–25
1.8
2.2
2500
Typ.
0.5
0.5
0.5
120
50
4.0
–120
–50
–4.0
5000
Max.
2.0
0.8
2.0
0.8
2.0
0.8
5.0
5.0
240
100
5.0
–5.0
–5.0
–240
–100
–5.0
5.5
5.5
7500
Symbol UnitTest conditions
VOH
VOH
VOL
VOL
VOL
VT+–VT-
VT+–VT-
VT+–VT-
IIH
IIH
IIH
IIH
IIL
IIL
IIL
IIL
VRAM
ROSC
Electrical Characteristics
Table 15 Electrical characteristics
(Vcc = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Note: One Time PROM version: 2.2 to 5.5 V.
51
38C1 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Power
source
current
Limits
Parameter Min. Typ.
3.0
0.8
1.5
4.7
0.9
2.5
0.6
0.3
0.4
0.9
0.3
0.6
1.2
0.8
0.8
1.8
0.9
1.0
0.5
0.3
0.3
0.7
0.4
0.4
13
5.5
19
6.5
7.0
3.5
10
3.5
600
90
30
0.1
0.5
0.5
0.4
Max.
6.0
1.6
3.0
9.4
1.8
5.0
1.2
0.6
0.8
1.8
0.6
1.2
2.4
1.6
1.6
3.6
1.8
2.0
1.0
0.6
0.6
1.4
0.8
0.8
26
11
38
13
14
7.0
20
7
1200
270
90
1.0
10
Symbol Unit
f(XIN) = 8 MHz
f(XIN) = 8 MHz (in WIT state)
f(XIN) = 4 MHz
f(XIN) = 8 MHz
f(XIN) = 8 MHz (in WIT state)
f(XIN) = 4 MHz
f(XIN) = 4 MHz
f(XIN) = 4 MHz (in WIT state)
f(XIN) = 2 MHz
f(XIN) = 4 MHz
f(XIN) = 4 MHz (in WIT state)
f(XIN) = 2 MHz
f(XIN) = 8 MHz
f(XIN) = 8 MHz (in WIT state)
f(XIN) = 4 MHz
f(XIN) = 8 MHz
f(XIN) = 8 MHz (in WIT state)
f(XIN) = 4 MHz
f(XIN) = 8 MHz
f(XIN) = 8 MHz (in WIT state)
f(XIN) = 4 MHz
f(XIN) = 8 MHz
f(XIN) = 8 MHz (in WIT state)
f(XIN) = 4 MHz
f(XIN) = stop
WIT instruction executed
f(XIN) = stop
WIT instruction executed
f(XIN) = stop
WIT instruction executed
f(XIN) = stop
WIT instruction executed
VCC = 5 V
VCC = 2.5 V
VCC = 2.5 V (in WIT state)
Ta = 25 °C
Ta = 85 °C
f(XIN) = 8 MHz, VCC = 5 V
at middle-, high-speed mode
f(XIN) = stop, VCC = 5 V
at ring oscillator operation mode
f(XIN) = stop, VCC = 5 V
at low-speed mode
Test conditions
ICC mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
Table 16 Electrical characteristics
(Vcc = 1.8 to 5.5 V (One Time PROM version: 2.2 to 5.5 V), Ta = –20 to 85°C, f(XCIN) = 32.768 kHz, output transistors “OFF”, AD converter
stopped, unless otherwise noted)
High-speed
mode
Middle-speed
mode
Low-speed
mode
Ring oscillator mode
f(XCIN) = stop
All oscillations stop
(STP instruction executed)
Current increased
when AD converter is operating
Vcc = 5 V
Mask ROM
version
Vcc = 5 V
One Time PROM
version
Vcc = 2.5 V
Mask ROM
version
Vcc = 2.5 V
One Time PROM
version
Vcc = 5 V
Mask ROM
version
Vcc = 5 V
One Time PROM
version
Vcc = 2.5 V
Mask ROM
version
Vcc = 2.5 V
One Time PROM
version
Vcc = 5 V
Mask ROM
version
Vcc = 5 V
One Time PROM
version
Vcc = 2.5 V
Mask ROM
version
Vcc = 2.5 V
One Time PROM
version
52
38C1 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
A-D Converter Characteristics
Table 17 A-D converter recommended operating condition
(Vcc = 2.0 to 5.5 V (One Time PROM version: 2.2 to 5.5 V), Ta = –20 to 85°C, unless otherwise noted)
Power source voltage
“H” input voltage
ADKEY0–ADKEY3
“L” input voltage
ADKEY0–ADKEY3
AD converter control clock
(low-speed mode and ring
oscillator mode excluded)
Unit
V
V
V
V
MHz
MHz
MHz
Limits
Parameter Min.
2.0
2.2
0.9VCC
0
Typ.
5.0
5.0
Max.
5.5
5.5
VCC
0.7VCC✕–0.5
20✕VCC–38
20✕VCC–26
3
40✕VCC–82
3
10✕VCC–19
8.0
Symbol
Mask ROM version
One Time PROM version
Mask ROM version VCC ≤ 2.2 V
2.2 < VCC ≤ 2.5 V
One Time PROM version VCC ≤ 2.5 V
2.5 < VCC ≤ 2.7 V
Mask ROM version 2.5 < VCC ≤ 5.5 V
One Time PROM version 2.7 < VCC ≤ 5.5 V
Conditions
VDD
VIH
VIL
f(XIN)
Table 18 A-D converter characteristics
(Vcc = 2.0 to 5.5 V (One Time PROM version: 2.2 to 5.5 V), Ta = –20 to 85°C, unless otherwise noted)
Resolution
Linearity error
Differential non-linearity error
Zero transition voltage
Full-scale transition voltage
Absolute accuracy
(quantification error excluded)
Conversion time (Note)
Analog input current
Unit
BIT
LSB
LSB
mV
mV
mV
mV
LSB
LSB
LSB
LSB
tc(φAD)
µA
Limits
Parameter Min.
0
0
5070
2535
106
Typ.
20
10
5100
2550
Max.
8
±1
±0.9
50
25
5120
2560
±2
±2
±5
±3
109
±5
Symbol
Ta = 25 °C, 2.5 ≤ VCC ≤ 5.5 V
Ta = 25 °C, 2.5 ≤ VCC ≤ 5.5 V
VCC = 5.12 V, Ta = 25 °C
VCC = 2.56 V, Ta = 25 °C
VCC = 5.12 V, Ta = 25 °C
VCC = 2.56 V, Ta = 25 °C
2.2 < V
CC
≤ 5.5 V (2.7 < V
CC
≤ 5.5 V for One T ime PROM version),
f(XIN) ≤ 8.0 MHz, or low-speed or ring oscillator mode
2.2 < V
CC
≤ 2.5 V (2.5 < V
CC
≤ 2.7 V for One T ime PROM version),
f(XIN) ≤ 2.0 MHz, or low-speed or ring oscillator mode
2.2 ≤ VCC < 2.3 V for One Time PROM version
Low-speed or ring oscillator mode excluded
Condition except above
Test conditions
—
LIN
DIF
V0T
VFST
ABS
Tconv
IIA
Note: The operation clock is XIN in the middle- or high-speed mode, or the ring oscillator in the other modes.
When the A-D conversion is executed in the middle- or high-speed mode, set f(XIN) ≥ 500 kHz.
tc(φAD): One cycle of control clock for A-D converter. XIN input is used in the middel- or high-speed mode, and ring oscillator is used in the low- or ring
oscillator mode for the control clock.
53
38C1 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0, INT1 input “H” pulse width
INT0, INT1 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
Serial I/O input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(SIN-SCLK)
th(SCLK-SIN)
Limits
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
2
125
50
50
250
105
105
80
80
1000
400
400
200
200
Typ. Max.
Symbol Unit
Table 20 Timing requirements 2
(Vcc =1.8 to 4.0 V (2.2 to 4.0 V for One Time PROM version), Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Timing Requirements And Switching Characteristics
Table 19 Timing requirements 1
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(RxD-SCLK)
th(SCLK-RxD)
Limits
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
2
125
166
50
70
50
70
1000/VCC
1000/(5✕VCC–8)
tc(CNTR)/2–20
tc(CNTR)/2–20
230
230
2000
950
950
400
200
Typ. Max.
Symbol Unit
Reset input “L” pulse width
Main clock input
cycle time (XIN input)
Main clock input
“H” pulse width
Main clock input
“L” pulse width
CNTR0, CNTR1 input
cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0, INT1 input “H” pulse width
INT0, INT1 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
Serial I/O input hold time
2.0 V (One T ime PROM version: 2.5 V) ≤ VCC ≤ 4.0 V
VCC ≤ 2.0 V (One Time PROM version: 2.5 V)
2.0 V (One T ime PROM version: 2.5 V) ≤ VCC ≤ 4.0 V
VCC ≤ 2.0 V (One Time PROM version: 2.5 V)
2.0 V (One T ime PROM version: 2.5 V) ≤ VCC ≤ 4.0 V
VCC ≤ 2.0 V (One Time PROM version: 2.5 V)
2.0 V (One T ime PROM version: 2.5 V) ≤ VCC ≤ 4.0 V
VCC ≤ 2.0 V (One Time PROM version: 2.5 V)
54
38C1 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
twH(SCLK)
twL(SCLK)
td(SCLK-SOUT)
tV(SCLK-SOUT)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
twH(SCLK)
twL(SCLK)
td(SCLK-SOUT)
tV(SCLK-SOUT)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Limits
Parameter Min.
tc(SCLK)/2–30
tc(SCLK)/2–30
–30
Typ.
25
25
Max.
140
30
30
200
40
40
Symbol Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P55/SOUT P-channel output disable bit of the serial I/O control register (bit 4 of address 001D16) is “0.”
2: The XOUT, XCOUT pins are excluded.
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time P20–P27
CMOS output rising time P30–P34, P44–P47,
P50–P57, P60–P64(Note 2)
CMOS output falling time (Note 2)
Table 21 Switching characteristics 1
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
tC(SCLK)/2–80
tC(SCLK)/2–80
–30
Typ.
60
60
Max.
350
80
80
400
120
120
Symbol Unit
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time P20–P27
CMOS output rising time P30–P34, P44–P47,
P50–P57, P60–P64(Note 2)
CMOS output falling time (Note 2)
Table 22 Switching characteristics 2
(Vcc = 1.8 to 4.0 V (2.2 to 4.0 V for One Time PROM version), Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Notes 1: When the P55/SOUT P-channel output disable bit of the serial I/O control register (bit 4 of address 001D16) is “0.”
2: The XOUT, XCOUT pins are excluded.
Fig. 50 Circuit for measuring output switching characteristics
M
easurement output p
i
n
1
0
0
p
F
C
M
O
S
o
u
t
p
u
t
N
ote:
Wh
en
bi
t 4 o
f
t
h
e ser
i
a
l
I
/
O
contro
l
re g
i
ster
(
a
dd
ress
001D
16
) is “1” (N-channel open-drain output mode).
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
(
N
o
t
e
)
1
k
Ω
1
0
0
p
F
M
easurement output p
i
n
55
38C1 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 51 Timing chart
0
.
2
VC
C
td(
SC
L
K-
SO
U
T)
tf
0.2VCC
0
.
8
VC
C
0.8VCC
tr
ts
u(
SI
N-
SC
L
K)th(
SC
L
K-
SI
N)
tv(
SC
L
K-
SO
U
T)
tC(SCLK)
tWL(SCLK) tW
H(
SC
L
K)
SO
U
T
SI
N
SC
L
K
0
.
2
VC
C
tW
L(
XI
N)
0
.
8
VC
C
tWH(XIN)tC(XIN)
XI
N
0.2VCC 0.8VCC
tW(RESET)
R
E
S
E
T
0
.
2
VC
C
tW
L(
C
N
T
R
)
0
.
8
VC
C
tWH(CNTR)
tC(CNTR)
0
.
2
VC
C
tW
L(
I
N
T
)
0
.
8
VC
C
tWH(INT)
C
N
T
R0,
C
N
T
R1
I
N
T0
,
I
N
T1
56
38C1 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PACKAGE OUTLINE
LQFP64-P-1010-0.50 –
Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
64P6Q-A Plastic 64pin 10✕10mm body LQFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A2
b
c
D
E
HE
L
L1
y
b2
Dimension in Millimeters
HD
A1
0.225 ––
I21.0 ––
MD10.4 ––
ME10.4
10°0°0.1
1.0 0.70.50.3 12.212.011.8 12.212.011.8 0.5 10.110.09.9 10.110.09.9 0.1750.1250.105 0.280.180.13 1.4
01.7
e
e
E
HE
1
64 49
48
33
3217
16
HD
D
MD
ME
A
F
y
b2
I2Recommended Mount Pad
Lp
0.45
–
–
0.6
0.25
–
0.75
–
0.08
x
A3
bxM
A1A2
L1
L
Detail F Lp
A3
c
e
MMP
LQFP64-P-1414-0.8 Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
64P6U-A
Plastic 64pin 14✕14mm body LQFP
–
0.1
0.8
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.225 ––
I
2
––
M
D
14.4 ––
M
E
14.4
0°8°
0.1
0.2
1.0 0.70.50.3
16.215.8
14.113.9
16.215.8
14.0 14.113.9 14.0
16.0
16.0
0.1750.1250.105 0.450.370.32 1.4
01.7
e
Lp 0.45
0.95
–
–
0.6
0.25
–
0.75
–
x
A3
Recommended Mount Pad
Detail F
MMP
E
H
E
1
17 32
64 49
16
48
33
H
D
D
A
ybx
M
eF
M
D
l
2
b
2
M
E
e
A
1
A
2
L
1
L
Lp
A3
c
© 2002 MITSUBISHI ELECTRIC CORP.
Specifications subject to change without notice.
Notes regarding these materials
•These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
•Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
•All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by
Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
•When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision
on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
•Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
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•The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
•If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
•Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Keep safety first in your circuit designs!
•Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
38C1 Group
MITSUBISHI MICROCOMPUTERS
REVISION HISTORY 38C1 GROUP DATA SHEET
Rev. Date Description
Page Summary
(1/2)
1.0 01/16/02
2.0 03/28/02
2.1 05/09/02
First Edition
1 FEATURES; • Interrupts and • Power dissipation revised.
4 PIN DESCRIPTION; VL1–VL3 0 ≤ VL1 ≤ VL2 ≤ VL3 → 0 ≤ VL1 ≤ VL2 < VL3
6 Table 2; Date revised. Jan. → Mar.
10 Fig. 7; Bits 3 and 6 Description added.
12 Fig. 10; Address 000716 Port P3 direction register (P3D)
Address 000816 “ADKEY pin selection” added.
14 Table 5; Note 2 revised.
18
INTERRUPTS; fourteen sources → thirteen sources, eight internal → seven internal
20 Fig. 17; PULL register A Bit 2 = “1” → PULL register Bit 3 = “1”
27 ● A-D Converter description added.
28 A-DKEY Control Circuit; Description revised all.
Fig. 27; Figure title and note “pin” added.
32 Common Pin and Duty Ratio Control; Description added.
Table 9; Note revised.
36 Fig. 35; Bits 0 and 1 Functional description revised.
● RRF register; Description revised.
41 Fig. 43; Low-speed mode CM3 = 1 → CM3 = * (Note 9)
44 (3) line 5; voltage and temperature → voltage or/and temperature
47 to 54 ELECTRICAL CHARACTERISTICS ; Most contents revised.
47 Table 12; VCC revised, VL3 and Notes added.
49 Table 14; Note revised.
51 Table 16; Most contents revised.
52 Table 17; Added.
Table 18; Most contents revised.
53 Table 20; “(2.2 to 4.0 V for One Time PROM version)” added.
54 Table 22; “(2.2 to 4.0 V for One Time PROM version)” added.
56 PACKAGE OUTLINE revised.
6 Fig. 4 and Table 2; Revised.
10 [CPU Mode Register (CPUM)]; Description revised.
16 Fig. 13; Revised.
22 ● Timer X, ■ Note on count source selection bit; Description revised.
25 Fig. 23; Note revised.
39 Clock generating circuit; Note revised.
47 Table 12;
“H” input voltage ADKEY0–ADKEY3, “L” input voltage ADKEY0–ADKEY3 eliminated.
49 Table 14; Note 3 added.
52
Table 17; “H” input voltage ADKEY0–ADKEY3, “L” input voltage ADKEY0–ADKEY3 added.
REVISION HISTORY 38C1 GROUP DATA SHEET
Rev. Date Description
Page Summary
(2/2)
2.2 07/11/02 25 ■ Notes on Serial I/O added.
27 [A-D Control Register (ADCON)] 003416
Also, when the bit 4 is “1”, do not write “0” to bit 3 by program.
28 Please do not write “0” in the AD conversion completion bit
5th item;
• Return operation by reset, STOP or WIT under A-D conversion operation at
selecting ADKEY function is performed.
46 Table 11 Absolute Maximum Ratings
VI Input voltage CNVSS (Mask ROM version) → –0.3 to VCC+0.3
47 VCC when oscillation starts revised.
Note 2 revised.
49 Table 14 Recommended operating conditions;
f(CNTR0), f(CNTR1) and f(XIN) revised.
Note 4 added.
51 Table 16 Electrical characteristics revised.
52 Table 17 A-D characteristics recommended operating condition; f(XIN) revised.
Table 18 A-D converter characteristics; ABS revised.
54 Table 21, 22 Switching characteristics; tr(CMOS) revised.
