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Preliminary Product Specifica tion
PS003807-1002
Z86D9 90 /Z 8 6D 99 1 OT P an d
Z86L99X ROM
Low-Voltage Micro-
controllers with ADC
P R E L I M I N A R Y PS003807-1002
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Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
PS003807-1002 P R E L I M I N A R Y
iii
Table of Contents
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Counter/Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Input/Output and Interr upts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
User-Programmable Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pins Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operational Descript ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Central Pro c es s in g U n it (C PU) De sc r i p ti o n . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Memory (ROM/OTP and RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Register Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Registers (Grouped by Functio n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Absolute Ma ximum R a tin g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Analo g -to-Di gi ta l C o n v e rte r Cha racte ri stics . . . . . . . . . . . . . . . . . . . . . . . . 8 9
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
PS003807-1002 P R E L I M I N A R Y
iv
List of Figures
Figure 1. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figu re 2 . 48-Pin SSO P P in A ss ig n ment s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figu re 3 . 40-Pin DIP P in Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. 28-Pin SOIC/DIP Pin Assignment—User Mode . . . . . . . . . . . . . . . . 7
Figure 5. Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Standard Z8 Register File (Work ing Reg. Groups 0– F, Bank 0) . . . 13
Figure 7. Z8 Expanded Register File Arc h itecture . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. External Interrupt Sources IRQ0–IRQ2 Block Diagram . . . . . . . . . . 17
Figure 10. IRQ Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Interrupt Request Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. General Input/Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figu re 1 4 . A D C B lo ck Diag r am . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figu re 15 . Low-P a s s Fil te r (with 8 -MHz Cry s ta l ) . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. Active Glitch/Power Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 17. I-V Characteristics for the Current Sink Pad P43 . . . . . . . . . . . . . . 34
Figure 18. T1 Counter/Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 19. Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figu re 20 . Prescaler 1 Reg i ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. Counter/Timer 1 Regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 22. Timer Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 23. Starting the Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 24. Counting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 25. Timer Mode Register TOUT Opera t io n . . . . . . . . . . . . . . . . . . . . . . . 4 0
Figure 26. Counter/Timer Output Using TOUT . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 27. Internal Clock Output Using TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 28. Timer Mode Register TIN Opera ti o n . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 29. Prescaler 1 TIN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 30. External Clo ck Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 31. Gated Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 32. Triggered Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 33. Counter/Timer Archi tecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 34. Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
PS003807-1002 P R E L I M I N A R Y
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Figure 35. Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 36. Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 37. 48-Pin SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 38. 40-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 39. 28-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 40. 28-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
PS003807-1002 P R E L I M I N A R Y
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List of Tables
Tab le 1. Z86 L99/Z 8 6D99 Fe at u re Co m p a rison . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Interrupt Edge Select for External Interrupts . . . . . . . . . . . . . . . . . . 17
Table 5. Control and Status Register Reset Conditi ons . . . . . . . . . . . . . . . . 20
Table 6. Clock Status in Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Special Port Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Tabl e 8. Activ e G lit c h /F ilter Sp e c ifi ca t io n s (P re li m in a r y) . . . . . . . . . . . . . . . . 3 2
Table 9. Current Sink Pad P43 Specificatio ns (Preliminar y) . . . . . . . . . . . . . 33
Table 10. I/O Port Registers (Group 0, Bank 0, Registers 0–F) . . . . . . . . . . . 52
Table 11. Timer Control Regist ers (Group 0, Bank D, Registers 0–F) . . . . . . 53
Table 12. Control and Status Registers (Group F, Bank 0,
Registers 0–F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 13. SMR and Port Mode Registers (Group 0, Bank F,
Registers 0–F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 14. Register Description Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 15. FLAGS Register [Group/Bank F0h, Register C (R252)] . . . . . . . . . 57
Table 16. RP Register [Group/Bank F0h, Register D (R253)] . . . . . . . . . . . . . 58
Table 17. SP Register [Group/Bank F0h, Register F (R255)] . . . . . . . . . . . . . 59
Table 18. LB Register (Group/Bank 0Dh, Register C) . . . . . . . . . . . . . . . . . . . 60
Table 19. ADCCTRL Register (Group/Bank 0Fh, Regi ster 8) . . . . . . . . . . . . . 61
Table 20. ADCDATA Register (Group/Bank 00h, Register 7) . . . . . . . . . . . . . 62
Table 21. IMR (Group/Bank 0Fh, Register B) . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 22. IPR (Group/Bank 0Fh, Register 9) . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 23. IRQ (Group/ Ba nk 0 Fh, Register A) . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 24. P456CON Register (Group/ Bank 0Fh, Register 0) . . . . . . . . . . . . . 67
Table 25. P3M Register [Group/Bank F0h, Register 7 (R247)] . . . . . . . . . . . . 68
Table 26. P2 Register [Group/Bank 00h, Register 2 (R2)] . . . . . . . . . . . . . . . 68
Table 27. P2M Register [Group/Bank F0h, Register 6 (R246)] . . . . . . . . . . . . 68
Table 28. P4 Register [Group/Bank 00h, Register 4 (R4)] . . . . . . . . . . . . . . . 69
Table 29. P4M Register (Group/ Bank 0Fh, Register 2) . . . . . . . . . . . . . . . . . . 69
Table 30. P5 Register [Group/Bank 00h, Register 5 (R5)] . . . . . . . . . . . . . . . 70
Table 31. P5M Register (Group/ Bank 0Fh, Register 4) . . . . . . . . . . . . . . . . . . 70
Table 32. P6 Register [Group/Bank 00h, Register 6 (R6)] . . . . . . . . . . . . . . . 71
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
PS003807-1002 P R E L I M I N A R Y
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Table 33. P6M Register (Group/ Bank 0Fh, Register 6) . . . . . . . . . . . . . . . . . . 71
Table 34. T1 Register [Group/Bank F0h, Register 2 (R242)] . . . . . . . . . . . . . 72
Table 35. TMR Register [Group/Bank F0h, Register 1 (R241)] . . . . . . . . . . . . 72
Table 36. PRE1 Register [Group/Bank F0h, Register 3 (R243)] . . . . . . . . . . . 73
Table 37. CTR1 Register (In Transmit Mode )
(Group/Bank 0Dh, Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 38. CTR1 Register (in Demodulation Mode)
(Group/Bank 0Dh, Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 39. CTR3 Register (Group/Bank 0Dh, Register 3) . . . . . . . . . . . . . . . . 76
Table 40. CTR0 Register (Group/Bank 0Dh, Register 0) . . . . . . . . . . . . . . . . 77
Table 41. HI8 Register (Gr oup/Bank 0Dh, Register B) . . . . . . . . . . . . . . . . . . 78
Table 42. LO8 Register (Group/Bank 0Dh, Register A) . . . . . . . . . . . . . . . . . . 78
Table 43. TC8H Register (Group/Bank 0Dh, Register 5) . . . . . . . . . . . . . . . . 79
Table 44. TC8L Register (Group/Bank 0Dh, Register 4) . . . . . . . . . . . . . . . . . 79
Table 45. CTR2 Register (Group/Bank 0Dh, Register 2) . . . . . . . . . . . . . . . . 80
Table 46. HI16 Register (Gr oup/Bank 0Dh, Register 9) . . . . . . . . . . . . . . . . . 81
Table 47. LO16 Register (Group/Bank 0Dh, Register 8) . . . . . . . . . . . . . . . . . 81
Table 48. TC16H Register (Group/Bank 0Dh, Register 7) . . . . . . . . . . . . . . . 82
Table 49. TC16L Register (Group/Bank 0Dh, Register 6) . . . . . . . . . . . . . . . . 82
Table 50. SMR Register (Group/Bank 0 Fh, Register B) . . . . . . . . . . . . . . . . . 83
Table 51. P2SMR Register (Group/Bank 0Fh, Register 1) . . . . . . . . . . . . . . . 84
Table 52. P5SMR Register (Group/Bank 0Fh, Register 5) . . . . . . . . . . . . . . . 84
Table 53. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 54. DC Characteristics for the Z86D99X (OTP Only) . . . . . . . . . . . . . . 87
Table 55. DC Characteristics for the Z86L99X (Mask Only) . . . . . . . . . . . . . . 88
Table 56. Analog-to-Digital Converter Charac teristics . . . . . . . . . . . . . . . . . . . 89
Table 57. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
PS003807-1002 P R E L I M I N A R Y
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Architectural Overview
The Z86D99 is a low-voltage genera l-purpose one-time programmable (OTP) Z8®
microcontroller with an integrated four-cha nnel 8-bit sigma delta analog-to-digital
converter. The Z86L99 is the read-only memory (ROM) version of this controller.
The Z86D99/Z86L9 9 family is designed t o be used in a wide va ri ety of embedded
control applications including battery chargers, home appliances, infrared (IR)
remote control s, security systems, and wireless keyboards.
It has three count er/timer s, a general-pur pose 8-bit counter /timer wit h a 6-bit pres-
caler and an 8-bit/16-bit counter/timer pair that can be used individually for gen-
eral-purpose timing or as a pair to automate the generation and reception of
complex pulses or signals. Unique features of the Z86D99/Z86L99 family of prod-
ucts include 489 bytes of general-purpose random-access memory (RAM), 256
bytes of which are mapped into the program memory space and can be used to
store data variables or as executable RAM, a low-battery detection flag, and a
controlled current output pi n, which is a regulated current source that sinks a pre-
defined current (ICCO). Table 1 highlights the basic product features of these
microcontrollers.
The Z8 microcontrol ler core offers more flexibility and performance than accumu-
lator-based microcontrollers. All 256 general-purpose registers, including dedi-
cated input/output (I/O) port regist ers, can be used as accumulators. This unique
register-to-register architecture avoids accumulator bottlenecks for high code effi-
ciency. The regist ers can be used as address pointers for indirect addressing, as
index registers, or for implementing an on-chip stack.
The Z8 has a sophisticated interrupt str ucture and automatic ally saves the pro-
gram counter and status flags on the stack for fast context-switching. Speed of
execution and smooth programming are also supported by a “working register
area” with short 4-bit register addresses.
Table 1. Z86L99/Z86D99 Feature Comparison
Pins I/O Memory
(Bytes) Operating
Voltage (V) ADC Timers Watch-Dog
Timer
Z86D990 40/48 32 32K OTP 3.0–5.5 4 channel 3 Yes
Z86D991 28 24 32K OTP 3.0–5.5 — 3 Yes
Z86L990 40/48 32 16K ROM 2.3–5.5 4 channel 3 Yes
Z86L991 28 24 16K ROM 2.3–5.5 — 3 Yes
Z86L996 28 24 4K ROM 2.3–5.5 — 3 Yes
Z86L997 28 24 8K ROM 2.3–5.5 — 3 Yes
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
PS003807-1002 P R E L I M I N A R Y
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The Z8 instruct ion set, consisting of 43 basic instructions, is opt imized for high-
code density and reduced execution time. It is similar in form to the ZiLOG Z80
instruction set. The eight instruction types and six addressing modes together
with the ability to opera te on bi ts, 4-bit nibbles or binary coded decimal (BCD) dig-
it s, 8-bit byt es, and 16-bit words, make for a code-ef fici ent, flexib le microcont roller.
Features
•
Four-channel, 8-bit sigma delta analog-to- digital (A/D) converter with external
voltage references (not availa ble in the 28-pin configur ation)
•
Two independent analog comparators
•
Controlled current output
•
489 bytes of RAM
–
233 bytes of general -purpose register -based RAM
–
256 bytes of RAM mapped into the program me mory space that can be
used as data RAM or executable RAM
•
32 Kbytes of OTP memory (Z86D99X)
•
16 Kbytes of ROM (Z86L99X)
Counter/Timers
•
Special architecture to automate generation and reception of complex pulses
or signals:
–
Programmable 8- bit counter /timer (T8) with two 8- bit captur e registe rs and
two 8-bit load registers
–
Programmable 16-bit counter/timer (T16) with one 16-bit capture register
pair and one 16-bit load register pair
–
Programmable input glitch filter for pulse reception
•
One general-purpose 8-bit counter/timer (T1) with 6-bit prescaler
Input/Output and Interrupts
•
Thirty- two I/ Os, t wenty- nine o f which are bi direc tional I/Os wi th prog rammable
resistive pull-up transistors (24 I/Os are available in the 28-pin configuration)
•
Sixteen I/Os are selectable as stop-mode recovery sources
•
Six interrupt vectors wit h nine interrupt sources
–
Three external sources
–
Two comparator interrupts
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
PS003807-1002 P R E L I M I N A R Y
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–
Three timer int errupt s
–
One low-batter y detector flag
Operating Characteristics
•
8-MHz operation
•
3.0 V to 5.5 V operating voltage (Z86D990/Z86D991)
•
2.3 V to 5.5 V operating voltage (Z86L990/Z86L991)
•
Low power consumption with three standby modes:
–
Stop
–
Halt
–
Low Voltage Standby
•
Low-battery detection flag
•
Low-voltage protect ion ci rcuit (also known as VBO, or vol tage brownout,
circuit)
•
Watch-dog timer and power-on reset circuits
User-Programmable Option Bits
•
Clock source—RC/other (LC, resonator, or crystal)
•
Watch-dog timer permanently enable
•
32-kHz crystal
•
Port 20–27 pull-up resistive transistor
•
Port 40–42 pull-up resistive transistor
•
Port 44–47 pull-up resistive transistor
•
Port 50–51 pull-up resistive transistor
•
Port 54–57 pull-up resistive transistor
•
Port 60–63 pull-up resistive transistor (not available in Z86D991/Z86L991)
•
Port 64–67 pull-up resistive transistor (not available in Z86D991/Z86L991)
•
P43 high impedance in STOP mode (available in OTP only)
Force P43 to output a 1 in the open-drain configuration
Z86D990/Z86D991 OTP and Z86L99X ROM
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Functi onal Block Diagram
Figure 1 shows the functional block diagram for the microcontrollers.
Figure 1. Functional Block Diagram
Register File
256 x 8-bit
Z8 Core
VDD_padring***
VDD_CORE
Program
Memory
††
256 Bytes
Two Analog
Comparators
16-Bit C/T
(Modulation)
MUX
8-Bit A/D† ADC0/P44
ADC1/P45
ADC2/P46
ADC3/P47
Port 2
Port 6
**
Port 5
Port 4
7
0
7
0
7
0
7
0
Power Filt er
8
Expanded
Register File
8
8-Bit C/T
(General)
8-Bit C/T
(Carrier)
VRef–
VRef+
Machine
Timing
and
Instruction
Control
XTAL 1
XTAL 2
*Controlled Current Output
* Controlled
Current
Output P43
P53
CREF2
CREF1
P50
P52
CIN2
CIN1
P51
**P6 is only in the Z86L990/Z86D990.
†ADC is only in the Z86L990/Z86D990.
††Program memory is as follows:
Z86D990 32K OTP
Z86D991 32K OTP
Z86L99 0 16K ROM
Z86L99 1 16K ROM
***In the 28-pin package, VDD_padring and VDD_CORE
are bonded together.
Z86D990/Z86D991 OTP and Z86L99X ROM
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Pin Descriptions
Figure 2 through Figure 4 show the pin names and locations.
Figure 2. 48-Pin SSOP Pin Assignments
P62
P63
P25
P26
P27
NC
AVSS
VREF-
P44
P45
P46
P47
VREF+
AVDD
VDD_CORE
VDD_padring
XTAL2
XTAL1
NC
P51
P52
P53
P54
P64
P61
P60
P24
P23
P22
NC
NC
P21
P20
P43
VSS
VSS
P42
P41
P40
P50
P56
NC
NC
P57
P55
P67
P66
P65
48
Z86D990/
Z86L990
1
24 25
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
281
27
26
47
Notes:
1. Both VSS pins must be connected to ground.
2. NC is no connection to the die.
3. AVDD must be connected to VDD_CORE and a 10-µF capacitor for good A/D conversion.
4. Power must be connected to VDD_padring. Current passes to VDD_CORE thr ough the internal
power filter.
Z86D990/Z86D991 OTP and Z86L99X ROM
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Figure 3. 40-Pin DIP Pin Assignment
P62
P63
P25
P26
P27
AVSS
VRef–
P44/ADC0
P45/ADC1
P46/ADC2
P47/ADC3
VRef+
AVDD/VDD_CORE
VDD_padring
XTAL2
XTAL1
P51/CIN1/Ca p tive Timer Input
P52/CIN2/T1 Timer Input (TIN)
P53/CREF2
P54/COUT1
P61
P60
P24
P23
P22
P21
P20
P43/Combined T8 T1 6 Output
VSS
P42
P41/ T16 Output
P40/ T8 Output
P50/CREF1
P56/ T1 Timer Outp ut
P57
P55/COUT2
P67
P66
P65
P64
40
Z86D990/
Z86L990
1
20 21
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Notes:
1. AVDD must be connected to VDD_CORE and a 10-µF cap acitor f or good A/D conversion.
2. Po wer mus t be connected to VDD_padring. Current pas s e s to V DD_CORE through the inte rnal
power filter.
Z86D990/Z86D991 OTP and Z86L99X ROM
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Figure 4. 28-Pin SOIC/DIP Pin Assignment—User Mode
Pins Configuration
Table 2 describes the pins.
Table 2. Pin Descriptions
Pin #
Symbol 28
PDIP/SOIC 40
PDIP 48
SSOP Direction Description
P20 24 34 40 I/O Port 2 Bit 0
P21 25 35 41 I/O Port 2 Bit 1
P22 26 36 44 I/O Port 2 Bit 2
P23 27 37 45 I/O Port 2 Bit 3
P24 28 38 46 I/O Port 2 Bit 4
P25 1 3 3 I/O Port 2 Bit 5
P26 2 4 4 I/O Port 2 Bit 6
P27 3 5 5 I/O Port 2 Bit 7
P40 19 29 34 I/O Port 4 Bit 0, T8 Output
P25
P26
P27
P44/ADC0
P45/ADC1
P46/ADC2
P47/ADC3
VDD*
XTAL2
XTAL1
P51/CIN1/Capture Timer Input
P52/CIN2/T1 Timer Input
P53/CREF2
P54/COUT1
P24
P23
P22
P21
P20
P43/Comb ined T8 T16 Output
VSS**
P42
P41/T16 Output
P40/T8 Output
P50/CREF1
P56/T1 Timer Output
P57
P55/COUT2
Z86D991/
Z86L991
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Notes:
1. P43 is a controlled current output.
2. P54, P55, P56, and P57 are high drive
outputs.
* VDD = VDD_CORE + VDD_padring + AVDD
Z86D990/Z86D991 OTP and Z86L99X ROM
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P41 20 30 35 I/O Port 4 Bit 1, T16 Output
P42 21 31 36 I/O Port 4 Bit 2
P43 23 33 39 Output T8/T16 Output, Controlled current output
P44 4 8 9 I/O Port 4 Bit 4, A/D Channel 0*
P45 5 9 10 I/O Port 4 Bit 5, A/D Channel 1*
P46 6 10 11 I/O Port 4 Bit 6, A/D Channel 2*
P47 7 11 12 I/O Port 4 Bit 7, A/D Channel 3*
P50, CREF1 18 28 33 I/O Port 5 Bit 0, Comparator 1 reference
P51, CIN1 11 17 20 I/O Port 5 Bit 1, Capture timer input, IRQ2
P52, CIN2 12 18 21 Input Port 5 Bit 2, Timer 1 timer input, IRQ0
P53, CREF2 13 19 22 Input Port 5 Bit 3, Comparator 2 reference, IRQ1
P54 14 20 23 I/O Port 5 Bit 4, High drive output
P55 15 25 28 I/O Port 5 Bit 5, High drive output
P56 17 27 32 I/O Port 5 Bit 6, Timer 1 output, High drive output
P57 16 26 29 I/O Port 5 Bit 7, High drive output
P60 39 47 I/O Port 6 Bit 0
P61 40 48 I/O Port 6 Bit 1
P62 1 1 I/O Port 6 Bit 2
P63 2 2 I/O Port 6 Bit 3
P64 21 24 I/O Port 6 Bit 4
P65 22 25 I/O Port 6 Bit 5
P66 23 26 I/O Port 6 Bit 6
P67 24 27 I/O Port 6 Bit 7
XTAL1 10 16 18 Input Crystal, Oscillator clock
XTAL2 9 15 17 Output Crystal, Oscillator clock
AVDD 13 14 Analog power supply
VDD_CORE 13 15 Z8 core power supply
AVSS 6 7 Analog ground
VRef– 7 8 Input A/D converter lower reference
VRef+ 12 13 Input A/D converter upper reference
VDD_padring 8** 14 16 Power supply (pad ring)
VSS 22** 32 37, 38 Ground
Notes: *A/D converter is not available in the 28-pin configuration.
**In the 28-pin configuration, all three (core, pad ring, and analog) powers are tied together.
Table 2. Pin Descriptions (Continued)
Pin #
Symbol 28
PDIP/SOIC 40
PDIP 48
SSOP Direction Description
Z86D990/Z86D991 OTP and Z86L99X ROM
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Operational Description
Central Processing Unit (CPU) Description
The Z8 architecture i s characterized by a flexible I/O scheme, an efficient register
and address sp ace struc ture and a number of ancil lary feat ures for cost- sensitiv e,
high-volu me embedded control applica ti ons. ROM-ba sed products are geared for
high-volume production (where the software is stable) and one-time programma-
ble equivalent s for proto typing as well as volume product ion where time to market
or code flexibility is cr itical.
Architecture Type
The Z8 register- oriented arc hitecture centers around an internal register file com-
posed of 256 consecuti ve bytes, known as the st andard register file. The standard
register file consists of 4 I/O port registers (R2, R4, R5, and R6), 12 control and
stat us registers, 233 general-purpose registers, and 7 registers reserved for future
expansion. In addition to the standard register file, the Z86D99/Z86L99 family
uses 21 control and status registers located in the Z8 expanded register file. Any
general-purpose register can be used as an accumulator and address pointer or
an index, dat a, or stack regi ster.
All acti ve regist ers can be refe renced or modi fied by any i nstructi on that access es
an 8-bit register, without the requirement for special instructions. Registers
accessed as 16 bi t s are treated as ev en-odd regi ster p airs. I n this case, the dat a’ s
most significant byte (MSB) is stored in the even-numbered register, while the
least significant byte (LSB) goes in to the next higher odd-numbered regis ter.
The Z8 CPU has an instruct ion set des igne d for the l arge regi ster fi le. The i nst ruc-
tion set provides a full compliment of 8-bit arithmetic and logical operations. BCD
operations are supported usi ng a decimal adjustment of bi nary values, and 16-bit
quantities for addresses and counters can be incremented and de cremented. Bit
manipulation and Ro tate and Shift instructions complete the data-manipulatio n
cap abili ties of the Z8 CPU. No speci al I/ O instr ucti ons ar e necessar y beca use the
I/O is mapped into the register file.
CPU Control Registers
The standard Z8 control registers govern the operation of the CPU. Any instruc-
tion which ref erences the register file can acces s these control reg isters. The fol-
lowing are available control registers:
•
Register Pointer (RP)
•
Stack Pointer (SP)
•
Program Control Flags (FLAGS)
Z86D990/Z86D991 OTP and Z86L99X ROM
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•
Interrupt Control (IPR, IMR, and IRQ)
•
Stop Mode Recovery (SMR, P2SMR, and P5SMR)
•
Low-Battery Detect (LB) Flag
The Z8 uses a 16-bit Program Counter (PC) to determine the sequence of curr ent
program instr u ctions. The PC is not an addressable register.
Peripheral registers are used to transfer data, configure the operating mode, and
control the operation of the on-chip peripherals. Any instruction that references
the register file can access the peri pheral registers. The following are peri pheral
contro l registers:
•
Analog/Digital Converter (ADCCTRL and ADCDATA)
•
T1 Timer/Counter (TMR, T1, and PRE1)
•
T8 Timer/Counter (CTR0, HI8, LO8, TC8H, and TC8L)
•
T16 Timer/Counter (CTR2, HI16, LO16, TC16H, and TC16L)
•
T8/T16 Control Registers (CTR1and CTR3)
In addition, the four port registers are considered to be peripheral registers. The
following are port control registers:
•
Port Configuration Registers (P456 CON and P3M)
•
Port 2 Control and Mode Registers (P2 and P2M)
•
Port 4 Control and Mode Registers (P4 and P4M)
•
Port 5 Control and Mode Registers (P5 and P5M)
•
Port 6 Control and Mode Registers (P6 and P6M)
The functions and applications of the control and peripheral registers are
explained i n “Control and Status Registers” on page 52.
Memory (ROM/OTP and RAM)
There are four basic address spa ces available to support a wide range of configu-
rations:
•
Program memory (on-chi p)
•
Stan dard register file
•
Expanded register file
•
Executable RAM
The Z8 standard register fi le totals up to 256 consecutive bytes organiz ed as 16
groups of 16 eight-bit registers. These registers consist of I/O port registers,
Z86D990/Z86D991 OTP and Z86L99X ROM
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general-purpose RAM registers, and control and status registers. Every RAM reg-
ister act s lik e an accumulat or, speeding inst ructi on e xecutio n and maximiz ing cod -
ing efficiency. Working register groups allow fast context switching.
The st andard regi ster fi le of th e Z8 (kno wn as Bank 0 ) has be en expanded to for m
16 exp anded register fil e (ERF) banks. The expanded register fi le allows for addi-
tional system control regi sters and for the mapping of additional peripheral
devices i nto the r egi ster ar ea. Each ERF bank c an pot ential ly consi st of up to 256
register s (the same amount as in the standar d regi ster file) that can then be
divided into 16 worki ng register groups. Currently, only Group 0 of ERF Banks F
and D (0Fh and 0Dh) has been impleme nted.
In addition to the standard program memory and the RAM register files, the
Z86D99/Z86L99 family also has 256 bytes of executable RAM that has been
mapped into the upper 256 bytes of the program memory address space (FF00h–
FFFFh). Dat a can be writ ten to the executabl e RAM by using the LDC instru ction.
Program Memory Structure
The first 12 bytes of program memory are reserved for the interrupt vectors.
These locati ons contain six 16-bit vectors that correspond to the six a vailable
interr upts ( IRQ0 through IRQ5. ) Address 12 (0Ch) up to 32,767 (7FFFh) consist s of
on-chip one-t ime programmable memory. The Z86L99X only has the 4K/8K/16K
ROM size.
After any reset opera tion (power-on reset, watch-dog timer ti me o ut, and stop
mode recovery), program execution res umes with the initial instruction fetch from
location 000Ch. After a re set, the fi r st rout in e execu ted must be o ne th at i niti aliz es
the control regi sters to the required system configuration.
A unique feature of the Z86D99/Z86L99 family is the pres ence of 256 bytes of on-
chip execu table RAM. This random-access memory is in additi on to the standard
Z8 register file memory available on all Z8 microcontrollers. As illustrated in
Figure 5, the executable RAM is mapped into the upper 256 bytes of the 64K pro-
gram memory address space (FF00h–FFFFh). Data can be written to the execut-
able RAM by using the LDC instruction.
Memory locations between 8000h and FEFFh have not been implemented on the
Z86D99X microco ntrollers.
The Z86D99/Z86L99 famil y does not have the capability of access ing external
memory.
Z86D990/Z86D991 OTP and Z86L99X ROM
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Z8 Standard Register File (Bank 0)
Bank 0 of the Z8 exp anded register fil e architecture is known as the stan dard reg-
ister fi le of the Z8. As shown in Figure 6, the Z8 standard reg ister file consists of
16 groups of sixteen 8-bit registers known as Working Register (WR) groups.
Wo rking Register Group F cont ains va rious control and st atus register s. The lower
half of Working Register Group 0 consists of I/O port registers (R0 to R7), the
upper eight registers are available for use as general-purpose RAM registers.
Working Register Group 1 through Group E of the standard register file are avail-
able to be us ed as general-purpos e RAM registers. The user can use 233 bytes of
general-purpose RAM registers in the standard Z8 register file (Bank 0).
Location (Hex)
FFFF 256 bytes
Executable RAM
FF00 Not Implemented
3FFF/7FFF
(ROM)/(OTP) PROGRAM
MEMORY
000C Location of the first byte of the initial instruction executed after
RESET
000B IRQ5 (lower byte)
000A IRQ5 (upper byte)
0009 IRQ4 (lower byte)
0008 IRQ4 (upper byte)
0007 IRQ3 (lower byte)
0006 IRQ3 (upper byte)
0005 IRQ2 (lower byte)
0004 IRQ2 (upper byte)
0003 IRQ1 (lower byte)
0002 IRQ1 (upper byte)
0001 IRQ0 (lower byte)
0000 IRQ0 (upper byte)
Figure 5. Program Memory Map
Z86D990/Z86D991 OTP and Z86L99X ROM
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Figure 6. Standard Z8 Register File (Working Reg. Groups 0–F, Bank 0)
Z8 Expanded Register File
In addition to the Standard Z8 Register File (Bank 0), Expanded Register File
Banks F and D of Working Register Group 0 have been implemented on the
Z86D99/Z86L99. Fig ure 7 illu strates the Z8 Expanded Register File architecture.
These two expanded register file banks of Working Register Group 0 provide a
total of 32 additional RAM control a nd status registers. The Z86D99/Z86L99 fam-
ily has implemented 21 of the 32 available registers.
Grp/Bnk Reg Working Register Group Function
(F0h) r0 to 15 Control and Sta tus Registers
(E0h) r0 to 15 General-purpos e RAM registe r s
(D0h) r0 to 15 General-purpose RAM registers
(C0h) r0 to 15 General-purpose RAM registers
(B0h) r0 to 15 General-purpose RAM registers
(A0h) r0 to 15 General-purpos e RAM registe r s
(90h) r0 to 15 General-purpos e RAM registe r s
(80h) r0 to 15 General-purpose RAM registers
(70h) r0 to 15 General-purpose RAM registers
(60h) r0 to 15 General-purpos e RAM registe r s
(50h) r0 to 15 General-purpos e RAM registe r s
(40h) r0 to 15 General-purpos e RAM registe r s
(30h) r0 to 15 General-purpos e RAM registe r s
(20h) r0 to 15 General-purpos e RAM registe r s
(10h) r0 to 15 General-purpos e RAM registe r s
r8 to 15 General-purpos e RAM registe r s
(00h)r0 to 7I/O Port Registers
Z86D990/Z86D991 OTP and Z86L99X ROM
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Figure 7. Z8 Expanded Register File Architecture
Clock Circuit Description
The Z8 derives its timing from on-board clock circuitr y connected to pins XTAL1
and XTAL2. The clock circu it ry consists of an oscillator, a divide-by- two shaping
circuit, and a clock buffer. The oscillator’s input is XTAL1, and the oscillator ’s out-
put is XTAL2. The clock can be d riven by a cryst al , a ceramic r esonator, LC clock,
RC, or an external cl ock source.
Clock Control
The Z8 offers software control of the i nternal system clock using programming
register bits in the SMR register. This register selects the clock divide value and
determines th e mode of STOP Mode Recovery.
The default set ti ng is external clock divide-by-two. When bits 1 and 0 of the SMR
register are set t o 0, th e System Clock (SCLK) and Timer Clock (TCLK) are equa l
to the external clock frequency divided by two.
When bit 1 of the SMR register is set to 1, then SCLK and TCLK equal the exter-
nal clock frequency. Refer to Table 53 on page 85 for the maximum clock fre-
quency.
A divide-by-16 prescaler of SCLK and TCLK allows the user to selecti vely reduce
device power consumption during normal processor execution (under SCLK con-
trol) and/or HALT mode, where TCLK sources counter/timers and interrupt logic.
Combining the divide-by-two circuitry with the divi de-by-16 prescaler allows the
external clock to be divided by 32.
Z8 Standard Register File
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Bank 0
Control and Status Reg.
I/O Port Registers
Working
Register
Groups
Ba nks 2 through C are
Reserved—Not Implemented
Group 0, Bank D
Group 0, Bank F
(Bank E is also reserved)
General-Purpose
RAM Registers
Z8 Expanded Register Files
Timer
Control
Registers
St op Mode
Recovery and
Port Mode
Bank F
Registers
Z86D990/Z86D991 OTP and Z86L99X ROM
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Interrupts
The Z86D99/Z8 6L99 family allo ws up to si x dif ferent int errupt s, three ex ternal and
three internal, from nine possible sources. The six interrupt s are assigned as fol-
lows:
•
Three edge-tr iggered external interrupts (P51, P52, and P53), two of whic h
are shared with the two analog comparators
•
One internal i n terrupt assigned to the T8 Timer
•
One internal i n terrupt assigned to the T16 Timer
•
One internal interrup t shared between the Low-Battery Detect flag and the T1
Timer
Table 3 presents the interrupt types, the interrupt sourc e s, and the location of the
specific interrupt vectors.
These interrupts can be masked and their priorities set by using the Interrupt
Mask Register (I MR) a nd Interrupt Priority Regis ter (IPR) (Figure 8.) When more
than one interr upt is pending, priorit ies are resolv ed by a prior ity encoder, con-
trolled by the IPR.
Table 3. Interrupt Types, Sources, and Vectors
Name Source Vector
Location Comments
IRQ0P52 (F/R), Comparator 2 0,1 External interrupt (P52) is triggered by
either rising or falling edge; internal
interrupt generated by Comparator 2
is mapped into IRQ0
IRQ1P53 (F) 2,3 External interrupt (P53) is triggered by
a falling edge
IRQ2P51 (R/F), Comparator 1 4,5 External interrupt (P51) is triggered by
either a rising or falling edge; internal
interrupt generated by Comparator 1
is mapped into IRQ2
IRQ3T16 Timer 6,7 Internal interrupt
IRQ4T8 Ti mer 8,9 Internal interrupt
IRQ5LVD, T1 Timer 10,11 Internal interrupt, LVD flag is
multiplexed with T1 Timer End-of-
Count interrupt
Notes: F = Falling-edge triggered; R = Rising-edge triggered.
When LVD is enabled, IRQ5 is triggered only by low-voltage detection. Timer
1 does not generate an interrupt.
Z86D990/Z86D991 OTP and Z86L99X ROM
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Figure 8. Interrupt Block Diagram
Interrupt requests are stored in the Interrupt Request Register (IRQ), which can
also be used for poll ing. When an interrupt request is grant ed, the Z8 enters an
“interrupt machine cycle” that globally disables all other interrupts, saves the pro-
gram counter (the addr ess of t he next i nstructi on to be ex ecuted) and st atus f lags,
and finally branc hes to the vector loca tion for the interrupt granted. It is only at th is
point that control passes to the interrupt service routine for the specific interrupt.
All six interrupts can be globally disabled by reset ti ng the master Interrupt Enable
(bit 7 of the IMR) with a Disabl e Interrupts (DI) in struction. Interrupts are globally
enabled by setti ng the same bit with an Enable Interr upts (EI) instruction.
Descriptions of three interrupt control registers—the Interrupt Request Register,
the Interrupt Mask Register, and the Interrupt Priority Register—are provided in
“Register Summary” on page 52. The Z8 family suppor ts both vectored and polled
interrupt handling.
External Interrupt Sources
External sour ces involve interrupt request lines P51, P52, and P53 (IRQ2, IRQ0,
and IRQ1, respectively.) IRQ 0, IRQ1, and IRQ2 are generated by a transition on
the corresponding port pin. As shown in Figure 9, when the appropriate port pin
(P51, P52, or P53) tr ansitions, the first flip-flop is set. The next two flip-flops syn-
chronize the request to the internal clock and delay it by two internal clock peri-
ods. The output of the most recent flip-flop (IRQ0, IRQ1, or IRQ2) sets the
corresponding Interrupt Request Register bit .
EI Instruction
Power-On Reset (POR)
S
R
Interrupt Request Register
(IRQ,FAH)
Reset
Z86D990/Z86D991 OTP and Z86L99X ROM
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Figure 9. External Interrupt Sources IRQ0–IRQ2 Block Diagram
The programming bit s for the Interr upt Edge Select f unction are located in the IRQ
register, bits 6 and 7. The configuration of these bits and the resulting interrupt
edge is shown in Table 4.
Although int e rrupts are edge triggered, minimum interrupt
request Low and High times must be observed for proper
operation. See “Electri cal Character istics” on page 85 for exact
timing requir ements (TWIL, TWIH) on external interrupt
requests.
Internal Interrupt Sources
Internal sources are ORed with the external sources, so that eit her an internal or
external source can trigger the interrupt.
Interrupt Request Register Logic and Timing
Figure 10 shows the logic diagra m for the Inter rupt Request Regis ter. The leading
edge of an interrupt request sets the first flip-flop. It remains set until the interrupt
requests are sampled.
Table 4. Interrupt Edge Select for External Interrupts
Interrupt Request Regist er Interrupt Edge
Bit 7 Bit 6 IRQ2 (P51) IRQ0 (P52)
0 0 Falling Falling
0 1 Falling Rising
1 0 Rising Falling
1 1 Rising/Falling Rising/Falling
Note:
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Figure 10. IRQ Logic
Internal interrupt requests are sampled during the most recent clock cycle before
an Op Code fetch (see Figure 11.) External interrupt requests are sampled two
internal clocks earlier than internal interrupt requests because of the synchron iz-
ing fli p-flop s shown in Figure 9.
Figure 11. Interrup t Request Timing
At sample time, t he interrupt request is t ransferred to the second flip- flop shown in
Figure 10, which drives the interrupt mask and priority logic. When an interrupt
cycle occurs, this flip-flop is reset only for the highest priority level that is enabled.
The user has direct access to the second fl ip-flop by reading and writing to the
IRQ. The IRQ is read by specif ying it as the source register of an instruction, and
the IRQ is written by specifying it as the destination register.
Inte rr u p t In itializ a tion
Aft er RESET, all interr upt s ar e disabled and must be re-i nitiali zed before vecto red
or polled interr upt processing can begin. The Interr upt Priority Register, Interrupt
Mask Register, and Int err upt Request Regist er must b e init ia lized, in t hat or der, to
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start the interr upt process. However, the IPR does not have to be initi alized for
polled processing.
Interrupts must be globally enabled using the EI instruction. Setting bit 7 of the
IMR is not sufficient. Subsequent to this EI instruction, interrupts can be enabled
either by IMR manipulati on or by use of the EI instructi on, with equivalent effects.
Additiona lly, interrupts must be disabled by executing a DI instruction before the
IPRs or I MRs can be modified. Interrupts can then be enabled by executing an EI
instruction.
IRQ Software Interrupt Generat ion
IRQ can be used t o gener ate software interrupt s by spec if ying I RQ as th e dest ina-
tion of any instruction referencing the Z8 Standard Register File. These Software
Interrupts (SWIs) are controlled in the same manner as hardware-generated
request s (the IPR and the I MR control the prior ity and enabling of each SWI level).
To generate a SWI, the request bit in the IRQ is set as follows:
OR IRQ, #NUMBER
where the immediate data, NUMBER, has a 1 in the bit position corresponding to
the appropriate level of the SW I.
For example, f or an SWI on IRQ5 , NUMBER has a 1 in bit 5. Wi th thi s i nstru ctio n,
if the interrupt system is global ly enabled, IRQ5 is enabled, and there are no
higher priority pending requests, control is transferred to the service routine
pointed to by the IRQ5 vector.
Reset Conditions
A system reset overrides all other operating conditions and puts the Z8 into a
known state. The control and st atus registers are reset to t heir default conditions
aft er a power-on reset (POR) or a W atch-Dog Timer (WDT) time-out while in RUN
mode. The cont rol and status registers are not reset to their default conditions
after Stop Mode Recovery (SMR) while in HALT or STOP mode.
General-pur pose registers are undefined after the device is powered up. Reset-
ting the Z8 does not affect the contents of the general-purpose registers. The reg-
isters keep their most recent value after any reset, as long as the reset occurs in
the specified VCC operating range. Registers do not keep their most recent state
from a VLV reset, if VCC drops below VRAM (see Table 54 on page 87).
Following a reset (see Table 5), the first routi ne executed must be one that initial-
izes the contr o l registers to the required system confi guration.
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Table 5. Control and Status Register Reset Conditions
Address Reset Value
Register Function Grp/Bnk Register Symbol R/W 76543210
Register Pointer F0h r13 (R253) RP R/W00000000
Stack Pointer F0h r15 (R255) SP R/WXXXXXXXX
Program Control Flags F0h r12 (R252) Flags R/WXXXXXXXX
Low Battery Detect 0Dh r12 LB R/W11111X00
ADC Control 0Fh r8 ADCCTRL R/W 00000000
ADC Data 00h r7 (R7) ADCDATA R 00000000
Interrupt Mask F0h r11 (R251) IMR R/W00000000
Interrupt Priority F0h r9 (R249) IPR W 00000000
Interrupt Request F0h r10 (R250) IRQ R/W00000000
Port Configuration (A) 0Fh r0 P456CONR/W00000111
Port Configuration (B) F0h r7 (R247) P3M W 11111111
Port 2 Data 00h r2 (R2) P2 R/WXXXXXXXX
Port 2 Mode F0h r6 (R246) P2M W 11111111
Port 4 Data 00h r4 (R4) P4 R/WXXXXXXXX
Port 4 Mode 0Fh r2 P4M R/W11111**111
Port 5 Data 00h r5 (R5) P5 R/WXXXXXXXX
Port 5 Mode 0Fh r4 P5M R/W11111111
Port 6 Data 00h r6 (R6) P6 R/WXXXXXXXX
Port 6 Mode 0Fh r6 P6M R/W11111111
T1 Timer Data F0h r2 (R242) T1 R/W00000000
T1 Timer Mode F0h r1 (R241) TMR R/W00000011
T1 Timer Prescale F0h r3 (R243) PRE1 R/W00000000
T8/T16 Control (A) 0Dh r1 CTR1 R/W000*0*0000
T8/T16 Control (B) 0Dh r3 CTR3 R/W000*XXXXX
T8 Timer Control 0Dh r0 CTR0 R/W0 0 0*0*0*0*0*0
T8 High Capture 0Dh r11 HI8†RW00000000
T8 Low Capture 0Dh r10 LO8†R/W00000000
T8 High Load 0Dh r5 TC8H†R/W00000000
T8 Low Load 0Dh r4 TC8L†R/W00000000
T16 Timer Control 0Dh r2 CTR2 R/W00000000
T16 High Capture 0Dh r9 HI16†R/W00000000
T16 Low Capture 0Dh r8 LO16†R/W00000000
T16 High Load 0Dh r7 TC16H†R/W00000000
T16 Low Load 0Dh r6 TC16L†R/W00000000
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Power-On Reset
A POR (cold star t) always resets the Z8 control and statu s registe rs to their default
conditions. A POR sets bit 7 of the Stop Mode Recovery regist er to 0 to indicate
that a cold st art has occurred.
A timer circuit clocked by a dedicated on-boa rd RC osc il lator is used for the
Power-On Reset Timer (TPOR) function. The POR time is specified as T POR.
TPOR time allows VCC and the oscillator circ uit to stabilize before i n struction exe-
cution begins.
The POR delay timer circ uit is a one-shot timer t ri ggered by one of three condi-
tions:
•
Power Fail to Power OK status including recovery from Low Voltage (V LV)
Standby mode
•
STOP-Mode Recovery (when bit 5 of the SMR register = 1)
•
WDT time-out
Under normal operating conditions, a stop mode recovery event always triggers
the POR delay timer. This delay is necessary to allow the external oscillator time
to stabilize. When using an RC or LC oscillator (with a low Q factor), the shorter
wake-up time means the delay can be eliminated.
Bit 5 of the SMR register selects whether the POR timer delay is used after S top-
Mode Recovery or is bypa ssed. If bi t 5 =1, t hen the POR ti mer delay i s used . If bit
5 = 0, then the POR timer delay is bypassed. In th is case, the SMR source must
be held in the recover y state for 5 TpC to pass the Reset signal internally.
Watch-Dog Timer (WDT)
The WDT is a retriggerabl e one-shot timer that resets the Z8 if it reaches its
terminal count. When operating in the RUN modes, a WDT reset is functionally
Stop Mode Recovery 0Fh r11 SMR R/W00100000
Port 2 SMR Source 0Fh r1 P2SMR R/W00000000
Port 5 SMR Source 0Fh r5 P5SMR R/W00000000
Notes: †This register is not reset following Stop Mode Recovery (SMR).
*This bit is not reset following SMR.
X means this bit is undefined at POR and is not reset following SMR.
**In OTP, the default for P43 is open-drain output at power up; you need to
initialize the P43 data. In the mask part, the P43 output is disabled until it is
config ured as outp ut.
Table 5. Control and Status Register Reset Conditions (Continued)
Address Reset Value
Register Function Grp/Bnk Register Symbol R/W 76543210
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equivalent to a hardwar e POR reset. If the mask option of the permanently
enabled watch-dog timer is selected, it runs when power up. If the option is not
selected, the WDT is initially enabled by executing the WDT instr uction and
refreshed on subsequent executions of the WDT instruction.
The WDT instruction does not af fect the Zero (Z), Sign (S), and Overflow (V) fl ags.
Permanently enabl ed WDTs are al ways enabled, and the WDT instruction is used
to refresh it. The WDT cannot be disabled after it has been initially enabled. The
WDT is off during both HALT and STOP modes.
The WDT ci rcuit is d riven by an on- board RC oscillator. The time-out period f or the
WDT is fixed to a typical value (see Table 57 on page 90).
Power Management
In addition to the standard RUN mode, the Z8 supports t hree power-down modes
to minimize device current consumption. The following three modes are sup-
ported:
•
HALT
•
STOP
•
Low-Voltage Standby
Table 6 shows the status of the internal CPU clock (SCLK), the in ternal Timer
clock (TCLK), the external oscillator, and the Watch-Dog Timer during the RUN
mode and three low-power modes.
Using the Power-Down Modes
In order to enter HALT or STOP mode, it is neces sary to first flush the instruction
pipeline to avoid suspending execution in mid-instruction. You can flush the
Table 6. Clock Status in Operating Modes
Operating Mode SCLK TCLK External OSC WDT*
RUN On On On On
HALT Off On On Off
STOP Off Off Off Off
Low-Voltage Standby Off Off Off Off
Note: * When WDT is enabled by the mask option bit
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instruc tion pipeline by executing a NOP (Op Code = FFh) immediately before the
appropriate sleep instruction. For example:
or
HALT
HALT mode suspends instruction execution and turns off the internal CPU clock
(SCLK). The on-chip oscillator circuit remains active, so the internal Timer clock
(TCLK) continues to run and is applied to the count er/timers and int errupt logic.
An interrupt request, either internally or externally generated, must be executed
(enabled) to exit HALT mode. After the interrupt service routine, the program con-
tinues from the instruction immediately following the HALT.
The HALT mode can also be exited by a POR. In this case, the program execution
restarts at the reset address 000Ch.
STOP
STOP mode provides the lowest possible d evice standby current. This instruction
turns off both the internal CPU clock (SCLK) and internal Timer clock (TCLK) and
reduces the standby current to the minimum.
The STOP mode is terminated by a POR or SMR source. Terminating the STOP
mode causes the processor to restar t the application program at address 000Ch.
When the STOP instruction is executed, the microcont roller goes into the
STOP mode despite any state/change of the state of the port. The ports
need to be checked i mmediately before the NOP and ST OP instru ctions to
ensure the right input log ic bef ore waiting for the change of the ports.
S top Mode Recovery Sources
Exiting STOP mode using an SMR source is great ly simplified in the Z86D99/
Z86L99 family. The Z86D99/Z86L99 family of products allows 16 individual I/O
Mnemonic Comment Op Code
NOP ; clear the pipeline FFh
STOP ; enter STOP mode 6Fh
Mnemonic Comment Op Code
NOP ; clear the pipeline FFh
HALT ; enter HALT mode 7Fh
Note:
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pins (Port s 2 and 5) to be used as stop-mode rec overy source s. The ST OP mode
is exited when one of these SMR sources is toggled. A transition fr om either lo w to
high or high to low on any pin of Port 2 or Port 5 if the pin is identified as an SMR
source will effect an SMR.
There are three regi sters that contr ol STOP mode recovery:
•
Stop Mode Recovery
•
Port 2 Stop Mode Recovery (P2SMR)
•
Port 5 Stop Mode Recovery (P5SMR)
The functions and applications of these registers are explained in “Stop-Mode
Recovery Control Registers” on page 82.
Low-Voltage Standby
An on-chip voltage comparator checks that the VCC level is at the required l evel
for correc t operation of the Z8. When VCC falls below the low-voltage trip voltage
(VLV), reset is globally driven, and then the devi ce is put in a low-current standby
mode with the external oscillator stopped. If t he VCC remains above VRAM, the
RAM content is preserved.
When the power level rises above the VLV level, the device performs a POR and
functions normally.
The minimum operat ing vol tag e varies wi t h temperatu re and o perati ng frequenc y,
while V LV varies with temper ature only.
I/O Ports
The Z86D99/Z86L99 family has up to 32 lines dedicated t o input and output i n the
40-pin configuration. These lines are grouped into four 8-bit ports known as Port
2, Port 4, Port 5, and Port 6. All fo ur port s are bit p rogrammable as ei ther inp ut s or
outputs with the exception of P52, P53, and P43. P52 and P53 are input only as
they are used in OTP programming. P43 is the cont rolled current output and is
therefore output only.
All ports have push-pull CMOS outputs. In addition, the push-pull outputs can be
turned off for open-dr ain operation using the P456CON regist er.
Internal resistive pull-up transistors are avai lable as a user-defined OTP/mask
option on all ports. For Ports 4, 5, and 6, the pull-ups are nibble selectable. For
Port 2, the pull-up option applies to all ei ght I/O lines.
Internal pull-ups are disabled on any given pin or group of port
pins when those pins are programmed as outputs.
Note:
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Mode Registers
Each port has an associat ed Mode Register that determines the port’ s functions
and allows dynamic change in port functions during program execution. Port and
Mode Registers are mapped int o the Standard Regis ter File. Because of their
close associ ation, Port and Mode Regis ters are treated li ke any other general- pur-
pose register. There are no special instructions for port manipulation. Any instruc-
tion that addresses a register can address the ports. Data can be directly
accessed in the Port Regist er, with no extra moves.
Input and Output Registe rs
Each of the four ports (Ports 2, 4, 5, and 6) has an input regi ster, an output regi s-
ter, and associated buf f er and cont rol log ic. Bec ause ther e are sepa rat e input and
output registers associated with each port, writing bits defined as inputs store the
data in th e output register . This data cannot be read as long as the bits are defined
as inputs. However, if the bits are reconfigured as output, the data stored in the
output register is reflected on the output pins and can then be read. This mecha-
nism allows the user to initiali ze the outputs before driving their loads.
Because port inpu ts are async hrono us to th e Z8 i nternal clock , a READ operat ion
could occur during an input transition. In this case, the logic level might be uncer-
tain (somewhere between a logic 1 and 0).
General Port I/O
The eight I/O lines of each port (except P43, P52, and P53) can be configured
under software contr ol to be either in put or output, independently. Bits pro-
grammed as outputs can be globally programmed as either push-pull or open-
drain. See Figure 12.
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Figure 12. General Input/Output Pin
Read/Write Operations
The port s are accessed as general-purpose re gisters. Po rt registers are wr itten by
specifyi ng the port register as an instru ction’s destination re gister. Writing t o a port
causes dat a t o be stor ed in the out put regist er o f the port, and re flect ed ext ernall y
on any bit configured as an output.
Ports are read by specifying the port register as the source regi ster of an instruc-
tion. When an output bit is read, data on the external pin i s returned. Under normal
loading conditions, returning data on the external pin is equivalent to reading the
output register. However, if a bit is defined as an open-drain output, the dat a
returned is the value forced on the output pin by the external system. This value
might not be the same as the data in the output register. Reading input bi ts also
returns data on the external pins.
Open-Drain
I/O
OTP/Mask
Option VCC
*
Pad
Out
In
Pull-Up
Note: * Pull-up resistance is
about 200 KΩ at 2.3 V and
75 KΩ at 5.0 V with +50%
tolerance.
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S pecial Functions
Table 7 defines the special functions of Ports 4 and 5.
Table 7. Special Port Pin Functions
Function Pin Signal Configuration Register
Analog Comparator Inputs P51 CIN1 P456CON
P52 CIN2 P456CON
Analog Comparator
References P50 CREF1
P53 CREF2
Analog Comparator Outputs P54 COUT1
P55 COUT2
ADC Channels P44 ADC0 ADCCTRL
P45 ADC1 ADCCTRL
P46 ADC2 ADCCTRL
P47 ADC3 ADCCTRL
External Interrupts P52 IRQ0IMR and IRQ
P53 IRQ1IMR and IRQ
P51 IRQ2IMR and IRQ
TIN External Clock Input P52 TIN TMR and PRE1
Capture Timer Input P51 Demodulator_Input CTR1
T1 Timer Output P56 T1OUT TMR
T8 Output P40 P40_Out CTR0
T16 Output P41 P41_Out CTR2
Combined T8/T16 Output
Controlled Current Output P43 P43_Out CTR1
ZiLOG Test Mode P41 DSn Enable P456CON
P42 ASn Enable P456CON
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Peripherals
Analog Comparators
The Z86D99/Z86L99 family includes two independent on-chip general-purpose
analog comp arators a s shown in Figure 13. The compar ators are mul tiplexed wit h
a digital input si gnal by the P456CON register. They can also be used to generate
interrupts IRQ0 and IRQ2. The comparators are turned off in STOP mode.
Figure 13. Analog Comp arators
Analog/Digi tal Converter (ADC)
The Z86D99/Z86L99 family incorporates an 8-bit ADC that uses a sigma delta
architecture (Figure 14) comprised of a modulator and a digital filter. The input is
selected (bit 3,2 from ADCCTRL) with an analog mux from 4 (P47–P44) pins that
can be configured as anal og inputs (bit 7–4 from ADCCTRL).
Whenever an input pin has an analog value, the digital input
buf fer has to be di sabled i n order to reduce the c urr ent thr ough
the device.
+
–
+
–
P51
Comparator 1
P50
P52
Comparator 2
P53
P456CON
P456CON
IRQ2, P51 Data Latc h
IRQ0, P52 Data Latch
(CIN1)
(CREF1)
(CIN2)
(CREF2) Bit4 1 = comparator
0 = di gital
Bit5 1 = comparator
0 = di gital
Note:
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Figure 14. ADC Block Diagram
The low-pass filter transfer function is presented in Figure 15 with the –3-dB fre-
quency given by the formula:
where fADC is the sampling frequency of the modulator.
f3db 0.0021 fADC
⋅=
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Figure 15. Low-Pass Filter (with 8-MHz Crystal)
The sampling frequency of the modulator fADC can be select ed between fSCLK and
fSCLK/2 (bit1 from ADCCTRL). Reducing the clock frequency lower s the power
dissipated in the ADC block.
The ADC can be enabled or disabled. When enabled, the Σ∆ converter tracks the
input voltage. When switching between the channels (step response), the
required time to reach the fi nal val ue i s given by the time cons tan t of the l ow-p ass
filter:
When availabl e, t he refer ence for t he ADC is s et exte rnall y with the V ref+ and Vref-
pins. The output code represents the following ratio:
00.5 11.5 22.5 3 3.5 4 4.5 5
20
18
16
14
12
10
8
6
4
2
0
Filter response
log10(f)
Out/In[db]
Tdelay 2
f3db
---------2
0.0021fADC
----------------------------952
fADC
-----------== =
Dout Vin VRef-
–
VRef+VRef-
–
-------------------------------256×=
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Though th e ADC functions for smaller input volt age r ange (VRef+–VRef-), the noise
and offsets remai n constant over the specified elect ri cal range. The errors of the
converter increase due to small input signals.
For fast access to the output of the ADC, the current data is available in the ADC
result register (r8, bank00).
To reduce the interference between the digital part and the analog part, separate
AVSS and AVDD pins are available on the packages where the ADC can be used.
In the smaller packages, which do not support the ADC, the
user must keep the converter not active in order to not have
power dissipated in the ADC block. By default, ADC is off.
Active Glitch Filter
The Z86D99/Z86L99 family incorporates an active power/glitch filter that can be
used to improve the quality of the power supply when the device is operating in
noisy environments. The chips use three sep a rate power buses:
•
p ad ring power bus (all the ou tput drivers plus the crystal/RC oscil lator) called
VDD_padring
•
core power bus (all digit al circuit ry) called VDD_CORE
•
analog power bus (all analog circuitry) called AVDD
Depending on the pin availability, one or more of the power buses are connected
together.
The active power filter can be used in the packages that have the VDD separate.
Figure 16 shows the internal schematic.
Note:
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Z86D99/Z86L99
Figure 16. Active Glitch/Power Filter
When the internal power/glitch filter is not used, both VDD_padring and VDD_CORE
must be connected together externally to the power supply.
When the internal circuitry is used, the VDD_padring has to be connected to the
power supply and the VDD_CORE has to be connected to an external energy stor-
age cap acitor ( 1−10 µF range). The core is connec ted only t o this capac itor duri ng
power supply glitches.
Table 8 describes the active glit ch/filter specifications.
On the wafer level, al l three power buses are availab le. Depending on the number
of pins of the package, one or more power buses are connected together.
The active glitch/power filter effectively increases the noise immunity for battery-
operated designs where the controller is driving high current loads (for example,
IR LED ).
Table 8. Active Glitch/Filter Specifications (Preliminary)
Parameter Max Min Condition
Diff. stage gain 75 dB
Diff. stage bandwidth 15 MHz
Rise time 255 ns 50 mV pulse
Fall time 214 ns 50 mV pulse
Rdson 10 Ω
VDD_padring
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Controlled Curr ent Output
P43 is an open-drain output-only pin on the Z86D990/D991, but it can be config-
ured as output or Tristate H igh Impedance on the Z86L990/L991. To function
properly, Bit 3 of P4M must be set to zero to configure the pin as an open-drain
output. For the Z86L990/L991 af ter reset, P43 default s to T ristate High Impedance
while the Z86D990/D991 P43 is always configured as output. The data at Port 4
must be initialized as it is undefined at power-on reset.
The current outp ut is a c ontr olled current source t hat i s contr olled by t he output of
the value of P43 (see Table 9). P43 cannot
be configured as input , and if P43 is
read, P43 always returns the state of the output value (1 for no sink and 0 for
sink).
P43 uses internal cu rrent reference and will draw current i f it outputs a low logic
even without ext e rnal connection. This applies to both Run mode and Stop mode.
The pad driver can function in two modes:
•
controlled current output, when the voltage on the pad is over a minimum
value
•
resisti ve pull down when the driver cannot regul ate the current; in this mode,
the gate of the NMOS pull down is raised to the power rail.
The I-V character istics of the pad are presented in Figure 17.
Table 9. Current Sink Pad P43 Specifications (Preliminary)
Parameter Min Max Conditions
Rise time 0.4 µLED load
Fall time 0.02 µLED load
Voutmin 0.54 V @27C
Comparator response 0.2 µ
Regulated current 80 mA 120 mA
Internal resistance 80 Ω
Vpad Voutmin
>
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Figure 17. I-V Characteristics for the Current Sink Pad P43
The CPU reads the mode of the pad dri ver by reading bit number 2 from the LB
register. This bit is the output of a Set-Reset flip-flop that sets whenever the volt-
age on the pad is lower than Voutmin and is reset by a CPU write to the respective
register.
T1 Timer
The Z86D99/Z86L99 family provi des one general-purpose 8-bit counter/t imer, T1,
driven by its own 6-bit presca ler , PRE1. The T1 count er/timer is independent of t he
processor instruction sequence, which rel ieves sof tware from time-cri tical opera-
tions such as interval timing and event counting.
The T1 counter/timer operates in either single-pass or continuous mode. At the
end-of-count, counting either stops or the initial value is reloaded and counting
continues. Under software control, new valu es are loaded immediately or when
the end-of-count is reached. Software also controls the counting mo de, how the
counter/timer is started or stopped, and the counter/timer’s use of I/O lines. Both
the counter and prescaler registers can be altered while the counter/timer i s run-
ning.
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Counter/timer 1 is driven by a timer clock generated by dividing the internal clock
by four. The divide-by-four stage, the 6-bit prescaler, and the 8-bit counter/timer
form a synch ronous 16- bit divi de chain. Count er/timer T1 can also be driven by an
external input (TIN) using Port P52. Port P56 can serv e as a timer output (TOUT)
through which T1 or the internal clock can be output . The timer output toggles at
the end-of-count. Figure 18 is a block diagram of the counter/timer.
Figure 18. T1 Counter/Timer Block Diagram
OSC
+2
+4
+2
External Clock
Clock
Logic
Internal
Clock
TINP31
8-Bit
Down Counter
6-Bit
Down Counter
T1
Initial Value
Register
PRE1
Initial Value
Register
T1
Current Value
Register
Internal Data Bus
TOUT
P56
IRQ5
Internal Clock
Gated Clock
Trigger ed Clock
Write Write Read
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The counter/t imer, prescaler, and associated mode registers are mapped into the
register fi le as shown in Figure 19. The sof tware uses the counter/ ti m er as a gen-
eral-pur pose register, which eliminates the need for special instructions.
Figure 19. Register File
Prescaler and Counter/Timer
The prescaler PRE1 (F3h) consists of an 8-bit reg ister and a 6-bit down-co unter as
shown in Fi gure 18 on page 35. The prescaler register is a read-write register.
Figure 20 shows the prescaler register.
R243 PRE1
Prescaler 1 Registe r
(F3h; Read/Write)
Figure 20. Prescaler 1 Register
DEC Hex identifiers
243 T1 prescaler F3 PRE1
242 Timer/counter 1 F2 T1
241 Timer mode F1 TMR
D7D6D5D4D3D2D1D0
Count mode
1 = T1 modulo-N
0 = T1 single pass
Clock source
1 = T1 internal
0 = T1 external (TIN)
Prescaler modulo
(range: 1–64 decimal,
01h–00h)
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The six most signi ficant bits (D2–D7) of PRE1 hold the prescaler count modulo, a
value from 11 to 64 decimal. The prescaler register also contains control bits that
specify T1 counting modes. These bits also indicate whether the clock source for
T1 is internal or external.
The counter/ timer T1 (F2h) consist s of an 8-bit do wn-coun ter, a write-only regi ster
that holds the i nitial coun t value, and a read-only register that holds the current
count value (see Figure 18 on page 35). The initi al value can range f rom 1 t o 256
decimal (01h, 02h, ..., 00h). Figure 21 illustrates the counter/timer register.
R242 T1
Counter/Timer 1 Register
(F2h; Read/Write)
Figure 21. Counter/Timer 1 Register
Counter/Timer Operation
Under software control, T1 is started and stopped using the Timer Mode regis ter
(F1h) bits D2–D3: a Load bit and an Enable Count bit. See Figu re 22.
R241 TMR
Timer Mode Register
(F1h; Read/Write)
Figure 22. Timer Mode Register
D7D6D5D4D3D2D1D0
Initial value when written
(range 1–256 decimal, 01h–00h)
Current value when read
D3D2D1D0
Reserved
0 = No function
1 = Load T1
0 = Disable T1 co unt
1 = Enable T1 count
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Load and Enable Count Bits
Setting the Load bit D2 to 1 transfers the initial values in the prescaler and the
counter/t imer registers into their resp ective down-counters. The next inte rnal clock
resets bit D2 to 0, readying the Load bit for the next load operation. The initial val-
ues can be loaded into the down-counters at any time. If the counter/timer is run-
ning, the counter/timer continues to run and starts the count over with the initial
value. Therefore, the Load bit actually functions as a softwar e re-trigger.
The T1 counter/timer remains at rest as long as the Enable Count bit D3 is 0. To
enable counti ng, the Enable Count bit D3 must be set to 1. Counting actually st arts
when the Enable Count bit is written by an instruction. The f irst decrement occurs
four internal clock periods after the Enable Count bit has been set.
The Load and Enable Count bit s can be set at the same time. For example, using
the instr uction OR TMR #%0C sets both D2 and D3 of TMR to 1. The initi al values of
PRE1 and T1 are loaded into their respective counters, and the count is started
after the M2T2 machine st ate after the operand is fetched as shown in Figure 23.
Figure 23. Starting the Count
Prescaler Operations
During counti ng, the programmed clock sour ce drives the prescaler 6-bit coun ter.
The counter is counted d own from the value specified by bits D2–D7 of the corre-
sponding prescaler register, PRE0 or PRE1 (Figure 24). When the prescaler
counter reaches it s end-of-count, the initial val ue is reloaded and co unting contin-
ues. The prescaler never actually reaches zero. For example, if the prescaler is
set to divide by three, the count sequence is as follows:
3-2-1-3-2-1-3-2...
M3M1M2Mn
T1T2T3T1T2T3T1T2T3T1T2T3
#03 is fetched TMR is written;
counter/timers
are loaded
first decrement
occurs four
clocks later
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R243 PRE1
Prescaler 1 Registe r
(F3h; Read/Write)
Figure 24. Counting Modes
When the PRE1 register i s loaded with 000000 in the six most significant bits, the
prescaler divides by 64. If that number is 000001, the prescaler does not divide
and pa sses its clock on to T1.
Each time the prescaler reaches its end-of-count, a carry i s generated, which
allows the counter/t imer to decrement by one on the next timer clock i nput. When
T1 and PRE1 both reach their end-of-count, an interrupt reques t is generated—
IRQ5 fo r T1. Depending on the counting mode selected, the counter/timer either
comes to rest with its value at 00h (single-p ass mode), or the ini tial value is auto-
maticall y reloaded and counting conti nues (continuous mode). In single-pass
mode, the prescal er still continues to decrement when the timer T1 has reached
its end-of-count. The prescaler al ways starts from its programmed value upon
restarting the counter.
The counting modes are controlled by bit D0 of PRE1, with D0 cleared to 0 fo r s in -
gle-pass counting mode or set to 1 for continuous mode.
The counter/timer can be stopped at any time by setting the Enable Count bit t o 0
and restarted by setti ng the Enabl e Count bit back to 1. The T1 counter/t imer con -
tinues its count value at the time it was stopped. The current value in the T1
counter/timer can be read at any time with out affecting the counting operation.
New initial values can be written to the pres caler or the counter /timer regist ers at
any time. These values are transferred to their respective down-counters on the
next load operation. If the counter/timer mode i s continuous, the next load occurs
on the timer clock following an end-of-count. New initial values must be written
before the load operati on because the prescaler always effectively operates in
continuous count mode.
If the value loaded in the T1 register is 01h, the timer is actual ly not timing or
counting at all; the timer is passing the prescaler end-of-count through. Because
the prescaler is continuously running, regardless of the single-pass/continuous
mode operation, the 8-bit timer continuously times out at the rate of the prescaler
end-of-count if the T1 timer val ue is programmed to 01h.
D0
Count mode
1 = T1 modulo-N
0 = T1 single pass
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The time interval (i) until end-of-count, is given by
i = t x p x v
where t is 8 divided by XTAL frequency, p is the prescaler value (1 – 64), and v is
the counter/timer value (1 – 256). The prescaler and counter/timer are true divide-
by-n counters.
TOUT Modes
The Timer Mode register TMR (F1h) (Figure 25) is used in conju nction with the
Port 5 Mode regi ster P5M to confi gure P56 for TOUT oper ation. In order for TOUT to
function , P56 must be defi ned as an output line by sett ing P5M bit D6 to 0. Output
is controlled by one of the counter/timers (T0 or T1) or the internal clock.
R241 TMR
Timer Mode Register
(F1h; Read/Write)
Figure 25. Timer Mode Register TOUT Operat i on
The P56 output is selec ted by TMR bits D7 and D6. T 1 is selected by setting D7
and D6 to 1 and 0, res pective ly. The counter/ timer TOUT mode is turned off by set-
ting TMR b its D7 and D6 both to 0, freeing P36 to be a data output line.
TOUT is i nitialized to a logic 1 whenever the TMR Load bit D2 is set to 1.
At end-of-count, the interr upt request line IRQ5 clocks a toggle flip-flop. The out-
put of this fl ip-flo p drives the TOUT line P56. In all cases, when the counter/t imer
reaches its end-of-count, TOUT toggles to its opposite state (see Figur e 26). If, fo r
example, the counter/timer is i n continuous co unting mode, TOUT has a 50% duty
cycle output . You can control the duty cycle by varying the init ial values af ter each
end-of-count.
D7D6D2
0 = No function
1 = Load T1
TOUT modes
TOUT off = 00
Reserved = 01
T1 out = 10
Internal cl oc k out = 11
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Figure 26. Counter/Timer Output Using TOUT
The internal clock can be selected as output instead of T1 by setting TMR bits D7
and D6 both to 1. The internal cl ock (XTAL fr equency/2) is then directly output on
P56 (Figure 27).
Figure 27. Internal Clock Output Using T OUT
While prog rammed as TOUT, P56 cannot be modified b y a wri te to por t reg ister P5.
However, the Z8 software can examine P56’s current output by reading the port
register.
TIN Modes
The Timer Mode register TMR (F1h) (Figure 28) is used in conju nction with the
Prescaler register PRE1 (F3h) (Figur e 29) to configure P5 2 as TIN. TIN is used in
conjunc tion with T1 in one of four modes:
•
External cl ock input
•
Gated internal clock
•
Triggered internal clock
•
Retriggerable internal clock
+2 P56
TOUT
IRQ5 (T1 end-of-count)
OSC +2
Internal clock
P56TOUT
TMR
TMR
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R241 TMR
Timer Mode Register
(F1h; Read/Write)
Figure 28. Timer Mode Register TIN Operation
R243 PRE1
Prescaler 1 Registe r
(F3h; Write Only )
Figure 29. Prescaler 1 TIN Operation
The T1 counter/timer clock source must be configured for external by sett ing
PRE1 bit D2 to 0. The Timer Mode register bits D5 and D4 can then be used to
selec t the TIN operation.
For T1 to start counting as a result of a TIN input, the Enable Count bit D3 in TMR
must be set to 1. When using TIN as an external cl ock or a gate input, the initial
values must be loaded int o the down-counters by setting the Load bit D2 in TMR
to 1 before counting begins. Ini tial values are aut omatically loaded i n Trigger and
Retrigger modes, so software loading is unnecessary.
Configure P52 as an input line by setting P5M bit D2 to 1.
D5D4
TIN modes
External clock input = 00
Gate input = 01
Trigger input = 10
(non-retriggerable)
Trigger input = 11
(retriggerable)
D1
Clock source
1 = T1 internal
0 = T1 external (TIN)
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Each High-to-Low transition on TIN generates interrupt request IRQ0, regardless
of the select ed TIN mode or the enabled/disabled st ate of T1. IRQ0 must t here fore
be masked or enabled accordi ng to the needs of the application.
External Clock Input Mode
The TIN External Clock Input mode (TMR bits D5 and D4 both set to 0) supports
the counti ng of exter nal event s, where an event is c onsidere d to be a High- to-Low
transition on TIN (see Figure 30) occurrence (single-pass mode) or on every nth
occurrence (continuous mode) of that event.
Figure 30. External Clock Input Mode
Gated Internal Clock Mode
The TIN Gated Internal Clock mode (TMR bits D5 and D4 set to 0 and 1, respec-
tively) measures the duration of an external event. In this mode, the T1 prescaler
is driven by the internal timer clock, gated by a High level on TIN (see Figure 31).
T1 counts while TIN is High and stops counting when TIN is Low. Interrupt request
IRQ0 is generated on the Hi gh-to-Low transition of TIN, signaling the end of the
gate input. Interrupt request IRQ5 is generated if T1 reaches its end-of-count.
Figure 31. Gated Clock Input Mode
P52 D
Internal clock
T1 IRQ5
TIN clock D PRE1
IRQ0
TMR
D5–D4 = 00
P52D
Internal clock
+2
IRQ5
TIN
gate D
OSC
IRQ0
TMR
D5–D4 = 01
+4 T1 PRE1
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Triggered Input Mode
The TIN Triggered Input mode (TMR bits D5 and D4 set to 1 and 0, respe ctively)
causes T1 to st art counting as the result of an exter nal event (see Figure 32). T1 is
then loaded and clocked by t he internal timer clock f ollowing the fi rst High-to- Low
transition on the TIN input. Subsequent TIN tr ansitions do not af fect T1. In the sin-
gle-pass mode, the Enable bit is reset whenever T1 reaches its end-of-count. Fur-
ther TIN transitions have no effect on T1 until sof tware sets the Enable Count bit
again. In c ontinuous mode, when T1 is triggered, counting continues until soft ware
reset s the Enable Count bit. Interrupt request IRQ5 is generat ed when T1 reaches
its end-of-count.
Figure 32. Triggered Clock Mode
Retriggerable Input Mode
The TIN Retriggerable Input mode (TMR bits D5 and D 4 bo th set to 1) causes T1 to
load and start counting on every occurrence of a High-to-Low tr ansition on TIN
(see Figure 32). Inter rupt request IRQ5 is gener ated if the programmed time inter-
val (determined by T1 prescale r and counter/timer register initial values) has
elapsed since the last High-to-Low transition on TIN. In single-pass mode, the
end-of-count resets the Enable Count bit. Subsequent TIN transitions do not
cause T1 t o load and st art c ounting until s of tware se t s the Ena ble Count bi t again.
In conti nuous mode , counti ng continues when T1 i s t riggered unt il sof t ware res et s
the Enable Count bi t. When enabled, each High-to- Low TIN transition causes T1 to
P52D
Internal clock
+2
IRQ5
TIN
trigger D
OSC
IRQ0
TMR
D5–D4 = 11
+4 T1 PRE1
Edge
trigger
TMR
D5 = 1
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reload and restart counting. Interrupt request IRQ5 is generated on every end-of-
count.
T8 and T16 Timer Operati on
The T8 timer is a programmable 8-bit counter/timer with two 8-bit capture regis-
ters and two 8-bit load registers. The T16 timer is a programmable 16-bi t counter/
timer with one 16-bit capture register pair and one 16-bit load regis ter pair. See
Figure 33. The T8 and T16 counters/timers have two modes of operation:
•
The transmit mode is used to generate complex waveforms. There are two
submodes:
–
The normal m ode can be used in single-pass or modulo-N (repeating)
mode.
–
The ping-pong mode is used when the T8 timer counts down, enables the
T16 timer that counts down, enabling T8, and so on, unt il the mode is
disabled.
•
The demodulation mode is used to capture and demodulate complex
waveforms.
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Figure 33. Counter/Timer Architecture
T8 Transmit Mode
Before T8 is enabled, the output of T8 depends on CTR1, D1. If CTR1, D1 is 0,
T8_OUT is 1. If CTR1, D1 is 1, T8_OUT is 0.
When T8 is enable d, the output T8_OUT swi tches to the initi al value (CTR1 D1). If
the initial value (CTR1 D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into
the counter. In single-pass mode (CTR0 D6), T8 counts down to 0 and stops,
T8_OUT toggles, the ti me-out s t atus bit ( CTR0 D5) is set , and a time-out i nterr upt
can be generated if it is enabled (CTR0 D1). In modulo-N mode, upon reaching
terminal count, T8_ OUT i s toggl ed, but no inte rr upt i s gen erated. Then T8 loa ds a
new count ( if T8_OUT leve l is 0), TC8L i s loaded; i f T8_OUT is 1 , TC8H is l oaded.
HI16
16-Bit
T16
8-Bit
T8
Glitch
Filter
Edge
Detect
Circuit
LO16
And/Or
Logic Timer
8/16
8 8
Ti mer 16
Ti mer 8
HI8 LO8
8 8
TC8H TC8L
8 8
TC16H TC16L
8 8
16 SCLK Clock
Divider
T16 Clocked
Input 1 2 4 8
SCLK Clock
Divider
T8 Clock Divider
1 2 4 8
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T8 count s down to 0, toggles T8_OUT, set s the time-out st atus bit (CTR0 D5), and
generates an int e rrupt if enabled (CTR0 D1). This completes one cycle. T8 then
loads from TC8H or TC8L, according to the T8_OUT level, and repeats the cycle.
The user can modify the values in TC8H or TC8L at any time.The new values t ake
effect when they are loaded. Do not write these registers at the ti me the values
are to be loaded into the counter/timer. An initial count of 1 is not allowed. An ini-
tial count of 0 causes TC8 to count from 0 to FFh to FEh. Transition from 0 to FFh
is not a time-out condition (see Figure 34).
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Figure 34. Transmit Mode Flowchart
Set Tim e-out Sta tus Bit
(CTR 0 D 5) and Ge nerate
Timeo u t_Int. if Enabled
Set T ime-out Status Bit
(CTR0 D5) and Generate
Timeout_In t. if Enabled
T8 (8-Bit)
Transmit Mode
No T8_Enable Bit Set
CTR0 D7
Yes
CTR1 D1
Value
Rese t T 8_E nable Bit
01
Load TC8 L
Reset T8_OUT
Load TC8H
Set T8_OUT
Enab le T8
No T8_Timeout
Yes
Single Pass Single
Modulo-N
T8_OUT Value 0
Enable T 8
No T8_Timeout
Yes
Disable T8
Pass?
Load TC 8H
Set T8_OUT
Load TC8L
Reset T8_OUT
1
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Do not use the same instruct ions for stopping the counter/
timers and setting the status bit s. Two successive commands
are necessary—the fi rst command for stopping counter/timers
and the second command for resett ing the status bits—
because one counter /timer cloc k interval must complete for the
initi ated event to actually occur.
T8 Demodulation Mode
Program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (ri sing,
falling, or both, dependin g on CTR1 D5, D4) is detected, it starts to count down.
When a subsequent edge (rising, falling, or both, depending on CTR1 D5, D4) is
detected duri ng counting, the current value of T8 is one’s complemented and put
into one of the capture registers. If T8 is a positive edge, data is placed in LO8. If
T8 is a negative edge, data is placed in H18. One of the edge-detect status bits
(CTR1 D1, D0) is set, and an interrupt can be gener ated if enabled (CTR0 D2).
Meanwhile, T8 is l oaded with TC8H and sta rts counti ng again. If T8 reach es 0, the
time-out s tatus bit (CTR0 D5) is set, and an interrupt can be generat ed if enabled
(CTR0 D1), and T8 continues counting from FFh (see Figure 35).
Note:
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Figure 35. Demodulation Mode Flowchart
T8 (8-Bit)
Demo dulation Mode
T8 Enable
CTR0, D7
No
Yes
FFh→ TC8
First
Edge Present
Enable TC8
T8_Enable
Bit Set
Edge Present
T8 Time Out
Set Edge Present Status
Bit and Trigger Data
Capture Int. if Enabled
Set T ime-out S tatus
Bit and Trigger Time
Out Int. if Enabled
Contin ue C oun tin g
Disable TC8
No
Yes
No
Yes
Yes
Yes
No
No
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T16 Transit Mode
In normal or ping-pong mode, the output of T16, when not enabled, is dependent
on CTR1, D0. If CTR1, D0 i s a 0, T16_ OUT is a 1; if CTR1, D0 is a 1, T16_OUT is
0. The user can force the output of T16 to either a 0 or 1, whether it is enabled or
not, by programming CTR1 D3, D2 to a 10 or 11.
When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched
to it s initial value (CTR1 d0). When T16 counts down to 0, T16_OUT i s toggled (in
normal or ping-pong mo de), an interrupt is genera ted if enabled (CTR2 D1), and a
stat us bit (CTR2 D5) is set. If it is in modulo-N mode, i t is loaded wit h TC16H * 256
+ TC16L, and the counting continues.
The user can modif y the values in TC16H and TC16L at any t ime. The new values
take effect when they are loaded. Do not load these registers at the time the val-
ues are to be loaded into the counter/timer. An initi al count of 1 is not allowed. An
initi al count of 0 causes T16 to count from 0 to FFFFh to FFFEh. Transition from 0
to FFFFh is not a time-out condition.
T16 Demodulation Mode
Program TC16L and TC16H to FFh. After T16 is enabled, when the first edge (ris-
ing, falling, or both, depending on CTR1 D5, D4) is detected, T16 captures HI16
and LO16, reloads, and begins counting.
Ping-Pong Mode
This operati on mod e is onl y va lid in transmit mode. T8 and T16 must be pro-
grammed in single-pass mode (CTR0 D6, CTR2 D6), and ping-pong mode must
be programmed in CTR1 D3, D2. The user can begin the operation by enabli ng
either T8 or T16 (CTR0 D7 or CTR2 D7). For example, if T8 is enabled, T8_OUT
is set to this i nitial value (CTR1 D1). According to T8_OUT’s level, TC8H or TC8L
is loaded int o T8. After the termi nal count is reached, T8 is di sabled, and T16 is
enabled. T16_OUT switches to its ini ti al value (CTR1 D0), data from TC16H and
TC16L is loaded, a nd T16 starts to count. After T16 reaches the ter minal count, it
stops . T8 is enabled agai n, and the whole cycle r epeats. In terrupts can be allowed
when T8 or T16 reaches terminal control (CTR0 D1, CTR2 D1). To stop the ping-
pong operation, write 00 to bits D3 and D2 or CTR1.
Enabling ping-pong operation while the counters/timers are
running can cause intermittent counter/timer function. Disable
the counters/timers, then reset the status flags before starting
the ping-pong mode.
Note:
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Control and Status Registers
The Z86D99/Z86L99 family has 4 I/O port registers, 33 status and control regis-
ters, and 233 general-purpose RAM registers. The I/O port and control registers
are incl uded in t he general-p urpose r egister memory t o allow any Z8 ins truction to
process I/O or control information directly, thus elim inating the requirement for
special I/O or control instructions. The Z8 instruction set permits direct access to
any of these 37 registers. In addition, each of the 233 general-pur pose registers
can also function as an accumulator, an address pointer, or an index register.
Registers identified as “Reserved” do not exist or have not been implemented in
this design.
Register Summary
Table 10 through Tabl e 13 summarize the name and location of all registers. The
register -by-register descriptions follow this section.
Table 10.I/O Port Registers (Group 0, Bank 0, Registers 0–F)
Grp/Bnk Reg Register Function Identifier
(00h)rF General-Purpose RAM Register GPR
(00h)rE General-Purpose RAM Register GPR
(00h)rD General-Purpose RAM Register GPR
(00h)rC General-Purpose RAM Register GPR
(00h)rB General-Purpose RAM Register GPR
(00h)rA General-Purpose RAM Register GPR
(00h)r9 General-Purpose RAM Register GPR
(00h)r8 General-Purpose RAM Register GPR
(00h)r7 Analog/Digital Converted Data ADCDATA
(00h)r6 Port 6 Control Register P6
(00h)r5 Port 5 Control Register P5
(00h)r4 Port 4 Control Register P4
(00h)r3 Reserved
(00h)r2 Port 2 Control Register P2
(00h)r1 Reserved
(00h)r0 Reserved
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Table 11.Control and Status Registers (Group F, Bank 0, Registers 0–F)
Grp/Bnk Reg Register Function Identifier
(F0h)rF Stack Pointer SP
(F0h)rE Gener al- pur pose RAM Regis ter GP R
(F0h)rD Register Pointer RP
(F0h)rC Program Control Flag Register Flags
(F0h)rB Interrupt Mask Register IMR
(F0h)rA Interrupt Request Register IRQ
(F0h)r9 Interrupt Priority Register IPR
(F0h)r8 Reserved
(F0h)r7 Port 3 Mode Register P3M
(F0h)r6 Port 2 Mode Register P2M
(F0h)r5 Reserved
(F0h)r4 Reserved
(F0h)r3 T1 Prescale Register PRE1
(F0h)r2 T1 Data Register T1
(F0h)r1 T1 Mode Register TMR
(F0h)r0 Reserved
Table 12.Timer Control Registers (Group 0, Bank D, Registers 0–F)
Grp/Bnk Reg Register Function Identifier
(0Dh)rF Reserved
(0Dh)rE Reserved
(0Dh)rD Reserved
(0Dh)rC Low-Battery Detect Flag LB
(0Dh)rB T16 MS-Byte Capture Register HI8
(0Dh)rA T16 LS-Byte Capture Register LO8
(0Dh)r9 T8 High Capture Register HI16
(0Dh)r8 T8 Low Capture Register LO16
(0Dh)r7 T16 MS-Byte Hold Register TC16H
(0Dh)r6 T16 LS-Byte Hold Register TC16L
(0Dh)r5 T8 High Hold Register TC8H
(0Dh)r4 T8 Low Hold Register TC8L
(0Dh)r3 T8/T16 Control Register B CTR3
(0Dh)r2 T16 Control Register CTR2
(0Dh)r1 T8/T16 Control Register A CTR1
(0Dh)r0 T8 Control Register CTR0
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Register Error Conditions
Registers in the Z8 S tand ard Register File must be use d corr ectly because certa in
conditions produce inconsistent results and must be avoided.
•
Registers F5h–F9h are writ e-only registers. If an attempt is made to read these
registers, FFh is returned. Reading any write-only register returns FFh.
•
When the Regist er Pointer ( register FDH) is read, the l east signif icant four bit s
(lower nibble) indicate the current Expanded Register File Bank. (For
example, 0000 indicates the Standard Register File, while 1010 indicates
Expanded Register File Bank A.)
•
Wr iting to bits that are selected as timer outputs changes the I/O register but
has no effect on the pin signal.
•
The Z8 instruct ion DJNZ uses any general-purpose worki ng register as a
counter.
•
Logical instructions such as OR and AND require that the current contents of
the operand be read . They do no t function properly on write-only register s.
Table 13.SMR and Port Mode Registers (Group 0, Bank F, Registers 0–F)
Grp/Bnk Reg Register Function Identifier
(0Fh)rF Reserved
(0Fh)rE Reserved
(0Fh)rD Reserved
(0Fh)rC Reserved
(0Fh)rB Stop Mode Recovery Register SMR
(0Fh)rA Reserved
(0Fh)r9 Reserved
(0Fh)r8 ADC Control Register ADCCTRL
(0Fh)r7 Reserved
(0Fh)r6 Port 6 Mode P6M
(0Fh)r5 Port 5 Stop Mode Recovery P5SMR
(0Fh)r4 Port 5 Mode Register P5M
(0Fh)r3 Reserved
(0Fh)r2 Port 4 Mode Register P4M
(0Fh)r1 Port 2 Stop Mode Recovery P2SMR
(0Fh)r0 Port Configuration Register P456CON
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Registers (Grouped by Function)
The followi ng is a summary of the 37 special-purpos e regi sters of the Z86D99/
Z86L99 family grouped by function. The following are the functional groups:
•
Flags and Pointers
•
Analog-to-Digital Converter Control
•
Interrupt Control
•
I/O Port Control
•
Timer Control—General-Purpose Timer (T1)
•
Timer Control—T8 and T16 Timers
•
Stop-Mode Recovery Control
For any of the registers described in this section (see Table 14), bits identified as
“Reserved” either do not exist (meaning they have not been implemented in this
design) or have a special purpose in a ZiLOG engineering or test environment.
Do not attempt to use these bits as the results are
unpredictable and meaningless.
Table 14.Register Description Locations
Address
Grp/Bnk Register Register Function Symbol Location
00h r2 (R2) Port 2 Data P2 page 68
00h r4 (R4) Port 4 Data P4 page 69
00h r5 (R5) Port 5 Data P5 page 70
00h r6 (R6) Port 6 Data P6 page 71
00h r7 (R7) ADC Data ADCDATA page 62
0Dh r0 T8 Timer Control CTR0 page 77
0Dh r1 T8/T16 Control (A) CTR1 page 74
0Dh r2 T16 Timer Control CTR2 page 80
0Dh r3 T8/T16 Control (B) CTR3 page 76
0Dh r4 T8 Low Load TC8L†page 79
0Dh r5 T8 High Load TC8H†page 79
0Dh r6 T16 Low Load TC16L†page 82
0Dh r7 T16 High Load TC16H†page 82
0Dh r8 T16 Low Capture LO16†page 81
0Dh r9 T16 High Capture HI16†page 81
0Dh r10 T8 Low Captur e LO8 †page 78
Caution:
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Flags and Pointer Registers
In additi on to the thr ee standard Z8 flag and pointer registers (Pr ogram Control
Register Pointer, and Stack Pointer), the Z86D99/Z86L99 family includes a Low-
Battery Detec t Flag register.
0Dh r11 T8 Hig h Capture HI 8†page 78
0Dh r12 Low Battery Detect LB page 60
0Fh r0 Port Configuration (A) P456CON page 67
0Fh r1 Port 2 SMR Source P2SMR page 84
0Fh r2 Port 4 Mode P4M page 69
0Fh r4 Port 5 Mode P5M page 70
0Fh r5 Port 5 SMR Source P5SMR page 84
0Fh r6 Port 6 Mode P6M page 71
0Fh r8 ADC Control ADCCTRL page 61
0Fh r11 Stop Mode Recovery SMR page 83
F0h r1 (R241) T1 Time r Mod e TMR page 72
F0h r2 (R242) T1 Timer Data T1 page 72
F0h r3 (R243) T1 Ti me r Pres ca le P RE 1 page 73
F0h r6 (R246) Port 2 Mode P2M page 68
F0h r7 (R247) Port Configuration (B) P3M page 67
F0h r9 (R249) Interrupt Priority IPR page 64
F0h r10 (R250) In ter r upt Requ est IRQ page 65
F0h r11 (R251) Interrupt Mas k IMR page 63
F0h r12 (R252) Program Control Flags Flags page 57
F0h r13 (R253) Register Pointer RP page 58
F0h r15 (R255) Stack Pointer SP p age 59
Note: †This register is not reset following Stop Mode Recovery
(SMR).
Table 14.Register Description Locations (Continued)
Address
Grp/Bnk Register Register Function Symbol Location
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Program Control Flag Register (Flags)
The Program Control Fl ag register (see Table 15) reflects the curr ent status of the
Z8 as shown in Table 15. The FLAGS register contains six bits of status informa-
tion tha t are set or clear ed by CPU operations. Four of the bit s (C, V, Z, and S) can
be tested for use wi th condition al jump in structio ns. Two flags (H and D) cannot be
tested and are used for BCD arithmetic. The two remaining flags in the register
(F1 and F2) are available to the user, but they must be set or cleared by instruc-
tions and are not usable with conditional jumps.
Table 15.FLAGS Register [Group/Bank F0h, Register C (R252)]
Bit 76543210
Bit/FieldCZSVDHF2F1
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset XXXXXXXX
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7_______ Carry Flag (C) R/W 1 Indicates the “carry out” of bit 7
position of a register being used as
an accumulator; on Rotate and Shift
instructions this bit contains the most
recent value shifted out of the
specified register
_6______ Zero Flag (Z) R/W 1 Indicates that the contents of an
accumulator register is zero following
an arithmetic or logical operation
__5_____ Sign Flag (S) R/W X Stores the value of the most
significant bit of a result following an
arithmetic, logical, Rotate, or Shift
operation; in arithmetic operations on
signed numbers, a positive number is
identified by a 0, and a negative
number is identified by a 1
___4____ Overflow
Flag (V) R/W 1 For signed arithmetic, Rotate, and
Shift operations, the flag is set to 1
when the result is greater than the
maximum possible number (>127) or
less than the minimum possible
number (<-128) that can be
represen ted in two’s complem ent
form; following logical operations, this
flag is set to 0
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Register Pointer (RP)
Z8 instructions can access registers directly or indirectly using either a 4-bit or 8-
bit address field. The upper nibble of the Regist er Pointer, as described in
Table 16, contains the base address of the active Working Register GROUP. The
lower nibble contains the base address of the Expanded Register File BANK.
When using 4-bit add ressing, the 4-bi t addr ess of the working r egis ter (r0 to rF) is
combined with the upper nibble of the Register Pointer (id entifying the WR
GROUP), thus forming th e 8-bit actual address.
____3___ Decimal Adjust
Flag (D) R/W 1
0Used for BCD arithmetic—after a
subtracti on, the fla g is set to 1;
following an addition, it is cleared to 0
_____2__ Half Carry
Flag (H) R/W 1
0Set to 1, whenever an addition
generates a “carry out” of bit position
3 (overflow) of an accumulator; or
subtraction generates a “borrow into”
bit 3
______1_ User Flag (F2) R/W 1
0User definable
_______0 User Flag (F1) R/W 1
0User definable
Table 16.RP Register [Group/Bank F0h, Register D (R253)]
Bit 76543210
Bit/Field Working Register Group Expanded Register File Bank
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7654_____ Working Register
Group Pointe r R/W X Identifies 1 of 16 possible WR
Groups, each containing 16 Working
Registers
_____3210 Expanded
Register File
Bank Pointer
R/W X Identifies 1 of 16 possible ERF
Banks; only Banks 0, D, and F are
valid for the Z86D99/Z86L99 family
Table 15.FLAGS Register [Group/Bank F0h, Register C (R252)] (Continued)
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S tack Pointer (SP)
The Z86D99/Z86L99 famil y of products is configured fo r an internal stack. The
size of the st ack i s limit ed only by the available memory sp ace or gen eral-p urpose
RAM registers dedicated to this task. An 8-bit stack pointer, as described in
Table 17, is used for all stack operations.
Table 17.SP Register [Group/Bank F0h, Register F (R255)]
Bit 76543210
Bit/Fiel d Stack Point er
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset XXXXXXXX
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210 S t ack Pointer R/W X Points to the data stored on the top of
the stack; an overflow or underflow
can occur if the stack ad dress is
incremented or decremented during
normal stack operati ons
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Low-Battery Detect Flag (LB)
When the Z86D99/Z86L99 is used in a battery-operated application, one of the
on-chip comparators can be used to check t hat the VCC is at the requir ed l evel for
correct operation of the device. When voltage begins to approach the VBO point,
an on-chip low-battery detection circuit is tripped, which in turn sets a user-read-
able flag. The LB register, as described in Table 18, is used to set and reset the
LB flag.
The LB flag will be valid after enabling the detecti on for 20 µS
(design esti mation, not tested in pr oduction) . LB does not work
at ST OP mode. It must be disabl ed during STOP mode i n order
to reduce current.
Table 18.LB Register (Group/Bank 0Dh, Register C)
Bit 76543210
Bit/Field Reserved Pad
LVD LVD_
Flag LVD_
Enable
R/W WWWWWR/WR/WR/W
Reset 11111X00
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543___ Reserved R
W1
XAlwa ys reads 11111
No Effect
_____2__ Pad LVD R
R
W
1
0
X
Pad is not regulated when P43=0
(Vpad<Vmin; see page 33)
Pad is regulating the current when
P43=0 (Vpad>Vmin; see page 33)
Reset Pad LB flag
______1_ LVD_Flag R
R
W
1
0
X
LB Flag Set if VDD<VLV
LB Flag Reset
No Effect
_______0 LVD_Enable R/W 1
0Enable L B *
Disable LB
Note: * When LVD is enabled, IRQ5 is set only for low-voltage detection. Timer 1 will not generate
an interrupt request.
Note:
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Analog-to- Digital Converter Control Registers
The Z86D99/Z86L99 famil y features an 8-bit analog-to-digi tal converter with
external voltage references. The output of the ADC is stored in the ADC Data
Register, as shown in Table 20. The ADC is configured using the ADC Control
Register, as shown in Table 19.
ADC Control Register (ADCCTRL)
The ADCCTRL register controls the operation of the analog-to-digital converter.
Bit s 2 and 3 of the ADCCTRL register determine which of the four analog input
channels feeds i nto the ADC at any given time. Bits 4 through 7 enable or disable
the digital input buffer. When configured as an ADC input channel, the port has to
be configured i n Input Mode and with the digital input b uffer disabled.
Table 19.ADCCTRL Register (Group/Bank 0Fh, Register 8)
Bit 76543210
Bit/Field P47_
A/D P46_
A/D P45_
A/D P44_
A/D Channel
Selection A/D Pwr
On
ADC
Clock
Select
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7_______ P47_A/D R/W 1
0P47 configured as A/D Input
P47 configured as digital input
_6______ P46_A/D R/W 1
0P46 configured as A/D Input
P46 configured as digital input
__5_____ P45_A/D R/W 1
0P45 configured as A/D Input
P45 configured as digital input
___4____ P44_A/D R/W 1
0P44 configured as A/D Input
P44 configured as digital input
____32__ Channel
Selection R/W 11
10
01
00
Channel 3 (P47)
Channel 2 (P46)
Channel 1 (P45)
Channel 0 (P44)
______1_ A/D_PowerON R/W 1
0ON
OFF
_______0 ADC Clock Select R/W 1
0SCLK/2
SCLK
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ADC Data Register (ADCDATA)
The ADCDATA register is a read-only register that contains the digital out put of
the analog-to-digital conv erter. See Table 20.
)
Interrupt Control Registers
The Z8 allows up to six different interrupts from a variety of sources. These inter-
rupts can be masked and their priorities set by using the Interrupt Mask Register
and Interru pt Pri orit y Register. The Interru pt Request Regis ter stores the int errupt
requests for both vectored and polled interr upts.
Table 20.ADCDATA Register (Group/Bank 00h, Register 7)
Bit 76543210
Bit/Field ADC Data
R/W RRRRRRRR
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210 ADC Data R
WData
XOutput of the ADC
No Effect
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Interrupt Mask Register
The IMR, as described in Table 21, individually or global ly enables the six interrupt
requests. Bit 7 of the IMR is the master enable and must be set before any of the
individual interrupt r equests can be rec ognized. Bit 7 must be set and reset by the
enable inter rupts and disabl e interrupts i nstructions only. The IMR is auto matically
reset during an interrupt service rout ine and set following the execution of an
Interrupt Return (IRET) instruction.
Bit 7 must be reset by the DI instruction before the contents of
the Interr upt Mask Register or the In terrupt Priority Register are
changed except in the following situations:
–
Immediately after a hardware reset
–
Immediately aft er executi ng an inter rupt servi ce routi ne and bef ore IMR bit
7 has been set by any instruction
Table 21.IMR (Group/Bank 0Fh, Register B)
Bit 76543210
Bit/Field Master Re-
served IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7_______ Master R/W 1
0Enable Master Interrupt
Disable Master Interrupt
_6______ Reserved R
W1
XAlwa ys reads 1
No Effect
__5_____ IRQ5R/W 1
0Enable IRQ5
Disable IRQ5
___4____ IRQ4R/W 1
0Enable IRQ4
Disable IRQ4
____3___ IRQ3R/W 1
0Enable IRQ3
Disable IRQ3
_____2__ IRQ2R/W 1
0Enable IRQ2
Disable IRQ2
______1_ IRQ1R/W 1
0Enable IRQ1
Disable IRQ1
_______0 IRQ0R/W 1
0Enable IRQ0
Disable IRQ0
Note:
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Interrupt Priority Register (IPR)
The IPR, as described in Table 22, is a write-only register that sets priorities for
the vectored interrupts in order to resolve simultaneous interrupt requests. There
are 48 sequence possibilities for interrupts. The six interrupts, IRQ0 to IRQ5, are
divided int o three group s o f two interrupt reques ts each, as follows:
•
Group A consist s of IRQ3 and IRQ5
•
Group B consist s of IRQ0 and IRQ2
•
Group C consist s of IRQ1 and IRQ4
)
Priori ties can be set both within and between groups using the IPR. Bits 1, 2, and
5 of the IPR define the prior ity of individual members within the groups. Bits 0, 3,
and 4 are encoded to define six priority orders between the three gro u ps. Bits 6
and 7 are reserved.
Table 22.IPR (Group/Bank 0Fh, Register 9)
Bit 76543210
Bit/Field Reserved Grp A
IRQ3_5 Int_Group Grp B
IRQ0_2 Grp C
IRQ1_4 Int_
Group
R/W WWWWWWWW
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76______ Reserved W X No Effect
__5_____ Grp A Priority:
IRQ3 and IRQ5
W1
0IRQ3>IRQ5 (Group A)
IRQ5>IRQ3
___43__0 Interrupt Group
Priority W 111
110
101
100
011
010
001
000
Reserved
B>A>C
C>B>A
B>C>A
A>C>B
A>B>C
C>A>B
Reserved
_____2__ Grp B Priority:
IRQ0 and IRQ2
W1
0IRQ0>IRQ2 (Group B)
IRQ2>IRQ0
______1_ Grp C Priority:
IRQ1 and IRQ4
W1
0IRQ4>IRQ1 (Group C)
IRQ1>IRQ4
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Interrupt Request Register
The IRQ, as des cribed in Table 23, is a read/wr ite regist er that stores t he int errupt
requests for both vectored and polled interrupts. When an interrupt request is
made by any of the six inter rupts, the corresponding bit in the IRQ is set to 1.
Table 23.IRQ (Group/Bank 0Fh, Register A)
Bit 76543210
Bit/Field Interrupt Edge Set
IRQ5 Set
IRQ4 Set
IRQ3 Set
IRQ2 Set
IRQ1 Set
IRQ0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76______ Interrupt Edge
Trigger R/W 11
10
01
00
P51 Rise/FallingP52 Rise/Falling
P51 Rising P52 Falling
P51 FallingP52 Rising
P51 FallingP52 Falling
__5_____ Set IRQ5R
R
W
W
1
0
1
0
IRQ5 Inactive
IRQ5 Active
Set IRQ5
Reset IRQ5
___4____ Set IRQ4R
R
W
W
1
0
1
0
IRQ4 Inactive
IRQ4 Active
Set IRQ4
Reset IRQ4
____3___ Set IRQ3R
R
W
W
1
0
1
0
IRQ3 Inactive
IRQ3 Active
Set IRQ3
Reset IRQ3
_____2__ Set IRQ2R
R
W
W
1
0
1
0
IRQ2 Inactive
IRQ2 Active
Set IRQ2
Reset IRQ2
______1_ Set IRQ1R
R
W
W
1
0
1
0
IRQ1 Inactive
IRQ1 Active
Set IRQ1
Reset IRQ1
_______0 Set IRQ0R
R
W
W
1
0
1
0
IRQ0 Inactive
IRQ0 Active
Set IRQ0
Reset IRQ0
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Whenever a power-on reset is executed, the IRQ is reset to 00h and disabled.
Before t he IRQ accepts requests, i t must be enabled by executi ng an enable inter -
rupts instructi on.
IRQ is always cleared to 00h and is in read-only mode until th e
first EI ins truction that enab les the IRQ to be read/write. Setting
the Global Interrupt Enable bit in the Interrupt Mask Register
(IMR bit 7) does not enable the IRQ. Execution of an EI
instruction is required.
For polled processing, IRQ must be initialized by an EI instruction. To properly ini-
tialize the IRQ, the following code is provided:
CLR IMR ; make sure vectored interrupts are disabled
EI ; enable IRQ, otherwise it is read only
; not necessary, if interrupts were previously
; enabled
DI ; disable interrupt handling
IMR is cleared before the IRQ enabling sequence to ensure no unexpect ed inter-
rupts occur when EI is executed. This code sequence must be executed before
programming the application requir ed values for IPR and IMR.
I/O Port Control Registers
Each of the four ports (Ports 2, 4, 5, and 6) has an input regi ster, an output regi s-
ter, and an associated buffer and control logic. Because there are separate input
and output registers associated with each port, writing bits defined as inputs
stores t he data in the output register. This data cannot be read as long as the bi ts
are defined as inputs. However, if the bit s are reconfigured as output, the data
stored in the output register is reflected on the output pins and can then be read.
This mechanism allows the user to initialize the outputs before driving their loads.
Note:
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Port Configuration Registers (P456CON and P3M)
The port configuration regi ster (described in Table 24) switches the comparator
inputs from digital to analog and allows Ports 4, 5, and/or 6 to be switched from
push/pull active outputs to open drain outputs. In ZiLOG Test Mode, bit 3 of this
register is used to en able the Address Strobe/Data Strobe. Bit 3 is not a vail able i n
User Mode.
Port 2 output s are configur ed using the P3M Register, shown in Table 25. Bit 0 of
the P3M Register switches Port 2 from push/pull active to open drain outputs. No
other bits in this register are implemented.
Table 24.P456CON Register (Group/Bank 0Fh, Register 0)
Bit 76543 210
Bit/Field Not Used P51_
Mode P52_
Mode Reserved P6_
Output P5_
Output P4_
Output
R/W R/W R/W R/W R/W R/W W W W
Reset 00000 1 11†
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76______ Not Used R/W These bits exist but do not have any
function assigned to them; they are
reserved for future extensions and must
not be used.
__5_____ Comparator 1
Mode R/W 1
0Analog (P50, P51 as Inputs)
Digital inputs
___4____ Comparator 2
Mode R/W 1
0Analog comparator inputs (P52, P53
configured as Inputs)
Digital inputs
____3___ Reserved
_____2__ Port 6 Output
Configuration W1
0Push-Pull Active
Open Drain Outputs
Always reads back 1*
______1_ Port 5 Output
Configuration W1
0Push-Pull Active
Open Drain Outputs
Always reads back 1*
_______0 Port 4 Output
Configuration W1
0Push-Pull Active
Open Drain Outputs
Always reads back 1*†
Note: *Do not use the read-modify-write instructions (for example, OR and AND) with this register.
Bits 0, 1, and 2 always read back 1.
Note: †For Z86L990/L991, P43 can never be configured as push-pull. After any reset, P43 is
configured as tristate high impedance.
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Port 2 Control and Mode Registers (P2 and P2M)
Port 2 is a general-purpose 8-bit, bidirectional I/O port, as shown in Table 26.
Each of the eight Port 2 I/O lines can be independently programmed as either
input or output using the Port 2 Mode Register (see Table 27.)
Table 25.P3M Register [Group/Bank F0h, Register 7 (R247)]
Bit 76543210
Bit/Field Reserved P2_
Output
R/W WWWWWWWW
Reset 11111111
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7654321_ Reserved R
W1
XAlwa ys reads 1111111
No Effect
_________0 Port 2 Output
Configuration W1
0Push-Pull Active
Open Drain Outputs
Table 26.P2 Register [Group/Bank 00h, Register 2 (R2)]
Bit 76543210
Bit/Field Port 2 Data
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset XXXXXXXX
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210 Port 2 Data R/W Data Port 2 Input/Output Register
Table 27.P2M Register [Group/Bank F0h, Register 6 (R246)]
Bit 76543210
Bit/Field P27M P26M P25M P24M P23M P22M P21M P20M
R/W WWWWWWWW
Reset 11111111
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210
(by bit) Port 2 Mode
Select R
W
W
1
1
0
Alwa ys reads 11111111
Input
Output
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A bit set to 1 in the P2M Regist er configures the corresponding bit in Port 2 as an
input, whil e a bit set to 0 configures an output line.
Port 4 Control and Mode Registers (P4 and P4M)
Port 4 is a general-purpose 8-bit, bidirectional I/O port, as shown in Table 28.
Each of the eight Port 4 I/O lines can be independently programmed as either
input or output using the Port 4 Mode Register (see Table 29.)
.
A bit set to 1 in the P4M Regist er configures the corresponding bit in Port 4 as an
input, whil e a bit set to 0 configures an output line.
P43, the contr olled current output pad , cannot be configur ed as
an input. (P43 read = P43 out)
Table 28.P4 Register [Group/Bank 00h, Register 4 (R4)]
Bit 76543210
Bit/Field Port 4 Data
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset XXXXXXXX
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210 Port 4 Data R/W Data Port 4 Input/Output Register
Table 29.P4M Register (Group/Bank 0Fh, Register 2)
Bit 76543210
Bit/Field P47M P46M P45M P44M P43M P42M P41M P40M
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11111111
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7654_210
(by bit) Port 4 Mode
Select R/W 1
0Input
Output
____3___ P43
Mode Select R/W 0
1Output
Tristate High Impedance (available
on Z86L990/L991 only)
Note:
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Port 5 Control and Mode Registers (P5 and P5M)
Port 5 is a general-purpose 8-bit, bidirectional I/O port, as shown in Table 30.
Each of the eight Port 5 I/O lines can be independently programmed as either
input or output using the Port 5 Mode Register (see Table 31.)
A bit set to a 1 in the P5M Register confi gures the corresponding bit in Port 5 as
an input, while a bit set to 0 configures an output line.
Regardless of how P5M bit s 2 and 3 are set, P52 and P53 are
always in input mode.
Table 30.P5 Register [Group/Bank 00h, Register 5 (R5)]
Bit 76543210
Bit/Field Port 5 Data
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset XXXXXXXX
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210 Port 5 Data R/W Data Port 5 Input/Output Register
Table 31.P5M Register (Group/Bank 0Fh, Register 4)
Bit 76543210
Bit/Field P57M P56M P55M P54M P53M P52M P51M P50M
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11111111
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7654__10
(by bit) Port 5 Mode
Select R/W 1
0Input
Output
____32__ P53, P52
Mode Select R/W 1 Input
Regardless of what is written to this
pin, P53 and P52 are always in input
mode.
Note:
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Port 6 Control and Mode Registers (P6 and P6M)
Port 6 is a general-purpose 8-bit, bidirectional I/O port, as shown in Table 32.
Each of the eight Port 6 I/O lines can be independently programmed as either
input or output using the Port 6 Mode Register (see Table 33.)
A bit set to 1 in the P6M Regist er configures the corresponding bit in Port 6 as an
input, whil e a bit set to 0 configures an output line.
Timer Control Registers— General-Purpose Timer (T1)
The Z86D99/Z86L99 family provides one standar d 8 -bi t Z8 counter/timer, T1,
driven by its own 6-bit prescaler, PRE1. T1 is independent of the processor
instruction sequence, relieving software from time-critical operations such as
interval timing or event counti ng. There are three registers that control the opera-
tion of T1 : T1 Dat a Regi ster ( T1) , T1 Mode Re gister (TMR), and T1 Presc ale Reg -
ister (PRE1). Because the timer, prescaler, and mode register are mapped into
the st andard Z8 regi ste r file, t he sof twar e can treat t he counter/ tim er as a general -
purpose register, thus eliminati ng the requirement for special instructions.
Table 32.P6 Register [Group/Bank 00h, Register 6 (R6)]
Bit 76543210
Bit/Field Port 6 Data
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset XXXXXXXX
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210 Port 6 Data R/W Data Port 6 Input/Output Register
Table 33.P6M Register (Group/Bank 0Fh, Register 6)
Bit 76543210
Bit/Field P67M P66M P65M P64M P63M P62M P61M P60M
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11111111
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210
(by bit) Port 6 Mode
Select R/W 1
0Input
Output
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T1 Data Register (T1)
The counter/timer register (T1) c onsists of an 8-bit down coun ter, a write-only reg-
ister that holds the ini tial count value, and a read-only register that hol ds the cur-
rent count value. The initial value of T1 can range from 1 to 255 (0 represents
256) (see Table 34.)
T1 Mode Register (TMR)
Under software control , T1 counter /timer is st arted and stopped using the T1
Mode Register as shown in Table 35.
Table 34.T1 Register [Group/Bank F0h, Register 2 (R242)]
Bit 76543210
Bit/Field T1_Value
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210 T1 Value R
WData
Data Current Value
Initial Value (Range 1 to 256 Decimal)
Table 35.TMR Register [Group/Bank F0h, Register 1 (R241)]
Bit 76543210
Bit/Field TOUT_Mode TIN_Mode T1_
Count T1_
Load Reserved
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000011
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76______ TOUT Mode R/W 11
10
01
00
Internal Clock OUT on P56
T1OUT on P56
Reserved
Not used (P56 con fig ured as I/O )
__54____ TIN Mod e R/W 11
10
01
00
Trigger Input (Retriggerable)
Trigger Input (Not-retriggerable)
Gate Input
External Clock Input (TIN on P52)
____3___ T1 Count R/W 1
0Enable T1 Count
Disable T1 Count
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T1 Prescale Register (PRE1)
The T1 prescaler consists of an 8-bit register and a 6-bit down-counter. The six
most significant bits (D2–D7) of PRE1 hold the prescaler’s count modulo, a value
from 1 to 64 decimal, as shown in Table 36. The prescale register also contains
control bits that specify the cou nting mode and clock source for T1.
Timer Control Registers—T8 and T16 Timers
One of the unique features of the Z86D99/Z86L99 family is a special timer archi-
tecture to automate the generation and reception of complex pul ses or signals.
This timer ar chitecture consi sts of one programmable 8-bit counter timer with two
capture regi sters and two load regis ters and a progr ammable 16-bit counter/ timer
with one 16-bit capture register pair and one 16-bit load regi ster pa ir and their
associated control r egist ers. Thes e cou nter/t imers c an work i ndepende ntly o r c an
be combined together using a number of user-selectable modes governed by the
T8/T16 control regi sters.
_____2__ T1 Load R/W 1
0Load T1
No effect
______10 Reserved R
W1
XAlwa ys reads 11
No effect
Table 36.PRE1 Register [Group/Bank F0h, Register 3 (R243)]
Bit 76543210
Bit/Field Prescaler_Modulo Clock_
Source Count_
Mode
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
765432__ Prescaler Modulo R/W Data Range: 1 to 64 Decimal
_______1_ Clock Source R/W 1
0T1 Internal
T1 External (TIN on P52)
________0 Count Mode R/W 1
0T1 Modulo-n
T1 Single Pass
Table 35.TMR Register [Group/Bank F0h, Register 1 (R241)] (Continued)
Z86D990/Z86D991 OTP and Z86L99X ROM
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T8/T16 Control Regist er A (CTR1)
The T8/T16 Control Register A controls t he functions in common with both the T8
and T16 counter/ timers. The T8 a nd T16 counter/timers have two primary modes of
operation: Transmit Mode and Demodulation Mod e. Transmit Mode is used for
generating complex waveforms. The Transmit Mode has two submodes: Normal
Mode and Ping-Pong Mode. The settings for CTR1 in Transmit Mode are given in
Table 37.
Table 37.CTR1 Register (In Transmit Mode) (Group/Bank 0Dh, Register 1)
Bit 76543210
Bit/Field Mode P43
Out T8/T16_Logic Transmit_
Submode Initial_
T8_Out
Initial_
T16_
Out
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7_______ Mode R/W 1
0Demodulation
Transmit
_6______ P43_Out R/W 1
0P43 configured as T8/T16 Output
P43 configured as I/O
__54____ T8/T16 Logic R/W 11
10
01
00
NAND
NOR
OR
AND
____32__ Transmit_
Submode R/W 11
10
01
00
T16_Out = 1
T16_Out = 0
Ping-Pong Mode
Normal Operation
______1_ Initial_T8_Out R/W 1
0T8_Out set to 1 initially
T8_Out set to 0 initially
_______0 Initial_T16_Out R/W 1
0T16_Out set to 1 initially
T16_Out set to 0 initially
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In Demodulation Mode, the T8 and T16 counter/timers are used to capture and
demodulate complex waveforms. The settings for CTR1 in Demodulation Mode
are given in Table 38.
Table 38.CTR1 Register (in Demodulation Mode) (Group/Bank 0Dh, Register 1)
Bit 76543210
Bit/Field Mode Demod
_Input Edge_Detect Glitch_Filter Rising
Edge Falling
Edge
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7_______ Mode R/W 1
0Demodulation
Transmit
_6______ Demodulator_
Input R/W 1
0P20 as Demodulator Input
P51 as Demodulator Input
__54____ Edge_Detect R/W 11
10
01
00
Reserved
Both Edges
Rising Edge
Falling Edge
____32__ Glitch_Filter R/W 11
10
01
00
16 S CLK Cycles
8 SCLK Cycles
4 SCLK Cycles
No Filter
______1_ Rising_Edge R
R
W
W
1
0
1
0
Rising Edge Detected
No Rising Edge
Reset Flag to 0
No Effect
_______0 Falling_Edge R
R
W
W
1
0
1
0
Falling Edge Detected
No Fallin g Edge
Reset Flag to 0
No Effect
Z86D990/Z86D991 OTP and Z86L99X ROM
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T8/T16 Control Regist er B (CTR3)
The T8/T16 Control Register B, known as CTR3, is a new register to the Z86D99/
Z86L99 family. This register allows the T8 and T16 counters to be synchronized.
The settings of CTR3 are described in Table 39.
Table 39.CTR3 Register (Group/Bank 0Dh, Register 3)
Bit 76543210
Bit/Field T16_
Enable T8_
Enable Sync
Mode Reserved
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 000XXXXX
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7_______ T16 Enable R
R
W
W
1
0
1
0
Counter Enabled
Counter Disabled
Enable Counter
Stop Counter
_6______ T8 Enable R
R
W
W
1
0
1
0
Counter Enabled
Counter Disabled
Enable Counter
Stop Counter
__5_____ Sync Mode R/W 1
0Enable Sync Mode
Diable Sync Mode
___43210 Reserved R
W1
XAlwa ys reads 11111
No Effect
Z86D990/Z86D991 OTP and Z86L99X ROM
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T8 Control Register (CTR0)
As shown in Table 40, the T8 Contr ol Register, known as CTR0, contro ls the oper-
ation of the 8-bit T8 timer.
Table 40.CTR0 Register (Group/Bank 0Dh, Register 0)
Bit 76543210
Bit/Field T8_
Enable
Single/
Mod-
ulo-n Time_
Out T8_Clock
Capture
INT_
Mask
Counter
INT_
Mask P40_
Out
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7_______ T8 Enable R
R
W
W
1
0
1
0
Counter Enabled
Counter Disabled
Enable Counter
Stop Counter
_6______ Single/
Modulo-n R/W 1
0Single Pass
Modulo-n
__5_____ Time_Out R
R
W
W
1
0
1
0
Counter Timeout Occurred
No Counter Timeout
Reset Flag to 0
No Effect
___43___ T8 Clock R/W 11
10
01
00
SCLK/8
SCLK/4
SCLK/2
SCLK
_____2__ Capture Interrupt
Mask R/W 1
0Enable Data Capture Interrupt
Disable Data Capture Interrupt
______1_ Counter Interrupt
Mask R/W 1
0Enable Time_Out Interrupt
Disable Time_Out Interrupt
_______0 P40_Out R/W 1
0P40 configured as T8 Output
P40 configured as I/O
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T8 High Capture Register (HI 8)
The T8 High Capture Register, as described in Table 41, holds the captured data
from the output of the T8 counter /timer. This register is typically used to hold the
number of count s when the input signal is high (or 1).
T8 Low Capture Register (LO8)
The T8 Low Capture Register, as described in Table 42, holds the captured data
from the output of the T8 counter /timer. This register is typically used to hold the
number of count s when the input signal is low (or 0).
Table 41.HI8 Register (Group/Bank 0Dh, Register B)
Bit 76543210
Bit/Field T8_Capture_HI
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210 T8 Capture
High Value R
WData Captured Data
No Effect
Table 42.LO8 Register (Group/Bank 0Dh, Register A)
Bit 76543210
Bit/Field T8_Capture_LO
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210 T8 Capture
Low Value R
WData Captured Data
No Effect
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T8 High Load Register (TC8H)
The T8 High Load Register, as described in Table 43, is loaded with the co unter
value necessary to keep the T8_Out signal in the high state for the required time.
T8 Low Load Register (TC8L)
The T8 Low Load Register, as described in Table 44, is loaded with the counter
value necessary to keep the T8_Out signal in the lo w state for the required time.
Table 43.TC8H Register (Group/Bank 0Dh, Register 5)
Bit 76543210
Bit/Field T8_Level_HI
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210 T8 Level
High Value R/W Data Duration that T8_Out remains High
Table 44.TC8L Register (Group/Bank 0Dh, Register 4)
Bit 76543210
Bit/Field T8_Level_LO
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210 T8 Level
Low Value R/W Data Duration that T8_Out remains Low
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T16 Control Register (CTR2)
The T16 Control Register, known as CTR2, controls the operation of the 16-b it T16
timer (see Table 45).
Table 45.CTR2 Register (Group/Bank 0Dh, Register 2)
Bit 76543210
Bit/Field T16_
Enable
Single/
Mod-
ulo-n Time_
Out T16_Clock
Capture
INT_
Mask
Counter
INT_
Mask P41_
Out
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7_______ T16 Enable R
R
W
W
1
0
1
0
Counter Enabled
Counter Disabled
Enable Counter
Stop Counter
_6______ Single/
Modulo-n R/W 1
0
1
0
In Tran sm it Mod e:
Single Pass
Modulo-n
In Demodulati on Mod e:
T16 Does Not Recognize Edge
T16 Recognizes Edge
__5_____ Time_Out R
R
W
W
1
0
1
0
Counter Timeout Occurred
No Counter Timeout
Reset Flag to 0
No Effect
___43___ T16 Clock R/W 11
10
01
00
SCLK/8
SCLK/4
SCLK/2
SCLK
_____2__ Capture Interrupt
Mask R/W 1
0Enable Data Capture Interrupt
Disable Data Capture Interrupt
______1_ Counter Interrupt
Mask R/W 1
0Enable Time_Out Interrupt
Disable Time_Out Interrupt
_______0 P41_Out R/W 1
0P41 configured as T16 Ou tput
P41 configured as I/O
Z86D990/Z86D991 OTP and Z86L99X ROM
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T16 MS-Byte Capture Register (HI16)
The T16 MS-Byte Capture Register, as described in Table 46, holds the captured
data from the output of the T16 counter/ti mer. This register hol ds the most signifi-
cant byte of the data.
T16 LS-Byte Capture Registe r (LO16)
The T16 LS-Byte Capture Register, as described in Table 47, holds the captured
data from the output of the T16 counter/ti mer. This register holds the least signifi-
cant byte of the data.
Table 46.HI16 Register (Group/Bank 0Dh, Register 9)
Bit 76543210
Bit/Field T16_Capture_HI
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210 T16 Capture HI R
WData MS-Byte of Captured Data
No Effect
Table 47.LO16 Register (Group/Bank 0Dh, Register 8)
Bit 76543210
Bit/Field T16_Capture_LO
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210 T16 Capture LO R
WData LS-Byte of Captured Data
No Effect
Z86D990/Z86D991 OTP and Z86L99X ROM
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T16 MS-Byte Load Register (TC16H)
The T16 MS-Byte Load Register, as described in Table 48, is loaded wit h the most
significant byte of the T16 counter value.
T16 LS-Byte Load Register (TC16L)
The T16 LS-Byte Load Regi ster, as describe d in Table 49, is load ed with t he least
significant byte of the T16 counter value.
S top- Mode Recov ery Control Registers
The Z86D99/Z86L99 family of products all ows 16 indi vidual I/O pins (Ports 2 and
5) to be used as a stop-mode recovery sources. The STOP mode is exited when
one of these SMR sources is toggled.
Table 48.TC16H Register (Group/Bank 0Dh, Register 7)
Bit 76543210
Bit/Field T16_Data_HI
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210 T16 Data HI R/W Data MS-Byte of the T16 Counter
Table 49.TC16L Register (Group/Bank 0Dh, Register 6)
Bit 76543210
Bit/Field T16_Data_LO
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210 T16 Data LO R/W Data LS-Byte of the T16 Counter
Z86D990/Z86D991 OTP and Z86L99X ROM
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Stop-Mode Recovery Register
The SMR register serve s two funct ions. Bit D7 of the SMR register, as shown in
Table 50, is the Stop Mode Flag that is set upon enteri ng stop mode. A 0 in this bi t
indicates t hat the device has been rese t by a POR or WDT Reset. A POR or WDT
Reset is sometimes referred to as a “cold” start. A 1 in bit D7 indi cates that the
device was awakened by a SMR source. Waking a device with a SMR source is
sometimes referred to as a “warm” start.
The Stop Mode Recovery source can be selected by any combination of P2 and
P5 by P2SMR and P5SMR, respecti vely. If the pi n is selected as t he SMR source,
it s logic level i s latched int o a register. A wait up si gnal is generated if it s logic level
changes. This applies to all selected pins for the SMR source.
The comparators of P5 cannot be used as an SMR source. The comparator i s
turned off in STOP mode.
The second functi on of the SMR regist er is the selectio n of the external clock
divide value. The purpose of this cont rol is to selectively reduce device power
Table 50.SMR Register (Group/Bank 0Fh, Register B)
Bit 76543210
Bit/Field Stop
Flag Re-
served Stop
Delay Reserved SCLK Select
R/W R R/W W R/W R/W R/W W W
Reset 00100000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7_______ Stop Mode Flag R
R
W
1
0
X
Stop Recovery (warm start)
POR/WDT Reset (cold start)
No Effect
_6______ Reserved R
W1
XAlwa ys reads 1
No Effect
__5_____ Stop Delay R
W
W
1
1
0
Alwa ys reads 1
Enable 5ms /Reset delay
Disable /Reset delay after SMR
___432__ Reserved R
W1
XAlwa ys reads 111
No Effect
_______10 System Clock
Select R
W
W
W
W
11
11
10
01
00
Alwa ys reads 11
SCLK, TCLK = XTAL/16
SCLK, TCLK = XTAL
SCLK, TCLK = XTAL/32
SCLK, TCLK = XTAL/2
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
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consumption duri ng normal processor execution (SCLK control) and/or HALT
mode (where TCLK sources counter/timers and interrupt logic).
Port 2 Stop Mode Recovery (P2SMR)
The P2SMR register, as described in Table 51, defines which I/ O li nes in Port 2
are to be used as stop mode recovery sources.
Port 5 Stop-Mode Recovery (P5SMR)
The P5SMR register, as described in Table 52, defines which I/ O li nes in Port 5
are to be used as st op-mode recovery sources.
Table 51.P2SMR Register (Group/Bank 0Fh, Register 1)
Bit 76543210
Bit/Field P27RS P26RS P25RS P24RS P23RS P22RS P21RS P20RS
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210
(by bit) Port 2 Stop Mode
Recovery R/W 1
0Recovery Source
Not
Table 52.P5SMR Register (Group/Bank 0Fh, Register 5)
Bit 76543210
Bit/Field P57RS P56RS P55RS P54RS P53RS P52RS P51RS P50RS
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field R/W Value Description
76543210
(by bit) Port 5 Stop Mode
Recovery R/W 1
0Recovery Source
Not
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
PS003807-1002 P R E L I M I N A R Y
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Electrical Characte ristics
This secti on covers the absolute maxi mu m ratings, standard test conditi ons, DC
characteri stics, and AC characteristics.
Absolute Maximum Ratings
Table 53 lists the absolut e max imum rat ings.
Stresses greater than those listed in the precedi ng table can cause permanent
damage to the device. This rating is a stress rating only. Functional operati on of
the device at any condi tion above those indicat ed in the operational sections of
these specif ications is not implied. Exposure to absol ute maximum rating condi-
tions for an extended period can aff e ct device reliability.
Standard Test Conditions
The characteri stics listed below apply for standard test conditi ons as noted. All
voltages are referenced to GND. Positive current flows into the referenced pin
(see Figure 36).
Table 53.Absolute Maximum Ratings
Symbol Description Min Max Units
VMAX Supply Voltage (*) –0.3 +7.0 V
TSTG Storage Temp. –65°+150°C
TAOper. Ambient Temp. † C
VRAM Minimum RAM Voltage 1.0 V**
Note:
*Voltage on all pins with respect to GND.
†See “Ordering Information” on page 95.
** Estimated value, not tested.
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
PS003807-1002 P R E L I M I N A R Y
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Figure 36. Test Load Diagram
DC Characteristics
Table 54 lists the DC characteristics f or the Z86D99X (OTP only). Table 55 lists
the DC characteristics for the Z86L99X (mask only).
From Output
Under Test
I150pF
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
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Table 54.DC Characteristics for the Z86D99X (OTP Only)
Symbol Parameter VDD Min Max Units Comments
VDD Power Supply Voltage 3 5.5
VCH Clock Input High Voltage 3.0 V
5.5 V 0.8Vdd
0.8Vdd Vdd+0.3
Vdd+0.3 V
VDriven by Ext. clock
generator
VCL Clock Input Low Voltage 3.0 V
5.5 V Vss–0.3
Vss–0.3 0.2Vdd
0.2Vdd Driven by Ext. clock
generator
VIH Input High Voltage 3.0 V
5.5 V 0.7Vdd
0.7Vdd Vdd+0.3
Vdd+0.3 V
V
VIL Input Low Voltage 3.0 V
5.5 V Vss–0.3
Vss–0.3 0.2Vdd
0.2Vdd V
V
VOH1 Output High Voltage
Regular I/O 3.0 V
5.5 V VDD–0.8
VDD–0.8 V
V–1.2 mA
VOH2 High Drive Pins (P54, P55, P56,
P57) 3.0 V
5.5 V VDD–0.8
VDD–0.8 V
V–5.0 mA
VOL1 Regular I/O
Output low voltage 3.0 V
5.5 V 0.4
0.8 V
V2 mA
4.0 mA
VOL2 High Drive Pins (P54, P55, P56,
P57) 3.0 V
5.5 V 0.4
0.8 V
V4 mA
7.0 mA
ICCO Controlled Current Output (P43) 3.0 V
5.5 V 70
70 120
120 mA
mA Vout = 1.2 V to VDD
(see Figure 17)
IIL Input Leakage 3.0 V
5.5 V –1
–1 1 µA
1 µAµA
µAVin=0 V, Vdd
Vin=0 V, Vdd
ICC Supply Current 3.0 V
5.5 V
3.0 V
5.5 V
10
15
250
850
mA
mA
µA
µA
at 8 M Hz
at 8 M Hz
at 32 KHz
at 32 KHz
ADC is off.
ICC1 Standby Current (Halt Mode) 3.0 V
5.5 V
3.0 V
5.5 V
3
5
2
4
mA
mA
mA
mA
Vin=0 V, Vdd
at 8 M Hz
Clock divided by 16
XTAL running
ADC is off.
ICC2 Sta ndb y Curren t (ST OP Mode) 3.0 V
5.5 V 20
30 µA
µAVin=0 V, Vdd; ADC is off.
P43=1 or high impedance
WDT, Comparators, Low
V oltage Detection, and ADC (if
applicable) are disabled. The
IC might draw more current if
any of the above peripherals is
enabled.
IADC Current with A/D Running 3.0 V
5.5 V 500
900 µA
µA
VLV Vdd Low-Voltage Protection 2.90 V Low voltage protection
is also known as
brownout.
Typical is 2.6 V.
VLB Low-Battery Detection VLV+
0.5 V
V
Z86D990/Z86D991 OTP and Z86L99X ROM
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Table 55.DC Characteristics for the Z86L99X (Mask Only)
Symbol Parameter VDD Min Max Units Comments
VDD Power Supply Vo ltage 2.3 5.5
VCH Clock Input High Voltage 2.3 V
5.5 V 0.8Vdd
0.8Vdd Vdd+0.3
Vdd+0.3 V
VDriven by Ext. clock generator
VCL Clock Input Low Voltage 2.3 V
5.5 V Vss–0.3
Vss–0.3 0.2Vdd
0.2Vdd Driven by Ext. clock generator
VIH Input High Voltage 2.3 V
5.5 V 0.7Vdd
0.7Vdd Vdd+0.3
Vdd+0.3 V
V
VIL Input Low Voltage 2.3 V
5.5 V Vss–0.3
Vss–0.3 0.2Vdd
0.2Vdd V
V
VOH1 Output High Voltage
Regular I/O 2.3 V
5.5 V 2.0
5.0 V
V–0.5 mA
2.3 V
5.5 V 1.9
5.0 V
V–1.2 mA
VOH2 High Drive Pins (P54, P55, P56, P57) 2.3 V
5.5 V 1.9
5.1 V
V–3 mA
2.3 V
5.5 V 1.7
4.7 V
V–5 mA
VOL1 Regular I/O
Output low voltage 2.3 V
5.5 V 0.4 V
0.4 V V
V2 mA
2.3 V
5.5 V 0.8 V
0.8 V V
V4 mA
VOL2 High Drive Pins (P54, P55, P56, P57) 2.3 V
5.5 V 0.4 V
0.4 V V
V4 mA
2.3 V
5.5 V 0.8 V
0.8 V V
V7 mA
ICCO Controlled Current Output (P43) 2.3 V
5.5 V 70
70 120
120 mA
mA Vout = 1.2 V to VDD at room
temperature (see Figure 17)
IIL Input Leakage 2.3 V
5.5 V –1
–1 1 µA
1 µAµA
µAVin=0 V, Vdd
Vin=0 V, Vdd
ICC Supply Current 2.3 V
5.5 V
2.3 V
5.5 V
3
8
250
850
mA
mA
µA
µA
at 8 MHz
at 8 MHz
at 32 KHz
at 32 KHz
ADC is off.
ICC1 Standby Current (Halt Mode) 2.3 V
5.5 V 2
5mA
mA Vin=0 V, Vdd
at 8 MHz
ICC2 Standby Current (STOP Mode) 2.3 V
5.5 V 8
25.0 µA
µAVin=0 V, Vdd;ADC is off.
WDT, Comparators, Low Voltage Detection,
and ADC (if applicable) are disabled. The IC
might draw more current if any of the above
peripherals is enabled.
ICC2 Standby Current (STOP Mode) 5.5 V 15 µAat 30 °C
ILV Standby Current (Low Voltage) 20 µAMeasured at VDD=VLV–0.2 V.
IADC Current with A/D Running 2.3 V
5.5 V 500
900 µA
µA
VLV Vdd Low-Voltage Protection 2.2 V Low voltage protection is also known as
brownout.
Typical is around 1.7 V at room temperature.
VLB Low-Battery Detection 3.0 V Typical is around 2.4 V at room temperature.
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
PS003807-1002 P R E L I M I N A R Y
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Analog-to-Digital Converter Characteristics
Table 56 lists the analog- to-digital conver ter character istics.
The ADC input is a switching capacitor that charges up to the applied input volt-
age whenever i t is configured as an ADC input. If you swi tch it fr om digital mode to
Table 56.Analog-to-Digital Converter Characteristics
Parameter Minimum Typical Maximum Units
Resolution 8bits
Integral Nonlinearity 0.5 1 LSB
Differential Nonlinearity 0.5 1 LSB
Zero Error at 25 °C7.8mV
Supply Voltage Range (OTP) 3.0 5.5 V
Supply Voltage Range (ROM) 2.3 5.5 V
Power Dissipation (No Load) 1.2 mW
Clock Frequency (f ADC) 4 MHz
Input Voltage Range VRef– VRef+ V
Step Respon se 2/(0. 0 02 1 X f AD C) s
ADC Input Capacitance 25 40 pF
Vref Input Capacitance 25 40 pF
VRef+ Range VRef–+2.0 AVDD V
VRef– Range AGND VRef+–2.0 V
(VRef+)–(VRef–)2.0 AV
DD V
Temperature Range 0 70 °C
3-db Frequency (0.0021 X f ADC) Hz
Signal to Noise 47 db
ADC Output Code Dout
Vref Input Source Impedance 1.0 kOhms
ADC Input Source Impedance 1.0 kOhms
Notes: Dout= [(Vin–VRef–)/(VRef+–VRef–)] X 256
f ADC = set in ADCCTRL configuration register
Step Response is the time to track the input if a step from VRef– to VRef+ is applied.
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
PS003807-1002 P R E L I M I N A R Y
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the ADC input mode, the switching capacitor starts to charge up from 0 V. For the
maximum swing (Dout = 0 to FF), it takes 2/(0.0021x f ADC). For an 8-MHz MCU
crystal (with clock divide-by-two mode), the inter nal system clock is 4 MHz. In
ADCCTRL, if you select the ADC frequency = system clock divided by 1 option,
f ADC = 4 MHz. The step response = 238 uS.
AC Characteristics
Table 57 lists the AC chara cteristics.
Table 57.AC Characteristics
No. Symbol Parameter VDD Min Max Units
1 TpC Input Clock Period 2.3 V
5.5 V 120
120 DC
DC ns
2 TrC, TfC Clock Input Rise and Fall Times 2.3 V
5.5 V 25 ns
25 ns
3 TwC Input Clock Width 2.3 V
5.5 V 5.0
5.0 ns
ns
4 TwTinL Timer Input Low Width 2.3 V
5.5 V 2TPC
2TPC ns
5 TwTinH Timer Input High Width 2.3 V
5.5 V 2
2TpC
TpC
6 TpT1in Timer 1 Input Period 2.3 V
5.5 V 8
8TpC
TpC
7 TrTin, TfTin Timer Input Rise and Fall Time 2.3 V
5.5 V 100
100 ns
ns
8 TwIL Interrupt Request Low Time 2.3 V
5.5 V 100
70 ns
ns
9 TwIH Interrupt Request Input High Time 2.3 V
5.5 V 5
5TpC
TpC
10 Twsm Stop-Mode Recovery Width S pec 2.3 V
5.5 V 12
12 ns
ns
12 Twdt Watch-Dog T imer Time Out 2.3 V
5.5 V 25
10 ms
ms
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
PS003807-1002 P R E L I M I N A R Y
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Packaging
Figure 37 through Figure 40 show the available package s.
Figure 37. 48-Pin SSOP
CONTROLLING DIMENSIONS : MM
LEADS ARE COPLANAR WITHIN .004 INCH
D
E H
A1
A2 A
e
SEATING PLANE
b
48 25
c
Detail A
Detail A
0-8˚
L
1 24
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
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Figure 38. 40-Pin PDIP
Figure 39. 28-Pin PDIP
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
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Figure 40. 28-Pin SOIC
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
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Design Considerations
The Z8 uses a Pierce oscillator with an internal feedback circu it. The advantages
of this circui t are low cos t, large out put signal , low-po wer level i n the cry stal, st abil-
ity wit h res p e c t to V CC and temperature, and low impedances (not disturbed by
stray effects.)
One drawback is the requirement for high gain in the amplifier to compensate for
feedback path losses. Traces connecting crystal, capacitors, and the Z8 oscillator
pins must be as short and wide as possible. Short and wide traces reduce para-
sitic inductance and resistance. The components (capacitors, crystal, and resis-
tors) m ust be placed as close as possible to the oscillator pins of the Z8.
The traces from the oscillator pins of the integrated circuit (IC) and the ground
side of the l ead cap aci to rs must be guar ded from all ot her trac es (c lock, VCC, and
syste m grou nd) to reduce cross-talk and noise injection . Guarding the traces is
usually accompl ished by keeping other traces and syst em ground trace planes
away from the oscil lator circuit and by placi ng a Z8 device VSS ground ring around
the traces/components. The ground side of the oscillator lead capacitors must be
connected to a single trace to the Z8 VSS (GND) pin. It must not be shared with
any other system ground trace or components except at the Z8 device VSS pin.
Not sharing the gr ound side of the oscillator l ead ca pacitors is to prevent differen-
tial system ground noise injection into the oscillator.
Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
PS003807-1002 P R E L I M I N A R Y
95
Ordering Information
For fast results, contact your local ZiLOG sale offices for assistance in ordering
part(s). Updated information can be found on the ZiLOG website:
HTTP://WWW.ZILOG.COM
Precharacterization Product
The product represented by this document i s newly introduced and ZiLOG has not
completed the ful l characterization of the product. The document states what
ZiLOG knows about this product at this time, but additional features or nonconfor-
mance with some aspects of the document might be found, ei ther by ZiLOG or its
customers in the course of further appl ication and charact e rization work. In addi-
tion, ZiL OG cautions that del ivery might be uncertain at t imes, due to star t-up yield
issues.
ZiLOG, Inc.
532 Race Street
San Jose, CA 95126-3432
Telephone: (408) 558-8500
FAX: 408 558-8300
Internet: HTTP://WWW.ZILOG.COM
Part PSI Description
Z86D99 (OTP) Z86D990PZ008SC
Z86D990HZ008SC
Z86D991PZ008SC
Z86D991SZ008SC
40-pin PDIP
48-pin SSOP
28-pin PDIP
28-pin SOIC
Z86L99 (Mask ROM) Z86L990PZ008SC
Z86L990HZ008SC
Z86L991PZ008SC
Z86L991SZ008SC
Z86L996PZ008SC
Z86L996SZ008SC
Z86L997PZ008SC
Z86L997SZ008SC
40-pin PDIP
48-pin SSOP
28-pin PDIP
28-pin SOIC
28-pin PDIP
28-pin SOIC
28-pin PDIP
28-pin SOIC
Emulator Z86L9900100ZEM Emulator/Programmer
Adapter Z8 6D99 001 00Z DH 48 SSOP Adap ter
Evaluation Board Z86L9900100ZCO Evaluation Board
