19-1349; Rev ta; 10/98 MA AALIV 1-Cell, Step-Up Two-Way Pager System IC General Description Features The MAX847 is a complete power-supply and monitor- ing system for two-way pagers or other low-power digi- tal communications devices. It requires few external compcnents. Included on-chip are: * A 1-cell input, 80mA output, synchronous-rectified boost DC-DC regulator with a digitally controlled +1.8V to +4.9V output + Three low-noise linear-regulator outputs * Three DAC-controlled comparators for software- * SPI-compatible serial interface Reset and low-battery (LBO) warning outputs # 80mA Output from 1 Cell at 90% Efficiency + 13pA Idle Mode (coast) Current + Selectable Low-Noise PWM or Low-Current Operation PWM Operating Frequency Synchronized to Seven Times an External Clock Source # Operates at 270kHz with No External Clock driven 3-channel A/D conversion + Automatic Backup-Battery Switchover Ordering Information * Gharger for NiCd, NiMH, lithium battery, or storage capacitor for RF PA power or system backup * Two 1.8 (typical) serial-controlled open-drain PART TEMP.RANGE _PIN-PACKAGE MAX847 EE 40C to+85C 28 QSOP Applications MOSFET switches An evaluation kit for the MAX847 (MAX847EVKIT) is available to aid in design and prototyping. Pin Configuration appears ai end of daia sheet. Two-Way Pagers GPS Receivers 1-Cell Powered Hand-Held Equipment Typical Operating Circuit INPUT SINGLE AA | + ALKALINE BATTERY O8V 101.8V Tt BATT LOW BATTERY pe LB xt INOUT _ LB0 OUT tr * FESET FIN IwouT | J R80 PGND t _1 cs REG2IN + = SERAL me MAXL/VI vo m 501 MAX847 __ SD0 OFS _ I 180) ig_ OR = QUTPUT2 DAIVERS DROIN REG2 > 9 85 ANALOG L DREND <= OUTPUT 1 = REG a 3V LOGIC FUN = __ ~L coast RUN = OUTPUT 3 Fes -- AD INPUT __J co = TV RECEVER JLLTL = _ OPTIONAL SYNC py RF oAgnp NICD Tf TOFFPA A* NiCd BATTERY STACK a oR STORAGE CAPACITOR idie Mode is a trademark of Maxim Integrated Products. SPI is a trademark of Motorola, Inc. MAXIMA Maxim Iniegrated Producis 1 For free samples & the latest literature: hitp://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. LVEXVWNMAX847 1-Cell, Step-Up Two-Way Pager System IC ABSOLUTE MAXIMUM RATINGS BATT, OUT, NICD, LBO, RSO to AGND...... ec. -0.3V to +6V REG1, OFS, REG2, REF, R2IN to AGND...-0.3V to (OUT + 0.3) SCL, SDO, SDI, CS, SYNC, FILT, DR2IN, CHO, LBI, RSIN, RUN to AGND. ow. -0.3V to (REG + 0.3V) REGS oe ee eee ene eneete ..-0.3V to (REG2 + 0.3V) DR1, DR2 to DRGND ..... ee -0.3V to (BATT + 0.3V) PGND, DRGND to AGND....... ees -0.3V to +0.3V LX1 to PGND 00... ce certs eeeeenentneenees -0.3V to (OUT + 0.3V) Continuous Power Dissipation (Ta = +70C} 28-Pin QSOP (derate 8mW/C above +70C) 00.00... 640mW Operating Temperature Range .......... ee Junction Temperature... ee Storage Temperature Range ........... cece Lead Temperature (soldering, 10sec) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections oi the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (OUT = 3.0V, BATT = 1.2V, NICD = 3.6V, Ta = -40C to +85C, unless otherwise noted. Typical values are at Ta = +25C.) (Note 1) PARAMETER | CONDITIONS MIN TYP MAX | UNITS GENERAL PERFORMANCE BATT Typical Operating Range OUT x (Note 2) Run or Coast Mode 0.8 08 Vv BATT Minimum Start-Up Voltage _ (Note 3) Ta = +25C 0.9 1.1 V Goast Mode Supply Current (Note 4) | REG2, REG3 and CH DAC off, VouT = 2.8V 13 25 HA Run Mode Supply Current (Note 4) REG2, REG3 and CH DAC on 875 1350 HA BATT Supply Current (Note 5) Coast mode 0.5 2 HA NICD Input Current, Standby Charger and Backup Modes off, NICD = 3.6V 1.2 3 WA (Note 6) NICD Input Supply Current, Backup | -kup mode, NICD = 3.6V, OUT= 3V 20 40 yA (Note 7) NIGD Input Gurrent, Power Fail Gharger and Backup Modes off, 12 3 yA (Note 8) BATT = OV and OUT = OV REG2 Supply Current (Note 4) Incremental supply current when on 50 HA REG3 Supply Current (Note 4) Incremental supply current when on 20 HA GH DAG Supply Current (Note 4) Incremental supply current when on 30 HA Reference Voltage IREF= Oto 20nA, OUT = 1.8V to 4.9V -1.5% 1.28 1.5% Vv . Ta= +25 1.8 2.8 - = a DRi, DR2 On-Resistance IpR = 120mA Ta= 40C to 4856 36 DR1, DR2 Leakage Current Vpr= 5V 1 250 nA SDO Output Low Ispo = 100HA 200 mv SDO Output High Isp = -100pA, from REG1 Vae V Logic Input Level Low Includes CS, SDI, SCL, DR2IN, SYNC, and RUN 0.4 V Logic Input Level High Includes CS, SDI, SCL, DR2IN, SYNC, and RUN VREG Vv . Logic Input = 0 to 3.3V; includes CS, SDI, SCL, _ Logic Input Current DRPIN, SYNC, and RUN 1 1 HA SERIAL-INTERFACE TIMING SPECIFICATIONS (Note 9} SCL Maximum Clock Rate 50% duty cycle 5 MHz SDI Setup Time, tos 100 ns SDI Hold Time, toy 50 ns MAAXILAAELECTRICAL CHARACTERISTICS (continued) (OUT = 3.0V, BATT = 1.2V, NICD = 3.6V, Ta = -40C to +85C, unless otherwise noted. Typical values are at Ta = +25C.) (Note 1) 1-Cell, Step-Up Two-Way Pager System IC PARAMETER CONDITIONS MIN TYP MAX | UNITS SCL to SDO Output Valid, tbo 70 ns CS to SDO Output Valid, tov 70 ns CS to SDO Disable, tra 70 ns CS to SCL Setup Time, tess 50 ns CS to SCL Hold Time, tesH 50 ns CS Pulse Width High, tosw 100 ns rte Width High or Low, 50 ns Dc-DC CONVERTER (Note 1 on Run Mode Circuit of Figure 2, OUT = 3.0V, BATT = 1.4V B80 115 mA (Note 1 ail GoastMode | Gircuit of Figure 2, OUT = 3.0V, BATT = 1.0V 15 40 mA (Note 11), Coast Mode Coast Mode, OUT = 1.8V to 4.9V -3.5 3.5 % (Note 12), Run Mode Run Mode, OUT = 1.8V to 4.9V -35 3.5 % CUTDAG Sep See | Coaster ir Made 270 | mv OUT Load Regulation IOUT = 1mA to 8OMA, Run Mode 25 mv OUT Line Regulation BATT = 0.8V to 1.5V 25 mV Maximum LX1 Duty Cycle OUT = 3.0V 76 83 % OUT Voltage Ripple louT = 80mA, CouT = 47LF with ESR < 0.250 70 mVp-p LX1 Switch Gurrent Limit During the inductor charge cycle 480 600 720 mA LX1 On-Resistance LX NMOS 0.48 08 2 PMOS 0.65 1.3 PHASE-LOCKED LOOP (PLL) Frequency, Free-Run Ta = +25C, FILT connected to REF 210 270 325 kHz Frequency, Locked faync = 38.4kHz 268.8 kHz Jitter (Note 14) fsync = 38.4kHz, FILT network = 1nF|| (22nF + 10kQ) +15 kHz Capture Time (Note 14) fsync = 38.4kHz, FILT network = 1nF || (22nF + 10k&) 1 25 ms NICD CHARGER Current High 0.2V < (QUT - NICD) 2V, 15mA_CHG = 1 ? 25 mA Current Low 0.2V < (OUT - NICD) < 2V, 1mA_CHG = 1 0.45 15 mA OUT Error, Backup Regulator OUT = 2.8V, louT= 20mA, NICD = 3.3V -3.5 3.5 % On Resistance (Note 15) Backup Mode, NICD = 3.3V 5 10 2 MA AXIMA LVEXVWN1-Cell, Step-Up Two-Way Pager System IC ELECTRICAL CHARACTERISTICS (continued) (OUT = 3.0V, BATT = 1.2V, NICD = 3.6V, Ta = -40C to +85C, unless otherwise noted. Typical values are at Ta = +25C.) (Note 1) MAX847 PARAMETER | CONDITIONS MIN TYP MAX | UNITS LINEAR REGULATORS REG1 PMOS On-Resistance QUT = 3.0V, IREa1 = 65mA 1.5 3.1 Q REG Supply Rejection (Note 15) | f = 268.8kHz, CRea1 = 10,F ceramic 15 25 dB REG1 Clamp Voltage lour=1mA, OUT=49v [A= +28 3288 34 Vv Ta = -40C to +85C 3.15 3.45 REG2 Voltage Drop IREG2 = 0 to 24mA, OUT = 3.0V, Rors= 15k 120 155 190 mV REG2 Load Regulation IREG2 = 0.1mA to 24mA 9 mV REG2 Supply Rejection f = 268.8kHz, CRea1 = 10uF, ceramic, 30 40 dB {Note 15) Rors = 15k, Cors = 0.1pF, IREg2 = 15mA REG3 Output Voltage IREG? = Oto 2mA 0.96 1.0 1.04 Vv REG3 Supply Rejection (Note 15) | f = 268.8kHz, Greqi = 1pHF ceramic 40 50 dB DATA-ACQUISITION AND VOLTAGE MONITORS LBI/RSIN Input Threshold Falling input 0.58 0.60 0.63 Vv (Note 15) Input Hysteresis 75 16 30 mY LBI/RSIN Input Gurrent -50 -3 50 nA LBO/RSO Output Low louT= 1mA 30 400 mV LBO/RSO Output Leakage Qutput = 5.5V 1 250 nA (Note 18) Response Time 10mV overdrive 15 50 Ls GHO Threshold Range (Note 15) 0.2 1.27 Vv GH1 Threshold Range (Note 15) | Measures NICD 1.2 5.08 Vv GH2 Threshold Range (Note 15) | Measures BATT 0.2 1.27 Vv CHO Threshold Resolution 10 mV {Note 15) Note 13) Resolution Measures NICD 40 mV Note 18) Resolution Measures BATT 10 mY CHO Error At thresholds of 200mV, 800mV, and 1270mV -2.0 2.0 % -15mV +15mV GH1 Error At thresholds of 1200mV, 3200mV, and 5080mV 3.0 3.0 % ; , -6OmvV +60mV CH2 Error At thresholds of 200mV, 800mV, and 1270mV 2.0 2.0 % -15mV +15mV CHO Input Hysteresis (Note 15) 1 2 4 mv GH1 Input Hysteresis (Note 15) 4 & 16 mV 4 MAAXIAA1-Cell, Step-Up Two-Way Pager System IC ELECTRICAL CHARACTERISTICS (continued) (OUT = 3.0V, BATT = 1.2V, NICD = 3.6V, Ta = -40C to +85C, unless otherwise noted. Typical values are at Ta = +25C.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX | UNITS CH2 Input Hysteresis (Note 15) 1 2 4 mv CHO Input Current CHO = 0.2V to 1.27V -100 100 nA GH Comparator Response Time . (Note 15) 10mV overdrive 0.6 1.0 Ls Note 1: Specifications to -40C are guaranteed by design, not production tested. Note 2: This is not a tested parameter, since the IC is powered from OUT, not BATT. The only limitation in the BATT range is the inability to generate more than 5 times, or less than 1.15 times the BATT voltage at OUT. This is due to PWM controller duty-cycle limitations in Run Mode. Note 3: Minimum start-up voltage is tested by determining when the LX pins can draw at least 50mA for 1 ps (min) at a 50kHz (min) repetition rate. This guarantees that the IC will deliver at least 200UA at the OUT pin. Note 4: This supply current is drawn from the OUT pin. Current drain from the battery depends on voltages at BATT and OUT and onthe DC-to-DC converters efficiency. Note 5: Gurrent into BATT pin in addition to the supply current at OUT. This current is roughly constant from Goast to Run Mode. Note 6: Current into NICD pin when NICD isnt being charged and isnt regulating OUT. Note 7: Current inte NICD pin when NICD is regulating OUT. Doesn't include current drawn from OUT by the rest of the circuit. Measured by setting the OUT regulation point to 2.8V and holding OUT at 3.0V. Note 8: Current into NICD pin when BATT and OUT are both at OV. This test guarantees that NICD won't draw significant current when the main battery is removed and backup is not activated. Note 9: Serial-interface timing specifications are not tested and are provided for design guidance only. Serial-interface functionali- ty is tested by clocking data in at 5MHz with a 50% duty-cycle clock and checking for proper operation. With OUT set below 2.5V, the serial-interface clock frequency should be reduced to 1MHz to ensure proper operation. Note 10: This specification is not directly tested but is guaranteed by correlation to LX on-resistance and current-limit tests. Note 11: Measured by using the internal feedback network and Coast-Mode error comparator to regulate OUT. Doesn't include ripple voltage due to inductor currents. Note 12: Measured by using the internal feedback network and Run-Mode error comparator to regulate QUT. Doesnt include ripple voltage due to inductor currents. Note 13: Uses the OUT measurement techniques described for the OUT Error, Coast Mode, and OUT Error Run Mode specifications. Note 14: PLL acquisition characteristics depend on the impedance at the FILT pin. The specification is not tested and is provided for design guidance only. Note 15: The limits in this specification are not guaranteed and are provided for design guidance only. Typical Operating Characteristics (Circuit of Figure 2, Ta = +25, unless otherwise noted.) EFFICIENCY vs. LOAD CURRENT EFFICIENCY vs. LOAD CURRENT EFFICIENCY vs. LOAD CURRENT (RUN MODE, Vout = 3.0) (COAST MQDE, Vout = 3.0) (COAST MODE, Vour = 2.4V) 100 5 100 ~ 100 2 An 3 =20 Vin= 1M Z Vin= 15 Z 90 (ot 3 90 z 30 z Ar LN ] = w acon = 80 3S 80 = 2 IN=0, F ~ > a 7 4 th 7 & 7 2 fy G 2 mw iw th yj th io a ey 80 80 if a by 50 50 40 40 40 1 10 100 1900 o 1 10 100 1000 o 1 10 100 1000 LOAD CURRENT (mA) LOAD CURRENT (mA) LOAD CURRENT (maj MA AXIMA 5 LVEXVWNMAX847 1-Cell, Step-Up Two-Way Pager System IC Typical Operating Characteristics (continued) (Circuit of Figure 2, Ta = +25C, unless otherwise noted.) NOGLOAD BATTERY CURRENT MAXIMUM LOAD CURRENT vs. START-UP INPUT VOLTAGE vs. BATTERY VOLTAGE BATTERY VOLTAGE vs. LOAD CURRENT 100 800 20 i (VouT=3.0) f +3 f : i | : 2 eo -| 90 \ 2 Fm RUN MODE 3 16 = \ & 14 = \ 200 7 = a 9) 5 i Te e 15 = 19 2 3 160 7 J & 40 = i - 08 E = 100 az x z / Yo COAST MODE 2 O86 0 = Ep ff O4 ~ sd VouT=3.0 OZ VouT=3.0V COAST MODE 5 5 COAST MCD 0 05 1 15 8 0 05 1 15 2 25 1 10 100 BATTERY VOLTAGE (V) BATTERY VOLTAGE (V) LOAD GURRENT (ma) NICD CHARGING CURRENT vs. NICD VOLTAGE DRi OR DR2 ON- RESISTANCE vs. VouT 25 3 > 2 Q = 2 = z 5 fia MN 7 N\ 5 AS = 3 NN ~ = 10 & 1 a Oo 2 5 15mA MODE Vour=4.5V 0 , 0 0) 4 2 8 4 #5 6 0 1 2 3 4 5 QUTPUT VOLTAGE (V) Vour VOLTAGE (V) LX NOISE SPECTRUM REG2 NOISE SPECTRUM (RUN MQOE, SYNC CPERATION) (RUN MODE} 100 = : 80 = > : g = = @ a 2 2 40 20 0 600 of 1 10 100 = 1000 10,000 FREQUENCY (kHz) FREQUENCY (kHa) 6 MAAXLAA1-Cell, Step-Up Two-Way Pager System IC Pin Description PIN NAME FUNCTION Connect LX1 to the inductor. LX1 is internally connected to an NFET that switches to PGND and a PFET 1 LX : that switches to OUT. 2 SDI Serial Data Input for SPI Interface 3 SDO Serial Data Output for SPI Interface 4 PGND Power Ground. Source of LX1 NFET. 5 SCL Serial Clock for SPI Interface 6 LBO Open-Drain Output for LB Gomparator 7 RSO Reset Output. Open drain goes low when RSIN drops below 0.6V. All serial registers are reset (or set) to POR state as well. 8 REF 1.28V Reference. Bypass with a 1pF capacitor. CHO is compared to a 7-bit DAC that adjusts from 0.2V to 1.27V. The comparison result is sent to the 9 CHO . CHO OUT register. 10 RSIN Reset Input. Triggers RSO and resets IC when input is below 0.6V. Comparator with hysteresis (18m). if LBI Low-Battery Input. Triggers LBO and internal serial bit. 42 FILT An external RG network sets the PLL loop response (at SYNC) to adjust frequency lock time versus jit- ter: 1nF || (22nF + 10kQ). Connect to REF when SYNG is not used. 13 SYNC Sync Input for PWM Switch Rate. A 38.4kHz input results in a 268.8kHz PWM rate (7 times the sync frequency). Resistor sets offset between OUT (or REG1 or any other point) and REG2. Rors = 15k results in 14 OFS 150mvV. 15 AGND Analog Ground 16 DRGND Ground for DR1 and DR2 FET Sources 17 DRi Open-Drain FET Switch. Activated via the serial-interface bit. 18 DR2IN Logic Input. ANDed with the DR2ON bit to control the DR2 switch. 19 DR2 Open-Drain FET. On via AND of the DR2ON bit and the DR@IN pin. 20 REG3 1V, 2mA Regulator Output. On via the serial interface. Low noise. 31 REG2 24mA REG2 Output. Linearly regulated to the voltage at the OFS pin (voltage difference = 10yA + Rors). REG2 isolates noise. 22 R2IN REG? Input. Connect to OUT, REG1, or another voltage source. 23 NICD 15mA or 1mA Settable Charge Current from QUT to 3-Cell NICD Stack. When the NICD_REG_ON bit is set (Table 2}, NICD becomes an input to the linear regulator at OUT, and the DC-DC converter is off. PFET output connected to OUT. Output is clamped such that it cannot rise above 3.3V, regardless of 24 REG the voltage set at OUT. DC-DG Converter Quip ut and Feedback Point. Digitally controlled from 1.8V to 4.9V in 100mV steps 25 OUT (Table 6). 26 BATT Positive Connection to Battery. The IC is powered from QUT. 27 cs Chip Select for SPI Serial Interface 2g AUN Run/Goast. Permits toggling between Run and Coast Modes via logic signal. Run is selected when either RUN or the internal RUN/COAST bit is high. Coast is selected when both are low. MA AXIMA LVEXVWNMAX847 1-Cell, Step-Up Two-Way Pager System IC 1-C.L+# > BATTERY IN st ur SCL SDI SDO CS AUN at ~ 22H BATT DTT TT FNS ASS TTT Pe I I N ; JA AXIAVI ' meen Mux _ = PWM (1) 7 (PFM IN My? ei asv D> , COAST) | N ! I I cH REGULATOR] = DAC , CHARGE 4) > Nico | Ross OR 1 15k PEF BACKUP c WV FEEDBACK __ | REGULATOR inv ee : + OFS I RUN |) > (2 a ! e1 LEO 7 ! COAST PLL = 7 CHO @) FROM ra) CHO - ; Hf P 1 | | Nico ri (a) Al_ I Ss} SERIAL YY rE st nr 1 ae Va (13) + + cr cHt 7 SYNC 7 10k ; = ovo-ove [Schone wf) CLAMPON WHEN I FROM HH > ) OV4 =1 = ; BATTERY | CPE CH2 33V v 7 CLAMP : =] DACO-DAC7 Ne ; | RESET eo 1 pe) CONTROL fou ; BIT BACKUP L I I I I I Figure f. Functional Diagram 8 MAAXIAA1-Cell, Step-Up Two-Way Pager System IC Detailed Description The MAX847 contains several functional blocks that simplify the integration of power-supply and monitoring functions within a 1-cell powered system. They are described in the following subsections. Voltage Regulators Regulator outputs include the following: + OUT: Main switch-mode boost output * REG: 1.58 switch and output voltage clamp. Switches REG1 to OUT and clamps REG1 at 3.3V when OUT is set to 3.4V or more. REG2: Linear-regulated, 24mA low-noise output that regulates so that VouUT - VREG@2 is a set difference voltage (10HA * Rors). Output peak-to-peak ripple is typically 2mV with a 10uUF bypass capacitor at REG2. REG2 clamps output at 3.3V. REGS: Low-noise, 1 linear regulator that supplies ema. Main DC-DC Boost Converter (OUT} OUT is the main DC-DG converters output. It supplies current from the internal synchronous-rectified boost reg- ulator and needs no external FETs or voltage-setting resistors. The output voltage (VOUT) is adjusted from 1.8V to 4.9V in 109mV steps (Tables 2 and 6} by internal DAC control using a serial-data command. OUT can supply up to 80mA, less the current supplied to the other regulators (REG1, REG2, and REG3). OUT can also be put into a low-current, pulse-skipping Coast Mode (13HA typical quiescent current) by reset- ting the RUN/COAST serial input bit and holding the RUN pin at OV. OUT supplies up to 40mA in Coast Mode. Typically, when changing from Run to Goast Mode, a lower OUT voltage is also set (Table 5) to fur- ther reduce system operating current. The extent of this reduction depends on the minimum operating voltage of the system components when they are in standby or sleep states. AA ALKALINE 28 Rt 350k BATT D5 REG! = pe ce A70K OME PGND 4 __f Amur CERAMIC c= = 8) 9 MAXUM 5, LE 9 B- 3.0VLOGIC a L co AD IN BH CHO MAX847 E tour __4| is ren 2 = 5 R6 SERIAL pe] SCL 14 2 ors F*$e-vw "0 w) SDI C7 Fore i 3 SD0 cos__ 15k 17 nace [2 ad B- 2.55V ANALOG a DRI m2 1.80. 19 | 1c 4 pavers | 1B Liu BB DRAIN 20 RB 18] reno REGS Vv 18M | we RCVR 38.4kHz = 45 " =< RA TL ee] SYNG asin LS 470k 12} eur reo LZ lL cto Ar 93 - tne a Co 4) Re NICD PTO MWC RESET Le cg Tor RUN AGND {:-> TO AF PA 2enF = i 45 _ RUN _ 28 LL mm 3-CAL = COAST - Nica = Figure 2. Standard Application Circuit MA AXIMA LVEXVWNMAX847 1-Cell, Step-Up Two-Way Pager System IC OUT can be set as low as 1.8V; however, some run mode functions are limited when VoUT is below 2.5V: + The allowed serial-interface clock rate is reduced. * Internal LX FET and DR1 and DR@2 on-resistance increases. Logie Supply (REG1) REG1 is not a regulator in the conventional sense, but rather a 1.50 PFET that acts as either a switch or a volt- age clamp, depending on the programmed OUT volt- age. When OUT is set to 3.3V or less, REG1 operates as a switch. When OUT is set to 3.4V or more, the REG1 output clamps at 3.3V. This arrangement limits VREG1 to an acceptable voltage for logic when OUT is programmed to a higher voltage (typically >4V} for charging (see Charger Circuit and Backup Linear Regulator sections). Low-Noise Analog Supply (REG2) REG2 is a linear, 24mA low-dropout regulating circuit whose input is R2IN. The REG2 output (VREG2) is set by Rors. Rors does not set an absolute voltage, but rather an offset level from R2IN (Figure 2). VREG2 is set by: VREG2 = VR2IN - 10WA+ ROFS Typically R2IN and Rors are tied to OUT, in which case: VOUT - VREG2 = 109A: Rors Rors adjusts VouT - VREGe to allow REG2 noise rejec- tion to be traded for voltage drop and consequent effi- ciency loss. A 15kQ (typical) Rors value sets a 150mV voltage difference. R2IN typically is supplied from OUT or REG1 but can be connected elsewhere as long as the voltage applied to R2IN does not exceed VOUT. For low- est output noise on REG2, connect RelN to REG1. Note that the REG2 output also clamps at 3.3V. Low-Noise, 1V Analog Supply (REG3) REGS is a 1V, low-noise linear regulator that supplies up to 2mA. REG3s input is internally connected to REG2. PWM Frequency Synchronization The MAX847 DC-DC converter operates with or without a clock at the SYNC input. If a SYNC clock is used, a PLL filter network must be connected at FILT (see R7, C9, and C10 in Figure 2). The DC-DG converter (in Run Mode) operates at 7fsync. The MAX84?7 is designed for a 38.4kHz SYNC clock and hence a 268.8kHz switching frequency. If a SYNC clock is not used then FILT must be tied to REF and R?, C9, and C10 should be omitted. Note that if a SYNC clock is not used, and FILT is not connected to REF, the MAX847 will not enter Run Mode. 10 QUT AMA AXLA MAX847 FILT Figure 3. Add PNP to allow start-up in Run Mede before the SYNC input clock is active. With no SYNC clock, and FILT tied to REF, the DC-DC converter nominally operates at 270kHz when in Run Mode. The Run Mode switching frequency has no rela- tion to the serial-data clock rate. On initial power-up, the MAX847 is designed to start in Coast Mode, with Run Mode normally commanded by system via the serial interface, or the RUN pin, after the system has started. Under some circumstances, the MAX847 may power up in Run Mode. These circum- stances are: 1) Ifa SYNG clock is not used (REF tied to FILT). 2) If the SYNC clock is used and is provided at initial power-up when REG1 is 1.5V or higher. 3) If the SYNC clock is used, the connection shown in Figure 3 is added, and the SYNC clock is present when RSO is cleared (logic high). These choices are outlined in Table 1. Voitage Detectors (LBO and Reset) The MAX847 contains two voltage-detector inputs: LBI and RSIN. The LBI and RSIN comparator outputs are open-drain pins (LBC and RSO) for a real-time hard- ware output. LBO is also readable via the serial inter- face. Both LBI and RSIN trigger at a 0.6V input threshold and have about 18mV hysteresis. RSC also triggers the MAX847 internal power-on reset (POR). 7-Bit ADC (CHO Input and CHT, CH2) Three analog channels are compared to a 7-bit, serially programmed digital-to-analog converter (CH DAC). The CH DAC voltage can be varied in 10mV steps from 200mV to VREF - 1LSB (or 1.27V) (Table 2). CHO is an external input, while CH1 and CH2 are signals internally generated from the NICD and BATT pins. NICD is inter- nally divided by four before being compared to CH DAC, while BATT directly connects to CH2. MAAXIAA1-Cell, Step-Up Two-Way Pager System IC Table 1. Run and Coast Mode Start-Up Requirements SYNC OPERATION CIRCUIT CONNECTION START-UP MODE CAPABILITY No SYNC clock is used. 1) Connect REF to FILT 2) Remove R7, C9, and C10 Can start in either Coast or Run Mode by tying RUN pin appropriately. In Run Mode the DC-DG converter operates at 270kHz. On initial power-up, system can supply SYNC clock to MAX847 when REG1 is greater than 1.5V. Use standard Figure 2 circuit Can start in either Coast or Run Mode by tying RUN pin appropriately. In Run Mode the DC-DG converter operates at 7isync once the SYNG clock is applied. On initial power-up, system can supply SYNC clock to MAX847 before, or concurrent with, RSO going high. Add Q1 as shown in Figure 3 Can start in either Coast or Run Mode by tying RUN pin appropriately. In Run Mode the DC-DG converter operates at 7fsync once the SYNC clock is applied. On start-up, system does not supply SYNC clock to MAX847 until after RSQ goes high. Use standard Figure 2 circuit Musi start in Coast Mode. Run Mode may then be started by the system after start-up. The comparison thresheld veltages for each channel are described in the following equations: VTH(CHO: pin 9) = D- 10mV VTH (GH1: NICD) = D- 40mV VTH(CH2: BATT) = D- 10mV where D is the decimal equivalent of the binary code DACO-DAC6 (Table 2). DACO is the LSB. A DAC code of 1111111 equates to D = 127. When all zeros are pro- grammed, the CH DAG and GH_comparators turn off. CHO, CH1, and CH2 comparison results reside in the three MSB locations of the output serial data (Table 5). The GH_ OUT data is delayed by one read cycle. In other words, each CH_ OUT bit is the result of the com- parison made against the CH DAC voltage pro- grammed during the previous serial-write operation. An analog-to-digital (A/D} conversion can be performed on a channel by using the system software to step through a successive-approximation routine or, if the input is partially known, by setting the CH DAC to a voltage near the estimated point and checking succes- sive CH_ OUT bits. A faster A/D shortcut can be used for battery measure- ments when the goal is a go, no go determination. For this type of test, the CH DAC can simply be set to the desired limit, and GH_ OUT supplies the result on the next serial-write operation. One instance in which this shortcut saves time is during a battery-impedance check. The unloaded battery voltage can first be mea- sured, if time allows, using one of the techniques described in the previous paragraph. Then the magni- MA AXIMA tude of the loaded voltage drop can be quickly checked with a single comparison to see if it is within the desired limit. The A/D circuitry can be invoked in both Run and Coast Mode. Open-Drain Drivers Two open-drain drivers (DR1 and DR2) are activated via the serial interface. DR1 and DR2 are grounded 1.8@ (typical) NFETs that can sink up to 120mA. The maximum sink current is limited by on-resistance and package dissipation to about 240mA total sink current for both switches. Note that DR1 and DR are designed to sink current only from the main battery (BATT) and cannot be pulled above BATT. DR2 is controlled by an external input (DR2IN) as well as a serial input bit. DR2IN is ANDed with the DR2ON serial-control bit, allowing DR2 to drive an audio beep- er. The audio-frequency clock is applied to DR@IN, and ON/OFF gating is applied to DR2ON. Both BR@IN (pin 18) and DR2ON (serial bit) must be high for DR2 to switch on. DR1 is controlled only by DR1ON (serial bit). Run and Coast Modes The MAX847s default mode is Coast. Run Mode is selected by either serial command (Table 2} or by pulling the RUN pin high. The RUN serial bit and the RUN pin are logically ORed. Both must be low to imple- ment Goast Made. In Coast Mode, the DC-DC convert- er pulses only as needed to satisfy the load, holding MAX847 operating current to typically 13uWA. In Run Mode the DC-DG converter employs fixed-frequency 11 LVEXVWNMAX847 1-Cell, Step-Up Two-Way Pager System IC pulse width modulation (PWM), as well as synchroniza- tion, to minimize noise. Some MAX847 functions are confined to Run Mode while others remain active in both Run and Coast. These are outlined as follows. Various circuit functions can be disabled as follows: Functions that always remain on are: * Serial l/O * Reference (REF) * OUT * REG LBI, RSIN (and LBO, RSO) Functions that can be programmed on or off are (Table 1): + DR1 and DR2 * REG2 and REG3 NICD charger (Note: This may overload OUT if turned on in Coast Mode when other loads are present) NICD backup regulator * CHO, CH1, CH2 and CH DAG Functions that afways turn off in Coast Mode are: * SYNC and PLL circuits * DC-DC PWM control circuits Table 2. Serial-Bit Assignments Power-On Reset The MAX&47 has an internal POR circuit (VOUT < 1.6V) to ensure an orderly power-up when a battery is first applied. This feature is separate from the RSO com- parator; however, if RSO goes low during operation, all serial registers are set to the same predetermined states as on power-up. The POR states for each regis- ter are listed in Table 3. Note that the MAX847 always comes out of reset in Coast Mode; consequently, it cannot supply full power until Run Mode is selected by either the RUN pin or ser- ial command. System software cannot exercise full load current until Run Mode is enabled. Charger Circuit A charger current source from OUT to NICD is activat- ed via a serial bit (Table 2). The current source can charge a small 3-cell NICD or NIMH battery (typically coin cell) or a 1-cell lithium battery. The charge current can be set to either 15mA or 1mA. When both 15mA and 1mA are set, the charger runs at 15mA. OUT sets the maximum charge (or float) voltage. When charging is implemented, VOUT must also be set high enough to allow sufficient headroom for the charger current source. The VOUT - VNICD difference should normally be between 0.2V and 0.5V. Charger current vs. output voltage is graphed in the Typical Operating Characteristics. Note also that charging current reduces the OUT current available for other loads. R2 (MSB) Ri Ro D4 D3 D2 DI Do RUN/ 0 0 0 DR2_ON DR1_ON REG3_ON REG2_ON COAST LBO_Sets_ 0 0 1 x BACKUP BACKUP 15mA_CHG | 1mA_CHG 0 1 0 ov4 ova ove Ovi Ovo 0 1 1 x X X x x 1 DACE DACS DACA DAC3 DAC2 DACI DACO Table 3. Serial-Bit Power-On-Reset (POR) States R2 Ri Ro D4 D3 D2 Dt Do 0 0 0 POR = 0 POR = 0 POR = 0 POR = 0 POR =0 0 0 1 x POR = 0 POR = 0 POR =0 POR =0 0 1 0 POR = 0 POR =1 POR =1 POR = 0 POR=0 0 1 1 x X X X X 1 POR =0 POR=0 POR =0 POR = 0 POR = 0 POR =0 POR=0 12 MAAXIAA1-Cell, Step-Up Two-Way Pager System IC Backup Linear Regulator The BACKUP serial input bit turns on the backup regu- lator, which sources current from NICD to OUT. This regulator backs up OUT by using the rechargeable bat- tery (at NICD) when the main battery (at BATT) is depleted or removed. The backup regulator pass devices resistance is typically 50, so it can typically supply 20mA with only 100mV of dropout. All DG-DC converter and charging circuitry is disabled when the backup regulator is turned on, but all other functions remain active. Activate BACKUP manually by serial command, or set it to trigger automatically when LBO goes low. Automatic Backup Setting the LBO_Sets_ BACKUP serial bit (Table 2) pro- grams the IC so that when LBO goes low, the backup regulator automatically turns on without instructions from the microprocessor (uP). When the LBO_ Sets_BACKUP bit is 0, the backup regulator is turned on only by setting the BACKUP bit. The BACKUP bit also overrides the LBO_Sets_ BACKUP bit. Figure 4 shows the logic for this function. If the main battery is depleted, and the NICD battery is drained during backup, RSO goes low while the back- up regulator is supplying OUT (if RSI is used to monitor OUT or REG1). When RSO falls, the serial registers reset to their POR states (with the DC-DC converter on in Goast Mode and the backup regulator off, Tables 2, 3, and 4}. This prevents the IC from getting hung up with the DC-DC converter off when a new main battery is inserted. This sequence is required because if the MAX847 did not default to DC-DC converter on when Table 4. Input-Bit Function Description coming out of reset, the UP (still reset by RSC) would not be able to provide the device with serial instructions to turn on. Serial Interface The MAX847 has an SPl-compatible serial interface. The serial-interface lines are Chip Select (CS), Serial Clock (SCL), Serial Data In (SDI), and Serial Data Cut (SDC). Serial input data is arranged in 8-bit bytes. Most bytes contain a 3-bit address pointer (R2, R1, RO) along with 5 bits of input data (D4D0). For common operations such as selecting Run or Coast Mode, acti- vating REG2 or REGS, or turning on DR1 or DR2, only the 000 (Re, R1, RO) address register needs to be writ- ten. The serial input data format for all MAX847 opera- tions is outlined in Tables 2, 3, and 4. 15mA_CHG To CHARGER {mA_CHG CONTROL [BO To rr BACKUP REGULATOR LBO_SETS_BACKUP BACKUP Figure 4. Logic for Charger Control and BACKUP, and for LBO Sets BACKUP Serial Inout Bits INPUT BIT FUNCTION RUN/COAST 1 = Run Mode, 0 = Coast Mode (POR state is Coast Mode). REG2_ON, REG3_ON 1 = Turn on selected regulator (POR state is off). DR1, DR2 1 = Turn on selected switch (POR state is off). 1mA_CHG, 15mA_CHG state is off). 1 = Turnon selected charge current to NICD. If both are set, the charge current is 15mA (POR 1 = Turn on backup linear regulator from NICD to OUT and disable DC-DC converter (POR BACKUP state is BACKUP off). Setting this bit overrides 1mMA_CHG, 15mA_CHG, and LBO_Sets BACK- UP (Figure 1). LBO Sets BACKUP 1 = Allow LBO to turn on backup regulator and disable DC-DC converter (POR state is no con- nection between LBO and BACKUP). OVO0-OV4 Sets OUT Output Voltage (POR state is VouT = 3.0V). DACO-DAC6 Sets 7-bit CH DAC voltage for A/D conversion (POR state is all zeros with DAC and compara- tors off). MA AXIMA 13 LVEXVWNMAX847 1-Cell, Step-Up Two-Way Pager System IC I I I I 1 1 I I css pe ! ee tcH ft I a cama I I I I I I SCLK } \ J \ y \ l I rst bot \ Figure 5. Detailed Serial-Interface Timing scL | | SD0 D7 D6 DS D4 G G G G oo SDI Re Ri Fo D4 D3 D2 D1 Do Figure 6. CS, SCL, SDO, and SDI Serial Timing Serial data is clocked in and out MSB first. Input data is latched on the GLK rising edge, and output data is shifted out on the CLK falling edge. When CS goes low, DO immediately contains the MSB output bit (D7). D6 is not clocked out until the falling clock edge that follows the first rising clock edge after a Chip Select. See the timing diagrams in Figures 5 and 6. 14 SPI writes and reads concurrently, so it may be neces- sary to perform dummy writes in order to read output data. Four output data bits (D?7-D4, Table 5) are sent from SDO each time a serial operation occurs. When R2 = 0, RO and Ril are address pointers. However, when Re = 1, the 7 remaining bits (Ri, RO and D4D0) become DAC programming bits. This vio- MAAXIAATable 5. Serial Output Data 1-Cell, Step-Up Two-Way Pager System IC D7 (MSB) D6 D5 D4 D3Do FUNCTION CH_ OUT and LBO output bits. A 1 indicates CH2 OUT CH1_OUT CHO _OUT LBO x that the selected channel (GH_) voltage is greater than the CH DAC voltage or that LBI is less than 0.6V. Table 6. VouT Output Voltage SERIAL-DATA BIT ova OV3 e fp ep ap ep a a a a as a et St st OO] OY OY CO] CO] CO] CO] Oo] lO] lO] LUO] LUO LO] LO] LOD 0 0 0 0 0 0 0 0 1 1 1 7 1 7 1 1 0 0 0 0 0 0 0 0 1 7 1 7 1 1 1 1 MA AXIMA OV2 =| =] =} =| of co] Oo] oF] =] =] =| =| co] a] ao] ao] =| =] =| =] a] ao] ao] of =] =| =|] =| ol ol ola oO <= ary =| =| oo] of =| =| oo] oF] =] =] co] of =] =] co] a] =| =] ao] Oo] = [ =] a] of =] =| co] oO] | =| ala +) Oo); +) oO] +] Of] Ae] CO] ty] OP ey] OF He] Oy sty] OY St] OP Ay] Oy] sty Oy] ty] Oy] He] Oy] ty Oy ty] Oy ty] Oo lation of programming etiquette (Ri and RO are some- times address bits and other times data bits) allows the CH DAC to be loaded with only one write operation. Writing all zeros to the GH DAC turns it, the GHO, CH1, and GH2 comparators, and the NICD and BATT voltage- sensing resistors off to minimize current consumption. This reduces current drain from OUT by about 30LA. Applications Information Component Selection The MAX847 requires minimal design calculation and is optimized for the component values shown in Figure 2. However, some flexibility in component selection is still allowed, as described in the following text. A list of suit- able components is provided in Table 7. Inductor L1 is nominally 22uUH, but values from 10uH to 47uH should be satisfactory. The inductor current rat- ing should be 500mA or more if full output current (80mA) is needed. If less output current is required, the inductor current rating can be reduced proportionally but should never be less than 250mA. Inductor resistance should be minimized for best effi- ciency, but since the MAX847 N-channel switch resis- tance is typically 0.450, efficiency does not improve significantly for coil resistances below 0.20. Filter capacitors G1-C4 should be low-ESR types (tan- talum or ceramic) for lowest ripple and best noise rejection. A high-frequency 0.1pF ceramic cap should be used in parallel to reduce transient noise at OUT. The values shown in Figure 2 are optimized for each outputs rated current. Lower required output current allows smaller capacitance values. Resistors at the LBI and RSIN inputs set the voltage at which the LBO and RSO outputs trigger. The voltage threshold for both LBI and RSI is 0.6V. The resistors required to set a desired trip voltage, VTRIP (Figure 2), are calculated by: R1 = R2[(VTRIP(LBO) / 0.6) - 1] R3 = R4[(VTRIP(RSO) / 0.6) - 1] 15 LVEXVWNMAX847 1-Cell, Step-Up Two-Way Pager System IC Table 7. External Components SUPPLIER | PARTNO. | COMMENTS INDUCTORS (22y1H) Coileraft DT1608C-223 0.1682, 3.18mm high, shielded LOHA4N220K 0.94, 2.6mm high, low current, low cost Murata high | LOH3C224 0.712, 2mm high, low current, low cost GD54-220 0.189, 4.5mm high . CD43-220 0.3780, 3.2mm high Sumida high CDRHe2B-220 ~| 2-848, Smm high, shielded TDK NLO565050-220K | 0.430, 5mm high CAPACITORS AVX TPS series Tantalum Marcon THGR series Ceramic Sprague 595D series Tantalum STORAGE CAPACITOR (optional at NICD pin) Polystor | A-10300 | 1.5F To minimize battery drain, use large values for R2 and R (>100k&) in the above equations; 470kQ is a good starting value. See the Low-Noise Analog Supply (REG2) section for information on selecting Rors. Since LBO and RSO are open-drain outputs, pull-up resistors (R5, R6) are usually required. Normally these will be pulled up to REG1. 100k& is recommended as a compromise between response time and current drain, although other values can be used. Since LBI and RSO are high (open circuit) during normal operation, current normally does not flow in R5 and R6 until a low-battery or reset event occurs. Logic Levels Note that since the MAX847s internal logic is powered from REG1, the input logic levels at the digital inputs: DR2IN, RUN, SYNC, CS, SCL, and SDI, as well as the logic output levels of SDO, are governed by the voltage of REG1. Logic high inputs at these pins should not exceed VAEGI. Digital inputs should either be driven from external logic (or a UP} powered from REG1, or by open-drain logic devices that are pulled up to REG1. 16 Board Layout and Noise Reduction The MAX8&47 makes every effort in its internal design to minimize noise and EMI. Nevertheless, prudent layout practices are still suggested for best performance. Recommendations include: 1} Keep trace lengths at L1 and LXi, as well as at PGND, as short and as wide as possible. Since LX14 swing between VBAT and VOUT at a high rate, mini- mizing LX1 trace length serves to reduce the PG board area that can act as an antenna. 2) The filter capacitors at OUT, REG1, REG2, and REGS should be placed as close as possible to their respective pins (no more than 0.5mm away). 3) A shielded inductor at L1 will minimize radiation noise, but may not be essential. Toroids will also exhibit EMI performance similar to that of shielded coils. 4) The LX1, OUT, and PGND pins are located at the uppermost part of the IC to facilitate PC layout. Keep power components in this area to minimize coupling to other parts of the circuit. Other pins in this area are digital and are not affected by close proximity to switching nodes. 5) Use a separate short wide ground trace for PGND and the ground side of the BATT and OUT filter capacitors. Tie this trace to the ground plane. Pin Configuration TOP VIEW e ut [7] [28] RUN sol [2] Biles soo [3 | [26] BATT pan [4 | 2%] OUT so. [FE] MAAXIAA Fie woe. MM? Tey nico nso [7 | Fala rer [| of] REGe cuo [3 | [20] REGS RSIN [10] sa] ore Lai [1] [8] OPIN act [te] 7] ont sync [13] +6] oFSND ors [14] 5] AND QSoOP MAAXIAA1-Cell, Step-Up Two-Way Pager System IC |. E/2 NOTES: 1. D& E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .006" PER SIDE. 3. HEAT SLUG DIMENSIONS X AND Y APPLY ONLY TO 16 AND 28 LEAD POWER-QSOP PACKAGES. 4. CONTROLLING DIMENSIONS: [NCHES. MILLIMETERS. x 3 VARIAT 7. PROPRIETARY [MF ORPATCON SVIAXAXI/VI TALE PACKAGE OUTLINE, OSOP, 150, 025 LEAD PITCH 21-0055 B MA AXIMA 17 Package Information QSOP EPS LVEXVWNMAX847 1-Cell, Step-Up Two-Way Pager System IC NOTES 18 MAAXIAA