NCP1850 Fully Integrated Li-Ion Switching Battery Charger with Power Path Management and USB On-The-Go Support The NCP1850 is a fully programmable single cell Lithium-ion switching battery charger optimized for charging from a USB compliant input supply and AC adaptor power source. The device integrates a synchronous PWM controller, power MOSFETs, and the entire charge cycle monitoring including safety features under software supervision. An optional battery FET can be placed between the system and the battery in order to isolate and supply the system. The NCP1850 junction temperature and battery temperature are monitored during charge cycle, and both current and voltage can be modified accordingly through I2C setting. The charger activity and status are reported through a dedicated pin to the system. The input pin is protected against overvoltages. The NCP1850 also provides USB OTG support by boosting the battery voltage as well as providing overvoltage protected power supply for USB transceiver. MARKING DIAGRAM WLCSP25 CASE 567FZ 1850 A Y WW G 1850 AYWW G = Specific Device Code = Assembly Location = Year = Work Week = Pb-Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 29 of this data sheet. Features * * * * * * * * * * * * * * * * * * http://onsemi.com 1.5 A Buck Converter with Integrated Pass Devices Input Current Limiting to Comply to USB Standard Automatic Charge Current for AC Adaptor Charging High Accuracy Voltage and Current Regulation Input Overvoltage Protection up to +28 V Factory Mode 250 mA Boosted Supply for USB OTG Peripherals Reverse Leakage Protection Prevents Battery Discharge Protected USB Transceiver Supply Switch Dynamic Power Path with Optional Battery FET Battery Temperature Sensing for Safe Operation Silicon Temperature Supervision for Optimized Charge Cycle Safety Timers Flag Output for Charge Status and Interrupts INTB Output for Interrupts I2C Control Bus up to 3.4 MHz Small Footprint 2.2 x 2.55 mm CSP Package These Devices are Pb-Free and are RoHS Compliant Applications * * * * Smart Phone Handheld Devices Tablets PDAs (c) Semiconductor Components Industries, LLC, 2013 May, 2013 - Rev. 1 1 Publication Order Number: NCP1850/D NCP1850 PIN CONNECTIONS 1 2 3 4 5 A IN IN SPM SDA SCL B CAP CAP OTG ILIMB FLAG C SW SW AGND ILIM NTC D PGND PGND SENSP SENSN FET E CBOOT TRANS CORE WEAK BAT (Top View) Figure 1. Package Outline CSP Table 1. PIN FUNCTION DESCRIPTION Pin Name Type A1 IN POWER Description Battery Charger Input. These two pins must be decoupled by at least 1 mF capacitor and connected together. A2 IN POWER A3 SPM DIGITAL INPUT System Power Monitor input. A4 SDA DIGITAL BIDIRECTIONAL I2C data line A5 SCL DIGITAL INPUT I2C clock line B1 CAP POWER B2 CAP POWER B3 OTG DIGITAL INPUT B4 ILIMB OPEN DRAIN OUTPUT Connect to interrupt pin of the system, active low B5 FLAG OPEN DRAIN OUTPUT Charging state active low. This is an open drain pin that can either drive a status LED or connect to interrupt pin of the system. C1 SW ANALOG OUTPUT C2 SW ANALOG OUTPUT C3 AGND ANALOG GROUND C4 ILIM DIGITAL INPUT Input current limiter level selection (can be defeated by I2C). C5 NTC ANALOG INPUT Input for the battery NTC (10 KW / B = 3900) or (4.7 KW / B = 3900) If not used, this pin must be tied to GND to configure the NCP1850 and warn that NTC is not used. D1 PGND POWER GND D2 PGND POWER GND D3 SENSP ANALOG INPUT CAP pin is the intermediate power supply input for all internal circuitry. Bypass with at least 4.7 mF capacitor. Must be tied together. Enables OTG boost mode. OTG = 0, the boost is powered OFF OTG = 1 turns boost converter ON Connection from power MOSFET to the Inductor. These pins must be connected together. Analog ground / reference. This pin should be connected to the ground plane and must be connected together. Power ground. These pins should be connected to the ground plane and must be connected together. Current sense input. This pin is the positive current sense input. It should be connected to the RSENSE resistor positive terminal. http://onsemi.com 2 NCP1850 Table 1. PIN FUNCTION DESCRIPTION Pin Name Type Description D4 SENSN ANALOG INPUT Current sense input. This pin is the negative current sense input. It should be connected to the RSENSE resistor negative terminal. This pin is also voltage sense input of the voltage regulation loop when the FET is present and open. D5 FET ANALOG OUTPUT E1 CBOOT ANALOG IN/OUT E2 TRANS ANALOG OUTPUT Output supply to USB transceiver. This pin can source a maximum of 30 mA to the external USB PHY or any other IC that needs +5 V USB. This pin is Overvoltage protected and will never be higher than 5.5 V. This pin should be bypassed by a 100 nF ceramic capacitor. E3 CORE ANALOG OUTPUT 5 V reference voltage of the IC. This pin should be bypassed by a 2.2 mF capacitor. No load must be connected to this pin. E4 WEAK ANALOG OUTPUT Weak battery charging current source input. E5 BAT ANALOG INPUT Battery FET driver output. When not used, this pin must be directly tied to ground. Floating Bootstrap connection. A 10 nF capacitor must be connected between CBOOT and SW. Battery connection http://onsemi.com 3 NCP1850 Table 2. MAXIMUM RATINGS Rating Symbol Value Unit VIN -0.3 to +28 V CAP (Note 1) VCAP -0.3 to +28 V Power balls: SW, CBOOT (Note 1) VPWR -0.3 to +24 V IN pin with respect to VCAP VIN_CAP -0.3 to +7.0 V SW with respect to SW VSW_CAP -0.3 to +7.0 V VCTRL -0.3 to +7.0 V Digital Input: SCL, SDA, SPM, OTG, ILIM (Note 1) Input Voltage Input Current VDG IDG -0.3 to +7.0 V 20 V mA Human Body Model (HBM) ESD Rating are (Note 2) ESD HBM 2000 V Machine Model (MM) ESD Rating are (Note 2) ESD MM 200 V IN (Note 1) Sense/Control balls: SENSP, SENSN, VBAT, FET, TRANS, CORE, NTC, FLAG, INTB and WEAK. (Note 1) Latch up Current (Note 3): All Digital pins( VDG), FET All others pins. ILU Storage Temperature Range Maximum Junction Temperature (Note 4) Moisture Sensitivity (Note 5) mA 10 100 TSTG -65 to + 150 C TJ -40 to + TSD C MSL Level 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. With respect to PGND. According to JEDEC standard JESD22-A108 2. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22-A114 for all pins. Machine Model (MM) 200 V per JEDEC standard: JESD22-A115 for all pins. 3. Latch up Current Maximum Rating: 100 mA or per 10 mA JEDEC standard: JESD78 class II. 4. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation. See Electrical Characteristics. 5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J-STD-020. Table 3. OPERATING CONDITIONS Symbol Parameter Conditions Min Typ Max Unit VIN Operational Power Supply (Note 6) 3 VINOV V VDG Digital input voltage level 0 5.5 V +85 C 10 mA TA ISINK CIN Ambient Temperature Range -40 25 FLAG sink current 1 mF Decoupling Switcher capacitor 4.7 mF Decoupling core supply capacitor 2.2 mF Decoupling system capacitor 10 mF Switcher Inductor 2.2 mH RSNS Current sense resistor 68 mW RqJA Thermal Resistance Junction-to-Air CCAP CCORE COUT LX TJ Decoupling input capacitor (Notes 7 and 8) Junction Temperature Range 60 -40 25 C/W +125 6. OVLO is selectable per metal option (see ELECTRICAL CHARACTERISTICS table). 7. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation. See Electrical Characteristics. 8. The RqJA is dependent on the PCB heat dissipation. Board used to drive this data was a 2s2p JEDEC PCB standard. http://onsemi.com 4 C NCP1850 Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between -40C to +85C and TJ up to + 125C for VIN between 3.6 V to 7 V (Unless otherwise noted). Typical values are referenced to TA = + 25C and VIN = 5 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit Valid input detection threshold VIN rising 3.55 3.6 3.65 V VIN falling 2.95 3.0 3.05 V VIN falling 4.3 4.4 4.5 V Hysteresis 50 100 150 mV VIN rising 5.55 5.65 5.75 V INPUT VOLTAGE VINDET VBUSUV USB under voltage detection VBUSOV USB over voltage detection VINOV VINOV Valid input high threshold Hysteresis 25 75 125 mV VIN rising 7.1 7.2 7.3 V Hysteresis 200 300 400 mV IINLIM set to 100 mA 70 85 100 mA IINLIM set to 500 mA 425 460 500 mA IINLIM set to 900 mA 800 850 900 mA IINLIM set to 1500 mA 1.4 1.45 1.5 A INPUT CURRENT LIMITING IINLIM Input current limit VIN = 5 V INPUT SUPPLY CURRENT IQ_SW VBUS supply current IOFF No load, Charger active state 15 mA Charger not active, NTC disable 500 mA CHARGER DETECTION VCHGDET Charger detection threshold voltage VIN - VSENSN, VIN rising 50 200 VIN - VSENSN, VIN falling 10 50 mV REVERVE BLOCKING CURRENT ILEAK VBAT leakage current Battery leakage, VBAT = 4.2 V VIN = 0 V, SDA = SCL = 0 V RRBFET Input RBFET On resistance (Q1) Charger active state, Measured between IN and CAP,VIN = 5 V 5 7 mA 45 90 mW 4.5 V -0.5 0.5 % -1 1 - BATTERY AND SYSTEM VOLTAGE REGULATION VCHG Output voltage range Programmable by I2C 3.3 Default value Voltage regulation accuracy Constant voltage mode, TA = 25C 3.6 I2C Programmable granularity 25 mV BATTERY VOLTAGE THRESHOLD VSAFE Safe charge threshold voltage VBAT rising 2.1 2.15 2.2 V VPRE Conditioning charge threshold voltage VFET = 3.1 V and 3.2 V 2.95 3 3.05 V VFET = 3.3 V, 3.4 V, 3.5 V and 3.6 V 3.15 3.2 3.25 9. Minimum transition time from states to states. http://onsemi.com 5 NCP1850 Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between -40C to +85C and TJ up to + 125C for VIN between 3.6 V to 7 V (Unless otherwise noted). Typical values are referenced to TA = + 25C and VIN = 5 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit 3.15 3.2 3.25 V 2 % BATTERY VOLTAGE THRESHOLD VFET End of weak charge threshold voltage VBAT rising Voltage range Default value Accuracy 3.4 -2 I2C Programmable granularity 100 mV VRECHG Recharge threshold voltage Relative to VCHG setting register 97 % VBUCKOV Overvoltage threshold voltage VBAT rising, relative to VCHG setting register, measured on SENSN or SENSP, QBAT close or no QBAT 115 % QBAT open. 5 V CHARGE CURRENT REGULATION Charge current range ICHG Programmable by I2C 400 Default value 950 Charge current accuracy I2C IPRE -50 Programmable granularity Pre-charge current 1000 1600 mA 1050 mA 50 mA 100 VBAT < VPRE 405 450 mA 495 mA ISAFE Safe charge current VBAT < VSAFE 8 10 12 mA IWEAK Weak battery charge current BATFET present, VSAFE < VBAT < VFET 80 100 120 mA 275 mA CHARGE TERMINATION IEOC Charge current termination VBAT VRECHG Current range 100 Default value Accuracy, IEOC < 200 mA 150 -25 I2C Programmable granularity 25 25 FLAG VFOL FLAG output low voltage IFLAG = 10 mA 0.5 V IFLEAK Off-state leakage VFLAG = 5 V 1 mA DIGITAL INPUT (VDG) VIH High-level input voltage 1.2 VIL Low-level input voltage RDG Pull down resistor IDLEAKK Input current VDG = 0 V -0.5 VSYSUV CAP pin supply voltage I2C registers available 2.5 VI2CINT* High level at SCL/SCA line VI2CIL SCL, SDA low input voltage VI2CIH SCL, SDA high input voltage V 0.4 500 V kW 0.5 mA I2C 1.7 0.8 * VI2CINT 9. Minimum transition time from states to states. http://onsemi.com 6 V 5 V 0.4 V V NCP1850 Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between -40C to +85C and TJ up to + 125C for VIN between 3.6 V to 7 V (Unless otherwise noted). Typical values are referenced to TA = + 25C and VIN = 5 V (Unless otherwise noted). Symbol Parameter Conditions VI2COL SCL, SDA low output voltage ISINK = 3 mA FSCL I2C clock frequency Min Typ Max Unit I2C 0.3 V 3400 kHz 150 C JUNCTION THERMAL MANAGEMENT TSD Thermal shutdown Rising 125 140 Falling 115 C -7 C TH2 Hot temp threshold 2 Relative to TSD TH1 Hot temp threshold 1 Relative to TSD -11 C TWARN Thermal warning Relative to TSD -15 C BATTERY THERMAL MANAGEMENT VNTCRMV VCOLD VHOT VNTCDIS VREG RNTCPU Battery removed threshold voltage Battery cold temperature corresponding voltage threshold VNTC Rising 2.3 2.325 2.4 BATCOLD[1:0]:00 1.775 1.8 1.825 BATCOLD[1:0]:01 1.7 1.725 1.75 BATCOLD[1:0]:10 1.625 1.65 1.675 BATCOLD[1:0]:11 1.55 1.575 1.6 V BATHOT[1:0]:00 800 825 850 BATHOT[1:0]:01 725 750 775 BATHOT[1:0]:10 650 675 700 BATHOT[1:0]:11 575 600 625 VNTC Falling 50 75 100 mV Internal voltage reference 2.35 2.4 2.45 V Internal resistor pull up 9.8 10 10.2 kW Switching Frequency - 3 - MHz Switching Frequency Accuracy -10 +10 % Battery hot temperature corresponding voltage threshold NTC disable corresponding voltage threshold mV BUCK CONVERTER FSWCHG TDTYC Max Duty Cycle Average 99.5 % IPKMAX Maximum peak inductor current 1.9 A RONLS Low side Buck MOSFET RDSON (Q3) Measured between PGND and SW, VIN = 5 V - 170 350 mW RONHS High side Buck MOSFET RDSON(Q2) Measured between CAP and SW, VIN = 5 V - 140 285 mW 5 5.5 V PROTECTED TRANSCEIVER SUPPLY VTRANS Voltage on TRANS pin ITRMAX TRANS current capability VIN 5 V 30 mA TIMING TWD Watchdog timer 32 s TUSB USB timer 2048 s 9. Minimum transition time from states to states. http://onsemi.com 7 NCP1850 Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between -40C to +85C and TJ up to + 125C for VIN between 3.6 V to 7 V (Unless otherwise noted). Typical values are referenced to TA = + 25C and VIN = 5 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit TIMING TCHG1 Charge timer TCHG2 TWU Safe-charge or pre-charge or weak-safe or weak- charge state. 3 h Full-charge state 2 h Wake-up timer 64 s VBAT rising 15 ms VBAT falling 127 ms TVRCHR Deglitch time for end of charge voltage detection TINDET Deglitch time for input voltage detection VIN rising 15 ms TDGS1 Deglitch time for signal crossing IEOC, VPRE, VSAFE, VCHGDET, VINEXT thresholds. Rising and falling edge 15 ms TDGS2 Deglitch time for signal crossing VFET, VBUSUV, VBUSOV thresholds. Rising and falling edge 1 ms From Weak Charge to Full Charge State 32 s From Wait to Charger active state 128 ms TSTWC TSTW Charger state timer (Note 9) From Weak Charge to Full Charge State, triggered on TST_SET level transition. TST TST_SET = 0 32 TST_SET = 1 16 ms 16 ms All others states 24 s BOOST CONVERTER AND OTG MODE VIBSTL Boost minimum input operating range VIBSTH Boost maximum input operating range 3.1 3.2 3.3 Boost running 2.9 3 3.1 4.4 4.5 4.6 5.1 5.15 V 3 % VOBST Boost Output Voltage DC value measured on CAP pin, no load 5.00 VOBSTAC Boost Output Voltage accuracy Measured on CAP pin Including line and load regulation -3 IBSTMX Output current capability FSWBST Switching Frequency 250 Maximum peak inductor current VOBSTOL Boost overload -10 MHz 10 1.9 Boost running, voltage on IN pin 4.3 V mA 1.5 Switching Frequency Accuracy IBPKM V Boost start-up 4.4 % A 4.5 V TOBSTOL Maximum capacitance on IN pin during start-up 10 mF ROBSTOL Maximum load on IN pin during start-up 50 W VOBSTOV Overvoltage protection VIN rising 5.55 5.65 5.75 V Hysteresis 25 75 125 mV 9. Minimum transition time from states to states. http://onsemi.com 8 NCP1850 BLOCK DIAGRAM CCAP 4.7mF CAP VCAP IN VBUS D+ D- GND CBOOT CIN Q1 Charge Pump 1mF VCORE CBOOT Drv Q2 10nF VCAP IINREG 5V reference VREG VCORE CORE Current, Voltage, and Clock Reference ICHG SW PWM generator CCORE Drv VTJ VCHG Q3 LX VCORE 2.2mF 2.2mF Drv TRANS CTRS PGND + IEOC VTJ + 0.1mF + TWARN - RSNS + Amp - 68mW SENSN + WEAK - V RECHG + + ICHG - V BATOV TH2 - TH1 - SENSP + TSD - USB PHY VBAT - I BAT I2C & DIGITAL CONTROLER + - V FET QBAT* + CSYS - VPRE OTG 10mF + - ILIM VSAFE BAT INTB DRV + VIN + VINDET - + VBUSUV - + VBUSOV AGND VINOV VBAT - VRMOVED + - BATFET detection & Drive VREG RNTCPU + VHOT - - + NTC VCOLD - + FET SPM VNTCDIS - + - DRV FLAG SCL VCHGDET + SDA * Optional Figure 2. Block Diagram http://onsemi.com 9 + NCP1850 TYPICAL APPLICATION CIRCUITS LX 2.2mH VBUS D+ D- ID GND CIN IN CBOOT CAP COUT 10mF 10nF SENSP WEAK FET CORE 2.2mF QBAT(*) BAT NTC CTRANS SYSTEM SENSN 4.7mF CCORE RSNS 68mW CBOOT NCP1850 1mF CCAP SW + TRANS 100nF FLAG SCL AGND SDA PGND SPM ILIM INTB OTG Figure 3. USB Charger with Battery External MOSFET LX VBUS D+ D- ID GND CIN CBOOT CAP 4.7mF CCORE 2.2mF CBOOT NCP1850 1mF CCAP SW IN SYSTEM 10nF SENSP RSNS SENSN 68mW WEAK CORE CSYS FET + 2.2mF 10mF BAT NTC CTRANS TRANS 100nF FLAG SCL AGND PGND SDA SPM ILIM INTB OTG Figure 4. USB Charger without Battery External MOSFET http://onsemi.com 10 NCP1850 CHARGE MODE OPERATION The NCP1850 is fully programmable through I2C interface (see Registers Map section for more details). All registers can be programmed by the system controller at any time during the charge process. The charge current (ICHG), charge voltage (VCHG), and input current (IINLIM) are controlled by a dynamic voltage and current scaling for disturbance reduction. Is typically 10 ms for each step. NCP1850 also provides USB OTG support by boosting the battery voltage as well as an over voltage protected power supply for USB transceiver. Overview The NCP1850 is a fully programmable single cell Lithium-ion switching battery charger optimized for charging from a USB compliant input supply. The device integrates a synchronous PWM controller; power MOSFETs, and monitoring the entire charge cycle including safety features under software supervision. An optional battery FET can be placed between the system and the battery in order to isolate and supply the system in case of weak battery. The NCP1850 junction temperature and battery temperature are monitored during charge cycle and current and voltage can be modified accordingly through I2C setting. The charger activity and status are reported through a dedicated pin to the system. The input pin is protected against overvoltages. Charge Profile In case of application without QFET (see Figure 4), the NCP1850 provides four main charging phases as described below. Unexpected behavior or limitations that can modify the charge sequence are described further (see Charging Process section). VBAT IBAT VCHG VRECHG ICHG IPRE VPRE IEOC ISAFE VSAFE Safe Charge Pre Charge Constant Current Constant Voltage End of Charge Figure 5. Typical Charging Profile of NCP1850 current. The battery stays in preconditioning until the VBAT voltage is lower than VPRE threshold. Constant Current (full charge): In the constant current phase (full charge state), the DC-DC convertor is enabled and an ICHG current is delivered to the load. As battery voltage could be sufficient, the system may be awake and sink an amount of current. In this case the charger output load is composed of the battery and the system. Thus ICHG current delivered by the NCP1850 is shared between the battery and the system: ICHG = ISYS + IBAT. Safe Charge: With a disconnected battery or completely empty battery, the charge process is in safe charge state, the charge current is set to ISAFE in order to charge up the system's capacitors or the battery. When the battery voltage reaches VSAFE threshold, the battery enters in pre-conditioning. Pre Conditioning (pre-charge): In preconditioning (pre charge state), the DC-DC convertor is enabled and an IPRE current is delivered to the battery. This current is much lower than the full charge http://onsemi.com 11 NCP1850 System awake VBAT VCHG VRECHG ICHG IBAT VBAT IBAT IPRE ISYS VPRE IEOC ISAFE VSAFE Safe Charge Pre Charge Constant Current Constant Voltage End of Charge Figure 6. Typical Charging Profile of NCP1850 with System Awake ICHG current is programmable using I2C interface (register IBAT_SET - bits ICHG[3:0]). measured input current and output voltage are below the programmed limit and asking for more power. But in the same time, the measured output current is at the programmed limit and thus regulates the DC-DC converter. In order to prevent battery discharge and overvoltage protection, Q1(reverse voltage protection) and Q2 (high side N-MOSFET of the DC-DC converter) are mounted in a back-to-back common drain structure while Q3 is the low side N MOSFET of the DC-DC converter. Q2 gate driver circuitry required an external bootstrap capacitor connected between CBOOT pin and SW pin. An internal current sense monitors and limits the maximum allowable current in the inductor to IPEAK value. Constant Voltage (full charge): The constant voltage phase is also a part of the full charge state. When the battery voltage is close to its maximum (VCHG), the charge circuit will transition from a constant current to a constant voltage mode where the charge current will slowly decrease (taper off). The battery is now voltage controlled. VCHG voltage is programmable using I2C interface (register VBAT_SET- bits CTRL_VBAT[5:0]). End of Charge: The charge is completed (end of charge state) when the battery is above the VRECHG threshold and the charge current below the IEOC level. The battery is considered fully charged and the battery charge is halted. Charging is resumed in the constant current phase when the battery voltage drops below the VRECHG threshold. IEOC current is programmable using I2C interface (register IBAT_SET- bits IEOC[2:0]). The charge cycle can also be halted manually through I2C (register CRTL2 bit CHG_HALT=1). Charger Detection, Start-up Sequence and System Off The start-up sequence begins upon an adaptor valid voltage plug in detection: VIN > VINDET and VIN - VBAT > VCHGDET (off state). Then, the internal circuitry is powered up and the presence of NTC and BATFET are reported (register STATUS - bit BATFET and NTC). When the power-up sequence is done, the charge cycle is automatically launched. At any time and any state, the user can holds the charge process and transit to fault state by setting CHG_EN to `0' (register CTRL1) in the I2C register. Furthermore, during fault state, NTC block can be disabled for power saving (bit NTC_EN register CTRL1) The I2C registers are accessible without valid voltage on VIN if VCAP > VSYSUV (i.e. if VBAT is higher than VSYSUV + voltage drop across Q2 body diode). At any time, the user can reset all register stack (register CTRL1 - bit REG_RST). Power Stage Control NCP1850 provides a fully-integrated 3 MHz step-down DC-DC converter for high efficiency. For an optimized charge control, three feedback signals controls the PWM duty cycle. These three loops are: maximum input current (IINLIM), maximum charge current (ICHG) and, maximum charge voltage (VCHG). The switcher is regulated by the first loop that reaches its corresponding threshold. Typically during charge current phase (VPRE < VBAT < VRECHG), the http://onsemi.com 12 NCP1850 Weak Battery Support Weak Wait An optional battery FET (QBAT) can be placed between the application and the battery. In this way, the battery can be isolated from the application and so-called weak battery operation is supported. Typically, when the battery is fully discharged, also referred to as weak battery, its voltage is not sufficient to supply the application. When applying a charger, the battery first has to be pre-charged to a certain level before operation. During this time; the application is supplied by the DC-DC converter while integrated current sources will pre-charge the battery to the sufficient level before reconnecting. The pin FET can drive a PMOS switch (QBAT) connected between BAT and WEAK pin. It is controlled by the charger state machine (Charging process section). The basic behavior of the FET pin is that it is always low. Thus the PMOS is conducting, except when the battery is too much discharged at the time a charger is inserted under the condition where the application is not powered on. The FET pin is always low for BAT above the VFET threshold. Some exceptions exist which are described in the Charging Process and Power Path Management section. The VFET threshold is programmable (register MISC_SET - bit CTRL_VFET). Weak wait state is entered from wait state (see Charging process section) in case of BATFET present, battery voltage lower than VFET and host system in shutdown mode (SPM = 0). The DCDC converter from VIN to SW is enabled and set to VCHG while the battery FET QBAT is opened. The system is now powered by the DC-DC. The internal current source to the battery is disabled. In weak wait state, the state machine verifies if the battery temperature is OK thanks to the NTC sensor. If NTC OK or if NTC is not present (NTC pin tied to 0), this state is left for weak safe state. In case of no battery, the NCP1850 stay in weak wait state (the system is powered by DC-DC). Weak Safe The voltage at VBAT, is below the VSAFE threshold. In weak safe state, the battery is charged with a linear current source at a current of ISAFE. The DC-DC converter is enabled and set to VCHG while the battery FET QBAT is opened. In case the ILIM pin is not made high or the input current limit defeated by I2C before timer expiration, the state is left for the safe charge state after a certain amount of time (see Wake up Timer section). Otherwise, the state machine will transition to the weak charge state once the battery is above VSAFE. Batfet Detection Weak Charge The presence of a PMOS (QBAT) at the FET pin is verified by the charging process during its config state. To distinguish the two types of applications, in case of no battery FET the pin FET is to be tied to ground. In the config state an attempt will be made to raise the FET pin voltage slightly up to a detection threshold. If this is successful it is considered that a battery FET is present. The batfet detection is completed for the whole charge cycle and will be done again upon unplug condition (VBAT < VINDET or VIN - VBAT < VCHGDET) or register reset (register CTRL1- bit REG_RST). The voltage at VBAT, is above the VSAFE threshold. The DC-DC converter is enabled and set to VCHG. The battery is initially charged at a charge current of IWEAK supplied by a linear current source from WEAK pin (i.e. DC-DC converter) to BAT pin. IWEAK value is programmable (register MISC_SET bits IWEAK). The weak charge timer (see Wake up Timer section) is no longer running. When the battery is above the VFET threshold (programmable), the state machine transitions to the full charge state thus BATFET QBAT is closed. http://onsemi.com 13 NCP1850 VBAT IOUT VCHG ICHG VRECHG VSYS IBAT IWEAK VBAT VFET IBAT ISYS IEOC ISAFE VSAFE Weak Wait Weak Safe Weak Charge Constant Current Constant Voltage End of Charge Figure 7. Weak Charge Profile In some application cases, the system may not be able to start in weak charge states due to current capability limitation or/and configuration of the system. If so, in order to avoid unexpected "drop and retry" sequence of the buck output, the charge state machine allows only three system power-up sequences based on SPM pin level: If SPM pin level is toggled three times during weak charge states, the system goes directly to safe charge state and a full charge mode sequence is initiated ("Power fail" condition in Charging process section). safety timer (Watchdog timer, Charge timer, Wakeup timer and USB timer) are detailed below. When a timer expires (condition "timeout" in Charging process section), the charge process is halted. Watchdog Timer Watchdog timer ensures software remains alive once it has programmed the IC. The watchdog timer is no longer running since I2C interface is not available. Upon an I2C write, automatically a watchdog timer TWD is started. The watchdog timer is running during charger active states and fault state. Another I2C write will reset the watchdog timer. When the watchdog times out, the state machine reverts to fault state and reported through I2C interface (register CHINT2- bit WDTO). Also used to time out the fault state. This timer can be disabled (Register CTRL2 bit WDTO_DIS). Power Path Management Power path management can be supported when a battery FET (QBAT) is placed between the application and the battery. When the battery is fully charged (end of charge state), power path management disconnects the battery from the system by opening QBAT, while the DC-DC remains active. This will keep the battery in a fully charged state with the system being supplied from the DC-DC. If a load transient appears exceeding the DC-DC output current and thus causing VSENSEN to fall below VRECHG, the FET QBAT is instantaneously (Within TPPM, see Electrical Characteristics) closed to reconnect the battery in order to provide enough current to the application. The FET QBAT remains closed until the end of charge state conditions are reached again or manually set through I2C (register CRTL2 bit CHG_HALT = 1) . The power path management function is enabled through the I2C interface (register CRTL2 bit PWR_PATH = 1). Charge Timer A charge timer TCHG is running that will make that the overall charge to the battery will not exceed a certain amount of energy. The charge timer is running during charger active states and halted during charger not active states (see Charging process section). The timer can also be cleared any time through I2C (register CTRL1 - bit TCHG_RST). The state machine transitions to fault state when the timer expires. This timer can be disabled (Register CTRL2 bit CHGTO_DIS). USB Timer A USB charge timer TUSB is running in the charger active states while halted in the charger non active states. The timer keeps running as long as the lowest input current limit Safety Timer Description The safety timer ensures proper and safe operation during charge process. The set and reset condition of the different http://onsemi.com 14 NCP1850 remains selected either by ILIM pin or I2C (register I_SET - bit IINLIM and IINLIM_EN). This will avoid exceeding the maximum allowed USB charge time for un-configured connections. When expiring, the state machine will transition to fault state. The timer is cleared in the off state or by I2C command (register CTRL1 - bit TCHG_RST). Input current limitation In order to be USB specification compliant, the input current at VIN is monitored and could be limited to the IINLIM threshold. The input current limit threshold is selectable through the ILIMx pin. When low, the one unit USB current is selected (IIN 100 mA), where when made high 5 units are selected (IIN 500 mA). In addition, this current limit can be programmed through I2C (register MISC_SET bits IINLIM) therefore defeating the state of the ILIMx pin. In case of non-limited input source, current limit can be disabled (register CTRL2 bit IINLIM_EN). The current limit is also disabled in case the input voltage exceeds the VBUSOV threshold. Wake up Timer Before entering weak charge state, NCP1850 verifies if the input current available is enough to supply both the application and the charge of the battery. A wake-up timer TWU verifies if ILIM pin is raised fast enough or application powered up (by monitoring register I_SET - bit IINLIM and IINLIM_EN level) after a USB attachment. The wake up timer is running in weak wait state and weak safe state and clears when the input current limit is higher than 100 mA. IBAT VBAT VCHG VRECHG ICHG IPRE VPRE IEOC ISAFE VSAFE Safe Charge Pre Charge Constant Current Constant Voltage End of Charge Figure 8. Typical Charging Profile of NCP1850 with Input Current Limit Input Voltage Based Automatic Charge Current `1' (register NTC_TH_SENSE). Knowing this, the user is free to halt the charge (register CTRL - bit CHG_EN) or reduce the charge current (register I_SET - bits ICHG). When chip temperature reaches TSD value, the charge process is automatically halt. Between TWARN and TSD threshold, a junction temperature management option is available by setting 1 to TJ_WARN_OPT bit (register CONTROL). In this case, if the die temperature hits TM1 threshold, an interrupt is generated again but NCP1850 will also reduce the charge current ICHG by two steps or 200 mA. This should in most cases stabilize the die temperature because the power dissipation will be reduced by approximately 50 mW. If the die temperature increases further to hit TM2, an interrupt is generated and the charge current is reduced to its lowest If the input power source capability is unknown, automatic charge current will automatically increase the charge current step by step until the VIN drops to VBUSUV. Upon VBUSUV being triggered, the charge current ICHG is immediately reduced by 1 step and stays constant until VIN drops again to VBUSUV. The ICHG current is clamped to the I2C register value (register IBAT_SET, bits ICHG). This unique feature is enabled through I2C register (register CRTL2 bit AICL_EN). Junction temperature management During the charge process, NCP1850 monitors the temperature of the chip. If this temperature increases to TWARN, an interrupt request (described in section Charge status reporting) is generated and bit TWARN_SNS is set to http://onsemi.com 15 NCP1850 Regulated Power Supply (Trans pin) level or 400mA. The initial charge current will be re-established when the die temperature falls below the TWARN again. If bit TJ_WARN_OPT = 0 (register CTRL1), the charge current is not automatically reduced, no current changes actions are taken by the chip until TSD. NCP1850 has embedded a linear voltage regulator (VTRANS) able to supply up to ITRMAX to external loads. This output can be used to power USB transceiver. Trans pin is enabled if a VBUS valid is connected on input pin (VBUSUV < VIN < VBUSOV) and can be disabled through I2C (bit TRANS_EN_REG register CTRL2). A current limiter protects the IC in case of short circuit on TRANS pin. Battery Temperature Management For battery safety, charging is not allowed for too cold or too hot batteries. The battery temperature is monitored through a negative temperature coefficient (NTC) thermistor mounted in the battery pack or on the phone PCB close to the battery pack. In some cases the NTC is handled by the platform and will not be connected to the charger IC. NCP1850 provides a NTC pin for monitoring an external NTC thermistor. NTC pin is connected to an internal voltage VREG through pull-up resistor (RNTCPU). By connecting a NTC thermistor between NTC pin and GND, internal comparators can monitors voltage variation and provides temperature information to the state machine. Charge Status Reporting Charge Status on FLAG Pin FLAG pin is used to report charge status to the system processor and also for interruption request. During charger active states and wait state, the pin FLAG is low in order to indicate that the charge of the battery is in progress. When charge is completed or disabled or a fault occurs, the FLAG pin is high as the charge is halted. Interruption on FLAG pin Upon any state or status change, the system controller can be informed by sensing FLAG pin. A TFLAGON pulse is generated on this pin in order to signalize all events listed in the STAT_INT, CH1_INT, CH2_INT, BST_INT registers. All these bits are read to clear. The register map indicated the active transition of each bits (column "TYPE" Register Map section). If more than 1 interrupt appears, only 1 pulse is generated while interrupt registers (STAT_INT, CH1_INT, CH2_INT, BST_INT) will not fully clear. The level of this pulse depends on the state of the charger (see Charging process section): - When charger in is charger active states and wait state the FLAG is low and consequently the pulse level on FLAG pin is high. - In the others states, the pulse level is low as the FLAG stable level is high. This Pulse can be globally masked due to the INT_FLG_MASK bit (Register CTRL1). VREG RNTCPU + - V RMOVED + - V COLD + - - + - + - + NTC VCHILLY + VWARM VHOT VNTCDIS NCP1850 Figure 9. NTC Monitoring Circuit Interruption on INTB Pin Two thresholds `cold' and `hot' are provided those are programmable. The corresponding voltage levels of these thresholds are respectively VCOLD and VHOT. Interrupts (describe in section Charge status reporting) are generated when crossing either threshold. The charge is halted outside the cold-hot window. In addition to the above, comparators monitor the NTC presence. When the NTC is removed (VNTC > VNTCRMV) , no more charge current is supplied to the battery and an interrupt is generated (describe in section Charge status reporting). This functionality can be disabled through programming (bit NTC_EN in register CTRL1). When the NTC is not used in the application the NTC pin can be tied to ground (VNTC < VNTCDIS) which will disable the battery temperature monitoring function. Upon any state or status change, the system controller can be informed by sensing INTB pin. This pin is tied low in order to signalize all events listed in the STAT_INT, CH1_INT, CH2_INT, BST_INT registers and can be individually masked with the corresponding mask bits in registers STAT_MSK, CH1_MSK, CH2_MSK and BST_MSK. All interrupt signals on INTB pin can be masked with the global interrupt mask bit (bit INT_MASK register CTRL1). All these bits are read to clear. The register indicated the active transition of each bits (column "TYPE" Register Map section). http://onsemi.com 16 NCP1850 If more than 1 interrupt appears, the INTB pin stay low while interrupt registers (STAT_INT, CH1_INT, CH2_INT, BST_INT) will not fully clear. If the battery is equipped with an NTC its removal is detected (VNTC > VNTCRMV) and the state machine transits to fault state and an interrupt is generated (bit BATRMV register CH1_INT). Then, in case of applications with BATFET, the state machine will end up in weak wait state so the system is powered by the DC-DC converter (see Weak Wait section) without battery. In case of application without BATFET, the state machine will end up in fault state (DC-DC off) so the system is not powered. With a battery pack without NTC support, the voltage at VBAT will rapidly reach the DCDC converter setting VCHG and then transition to end of charge state causing DC-DC off. Thus VBAT falls ("Battery fail" condition in Charging Process section). STATUS and CONTROL Registers The status register contains the current charge state, NTC and BATFET connection as well as fault and status interrupt (bits INT_REG in register STATUS). The charge state (bits STATE in register STATUS) is updated on the fly and corresponds to the charging state describe in Charging Process section. An interruption (see description below) is generated upon a state change. In the config state, hardware detection is performed on BAFTET and NTC pins. From wait state, their statuses are available (bit BATFET and NTC in register STATUS). INT_REG bits are different to 0 if an interruption appears (see description below). Thanks to this register, the system controller knows the chip status with only one I2C read operation. If a fault appears or a states change the controller can read corresponding registers for more details. Factory Mode During factory testing no battery is present in the application and a supply could be applied through the bottom connector to power the application. The state machine will support this mode of operation under the condition that the application includes a battery FET and uses batteries with NTC support (similar as no battery operation). In this case, the state machine will end up in weak wait state (see Weak Wait section). The application is supplied while the absence of the battery pack is interpreted as a battery pack out of temperature (VNTC > VCOLD). Through I2C the device is entirely programmable so the controller can configure appropriate current and voltage threshold for handle factory testing. Factory regulation mode (Register MISC_SET Bit FCTRY_MOD_REG) is accessible for factory testing purpose. In this mode, input and charge current loops are disabled, allowing full power to the system. Sense and Status Registers At any time the system processor can know the status of all the comparators inside the chip by reading VIN_SNS, VBAT_SNS, and TEMP_SNS registers (read only). These bits give to the system controller the real time values of all the corresponding comparators outputs (see BLOCK DIAGRAM). Battery Removal and No Battery Operation During normal charge operation the battery may bounce or be removed. The state transition of the state machine only occurs upon deglitched signals which allow bridging any battery bounce. True battery removal will last longer than the debounce times. The NCP1850 responses depend on NTC and BATFET presence: http://onsemi.com 17 NCP1850 CHARGING PROCESS CHARGER ACTIVE: WEAK CHARGE MODE CHARGER NOT ACTIVE MODE WEAK WAIT - BUCK: ON - IWEAK : OFF - ISAFE: OFF - FLAG : LOW - QFET: OFF VCAP > VSYSUV OFF -VIN < VINDET or -VIN - VBAT < VCHGDET - Charger OFF IQ < IOFF - I@C available Halt Charging : VNTC > VCOLD or VNTC < VWARM Start Charging : VNTC < VCOLD or VNTC > VWARM ANY STATE WEAK SAFE -VIN > VINDET and -VIN - VBAT > VCHGDET Batfet present and VBAT < VFET and SPM = 0 REG_RST = 1 CONFIG - BUCK: ON - IWEAK : OFF - ISAFE: ON - FLAG : LOW - QFET: OFF - Power-up - NTC and BATFET detection - Q1: ON VNTC > VCOLD or VNTC < VWARM or VBAT > VSAFE VBAT > VSAFE and w IINLIM 500mA WEAK CHARGE -VIN > VINOV or -VBAT >VBUCKOV or - Timeout or -Power fail or -TJ >TSD or -CHR_EN = 0 Power-up and detection done Fault removed and CHR_EN = 1 WAIT - BUCK: OFF - IWEAK : OFF - ISAFE: OFF - FLAG : LOW - QFET: ON - BUCK: ON - IWEAK : ON - ISAFE: OFF - FLAG : LOW - QFET: OFF -Timeout -TJ >TSD or -VIN > VINOV or -VBAT >VBATOV or -CHR_EN = 0 FAULT -BUCK: OFF -IWEAK : OFF -ISAFE: OFF -FLAG : HIGH -QFET: ON -Timeout -TJ >TSD or -VIN > VINOV or -VBAT >VBUCKOV or -VNTC > VNTCRMV or -CHR_EN = 0 -TJ >TSD or -VIN > VINOV or -VNTC > VNTCRMV or -CHR_EN = 0 END OF CHARGE - BUCK: OFF* - IWEAK : OFF - ISAFE: OFF - FLAG : HIGH - QFET: ON* VBAT >VFET FULL CHARGE - BUCK: ON - IWEAK :OFF - ISAFE: OFF - FLAG : LOW - QFET: ON -VBAT < VRECHG -VBAT > VRECHG and -( BAT < IEOC or CHG_HALT) VBAT > VPRE VBAT < VPRE -VBAT > VRECHG and - (IBAT < IEOC or CHG_HALT) -VSENSN < VRECHG and - pwr_path = 1 PRE CHARGE - BUCK: ON (precharge) - IWEAK :OFF - ISAFE: OFF - FLAG : LOW - QFET: ON -VBAT < VRECHG DPP Halt Charging : VNTC > VCOLD or VNTC < VWARM or Battery fail - BUCK: ON - IWEAK : OFF - ISAFE: OFF - FLAG : HIGH - QFET: ON VBAT > VSAFE VBAT < VSAFE Timeout SAFE CHARGE - BUCK: OFF - IWEAK : OFF - ISAFE: ON - FLAG : LOW - QFET: ON Start Charging : VCOLD > VNTC > VWARM CHARGER ACTIVE: FULL CHARGE MODE * See Power Path Management section. Figure 10. Detailed Charging Process http://onsemi.com 18 NCP1850 Boost Mode Operation turns off the PWM converter. A fault is indicated to the system controller (bit VBATLO register BST_INT) A toggle on OTG pin or OTG_EN bit (register CTRL1) is needed to start again a boost operation. The DC-DC Converter can also be operated in a Boost mode where the application voltage is stepped up to the input VIN for USB OTG supply. The converter operates in a 1.5 MHz fixed frequency PWM mode or in pulse skipping mode under low load condition. In this mode, where CAP is the regulated output voltage, Q3 is the main switch and Q2 is the synchronous rectifier switch. While the boost converter is running, the Q1 MOSFET is fully turned ON. Boost Status Reporting STATUS and CTRL registers The status register contains the boost status. Bits STATE in register STATUS gives the boost state to the system controller. Bits FAULTINT and STATINT in register STATUS are also available in boost mode. If a fault appears or a status changes (STATINT bits and FAULTINT) the processor can read corresponding registers for more details. Interruption In boost mode, valid interrupt registers are STAT_INT and BST_INT while CH1_INT and CH2_INT are tied to their reset value. Upon a state or status changes, the system controller is informed by sensing FLAG or INTB pins. Like in charge mode, TFLAGON pulse is generated on FLAG pin and low level is applied on INTB pin in order to signalize the event. The pulse level is low as the FLAG level is high in boost mode. Charge state transition even and all signals of register BST_INT can generate an interrupt request on INTB pin and can be masked with the corresponding mask bits in register BST_MSK. All these bits are read to clear. The register map indicates the active transition of each bits (column "TYPE" in see Register Map section). If more than one interrupt appears, INTB stay low while interrupt registers (listed just above) will not fully clear. Sense and status registers At any time the system controller can know the status of all the comparator inside the chip by reading VIN_SNS and TEMP_SNS registers (read only). These bits give to the controller the real time values of all the corresponding comparators outputs (see BLOCK DIAGRAM). Boost Start-up The boost mode is enabled through the OTG pin or I2C (register CTRL1 - bit OTG_EN). Upon a turn on request, the converter regulates CAP pin, and the output voltage is present on IN pin through the Q1 MOSFET which is maintained close unless OVLO event. During start-up phase, if the IN pin cannot reach voltage higher than 4.65V within 16ms, then a fault is indicated to the system controller (bit VBUSILIM register BST_INT) and the boost is turns-off. VIN Over-Voltage Protection The NCP1850 contains integrated over-voltage protection on the VIN line. During boost operation (VIN supplied), if an over-voltage condition is detected (VIN > VBUSOV), the controller turns off the PWM converter. OTG_EN bit (register CTRL1) is set to 0 and a fault is indicated to the system controller (bit VBUSOV register BST_INT) VIN Over-Current Protection The NCP1850 contains over current protection to prevent the device and battery damage when VIN is overloaded. When the IN voltage drops down to VBUSUV, NCP1850 determine an over-current condition is met, so Q1 MOSFET and PWM converter are turned off. A fault is indicated to the system controller (bit VBUSILIM register BST_INT). Battery Under-Voltage Protection During boost mode, when the battery voltage is lower than the battery under voltage threshold (VBAT < VIBSTL), the IC http://onsemi.com 19 NCP1850 I2C description NCP1850 can support a subset of I2C protocol, below are detailed introduction for I2C programming. FROM MCU to NCPxxxx FROM NCPxxxx to MCU START IC ADRESS 1 ACK 0 ACK DATA 1 ACK DATA n /ACK STOP READ OUT FROM PART STOP WRITE INSIDE PART 1 a READ /ACK START IC ADRESS DATA 1 ACK DATA n ACK If PART down not Acknowledge, the /NACK will be followed b a STOP or Sr If PART Acknowledges, the ACK can be followed by another data or Stop or Sr 0 a WRITE Figure 11. General Protocol Description The first byte transmitted is the Chip address (with LSB bit sets to 1 for a read operation, or sets to 0 for a Write operation). Then the following data will be: - In case of a Write operation, the register address (@REG) we want to write in followed by the data we will write in the chip. The writing process is incremental. So the first data will be written in @REG, the second one in @REG + 1 . The data are optional. - In case of read operation, the NCP1850 will output the data out from the last register that has been accessed by the last write operation. Like writing process, reading process is an incremental process. Read Out from Part The Master will first make a "Pseudo Write" transaction with no data to set the internal address register. Then, a stop then start or a Repeated Start will initiate the read transaction from the register address the initial write transaction has set: FROM MCU to NCPxxxx FROM NCPxxxx to MCU STETS INTERNAL REGISTER POINTER START IC ADRESS 0 ACK REGISTER ADRESS ACK STOP 0 a WRITE START IC ADRESS 1 ACK ACK DATA 1 REGISTER ADRESS VALUE DATA n /ACK STOP REGISTER ADRESS + (n - 1) VALUE n REGISTERS READ 1 a READ Figure 12. Read Out from Part The first WRITE sequence will set the internal pointer on the register we want access to. Then the read transaction will start at the address the write transaction has initiated. Write in Part: Write operation will be achieved by only one transaction. After chip address, the MCU first data will be the internal register we want access to, then following data will be the data we want to write in Reg, Reg + 1, Reg + 2, ., Reg +n. http://onsemi.com 20 NCP1850 Write n Registers: FROM MCU to NCPxxxx FROM NCPxxxx to MCU SETS INTERNAL REGISTER POINTER START IC ADRESS 0 ACK WRITE VALUE IN REGISTER REG + (n-1) WRITE VALUE IN REGISTER REG0 ACK REGISTER REG0 ADRESS ACK REG VALUE ACK REG + (n-1) VALUE STOP n REGISTERS WRITE 0 a WRITE Figure 13. Write in n Registers I2C Address NCP1851 has fixed I2C but different I2C address (0$10, 7 bit address, see below table A7~A1), NCP1851 supports 7-bit address only. Table 5. NCP1850 I2C ADDRESS I2C Address (Note 10) Default Hex A7 A6 A5 A4 A3 A2 A1 A0 $6C / $6D 0 1 1 0 1 1 0 X 10. Other addresses are available upon request. Table 6. REGISTERS MAP Bit Type Reset Name RST Value Function STATUS REGISTER - Memory Location: 00 7-4 R No_Reset STATE[3:0] 0000 Charge mode: -0000: OFF -0001: WAIT + STBY -0010: SAFE CHARGE -0011: PRE CHARGE -0100: FULL CHARGE -0101: VOLTAGE CHARGE -0110: CHARGE DONE -0111: DPP -1000: WEAK WAIT -1001: WEAK SAFE -1010: WEAK CHARGE -1011: FAULT Boost mode: -1100: BOOST WAIT(s_WAIT) -1101: BOOST MODE (s_ON) -1110: BOOST FAULT( s_FAULT) -1111: BOOST OVER LOAD (s_OL)) 3 R No_Reset BATFET 0 Indicate if a batfet is connected: 0: No BATFET is connected 1: BATFET is connected. 2 R No_Reset NTC 0 Indicate if a ntc resistor is present: 0: No NTC connected 1: NTC connected 1 R No_Reset STATINT 0 Status interrupt: 0: No status interrupt 1: Interruption flagged on STAT_INT register 0 R No_Reset FAULTINT 0 Fault interrupt: 0: No status interrupt 1: interruption flagged on CHRIN1, CHRIN2 or BST_INT register REG_RST 0 Reset: 0: No reset 1: Reset all registers CTRL1 REGISTER - Memory Location: 01 7 RW OFF STATE, POR, REG_RST http://onsemi.com 21 NCP1850 Table 6. REGISTERS MAP Bit Type Reset Name RST Value Function CTRL1 REGISTER - Memory Location: 01 6 RW OFF STATE, POR, REG_RST CHG_EN 1 Charge control: 0: Halt charging (go to fault state) or OTG operation 1: Charge enabled / Charge resume 5 RW OFF STATE, POR, REG_RST, CHGMODE OTG_EN 0 On the go enable: 0: no OTG operation 1: OTG operation (set by I2C or OTG pin) 4 RW OFF STATE, POR, REG_RST NTC_EN 1 ntc pin operation enable: 0:Battery temperature ignore, 1: Battery temperature modify the charge profile. 3 RW OFF STATE, POR, REG_RST TJ_WARN_OPT 0 Enable charge current vs Junction temperature 0: No current change versus junction temperature 1: Charge current is reduced when TJ is too high. 2 RW OFF STATE, POR, REG_RST CHG_HALT 0 Force End of Charge 0: Normal End of charge condition 1: Force EOC condition if VBAT > VRECHG 1 RW OFF STATE, POR, REG_RST, TRM_RST TCHG_RST 0 Charge timer reset: 0: no reset 1: Reset and resume charge timer (tchg timer)(self clearing) 0 RW OFF STATE, POR, REG_RST INT_MASK 1 INTB global interrupt mask 0: All Interrupts can be active. 1: All interrupts are not active CTRL2 REGISTER - Memory Location: 02 7 RW OFF STATE, POR, REG_RST, OTGMODE WDTO_DIS 0 Disable watchdog timer 0: Watchdog timer enable 1: Watchdog timer disable 6 RW OFF STATE, POR, REG_RST, OTGMODE CHGTO_DIS 0 Disable charge timer 0: Charge timer enable 1: Charge timer disable 5 RW OFF STATE, POR, REG_RST, OTGMODE PWR_PATH 0 Power Path Management: 0: Power Path disable 1: Power Path enable 4 RW OFF STATE, POR, REG_RST TRANS_EN_REG 1 Trans pin operation enable: 0 : Trans pin is still off 1 : Trans pin is supply 3 RW OFF STATE, POR, REG_RST INT_FLG_MASK 1 FLAG global interrupt mask 0 : All Interrupts are active. 1 : All interrupts are not active 2 RW OFF STATE, POR, REG_RST, OTGMODE IINSET_PIN_EN 1 Enable input current set pin: 0: Input current limit and AICL control by I2C 1: Input current limit and AICL control by pins ILIMx 1 RW OFF STATE, POR, REG_RST, OTGMODE IINLIM_EN 1 Enable input current limit: 0: No input current limit 1: Input current limit is IINLIM[3:0] 0 RW OFF STATE, POR, REG_RST, OTGMODE AICL_EN 0 Enable automatic charge current: 0: No AICL 1: AICL 0 0: Silicon temperature is below TWARN threshold 1: Silicon temperature is above TWARN threshold STAT_INT REGISTER - Memory Location: 03 7-6 R No_Reset Reserved 5 RCDual OFF STATE, POR, REG_RST TWARN http://onsemi.com 22 NCP1850 Table 6. REGISTERS MAP Bit Type Reset Name RST Value Function STAT_INT REGISTER - Memory Location: 03 4 RCDual OFF STATE, POR, REG_RST TM1 0 0: Silicon temperature is below T1 threshold 1: Silicon temperature is above T1 threshold 3 RCDual OFF STATE, POR, REG_RST TM2 0 0: Silicon temperature is below T2 threshold 1: Silicon temperature is above T2 threshold 2 RCDual OFF STATE, POR, REG_RST TSD 0 0: Silicon temperature is below TSD threshold 1: Silicon temperature is above TSD threshold 1 R No_Reset RESERVED 0 RCDual OFF STATE, REG_RST, POR, OTGMODE VBUSOK 0 0 0: changer not in USB range 1: charger in USB charging range VBUSUV < VIN < VBUSOV CH1_INT REGISTER - Memory Location: 04 R No_Reset RESERVED 0 4 RCDual OFF STATE, REG_RST, POR, OTGMODE VINLO 0 VIN changer detection interrupt: 1: VIN - VBAT > VCHGDET and VIN < VINDET 3 RCDual OFF STATE, REG_RST, POR, OTGMODE VINHI 0 VIN over voltage lock out interrupt: 1: VIN > VINOV 2 RCDual OFF STATE, REG_RST, POR, OTGMODE BATRMV 0 battery temp out of range interrupt: 1: VNTC > VNTCRMV 1 RCDual OFF STATE, REG_RST, POR, OTGMODE BUCKOVP 0 VBAT over voltage interrupt: 1: VBAT > VOVP 0 R No_Reset CHINT2 0 charger related interrupt (CH2_INT register) Battery Temperature exceeds NTC HOT threshold 7-5 CH2_INT REGISTER - Memory Location: 05 7 RCDual OFF STATE, REG_RST, POR, OTGMODE NTCHOT 0 5-6 R No_Reset RESERVED 00 4 RCDual OFF STATE, REG_RST, POR, OTGMODE NTCCOLD 0 Battery Temperature is lower than NTC COLD threshold 3 RCSingl e OFF STATE, POR, REG_RST, TRM_RST, OTGMODE WDTO 0 watchdog timeout expires interrupt: 1: 32s timer expired. 2 RCSingl e OFF STATE, POR, REG_RST, TRM_RST, OTGMODE USBTO 0 usb timeout expires initerrupt: 1: 2048s timer expired 1 RCSingl e OFF STATE, POR, REG_RST, TRM_RST, OTGMODE CHGTO 0 charge timeout expires interrupt: 1: 3600s timer expired 0 R No_Reset CHINT1 0 charger related interrupt (CH1_INT register) BST_INT REGISTER - Memory Location: 06 7-3 R No_Reset RESERVED 00000 2 RCDual OFF STATE, POR, REG_RST, CHGMODE VBUSILIM 0 http://onsemi.com 23 vbus overload interrupt: 1: Vbus voltage < VBUSUV NCP1850 Table 6. REGISTERS MAP Bit Type Reset Name RST Value Function BST_INT REGISTER - Memory Location: 06 1 RCDual OFF STATE, POR, REG_RST, CHGMODE VBUSOV 0 vbus overvoltage interrupt: 1: Vbus voltage < VBUSOV 0 RCDual OFF STATE, POR, REG_RST, CHGMODE VBATLO 0 vbat overvoltage interrupt: 1: Vbat voltage < VIBSTL VIN over voltage lock out comparator 1: VIN > VINOV VIN_SNS REGISTER - Memory Location: 07 7 R No_Reset VINOVLO_SNS 0 6 R No_Reset RESERVED 0 5 R No_Reset VBUSOV_SNS 0 VIN not is USB range comparator 1: VIN > VBUSOV 4 R No_Reset VBUSUV_SNS 0 VIN not is USB range comparator 1: VIN < VBUSUV 3 R No_Reset VINDET_SNS 0 VIN voltage detection comparator 1: VIN > VINDET 2 R No_Reset VCHGDET_SNS 0 VIN changer detection comparator 1: VIN - VBAT > VCHGDET 1 R No_Reset VBOOST_UV_SNS 0 VIN OTG under voltage comparator 1: VIN < VBUSUV 0 R No_Reset RESERVED 0 VBAT_SNS REGISTER - Memory Location: 08 7 R No_Reset NTC_REMOVAL_S NS 0 NTC removal comparator : 1: Battery removal, VNTC > VNTCRMV 6 R No_Reset VBAT_OV_SNS 0 VBAT over voltage comparator 1: VBAT > VOVP 5 R No_Reset VRECHG_OK_SNS 0 VBAT recharge comparator 1: VBAT > VRECHG 4 R No_Reset VFET_OK_SNS 0 VBAT weak charge comparator 1: VBAT > VFET 3 R No_Reset VPRE_OK_SNS 0 VBAT precharge comparator 1: VBAT > VPRE 2 R No_Reset VSAFE_OK_SNS 0 VBAT safe comparator 1: VBAT > VSAFE 1 R No_Reset IEOC_OK_SNS 0 End of charge current comparator 1: ICHARGE > IEOC 0 R No_Reset RESERVED 0 TEMP_SNS REGISTER - Memory Location: 09 NTC cold comparator : 1: VNTC < VCOLD 7 R No_Reset NTC_COLD_SNS 0 5-6 R No_Reset RESERVED 00 4 R No_Reset NTC_HOT_SNS 0 NTC disable comparator : 1: VNTC > VNTCDIS 3 R No_Reset TSD_SNS 0 Chip thermal shut down comparator 1: Chip Temp > TSD 2 R No_Reset TM2_SNS 0 Chip thermal shut down comparator 1: Chip Temp > tm2 http://onsemi.com 24 NCP1850 Table 6. REGISTERS MAP Bit Type Reset Name RST Value Function TEMP_SNS REGISTER - Memory Location: 09 1 R No_Reset TM1_SNS 0 Chip thermal shut down comparator 1: Chip Temp > tm1 0 R No_Reset TWARN 0 Chip thermal shut down comparator 1: Chip Temp > twarn STAT_MSK REGISTER - Memory Location: 0A 7-6 R No_Reset RESERVED 00 5 RW OFF STATE, POR, REG_RST TWARN_MASK 1 TWARN interruption mask bit. 4 RW OFF STATE, POR, REG_RST TM1_MASK 1 TM1 interruption mask bit. 3 RW OFF STATE, POR, REG_RST TM2_MASK 1 TM2 interruption mask bit. 2 RW OFF STATE, POR, REG_RST TSD_MASK 1 TSD interruption mask bit. 1 R No_Reset RESERVED 0 0 RW OFF STATE, POR, REG_RST, OTGMODE VBUSOK_MASK 1 VBUSOK interruption mask bit. CH1_MSK REGISTER - Memory Location: 0B 7-5 R No_Reset RESERVED 000 4 RW OFF STATE, POR, REG_RST, OTGMODE VINLO_MASK 1 VINLO interruption mask bit. 3 RW OFF STATE, POR, REG_RST, OTGMODE VINHI_MASK 1 VINHI interruption mask bit. 2 RW OFF STATE, POR, REG_RST, OTGMODE BATRMV_MASK 1 BATRMV interruption mask bit. 1 RW OFF STATE, POR, REG_RST, OTGMODE BUCKOVP_MASK 1 BUCKOVP interruption mask bit. 0 R No_Reset RESERVED 0 CH2_MSK REGISTER - Memory Location: 0C 7 RW OFF STATE, POR, REG_RST, OTGMODE NTCHOT_MASK 1 5-6 R No_Reset RESERVED 0 4 RW OFF STATE, POR, REG_RST, OTGMODE NTCCOLD_MASK 1 NTCCOLD interruption mask bit. 3 RW OFF STATE, POR, REG_RST, OTGMODE WDTO_MASK 0 WDTO interruption mask bit. 2 RW OFF STATE, POR, REG_RST, OTGMODE USBTO_MASK 0 USBTO interruption mask bit. 1 RW OFF STATE, POR, REG_RST, OTGMODE CHGTO_MASK 0 CHGTO interruption mask bit. http://onsemi.com 25 NTCHOT interruption mask bit. NCP1850 Table 6. REGISTERS MAP Bit Type Reset Name RST Value RESERVED 0 Function CH2_MSK REGISTER - Memory Location: 0C 0 R No_Reset BST_MSK REGISTER - Memory Location: 0D R No_Reset RESERVED 0000 3 RW OFF STATE, POR, REG_RST, OTGMODE VBUSILIM_MASK 1 VBUSILIM interruption mask bit. 2 RW OFF STATE, POR, REG_RST, OTGMODE VBUSOV_MASK 1 VBUSOV interruption mask bit. 1 RW OFF STATE, POR, REG_RST, OTGMODE VBATLO_MASK 1 VBATLO interruption mask bit. 0 RW OFF STATE, POR, REG_RST, OTGMODE STATEOTG_MASK 1 STATEOTG interruption mask bit. 7-4 VBAT_SET REGISTER - Memory Location: 0E 7-6 R No_Reset RESERVED 00 0-5 RW OFF STATE, POR, REG_RST, OTGMODE CTRL_VBAT [5:0] 001100 000000: 3.3 V 001100: 3.6 V 110000: 4.5 V Step: 0.025 V IBAT_SET REGISTER - Memory Location: 0F 7 R No_Reset RESERVED 0 6-4 RW OFF STATE, POR, REG_RST, OTGMODE IEOC[2:0] 010 000: 100 mA 010: 150 mA 111: 275 mA Step: 25 mA RW OFF STATE, POR, REG_RST, OTGMODE ICHG[3:0] 0110 Output range current programmable range: 0000: 400 mA 1011: 1.5 A Step : 100 mA 3-0 MISC_SET REGISTER - Memory Location: 10 7 RW OFF STATE, POR, REG_RST, OTGMODE TST_SET 0 Minimum transition time from Weak Charge to Full Charge State 0 : 32 s 1 : 16 ms 6 RW OFF STATE, POR, REG_RST, OTGMODE FCTRY_MOD_REG 0 Factory mode : 0: Factory mode disable 1: Enable factory mode. 5 RW OFF STATE, POR, REG_RST, OTGMODE IWEAK_EN 1 Charge current during weak battery states: 0: Disable 1: 100 mA 011 Battery to system re-connection threshold: 000: 3.1 V 001: 3.2 V 010: 3.3 V 011: 3.4 V 100: 3.5 V 101: 3.6 V 00 Input current limit range: 00: 100 mA 01: 500 mA 10: 900 mA 11: 1500 mA 4-2 1-0 RW OFF STATE, POR, REG_RST, OTGMODE RW OFF STATE, POR, REG_RST, OTGMODE CTRL_VFET[2:0] IINLIM[1:0] http://onsemi.com 26 NCP1850 Table 6. REGISTERS MAP Bit Type Reset Name RST Value RESERVED 0000 Function NTC_SET REGISTER - Memory Location: 11 R 7-4 No_Reset R0 = 10 kW, T0= 25C 2-3 OFF STATE, POR, REG_RST, OTGMODE RW BATCOLD[1:0] 01 B = 3380 00: -1C 01: 2C 10: 5C 11: 9C B = 3400 00: 1C 01: 5C 10: 8C 11: 11C R0 = 10 kW,T0= 25C 0-1 OFF STATE, POR, REG_RST, OTGMODE RW BATHOT[1:0] 10 B = 3380 |00: 43C 01: 47C 10: 52C 11: 57C B = 3400 00: 40C 01: 44C 10: 48C 11: 52C APPLICATION INFORMATION Components Selection The bandwidth is recommended to be high enough in case of application with a BATFET because the system can be directly connected to the buck output. And in this case, the battery does not play any role upon a load transient as it's disconnected from the buck converter. USB dedicated charge VIN = 5 V VCHG = 4.2 V ICHG = 1.5 A L1 = 2.2 mH DIL1 = 0.189 A IPEAKMAX = 1.59 A AC adaptor charge VIN = 16 V VCHG = 4.2 V ICHG = 1.5 A L1 = 2.2 mH DIL1 = 0.6 A IPEAKMAX = 1.8 A Resistance R1 R1 (charge current sense resistor) resistor is determined by considering thermal constrain as its value is 68 mW typical. The power dissipation is given by: Inductor L1 NCP1851 is recommended to be used with 2.2 mH inductor. Below will give inductor ripple and maximum current for two different application cases knowing the following relation: DI L + V BAT 1* The worst case is when V BAT * so when V BAT + DI LMAX + V BAT V IN L1 1 FSWCHG V BAT 2 is maximum V IN V IN 2 V IN DI 1 @ ;I + I CHG ) LMAX 4 L1 @ F SWCHG PEAKMAX 2 Capacitor C6 A 10 mF output capacitor is recommended for proper operation and design stability. The bandwidth of the system is defined by the following relation: F BW + 1 2p L 1 C6 + 33 kHz P R1 + R 1 (ICHG) 2 The worst case is ICHG = 1.5 A so PR1 = 0.153 W. http://onsemi.com 27 NCP1850 BILL OF MATERIAL LX 2.2mH VBUS D+ D- GND SW IN CIN CBOOT CAP CCAP COUT CBOOT NCP1850 1mF RSNS 68mW 10mF 10nF SYSTEM SENSP SENSN 4.7mF WEAK FET CORE CCORE 2.2mF QBAT (*) BAT NTC + TRANS CTRANS 100nF FLAG SCL SDA AGND SPM PGND ILIM INTB OTG Figure 14. NCP1850 Typical Application Example Item Part Description Ref Value PCB Footprint Manufacturer Manufacturer Reference 1 Ceramic Capacitor 25 V X5R CIN 1 mF 0603 MURATA GRM188R61E105K 2 Ceramic Capacitor 25 V X5R CCAP 4.7 mF 0805 MURATA GRM21BR61E475KA12L 3 Ceramic Capacitor 6.3 V X5R CCORE 2.2 mF 0402 MURATA GRM155R60J225M 4 Ceramic Capacitor 6.3 V X5R CTRS 0.1 mF 0402 MURATA GRM155R60J104K 5 Ceramic Capacitor 10 V X5R CBOOT 10 nF 0402 MURATA GRM155R60J103K 6 Ceramic Capacitor 6.3 V X5R COUT 10 mF 0603 MURATA GRM188R60J106M 7 SMD Inductor LX 2.2mH 3012 TDK VLS3012T-2R2M1R5 8 SMD Resistor 0.25 W, 1% RSNS 68 mW 0603 PANASONIC ERJ3BWFR068V 9 Power channel P-MOSFET QBAT 30 mW UDFN 2 * 2 mm ON Semiconductor NTLUS3A40PZ PCB Layout Consideration Particular attention must be paid with CCORE capacitor as it's decoupling the supply of internal circuitry including gate driver. This capacitor must be placed between CORE pin and PGND pin with a minimum track length. The high speed operation of the NCP1850 demands careful attention to board layout and component placement. To prevent electromagnetic interference (EMI) problems, attention should be paid specially with components CIN, LX, CCAP, and COUT as they constitute a high frequency current loop area. The power input capacitor CIN, connected from IN to PGND, should be placed as close as possible to the NCP1850. The output inductor LX and the output capacitor COUT connected between RSNS and PGND should be placed close to the IC. CCAP capacitor should also be place as close as possible to CAP and PGND pin. The high current charge path through IN, CAP, SW, inductor L1, Resistor R1, optional BAFTET, and battery pack must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. An IWEAK current can flow through WEAK and BAT traces witch defines the appropriate track width. It's suggested to keep as complete ground plane under NCP1850 as possible. PGND and AGND pin connection must be connected to the ground plane. Care should be taken to avoid noise interference between PGND and AGND. Finally it is always good practice to keep the sensitive tracks such as feedbacks connections (SENSP, SENSN, BAT) away from switching signal connections by laying the tracks on the other side or inner layer of PCB. http://onsemi.com 28 NCP1850 IN Power path Q1 Q2 CORE CIN 1mF CCORE Noise sensitive path 68m SW CAP 2.2mF LX 2.2mF RSNS 68mW Q3 4.7mF + 10mF CCAP CSYS NCP1850 PGND Figure 15. NCP1850 Power Path ORDERING INFORMATION Part Number NCP1850FCCT1G I2C Address Package Shipping $6C WLCSP25 (Pb-Free) TBD For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 29 NCP1850 PACKAGE DIMENSIONS WLCSP25, 2.06x2.06 CASE 567FZ ISSUE O EE PIN A1 REFERENCE D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. B E 2X DIE COAT A3 DIM A A1 A2 A3 b D E e 0.10 C A2 2X 0.10 C DETAIL A TOP VIEW MILLIMETERS MIN MAX --- 0.60 0.17 0.23 0.36 REF 0.04 REF 0.24 0.29 2.06 BSC 2.06 BSC 0.40 BSC A2 DETAIL A 0.10 C A RECOMMENDED SOLDERING FOOTPRINT* 0.05 C NOTE 3 25X A1 SEATING PLANE A1 PACKAGE OUTLINE e b 0.05 C A B 0.03 C C SIDE VIEW E e 0.40 PITCH D C 25X 0.40 PITCH B A 1 2 3 4 0.25 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 5 BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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