1 Watt, GaAs pHEMT MMIC
Power Amplifier, 27 GHz to 32 GHz
Data Sheet HMC1132
Rev. 0 Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
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Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Saturated output power (PSAT): 30.5 dBm at 22% power
added efficiency (PAE)
High output IP3: 35 dBm
High gain: 22 dB
DC supply: 6 V at 600 mA
No external matching required
32-lead, 5 mm × 5 mm LFCSP package
APPLICATIONS
Point-to-point radios
Point-to-multipoint radios
VSAT and SATCOM
Military and space
FUNCTIONAL BLOCK DIAGRAM
17
1
3
4
2
9
GND
NC
NC
GND 5
6
RFIN
GND 7
NC 8
GND GND
18 NC
19 GND
20 RFOUT
21 GND
22 NC
23 NC
24 GND
GND
12
V
DD1
11
NC
10
NC
13
NC
14
NC
15
V
DD2
16
GND
25
GND
26
NC
27
NC
28
NC
29
NC
30
NC
31
V
GG
32
GND
HMC1132
13528-001
PACKAGE
BASE
Figure 1.
GENERAL DESCRIPTION
The HMC1132 is a four-stage, GaAs pHEMT MMIC, 1 watt
power amplifier that operates between 27 GHz and 32 GHz.
The HMC1132 provides 22 dB of gain and 30.5 dBm of
saturated output power at 22% PAE from a 6 V power supply.
The HMC1132 exhibits excellent linearity and it is optimized
for high capacity, point-to-point and point-to-multipoint radio
systems. The amplifier configuration and high gain make it an
excellent candidate for last stage signal amplification before the
antenna.
The HMC1132 amplifier input/outputs (I/Os) are internally
matched to 50 Ω. The device is supplied in a compact, leadless
QFN, 5 mm × 5 mm surface-mount package.
HMC1132 Data Sheet
Rev. 0 | Page 2 of 14
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Specifications ............................................................... 3
Absolute Maximum Ratings ............................................................ 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Interface Schematics .....................................................................5
Typical Performance Characteristics ..............................................6
Theory of Operation ...................................................................... 10
Applications Information ............................................................... 11
Application Circuit ...................................................................... 11
Evaluation Board ............................................................................ 12
Bill of Materials ........................................................................... 12
Evaluation Board Schematic ..................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide ............................................................................... 14
REVISION HISTORY
7/2016—Revision 0: Initial Version
Data Sheet HMC1132
Rev. 0 | Page 3 of 14
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
TA = 25°C, VDD = VDD1 = VDD2 = 6 V, IDD = 600 mA.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 27 32 GHz
GAIN 20 22 dB
Gain Variation over
Temperature
0.036 dB/°C
RETURN LOSS
Input 6 dB
Output 14 dB
POWER
Output Power for 1 dB
Compression
P1dB 28 30 dBm
Saturated Output Power PSAT 30.5 dBm
OUTPUT THIRD-ORDER
INTERCEPT
IP3 35 dBm Measurement taken at 6 V at 600 mA, POUT ÷ tone = 20 dBm
SUPPLY VOLTAGE VDD 4 6 V
QUIESCENT SUPPLY CURRENT IDD 400 700 mA
HMC1132 Data Sheet
Rev. 0 | Page 4 of 14
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Drain Voltage Bias 6.5 V
RF Input Power (RFIN)
1
18 dBm
Channel Temperature 175°C
Continuous PDISS (T = 85°C) (Derate 61 mw/°C
Above 85°C)
5.49 W
Thermal Resistance (RTH) Junction to Ground
Paddle
16.4°C/W
Maximum Peak Reflow Temperature
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity (Human Body Model)
260°C
−40°C to +150°C
−40°C to +85°C
Class 0, passed
150 V
1 Maximum PIN is limited to 18 dBm or thermal limits constrained by maximum
power dissipation (see Figure 31), whichever is lower.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Data Sheet HMC1132
Rev. 0 | Page 5 of 14
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
17
1
3
4
2
9
GND
NC
NC
GND 5
6
RFIN
GND 7
NC 8
GND GND
18 NC
19 GND
20 RFOUT
21 GND
22 NC
23 NC
24 GND
GND
12
V
DD
1
11
NC
10
NC
13
NC
14
NC
15
V
DD
2
16
GND
25
GND
26
NC
27
NC
28
NC
29
NC
30
NC
31
V
GG
32
GND
HMC1132
TOP VIEW
(No t t o Scal e)
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD. EXPOSED PAD MUST
BE CONNE CTED TO RF/ DC GROUND.
13528-002
Figure 2. Pin Configuration
Table 3. Pad Function Descriptions
Pin No. Mnemonic Description
1, 4, 6, 8, 9, 16, 17,
19, 21, 24, 25, 32
GND Ground. These pins are exposed ground paddles that must be connected to RF/dc ground.
2, 3, 7, 10, 11, 13, 14,
18, 22, 23, 26 to 30
NC No Connect. These pins are not connected internally. However, all data was measured with these pins
connected to RF/dc ground externally.
5 RFIN RF Input. This pin is dc-coupled and matched to 50 Ω. See Figure 4 for the RFIN interface schematic.
12, 15 VDD1, VDD2 Drain Bias Voltage. External by pass capacitors of 100 pF, 10 nF, and 4.7 μF are required. See Figure 5
for the VDD1 and VDD2 interface schematic.
20 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the RFOUT interface
schematic.
31 VGG Gate Control for Amplifier. Adjust VGG to achieve the recommended bias current. External bypass
capacitors of 100 pF, 10 nF, and 4.7 μF are required. See Figure 7 for the VGG interface schematic.
EPAD
Exposed Paddle. The exposed pad must be connected to RF/dc ground.
INTERFACE SCHEMATICS
GND
13528-003
Figure 3. GND Interface
RFIN
13528-004
Figure 4. RFIN Interface
VDD1,VDD2
13528-005
Figure 5. VDD1 and VDD2 Interface
RFOUT
13528-006
Figure 6. RFOUT Interface
VGG
13528-007
Figure 7. VGG Interface
HMC1132 Data Sheet
Rev. 0 | Page 6 of 14
TYPICAL PERFORMANCE CHARACTERISTICS
30
–30
–20
–10
0
10
20
25 26 27 28 29 30 31 32 33 34
RESPONSE (dB)
FREQUENCY ( GHz)
S22
S21
S11
13528-008
Figure 8. Broadband Gain and Return Loss vs. Frequency
0
–16
–12
–14
–10
–8
–6
–4
–2
27 28 29 30 31 32 33 34
RETURN LO S S ( dB)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
13528-009
Figure 9. Input Return Loss vs. Frequency at Various Temperatures
35
25
27
29
31
33
26 27 28 29 30 31 32 33
P1dB (dBm)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
13528-010
Figure 10. P1dB vs. Frequency at Various Temperatures
28
14
18
16
20
22
24
26
27 28 29 30 31 32 33 34
GAI N ( dB)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
13528-011
Figure 11. Gain vs. Frequency at Various Temperatures
0
–25
–20
–15
–10
–5
27 28 29 30 31 32 33 34
RETURN LO S S ( dB)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
13528-012
Figure 12. Output Return Loss vs. Frequency at Various Temperatures
35
25
27
29
31
33
26 27 28 29 30 31 32 33
P1dB (dBm)
FREQUENCY ( GHz)
5V
5.5V
6V
13528-013
Figure 13. P1dB vs. Frequency at Various Supply Voltages
Data Sheet HMC1132
Rev. 0 | Page 7 of 14
35
25
27
29
31
33
26 27 28 29 30 31 32 33
P
SAT
(d Bm)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
13528-014
Figure 14. PSAT vs. Frequency at Various Temperatures
35
25
27
29
31
33
26 27 28 29 30 31 32 33
P1dB (dBm)
FREQUENCY ( GHz)
500mA
600mA
700mA
13528-015
Figure 15. P1dB vs. Frequency at Various Supply Currents (IDD)
40
20
25
30
35
26 27 28 29 30 31 32 33
IP3 ( dBm)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
13528-016
Figure 16. Output IP3 vs. Frequency at Various Temperatures,
POUT/Tone = 20 dBm
35
25
27
29
31
33
26 27 28 29 30 31 32 33
P
SAT
(d Bm)
FREQUENCY ( GHz)
5V
5.5V
6V
13528-017
Figure 17. PSAT vs. Frequency at Various Supply Voltages
35
25
27
29
31
33
26 27 28 29 30 31 32 33
P
SAT
(d Bm)
FREQUENCY ( GHz)
500mA
600mA
700mA
13528-018
Figure 18. PSAT vs. Frequency at Various Supply Currents (IDD)
40
20
25
30
35
26 27 28 29 30 31 32 33
IP3 ( dBm)
FREQUENCY ( GHz)
500mA
600mA
700mA
13528-019
Figure 19. Output IP3 vs. Frequency at Various Supply Currents,
POUT/Tone = 20 dBm
HMC1132 Data Sheet
Rev. 0 | Page 8 of 14
40
20
25
30
35
26 27 28 29 30 31 32 33
IP3 ( dBm)
FREQUENCY ( GHz)
5V
5.5V
6V
13528-020
Figure 20. Output IP3 vs. Frequency at Various Supply Voltages,
POUT/Tone = 20 dBm
60
0
10
30
50
20
40
10 12 14 16 18 20 22 24
IM 3 ( dBc)
P
OUT
/TONE (dBm)
27GHz
28GHz
29GHz
30GHz
31GHz
32GHz
13528-021
Figure 21. Output Third-Order Intermodulation Distortion (IM3)
at VDD = 5.5 V
40
0
5
25
35
15
10
20
30
1000
500
625
750
875
–10 –8 –6 –2 2 6 10–4 0 4 8 12 14
POUT (d Bm) , G AIN (dB), P AE ( %)
IDD ( mA)
INPUT POW E R ( dBm)
POUT
GAIN
PAE
IDD
13528-022
Figure 22. Power Compression at 27 GHz
60
0
10
30
50
20
40
10 12 14 16 18 20 22 24
IM 3 ( dBc)
P
OUT
/TONE (dBm)
27GHz
28GHz
29GHz
30GHz
31GHz
32GHz
13528-023
Figure 23. Output IM3 at VDD = 5 V
60
0
10
30
50
20
40
10 12 14 16 18 20 22 24
IM 3 ( dBc)
P
OUT
/TONE (dBm)
27GHz
28GHz
29GHz
30GHz
31GHz
32GHz
13528-024
Figure 24. Output IM3 at VDD = 6 V
40
0
5
25
35
15
10
20
30
1000
500
625
750
875
–10 –8 –6 –2 2 6 10–4 04812 14
P
OUT
(d Bm) , GAIN (dB), PAE ( %)
I
DD
(mA)
INP UT PO WER ( dBm)
P
OUT
GAIN
PAE
I
DD
13528-025
Figure 25. Power Compression at 29.5 GHz
Data Sheet HMC1132
Rev. 0 | Page 9 of 14
40
0
5
25
35
15
10
20
30
1000
500
625
750
875
–10 –8 –6 –2 2 6 10–4 0 4 8 12 14
P
OUT
(d Bm) , GAIN (dB), PAE (%)
I
DD
(mA)
INPUT POW E R ( dBm)
P
OUT
GAIN
PAE
I
DD
13528-026
Figure 26. Power Compression at 32 GHz
40
15
20
25
30
35
500 550 600 650 700
GAI N (dB) , P1dB (dBm), P
SAT
(d Bm)
I
DD
(mA)
GAIN
P1dB
P
SAT
13528-027
Figure 27. Gain and Power vs. Supply Current at 29.5 GHz
0
–80
–50
–60
–70
–40
–30
–20
–10
26 27 28 29 30 31 32 3433
ISOLATION (dB)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
13528-028
Figure 28. Reverse Isolation vs. Frequency at Various Temperatures
30
0
5
10
15
20
25
26 27 28 29 30 31 32 33
PAE (%)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
13528-029
Figure 29. PAE vs. Frequency at Various Temperatures, PIN = 10 dBm
40
15
20
25
30
35
5.0 5.2 5.5 5.7 6.0
GAI N ( dB), P1dB (dBm), P
SAT
(d Bm)
V
DD
(V)
GAIN
P1dB
P
SAT
13528-030
Figure 30. Gain and Power vs. Supply Voltage at 29.5 GHz
5
1
2
4
3
–10 –5 0 5 10 15
POWER DISSIPATI ON (W )
INPUT POW E R ( dBm)
27GHz
28GHz
29GHz
30GHz
31GHz
32GHz
13528-031
Figure 31. Power Dissipation at 85°C
HMC1132 Data Sheet
Rev. 0 | Page 10 of 14
THEORY OF OPERATION
The architecture of the HMC1132 power amplifier is shown in
Figure 32. The amplifier consists of a cascade of four, single-
stage amplifiers. This approach provides a high P1dB as well as
a high gain that is flat across the operating frequency range.
VDD1 provides drain bias to the first three gain stages, whereas
VDD2 provides drain bias to the fourth gain stage. VGG provides
gate bias to all four gain stages, allowing control of the total
quiescent drain current. RFIN and RFOUT provide dc paths to
GND as a way of increasing the overall ESD robustness of the
device.
13528-034
V
DD1
RFIN RFOUT
V
DD2
V
GG
Figure 32. Architecture and Simplified Block Diagram
Data Sheet HMC1132
Rev. 0 | Page 11 of 14
APPLICATIONS INFORMATION
The HMC1132 is a GaAs, pHEMT, MMIC power amplifier.
Capacitive bypassing is required for VDD1 and VDD2 as well as for
VGG (see Figure 33). Drain bias voltage must be applied to both
VDD1 and VDD2, and gate bias voltage must be applied to VGG.
Though the RFIN and RFOUT ports ac couple the signal, dc
paths to GND are provided to increase the ESD robustness of
the device. External dc blocking of RFIN and/or RFOUT is
desirable when appreciable levels of dc are expected to be
present.
All measurements for this device were taken using the typical
application circuit shown in Figure 33, configured as shown on
the evaluation printed circuit board (PCB).
The following is the recommended bias sequence during
power-up:
1. Connect the evaluation board to ground.
2. Set the gate bias voltage to −2 V.
3. Set the drain bias voltages to 6 V.
4. Increase the gate bias voltage to achieve a quiescent IDD =
600 mA.
5. Apply the RF signal.
The following is the recommended bias sequence during
power-down:
1. Turn off the RF signal.
2. Decrease the gate bias voltage to −2 V to achieve an IDD =
0 mA (approximately).
3. Decrease the drain bias voltages to 0 V.
4. Increase the gate bias voltage to 0 V.
The VDD = 6 V and IDD = 600 mA bias conditions are the
operating points recommended to optimize the overall
performance of the device. Unless otherwise noted, the data
shown was obtained using the recommended bias condition.
Operation of the HMC1132 at different bias conditions may
provide performance that differs from what is shown in the
Typical Performance Characteristics section. Biasing the
HMC1132 for higher drain current typically results in higher
P1dB, PSAT, and gain, though at the expense of increased power
consumption.
APPLICATION CIRCUIT
C23
4.7µF
V
DD1
V
GG
J1
RFIN J2
RFOUT
V
DD2
C13
10nF C3
100pF
C25
4.7µF C15
10nF C5
100pF
C30
4.7µF C20
10nF C10
100pF
17
1
3
4
2
9
5
6
7
818
19
20
21
22
23
24
12
11
10
13
14
15
16 25
26
27
28
29
30
31
32
HMC1132
13528-032
Figure 33. Typical Application Circuit
HMC1132 Data Sheet
Rev. 0 | Page 12 of 14
EVALUATION BOARD
The HMC1132 evaluation board is a 2-layer board fabricated
using Rogers 4350 and best practices for high frequency RF
design. The RF input and RF output traces have a 50 Ω
characteristic impedance. The circuit board is attached to a heat
sink using SN96 solder and provides a low thermal resistance
path. Components are mounted using SN63 solder allowing
rework of the surface-mount components without compromising
the circuit board to heat sink attachment.
The evaluation board and populated components are designed
to operate over the ambient temperature range of −40°C to
+85°C. During operation, to control the temperature of the
HMC1132, attach the evaluation board to a temperature
controlled plate. For proper bias sequence, see the Applications
Information section.
The evaluation board schematic is shown in Figure 35. A fully
populated and tested evaluation board (see Figure 34), is
available from Analog Devices, Inc., upon request.
13528-033
21
Figure 34. Evaluation Printed Circuit Board (PCB)
BILL OF MATERIALS
Table 4. Bill of Materials for Evaluation PCB EV1HMC1132LP5D
Item Description
J1, J2 Connector, SRI K connector. SRI PN 25-146-1000-92.
J3, J4
DC pins.
J5, J6 Connector, SRI K connector. Not populated.
C3, C5, C10 100 pF capacitors, 0402 package.
C13, C15, C20 10,000 pF capacitors, 0402 package.
C23, C25, C30 4.7 μF capacitors, Case A package.
U1 HMC1132LP5DE amplifier.
Heat Sink Used for thermal transfer from the HMC1132LP5DE amplifier.
PCB 131393 evaluation board. Circuit board material: Rogers 4350.
Data Sheet HMC1132
Rev. 0 | Page 13 of 14
EVALUATION BOARD SCHEMATIC
13528-035
J3
87759-1050
9
1
3
5
7
2
4
6
8
10
VG1
VD2
VD4
VD6
VD8
VD7
VD5
VD3
VD1
VG2
87759-1050
J4 9
1
3
5
7
2
4
6
8
10
J5
K_SRI-NS
DEPOP
J6
K_SRI-NS
DEPOP
THRUCAL
K_SRI-NS
J2J1
K_SRI-NS
RFOUT
RFIN
VD7
VD3
VG1
U1
HMC1132LP5DE
27
32
26
22
25
21
15
16
14
13
12
11
10
9
17
18
23
24
19
20
28
29
30
31
8
7
6
2
1
5
4
3
RFIN
NC
GND
GND
GND
VD1
VD2
NC
NC
NC
NC
GND
GND
NC
NC
VG
NC
NC
NC
GND
GND
GND
NC
NC
RFOUT
NC
GND
GND
GND
GND
NC
NC
++
+
C30
4.7µF C20
10nF C10
100pF
C23
4.7µF C13
10nF C3
100pF C5
100pF C15
10nF C25
4.7µF
Figure 35. Evaluation Board Schematic
HMC1132 Data Sheet
Rev. 0 | Page 14 of 14
OUTLINE DIMENSIONS
08-06-2015-A
1
0.50
BSC
BOTTOM VIEWTOP VIEW
SIDE VIEW
PIN 1
INDICATOR
32
9
16
17
24
25
8
EXPOSED
PAD
PIN 1
INDICATOR
SEATING
PLANE
COPLANARITY
0.08
0.30
0.25
0.18
5.10
5.00 SQ
4.90
1.53
1.34
1.15 F OR PROPE R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURAT ION AND
FUNCTION DES CRIPTIONS
SECTION OF THIS DATA SHEET.
0.55
0.50
0.35
0.50 M I N
3.15
3.00 SQ
2.85
PKG-000000
3.50 REF
6° BS C
Figure 36. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 1.34 mm Package Height
(HCP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature
Range
MSL
Rating2 Package Description3, 4
Package
Option
Package
Marking5
HMC1132LP5DE −40°C to +85°C MSL3 32-Lead Lead Frame Chip Scale Package [LFCSP] HCP-32-2
XXXX
H1132
HMC1132LP5DETR −40°C to +85°C MSL3 32-Lead Lead Frame Chip Scale Package [LFCSP] HCP-32-2
XXXX
H1132
EV1HMC1132LP5D Evaluation board
1 When ordering the evaluation fixture only, reference the model number, EV1HMC1132LP5D.
2 Maximum peak reflow temperature of 260°C.
3 HMC1132LP5DE lead finish is NiPdAu.
4 The HMC1132LP5DE is a premolded copper alloy lead frame.
5 HMC1132LP5DE 4-digit lot number is represented by XXXX.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13528-0-7/16(0)
