www.ti.com
FEATURES DESCRIPTION
APPLICATIONS
1
2
3
4
5
6
GND
DCQ PACKAGE
SOT223-6
(TOP VIEW)
NR/FB
OUT
GND
IN
EN
1
KTT (DDPAK) PACKAGE
(TOP VIEW)
2
3
4
5
EN
IN
GND
OUT
NR/FB
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Frequency (Hz)
100 10k 100k1k
Output Spectral Noise Density − µV/√Hz
IOUT = 1 mA
TPS79630
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
IOUT = 1.5 A
VIN = 5.5 V
COUT = 2.2 µF
CNR = 0.1 µF
0
10
20
30
40
50
60
70
80
Frequency (Hz)
110k 10M1k
Ripple Rejection − dB
IOUT = 1 mA
TPS79630
RIPPLE REJECTION
vs
FREQUENCY
IOUT = 1 A
VIN = 4 V
COUT = 10 µF
CNR = 0.01 µF
10 100 100k 1M
EN
NC
GND
NR
8
7
6
5
IN
IN
OUT
OUT
1
2
3
4
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
TPS796xx
SLVS351G – SEPTEMBER 2002 – REVISED DECEMBER 2005
ULTRALOW-NOISE, HIGH PSRR, FAST, RF, 1-ALOW-DROPOUT LINEAR REGULATORS
•1-A Low-Dropout Regulator With Enable
The TPS796xx family of low-dropout (LDO)low-power linear voltage regulators features high•Available in Fixed and Adjustable (1.2-V to
power supply rejection ratio (PSRR), ultralow-noise,5.5-V) Versions
fast start-up, and excellent line and load transient•High PSRR (53 dB at 10 kHz)
responses in small outline, 3 x 3 SON, SOT223-6,•Ultralow-Noise (40 µV
RMS
, TPS79630)
and 5-pin DDPAK packages. Each device in thefamily is stable with a small 1-µF ceramic capacitor•Fast Start-Up Time (50 µs)
on the output. The family uses an advanced,•Stable With a 1-µF Ceramic Capacitor
proprietary BiCMOS fabrication process to yield•Excellent Load/Line Transient Response
extremely low dropout voltages (e.g., 250 mV at 1 A).Each device achieves fast start-up times•Very Low Dropout Voltage (250 mV at Full
(approximately 50 µs with a 0.001-µF bypassLoad, TPS79630)
capacitor) while consuming very low quiescent•3 x 3 SON, 6-Pin SOT223-6, and
current5-Pin DDPAK Packages
(265 µA typical). Moreover, when the device is placedin standby mode, the supply current is reduced toless than 1 µA. The TPS79630 exhibits approximately•RF: VCOs, Receivers, ADCs
40 µV
RMS
of output voltage noise at 3.0-V output, witha 0.1-µF bypass capacitor. Applications with analog•Audio
components that are noise sensitive, such as portable•Bluetooth™, Wireless LAN
RF electronics, benefit from the high PSRR, low•Cellular and Cordless Telephones
noise features, and the fast response time.•Handheld Organizers, PDAs
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Bluetooth is a trademark of Bluetooth SIG, Inc.All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
PACKAGE DISSIPATION RATINGS
TPS796xx
SLVS351G – SEPTEMBER 2002 – REVISED DECEMBER 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integratedcircuits be handled with appropriate precautions. Failure to observe proper handling and installationprocedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precisionintegrated circuits may be more susceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PRODUCT V
OUT
(2)
TPS796 xxyyyzXX is nominal output voltage (for example, 28 = 2.8 V, 01 = Adjustable).YYY is package designator.Zis package quantity.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Output voltages from 1.3 V to 4.9 V in 100 mV increments are available; minimum order quantities may apply. Contact factory for detailsand availability.
over operating temperature range (unless otherwise noted)
(1)
UNIT
V
IN
range -0.3 V to 6 VV
EN
range -0.3 V to V
IN
+ 0.3 VV
OUT
range 6 VPeak output current Internally limitedESD rating, HBM 2 kVESD rating, CDM 500 VContinuous total power dissipation See Dissipation Ratings TableJunction temperature range, T
J
-40°C to 150°CStorage temperature range, T
stg
-65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE BOARD R
ΘJC
R
ΘJA
DDPAK High-K
(1)
2 °C/W 23 °C/WSOT223 Low-K
(2)
15 °C/W 53 °C/W3 x 3 SON High-K
(1)
1.2 °C/W 40 °C/W
(1) The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), multilayer board with 1 ounceinternal power and ground planes and 2 ounce copper traces on top and bottom of the board.(2) The JEDEC low-K (1s) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), two-layer board with 2 ouncecopper traces on top of the board.
2
www.ti.com
ELECTRICAL CHARACTERISTICS
TPS796xx
SLVS351G – SEPTEMBER 2002 – REVISED DECEMBER 2005
over recommended operating temperature range (T
J
= -40 to 125°C), V
EN
= V
IN,
, V
IN
= V
OUT(nom)
+ 1 V
(1)
, I
OUT
= 1 mA,C
OUT
= 10 µF, C
NR
= 0.01 µF (unless otherwise noted). Typical values are at +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IN
Input voltage
(1)
2.7 5.5 VI
OUT
Continuous output current 0 1 AOutput
TPS79601 1.225 5.5 – V
DD
Vvoltage rangeOutput
voltage TPS79601
(2)
0 µA ≤I
OUT
≤1 A, V
OUT
+ 1 V ≤V
IN
≤5.5 V
(1)
0.98V
OUT
V
OUT
1.02V
OUT
VAccuracy
Fixed V
OUT
0 µA ≤I
OUT
≤1 A, V
OUT
+ 1 V ≤V
IN
≤5.5 V
(1)
–2.0 +2.0 %Output voltage line regulation
V
OUT
+ 1 V ≤V
IN
≤5.5 V 0.05 0.12 %/V(∆V
OUT
%/V
IN
)
(1)
Load regulation ( ∆V
OUT
%/ ∆I
OUT
) 0 µA ≤I
OUT
≤1 A 5 mVTPS79628 I
OUT
= 1 A 270 365TPS79628DRB I
OUT
= 250 mA 52 90Dropout voltage
(3)
TPS79630 I
OUT
= 1 A 250 345 mV(V
IN
= V
OUT (nom)
- 0.1V)
TPS79633 I
OUT
= 1 A 220 325TPS79650 I
OUT
= 1 A 200 300Output current limit V
OUT
= 0 V 2.4 4.2 AGround pin current 0 µA ≤I
OUT
≤1 A 265 385 µAShutdown current
(4)
V
EN
= 0 V, 2.7 V ≤V
IN
≤5.5 V 0.07 1 µAFB pin current V
FB
= 1.225 V 1 µAf = 100 Hz, I
OUT
= 10 mA 59f = 100 Hz, I
OUT
= 1 A 54Power-supply ripple
TPS79630 dBrejection
f = 10 Hz, I
OUT
= 1 A 53f = 100 Hz, I
OUT
= 1 A 42C
NR
= 0.001 µF 54C
NR
= 0.0047 µF 46BW = 100 Hz to 100 kHz,Output noise voltage (TPS79630) µV
RMSI
OUT
= 1 A
C
NR
= 0.01 µF 41C
NR
= 0.1 µF 40C
NR
= 0.001 µF 50Time, start-up (TPS79630) R
L
= 3 Ω, C
OUT
= 1 µF C
NR
= 0.0047 µF 75 µsC
NR
= 0.01 µF 110EN pin current V
EN
= 0V -1 1 µAHigh-level enable input voltage 2.7 V ≤V
IN
≤5.5 V 1.7 V
IN
VLow-level enable input voltage 2.7 V ≤V
IN
≤5.5 V 0 0.7 V
(1) Minimum V
IN
= V
OUT
+ V
DO
or 2.7 V, whichever is greater. TPS79650 is tested at V
IN
= 5.5 V.(2) Tolerance of external resistors not included in this specification.(3) V
DO
is not measured for TPS79618 and TPS79625 because minimum V
IN
= 2.7 V.(4) For adjustable version, this applies only after V
IN
is applied; then V
EN
transitions high to low.
3
www.ti.com
_+
Thermal
Shutdown
Bandgap
Reference
1.225 V
VIN
Current
Sense
R2
GND
EN
SHUTDOWN
VREF
UVLO
ILIM
External to
the Device
FB
R1
UVLO
250 kΩ
Quickstart
IN OUT
_+
Thermal
Shutdown
VIN
Current
Sense
R1
R2
GND
EN
SHUTDOWN
VREF
UVLO
ILIM
Bandgap
Reference
1.225 V
UVLO
250 kΩNR
Quickstart R2 = 40k
IN OUT
TPS796xx
SLVS351G – SEPTEMBER 2002 – REVISED DECEMBER 2005
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
Table 1. Terminal Functions
TERMINAL
DESCRIPTIONNAME ADJ FIXED
NR N/A 5 Connecting an external capacitor to this pin bypasses noise generated by the internal bandgap. This improvespower-supply rejection and reduces output noise.EN 1 1 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdownmode. EN can be connected to IN if not used.FB 5 N/A This terminal is the feedback input voltage for the adjustable device.GND 3, Tab 3, Tab Regulator groundIN 2 2 Unregulated input to the device.OUT 4 4 Output of the regulator.
4
www.ti.com
TYPICAL CHARACTERISTICS
2.95
2.96
2.97
2.98
2.99
3.00
3.01
3.02
3.03
3.04
3.05
0.0 0.2 0.4 0.6 0.8 1.0
VOUT (V)
IOUT (A)
VIN = 4 V
COUT = 10 µF
TJ = 25°C
0
1
2
3
4
−40−25−10 5 20 35 50 65 80 95 110 125
VOUT (V)
TJ (°C)
IOUT = 1 mA
2.795
2.790
2.785
2.780
2.775
IOUT = 1 A
VIN = 3.8 V
COUT = 10 µF
290
300
310
320
330
340
350
−40−25−10 5 20 35 50 65 80 95 110 125
IGND (µA)
TJ (°C)
VIN = 3.8 V
COUT = 10 µF
IOUT = 1 mA
IOUT = 1 A
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Frequency (Hz)
100 10k 100k1k
IOUT = 1 mA
IOUT = 1.5 A
VIN = 5.5 V
COUT = 2.2 µF
CNR = 0.1 µF
Output Spectral Noise Density − µV/Hz
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency (Hz)
100 10k 100k1k
Output Spectral Noise Density − µV/Hz
IOUT = 1 mA
IOUT = 1 A
VIN = 5.5 V
COUT = 10 µF
CNR = 0.1 µF
0.0
0.5
1.0
1.5
2.0
2.5
Frequency (Hz)
100 10k 100k1k
VIN = 5.5 V
COUT = 10 µF
IOUT = 1 A
CNR = 0.1 µF
CNR = 0.01 µF
CNR = 0.0047 µF
CNR = 0.001 µF
Output Spectral Noise Density − µV/Hz
TPS796xx
SLVS351G – SEPTEMBER 2002 – REVISED DECEMBER 2005
TPS79630 TPS79628 TPS79628OUTPUT VOLTAGE OUTPUT VOLTAGE GROUND CURRENTvs vs vsOUTPUT CURRENT JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 1. Figure 2. Figure 3.
TPS79630 TPS79630 TPS79630OUTPUT SPECTRAL NOISE OUTPUT SPECTRAL NOISE OUTPUT SPECTRAL NOISEDENSITY DENSITY DENSITYvs vs vsFREQUENCY FREQUENCY FREQUENCY
Figure 4. Figure 5. Figure 6.
5
www.ti.com
0
10
20
30
40
50
60
RMS − Root Mean Squared Output Noise − µVRMS
CNR (µF)
IOUT = 250 mA
COUT = 10 µF
0.001 µF0.01 µF0.1 µF0.0047 µF
BW = 100 Hz to 100 kHz
0
10
20
30
40
50
60
70
80
Frequency (Hz)
110k 10M1k
Ripple Rejection − dB
IOUT = 1 mA
IOUT = 1 A
VIN = 4 V
COUT = 10 µF
CNR = 0.01 µF
10 100 100k 1M
0
0.25
0.50
0.75
1
1.25
1.50
1.75
2
2.25
2.50
2.75
3
0 100 200 300 400 500 600
t (s)
VIN = 4 V,
COUT = 10 µF,
IOUT = 1.0 A
Enable
CNR =
0.01 µF
CNR =
0.001 µF
CNR =
0.0047 µF
VOUT (V)
0
10
20
30
40
50
60
70
80
Frequency (Hz)
110k 10M1k
Ripple Rejection − dB
IOUT = 1 mA
IOUT = 1 A
VIN = 4 V
COUT = 10 µF
CNR = 0.1 µF
10 100 100k 1M
0
10
20
30
40
50
60
70
80
Frequency (Hz)
110k 10M1k
Ripple Rejection − dB
IOUT = 1 mA
IOUT = 1 A
VIN = 4 V
COUT = 2.2 µF
CNR = 0.01 µF
10 100 100k 1M
0
20
VIN (V)
t (µs)
5
4
2
−20
−40
3
40
6040200 80 100 120 140 160 180 200
IOUT = 1 A
COUT = 10 µF
CNR = 0.01 µF
dv
dt 1 V
s
∆VOUT (mV)
t (µs)
6
5
3
−20
−40
4
0
20
40
6040200 80 100 120 140 160 180 200
IOUT = 1 A
COUT = 10 µF
CNR = 0.01 µF
dv
dt 1 V
s
VIN (V)∆VOUT (mV)
t (µs)
2
1
−1
−75
−150
0
0
75
150
3002001000 400 500 600 700 800 900 1000
VIN = 3.8 V
COUT = 10 µF
CNR = 0.01 µF
di
dt 1 A
s
IOUT (A)∆VOUT (mV)
TPS796xx
SLVS351G – SEPTEMBER 2002 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS (continued)
TPS79630 TPS79628 TPS79630ROOT MEAN SQUARED OUTPUT DROPOUT VOLTAGE RIPPLE REJECTIONNOISE vs vsvs JUNCTION TEMPERATURE FREQUENCYBYPASS CAPACITANCE
Figure 7. Figure 8. Figure 9.
TPS79630 TPS79630RIPPLE REJECTION RIPPLE REJECTION START-UP TIMEvs vsFREQUENCY FREQUENCY
Figure 10. Figure 11. Figure 12.
TPS79618 TPS79630 TPS79628LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
Figure 13. Figure 14. Figure 15.
6
www.ti.com
0
50
100
150
200
250
300
350
0 100 200 300 400 500 600 700 800 9001000
VDO (mV)
IOUT (mA)
TJ = 125°C
TJ = −40°C
TJ = 25°C
0
50
100
150
200
250
300
2.5 3.0 3.5 4.0 4.5 5.0
VDO (mV)
VIN (V)
TJ = 125°C
TJ = −40°C
TJ = 25°C
IOUT = 1 A
COUT = 10 µF
CNR = 0.01 µF
200 µs/Div
4.0
3.5
2.5
0.5
0
3.0
1.0
1.5
2.0
500 mV/Div
3210 4 5 6 7 8 9 10
VOUT = 2.5 V
RL = 10 Ω
CNR = 0.01 µF
VIN
VOUT
ESR − Equivalent Series Resistance − Ω
IOUT (mA)
100
10
1
0.1
0.01
COUT = 10.0 µF
Region of Stability
101 500 750 10006030 250125
Region of
Instability
ESR − Equivalent Series Resistance − Ω
IOUT (mA)
Region of
Instability
100
10
1
0.1
0.01
COUT = 1 µF
Region of Stability
101 500 750 10006030 250125
ESR − Equivalent Series Resistance − Ω
IOUT (mA)
100
10
1
0.1
0.01
COUT = 2.2 µF
Region of Stability
101 500 750 10006030 250125
Region of
Instability
TPS796xx
SLVS351G – SEPTEMBER 2002 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS (continued)
TPS79625 TPS79630 TPS79601POWER UP/POWER DOWN DROPOUT VOLTAGE DROPOUT VOLTAGEvs vsOUTPUT CURRENT INPUT VOLTAGE
Figure 16. Figure 17. Figure 18.
TPS79630 TPS79630 TPS79630TYPICAL REGIONS OF STABILITY TYPICAL REGIONS OF STABILITY TYPICAL REGIONS OF STABILITYEQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCE(ESR) (ESR) (ESR)vs vs vsOUTPUT CURRENT OUTPUT CURRENT OUTPUT CURRENT
Figure 19. Figure 20. Figure 21.
7
www.ti.com
APPLICATION INFORMATION
Board Layout Recommendation to Improve
GNDEN NR
IN OUT
VIN VOUT
0.01µF
TPS796xx
2.2µF1 µF
External Capacitor Requirements
Regulator Mounting
Programming the TPS79601 Adjustable LDO
VOUT VREF 1R1
R2
(1)
TPS796xx
SLVS351G – SEPTEMBER 2002 – REVISED DECEMBER 2005
The TPS796xx family of low-dropout (LDO) regulators For example, the TPS79630 exhibits 40 µV
RMS
ofhas been optimized for use in noise-sensitive output voltage noise using a 0.1-µF ceramic bypassequipment. The device features extremely low capacitor and a 10-µF ceramic output capacitor. Notedropout voltages, high PSRR, ultralow output noise, that the output starts up slower as the bypasslow quiescent current (265 µA typically), and enable capacitance increases due to the RC time constant atinput to reduce supply currents to less than 1 µA the bypass pin that is created by the internal 250-k Ωwhen the regulator is turned off. resistor and external capacitor.
A typical application circuit is shown in Figure 22 .
PSRR and Noise PerformanceTo improve ac measurements like PSRR, outputnoise, and transient response, it is recommended thatthe board be designed with separate ground planesfor V
IN
and V
OUT
, with each ground plane connectedonly at the ground pin of the device. In addition, theFigure 22. Typical Application Circuit
ground connection for the bypass capacitor shouldconnect directly to the ground pin of the device.
Although not required, it is good analog design
The tab of the SOT223-6 package is electricallypractice to place a 0.1-µF — 2.2-µF capacitor near
connected to ground. For best thermal performance,the input of the regulator to counteract reactive input
the tab of the surface-mount version should besources. A 2.2-µF or larger ceramic input bypass
soldered directly to a circuit-board copper area.capacitor, connected between IN and GND and
Increasing the copper area improves heat dissipation.located close to the TPS796xx, is required for stabilityand improves transient response, noise rejection, and
Solder pad footprint recommendations for the devicesripple rejection. A higher-value input capacitor may be
are presented in an application bulletin Solder Padnecessary if large, fast-rise-time load transients are
Recommendations for Surface-Mount Devices,anticipated and the device is located several inches
literature number AB-132 , available for downloadfrom the power source.
from the TI web site (www.ti.com ).Like most low dropout regulators, the TPS796xxrequires an output capacitor connected between OUT
Regulatorand GND to stabilize the internal control loop. Theminimum recommended capacitance is 1 µF. Any
The output voltage of the TPS79601 adjustable1 µF or larger ceramic capacitor is suitable.
regulator is programmed using an external resistordivider as shown in Figure 28 . The output voltage isThe internal voltage reference is a key source of
calculated using Equation 1 :noise in an LDO regulator. The TPS796xx has an NRpin which is connected to the voltage referencethrough a 250-k Ωinternal resistor. The 250-k Ωinternal resistor, in conjunction with an external
where:bypass capacitor connected to the NR pin, creates alow-pass filter to reduce the voltage reference noise
•V
REF
= 1.2246 V typ (the internal referenceand, therefore, the noise at the regulator output. In
voltage)order for the regulator to operate properly, the current
Resistors R1 and R2 should be chosen forflow out of the NR pin must be at a minimum,
approximately 40-µA divider current. Lower valuebecause any leakage current creates an IR drop
resistors can be used for improved noiseacross the internal resistor, thus creating an output
performance, but the device wastes more power.error. Therefore, the bypass capacitor must have
Higher values should be avoided, as leakage currentminimal leakage current. The bypass capacitor
at FB increases the output voltage error.should be no more than 0.1-µF in order to ensure thatit is fully charged during the quickstart time providedby the internal switch shown in the functional blockdiagram.
8
www.ti.com
Regulator Protection
R1 VOUT
VREF 1R2
(2)
C1 (3 x 10–7) x (R1 R2)
(R1 x R2)
(3)
OUTPUT VOLTAGE
PROGRAMMING GUIDE
OUTPUT
VOLTAGE R1 R2 C1
GND FB
IN OUT
EN
VIN VOUT
R1 C1
R2
TPS79601 1 µF
1.8 V
3.6V
14.0 kΩ
57.9 kΩ
30.1 kΩ
30.1 kΩ
33 pF
15 pF
2.2 µF
TPS796xx
SLVS351G – SEPTEMBER 2002 – REVISED DECEMBER 2005
The recommended design procedure is to chooseR2 = 30.1 k Ωto set the divider current at 40 µA, C1 =
The TPS796xx PMOS-pass transistor has a built-in15 pF for stability, and then calculate R1 using
back diode that conducts reverse current when theEquation 2 :
input voltage drops below the output voltage (e.g.,during power-down). Current is conducted from theoutput to the input and is not internally limited. Ifextended reverse voltage operation is anticipated,external limiting might be appropriate.In order to improve the stability of the adjustableversion, it is suggested that a small compensation
The TPS796xx features internal current limiting andcapacitor be placed between OUT and FB. The
thermal protection. During normal operation, theapproximate value of this capacitor can be calculated
TPS796xx limits output current to approximately 2.8as Equation 3 :
A. When current limiting engages, the output voltagescales back linearly until the overcurrent conditionends. While current limiting is designed to preventgross device failure, care should be taken not toThe suggested value of this capacitor for several
exceed the power dissipation ratings of the package.resistor ratios is shown in the table below (see
If the temperature of the device exceedsFigure 23 ). If this capacitor is not used (such as in a
approximately 165°C, thermal-protection circuitryunity-gain configuration) then the minimum
shuts it down. Once the device has cooled down torecommended output capacitor is 2.2 µF instead of 1
below approximately 140°C, regulator operationµF.
resumes.
Figure 23. TPS79601 Adjustable LDO Regulator Programming
9
www.ti.com
THERMAL INFORMATION
TJTAPDmax x RθJC RθCS RθSA
PDmax VIN(avg)VOUT(avg)IOUT(avg)VIN(avg) I(Q)
A
B
C
TJ
A
RθJC
TC
B
RθCS
TA
C
RθSA
(a) (b)
DDPAK Package
SOT223 Package
CIRCUIT BOARD COPPER AREA
B
A
C
TPS796xx
SLVS351G – SEPTEMBER 2002 – REVISED DECEMBER 2005
increase in temperature due to the regulator's powerThe amount of heat that an LDO linear regulator
dissipation. The temperature rise is computed bygenerates is directly proportional to the amount of
multiplying the maximum expected power dissipationpower it dissipates during operation. All integrated
by the sum of the thermal resistances between thecircuits have a maximum allowable junction
junction and the case (R
ΘJC
), the case to heatsinktemperature (T
J
max) above which normal operation is
(R
ΘCS
), and the heatsink to ambient (R
ΘSA
). Thermalnot assured. A system designer must design the
resistances are measures of how effectively an objectoperating environment so that the operating junction
dissipates heat. Typically, the larger the device, thetemperature (T
J
) does not exceed the maximum
more surface area available for power dissipation andjunction temperature (T
J
max). The two main
the lower the object's thermal resistance.environmental variables that a designer can use toimprove thermal performance are air flow and Figure 24 illustrates these thermal resistances for (a)external heatsinks. The purpose of this information is a SOT223 package mounted in a JEDEC low-Kto aid the designer in determining the proper board, and (b) a DDPAK package mounted on aoperating environment for a linear regulator that is JEDEC high-K board.operating at a specific power level.
Equation 5 summarizes the computation:In general, the maximum expected power (P
D(max)
)consumed by a linear regulator is computed asEquation 4 :
(5)
The R
ΘJC
is specific to each regulator as determined(4)
by its package, lead frame, and die size provided inthe regulator's data sheet. The R
ΘSA
is a function ofwhere:
the type and size of heatsink. For example, black•V
IN(avg)
is the average input voltage.
body radiator type heatsinks can have R
ΘCS
values•V
OUT(avg)
is the average output voltage.
ranging from 5°C/W for very large heatsinks to50°C/W for very small heatsinks. The R
ΘCS
is a•I
OUT(avg)
is the average output current.
function of how the package is attached to the•I
(Q)
is the quiescent current.
heatsink. For example, if a thermal compound is usedFor most TI LDO regulators, the quiescent current is
to attach a heatsink to a SOT223 package, R
ΘCS
ofinsignificant compared to the average output current;
1°C/W is reasonable.therefore, the term V
IN(avg)
x I
(Q)
can be neglected.The operating junction temperature is computed byadding the ambient temperature (T
A
) and the
Figure 24. Thermal Resistances
10
www.ti.com
RθJAmax (125 55)°C2.5 W 28°CW
(9)
TJTAPDmax x RθJA
(6)
RθJA
TJ–TA
PDmax
(7)
15
20
25
30
35
40
0.1 1 10 100
Copper Heatsink Area − cm2
− Thermal Resistance −
θJA
R C/W
°
No Air Flow
150 LFM
250 LFM
DDPAK Power Dissipation
1 oz. Copper
Power Plane
1 oz. Copper
Ground Plane
2 oz. Copper Solder Pad
with 25 Thermal Vias
Thermal Vias, 0.3 mm
Diameter, 1,5 mm Pitch
PDmax (52.5)V x 1 A 2.5 W
(8)
TPS796xx
SLVS351G – SEPTEMBER 2002 – REVISED DECEMBER 2005
Even if no external black body radiator type heatsinkis attached to the package, the board on which theregulator is mounted provides some heatsinking
From Figure 25 , DDPAK Thermal Resistance vsthrough the pin solder connections. Some packages,
Copper Heatsink Area, the ground plane needs to belike the DDPAK and SOT223 packages, use a copper
1 cm
2
for the part to dissipate 2.5 W. The operatingplane underneath the package or the circuit board's
environment used in the computer model to constructground plane for additional heatsinking to improve
Figure 25 consisted of a standard JEDEC High-Ktheir thermal performance. Computer-aided thermal
board (2S2P) with a 1 oz. internal copper plane andmodeling can be used to compute very accurate
ground plane. The package is soldered to a 2 oz.approximations of an integrated circuit's thermal
copper pad. The pad is tied through thermal vias toperformance in different operating environments (e.g.,
the 1 oz. ground plane. Figure 26 shows the sidedifferent types of circuit boards, different types and
view of the operating environment used in thesizes of heatsinks, and different air flows, etc.). Using
computer model.these models, the three thermal resistances can becombined into one thermal resistance betweenjunction and ambient (R
ΘJA
). This R
ΘJA
is valid onlyfor the specific operating environment used in thecomputer model.
Equation 5 simplifies into Equation 6 :
Rearranging Equation 6 gives Equation 7 :
Using Equation 6 and the computer model generatedcurves shown in Figure 25 and Figure 28 , a designercan quickly compute the required heatsink thermalresistance/board area for a given ambienttemperature, power dissipation, and operatingenvironment.
Figure 25. DDPAK Thermal Resistance vs CopperHeatsink AreaThe DDPAK package provides an effective means ofmanaging power dissipation in surface mountapplications. The DDPAK package dimensions areprovided in the Mechanical Data section at the end ofthe data sheet. The addition of a copper planedirectly underneath the DDPAK package enhancesthe thermal performance of the package.
To illustrate, the TPS72525 in a DDPAK packagewas chosen. For this example, the average inputvoltage is 5 V, the output voltage is 2.5 V, theaverage output current is 1 A, the ambienttemperature 55°C, the air flow is 150 LFM, and theoperating environment is the same as documentedbelow. Neglecting the quiescent current, the
Figure 26. DDPAK Thermal Resistancemaximum average power is calculated as Equation 8 :
From the data in Figure 27 and rearrangingSubstituting T
J
max for T
J
into Equation 6 gives
Equation 6 , the maximum power dissipation for aEquation 9 :
different ground plane area and a specific ambienttemperature can be computed.
11
www.ti.com
0
100
120
140
160
180
PCB Copper Area − in2
− Thermal Resistance −
θJA
R C/W
°
No Air Flow
80
60
40
20
0.1 1 10
1
2
3
4
5
0.1 1 10 100
Copper Heatsink Area − cm2
TA = 55°C
No Air Flow
150 LFM
250 LFM
PD Maximum (W)
SOT223 Power Dissipation
PDmax (3.3 2.5)V x 1 A 800 mW
(10)
RθJAmax (125 55)°C800 mW 87.5°CW
0
1
2
3
6
0 25 50 75 100 150125
TA = 25°C
TA (°C)
4
5
4 in2 PCB Area
0.5 in2 PCB Area
PD Maximum (W)
TPS796xx
SLVS351G – SEPTEMBER 2002 – REVISED DECEMBER 2005
Figure 28. SOT223 Thermal Resistance vs PCBFigure 27. Maximum Power Dissipation vs Copper
AreaHeatsink Area
From the data in Figure 28 and rearrangingEquation 6 , the maximum power dissipation for adifferent ground plane area and a specific ambientThe SOT223 package provides an effective means of
temperature can be computed (see Figure 29 ).managing power dissipation in surface mountapplications. The SOT223 package dimensions areprovided in the Mechanical Data section at the end ofthe data sheet. The addition of a copper planedirectly underneath the SOT223 package enhancesthe thermal performance of the package.
To illustrate, the TPS72525 in a SOT223 packagewas chosen. For this example, the average inputvoltage is 3.3 V, the output voltage is 2.5 V, theaverage output current is 1 A, the ambienttemperature 55°C, no air flow is present, and theoperating environment is the same as documentedbelow. Neglecting the quiescent current, themaximum average power is calculated asEquation 10 :
Substituting T
J
max for T
J
into Equation 6 givesEquation 11 :
(11)
Figure 29. SOT223 Power DissipationFrom Figure 28 , R
ΘJA
vs PCB Copper Area, theground plane needs to be 0.55 in
2
for the part todissipate 800 mW. The operating environment usedto construct Figure 28 consisted of a board with 1 oz.copper planes. The package is soldered to a 1 oz.copper pad on the top of the board. The pad is tiedthrough thermal vias to the 1 oz. ground plane.
12
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS79601DCQ ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79601DCQG4 ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79601DCQR ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79601DCQRG4 ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79601KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS79601KTTR ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79601KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79601KTTT ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) Call TI Level-2-260C-1 YEAR
TPS79601KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) Call TI Level-2-260C-1 YEAR
TPS79618DCQ ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79618DCQG4 ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79618DCQR ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79618KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS79618KTTR ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79618KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79618KTTT ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79625DCQ ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79625DCQG4 ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79625DCQR ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79625DCQRG4 ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79625KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS79625KTTR ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79625KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79625KTTT ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79625KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 24-Feb-2006
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS79628DCQ ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79628DCQR ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79628DRBR ACTIVE SON DRB 8 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79628DRBRG4 ACTIVE SON DRB 8 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79628DRBT ACTIVE SON DRB 8 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79628DRBTG4 ACTIVE SON DRB 8 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79628KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS79628KTTR ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79628KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79628KTTT ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79628KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79630DCQ ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79630DCQG4 ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79630DCQR ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79630DCQRG4 ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79630KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS79630KTTR ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79630KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79630KTTT ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79630KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79633DCQ ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79633DCQG4 ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79633DCQR ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79633DCQRG4 ACTIVE SOT-223 DCQ 6 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79633KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS79633KTTR ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 24-Feb-2006
Addendum-Page 2
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS79633KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79633KTTT ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79633KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79650DCQ PREVIEW SOT-223 DCQ 6 TBD Call TI Call TI
TPS79650DCQR PREVIEW SOT-223 DCQ 6 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Feb-2006
Addendum-Page 3
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless
Mailing Address: Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2006, Texas Instruments Incorporated