1. Product profile
1.1 General description
Ultra low capacitance bidirectional double ElectroStatic Discharge (ESD) protection array
designed to protect up to two signal lines from the damage caused by ESD and other
transients. The device is housed in a leadless ultra small SOT883B (DFN1006B-3)
Surface-Mounted Device (SMD) plastic package.
1.2 Features and benefits
1.3 Applications
1.4 Quick reference data
PESD5V0U2BMB
Ultra low capacitance bidirectional double ESD protection
array
Rev. 1 — 13 March 2012 Product data sheet
SOT883B
ESD protection of up to two lines AEC-Q101 qualified
Ultra low diode capacitance Cd=2.9pF ESD protection up to 10 kV
Ultra low leakage current IRM =5nA IEC 61000-4-2; level 4 (ESD)
Computers and peripherals Portable electronics
Audio and video equipment SIM card protection
Cellular handsets and accessories FireWire
Communication systems High-speed data lines
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
Per diode
VRWM reverse standoff voltage - - 5 V
Cddiode capacitance f = 1 MHz; VR=0V - 2.9 3.5 pF
PESD5V0U2BMB All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 13 March 2012 2 of 13
NXP Semiconductors PESD5V0U2BMB
Ultra low capacitance bidirecti onal double ESD protection array
2. Pinning information
3. Ordering information
4. Marking
[1] For SOT883B binary marking code description, see Figure 1.
4.1 Binary marking code description
Table 2. Pinning
Pin Description Simplified outline Graphic symbol
1 cathode
2 cathode
3 common cathode
3
1
2
Transparent
top view
006aab331
3
1
2
Tabl e 3. Ordering i nfo rmation
Type number Package
Name Description Version
PESD5V0U2BMB DFN1006B-3 leadless ultra small plastic package;
3 solder lands; body 1.0 0.6 0.37 mm SOT883B
Table 4. Marking codes
Type number Marking code[1]
PESD5V0U2BMB 00011010
Fig 1. SOT883B binary marking code desc ription
MARKING CODE
(EXAMPLE)
PIN 1 INDICATION READING DIRECTION
READING DIRECTION
READING EXAMPLE:
0111
1011
006aac673
PESD5V0U2BMB All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 13 March 2012 3 of 13
NXP Semiconductors PESD5V0U2BMB
Ultra low capacitance bidirecti onal double ESD protection array
5. Limiting values
[1] Device stressed with ten non-repetitive current pulses (8/20 s exponential decay waveform according to
IEC 61000-4-5 and IEC 61643-321).
[2] Measured from pin 1 or 2 to 3.
[1] Device stressed with ten non-repetitive ESD pulses.
[2] Measured from pin 1 or 2 to 3.
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Per diode
IPPM rated peak pulse current tp=8/20s[1][2] -1.5A
Per device
Tjjunction temperature - 150 C
Tamb ambient temperature 55 +150 C
Tstg storage temperature 65 +150 C
Table 6. ESD maximum ratings
Tamb =25
C unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
Per diode
VESD electrostatic
discharge voltage IEC 61000-4-2
(contact discharge) [1][2] -10kV
machine mode l [2] -400V
MIL-STD-883
(human body model) -8kV
Table 7. ESD standards compliance
Standard Conditions
Per diode
IEC 61000-4-2; level 4 (ESD) > 8 kV (contact)
MIL-STD-883; class 3B (human body model) > 8 kV
PESD5V0U2BMB All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 13 March 2012 4 of 13
NXP Semiconductors PESD5V0U2BMB
Ultra low capacitance bidirecti onal double ESD protection array
6. Characteristics
[1] Device stressed with 8/20 s exponential decay waveform according to IEC 61000-4-5 and IEC 61643-321.
[2] Measured from pin 1 or 2 to 3.
[3] Non-repetitive current pulse, Transmission Line Pulse ( TLP) tp= 100 ns; square pulse;
ANS/IESD STM5-1-2008.
Fig 2. 8 /20 s puls e waveform according to
IEC 61000-4-5 and IEC 61643-321 Fig 3. ESD pulse waveform according to
IEC 61000-4-2
t (μs)
0403010 20
001aaa630
40
80
120
IPP
(%)
0
e−t
100 % IPP; 8 μs
50 % IPP; 20 μs
001aaa631
I
PP
100 %
90 %
t
30 ns 60 ns
10 %
t
r
= 0.7 ns to 1 ns
Table 8. Characteristics
Tamb =25
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Per diode
VRWM reverse standoff
voltage --5V
IRM reverse leakage current VRWM = 5 V - 5 100 nA
VBR breakdown voltage IR=5mA 5.56.59.5V
Cddiode capacitance f = 1 MHz; VR=0V - 2.9 3.5 pF
f=1MHz; V
R=5V - 1.9 - pF
VCL clamping voltage [1][2]
IPP =1A - - 10 V
IPPM =1.5A - - 12 V
rdyn dynamic resistance IR=10A [3] -0.6-
PESD5V0U2BMB All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 13 March 2012 5 of 13
NXP Semiconductors PESD5V0U2BMB
Ultra low capacitance bidirecti onal double ESD protection array
f=1MHz; T
amb =25C
Fig 4. Diode capacitance as a function of reverse
voltage; typical values Fig 5. V-I characteristics for a bidirectional
ESD protection diode
VR (V)
054231
006aab036
2.2
2.6
3.0
Cd
(pF)
1.8
006aab325
−V
CL
−V
BR
−V
RWM
V
CL
V
BR
V
RWM
−I
RM
I
RM
−I
R
I
R
−I
PP
I
PP
−+
I
PPM
−I
PPM
PESD5V0U2BMB All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 13 March 2012 6 of 13
NXP Semiconductors PESD5V0U2BMB
Ultra low capacitance bidirecti onal double ESD protection array
Fig 6. ESD clamping test setup and waveforms
006aab037
50 Ω
Rd
Cs
DUT
(DEVICE
UNDER
TEST)
GND
GND
450 Ω
RG 223/U
50 Ω coax
ESD TESTER
IEC 61000-4-2 network
Cs = 150 pF; Rd = 330 Ω
4 GHz DIGITAL
OSCILLOSCOPE
10×
ATTENUATOR
GND
GND
unclamped +8 kV ESD pulse waveform
(IEC 61000-4-2 network)
clamped +8 kV ESD pulse waveform
(IEC 61000-4-2 network)
unclamped -8 kV ESD pulse waveform
(IEC 61000-4-2 network)
clamped -8 kV ESD pulse waveform
(IEC 61000-4-2 network)
vertical scale = 10 V/div
horizontal scale = 15 ns/div
vertical scale = 10 V/div
horizontal scale = 15 ns/div
vertical scale = 10 V/div
horizontal scale = 100 ns/div
vertical scale = 10 V/div
horizontal scale = 100 ns/div
PESD5V0U2BMB All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 13 March 2012 7 of 13
NXP Semiconductors PESD5V0U2BMB
Ultra low capacitance bidirecti onal double ESD protection array
7. Application information
The device is designed for the protection of up to two bidirectional data or signal lines from
surge pulses and ESD damage. The device is sui table on lines wh ere the si gnal polar ities
are both, positive and negative with respect to ground.
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended:
1. Place the device as clos e to the input terminal or connector as possible.
2. Minimize the path length between the device and the protected line.
3. Keep parallel signal paths to a minimum.
4. Avoid running protected conductors in parallel with unprotected conductors.
5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
ground loops.
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Use ground planes whenever possible. For multilayer PCBs, use ground vias.
8. Test information
8.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is
suitable for use in automotive applications.
Fig 7. Application diag ram
006aac967
PESD5V0U2BMB
GND
signal lines
PESD5V0U2BMB All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 13 March 2012 8 of 13
NXP Semiconductors PESD5V0U2BMB
Ultra low capacitance bidirecti onal double ESD protection array
9. Package outline
10. Packing information
[1] For further information and the availability of packing methods, see Section 14.
Fig 8. Package outline SOT883B (DFN1006B-3)
Table 9. Packing methods
The indicated -xxx are the last thre e digits of the 12NC ordering code.[1]
Type number Package Description Packing quantity
10000
PESD5V0U2BMB SOT883B 2 mm pitch, 8 mm tape and reel -315
PESD5V0U2BMB All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 13 March 2012 9 of 13
NXP Semiconductors PESD5V0U2BMB
Ultra low capacita n ce bidire c ti onal double ESD protection array
11. Soldering
Reflow soldering is the only recommended soldering method.
Fig 9. Reflow soldering footprint SOT883B (DFN1006 B-3)
1.3
0.3
0.6 0.7
0.4
0.9
0.3
(2x)
0.4
(2x)
0.25
(2x)
R0.05 (8x)
0.7
Footprint information for reflow soldering SOT883B
sot883b_fr
occupied area
solder land
solder resist
solder land plus solder paste
solder paste deposit
Dimensions in mm
PESD5V0U2BMB All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 13 March 2012 10 of 13
NXP Semiconductors PESD5V0U2BMB
Ultra low capacita n ce bidire c ti onal double ESD protection array
12. Revision history
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PESD5V0U2BMB v.1 20120313 Product data sheet - -
PESD5V0U2BMB All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 13 March 2012 11 of 13
NXP Semiconductors PESD5V0U2BMB
Ultra low capacita n ce bidire c ti onal double ESD protection array
13. Legal information
13.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
13.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short dat a sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
13.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconduct ors’ aggregate and cumulat ive liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semicondu ctors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, the product is not designed ,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole re sponsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
NXP Semiconductors does not accept any liabil ity related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress rating s only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the obj ective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
PESD5V0U2BMB All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 13 March 2012 12 of 13
NXP Semiconductors PESD5V0U2BMB
Ultra low capacita n ce bidire c ti onal double ESD protection array
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
13.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
14. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors PESD5V0U2BMB
Ultra low capacita n ce bidire c ti onal double ESD protection array
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 March 2012
Document identifier: PESD5V0U2BMB
Please be aware that important notices concerning this document and the product(s)
described herei n, have been included in section ‘Legal information’.
15. Contents
1 Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4.1 Binary marking code description. . . . . . . . . . . . 2
5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Application information. . . . . . . . . . . . . . . . . . . 7
8 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 7
8.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 7
9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
10 Packing information . . . . . . . . . . . . . . . . . . . . . 8
11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
13.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
14 Contact information. . . . . . . . . . . . . . . . . . . . . 12
15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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