s In tel M27210 1M (64K x 16) WORD-WIDE EPROM MILITARY m Military Temperature Range m Fast Programming 55C to + 125C (Tc) Quick-Pulse Programming @ High-Performance HMOS* II-E Algorithms Seconds Typical 200 ns Access Time w New Word-Wide Pinout Low 200 mA Active Power Clean, Flow-Through Architecture m Complete Upgrade Capability - Standard EPROM Features PGM Dont Care Status Allows TTL Compatibility Wiring in Higher Order Addresses Two Line Control m 40-Pin DIP The Intel M27210 is a 5V only, 1,048,576-bit, Electrically Programmable Read Only Memory. It is organized as 64K-words of 16 bits each. It defines a new-clean memory architecture, oriented toward high-performance 16-bit and 32-bit CPUs, which simplifies circuit layout and offers a pin-compatible growth path to higher densities. The M27210s unique circuit design provides for no-hardware-change upgrades to 4N-bits in the future. Since the PGM pin is a dont care state during read mode, direct connections to higher order addresses, A16 and A17, can be made without affecting the devices read operation. The M27210 will be offered in a DIP with the same 4M-bit upgrade path. The M27210 provides the highest density and performance available to 16-bit and 32-bit microprocessors. Its by-16 organization makes it an ideal single-chip firmware solution in most microprocessor applications. The M27210s large capacity is sufficient for storage of operating system kernels in addition to standard bootstrap and diagnostic code. Direct execution of operating system software is made possible by the M27210s fast 200 ns access time, which yields no-WAIT-state operation in such high-performance CPUs as the 10 MHz 80286. The M27210 is part of a two product military megabit EPROM family. Another family member is the M27011. The 8 x 16K x 8 M27011 utilizes page addressing, and continued no-hardware-change upgrades to 32 M-bits in the same JEDEC-compatible 28-pin site. The M27210 shares several features with standard JEDEC EPROMs, including two-line output control for simplified interfacing. It can be programmed rapidly using Intels Quick-Pulse Programming Algorithm, typi- cally within 8 seconds. The M27210 is manufactured using a scaled version of Intels advanced HMOS* I!-E process which assures highest reliability and manufacturability. *HMOS is a patented process of Intel Corporation. DATA OUTPUTS Veco o_ 09-185 GND o> s arn {etter GE | OUTPUT ENABLE PGMe] CHIP ENABLE TE Roe malic OUTPUT BUFFERS ! vecoven |: Y-GATING Ao-Ais Y AONPUTS x : 1,048,576-BIT DECODER : CELL MATRIX : bydbdd td t 271050-1 Figure 1. Block Diagram January 1990 7-90 Order Number: 27 1050-004NOTE: Compatible Higher Density Word Wide EPROM Pin Configurations ara Shown in the Blacks Adjacent 7-91 to the M27210 Pins Figure 2. Cerdip Pin Configurations M27210 4M 2M M27210 2M 4M V VU pp | Vep ver O11 40 vec Veo | Yoo CE | CE eo2 3912 FGM PGM | Aiz Ors | O15 %5O35 380 Nc Aw | Ais O14 | Org %4C4 37D Ats Ais | Ats Og | O19 3095 sep Ata Aya | Ata Ore | O12 %2C16 asp As Aig | Ais Pin Names On | On %7 34D Ara Ara | Aye Ag-Ay7| ADDRESSES O10 | S10 %0C}s. ptt Ay | AN CE CHIP ENABLE Og | Cho 32D A0 Aw | Ato [OE __| OUTPUT ENABLE Os | Os at 10 ps Ao | Ae GND | GND GND E11 30(0 GND GND | GND es a 07 | 07 7412 20/948 Aa | Aa Og | O06 scii3 28, 47 Ay | Az N.C. NO INTERNAL CONNECT Os Os Oschis 27 As Ag Ag D.U. | DON'T USE OQ, | Og cis 2617) As As | As Oa | O3 sCh16 2p As Ag | Ag Oz | Og o17 2p As Ag | Ag O, | O1 Chis 23 42 Az | Az Op | Oo Soci9 2p Ar | Ay OE | OE dE cq 20 21740 Ao | Aa 271050-2intel M27210 ABSOLUTE MAXIMUM RATINGS* Case Operating Temperature NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. Under Bias .........--+-.55 55C to + 125C = * WARNING: Stressing the device beyond the Absolute Storage Temperature .......... 65C to + 125C Maximum Ratings may cause permanent damage. Al Input or Output Votages wit Tree re ee at On Ceoraonded and ox Respect to Ground........... 0.6V to +6.25V tended exposure beyond the Operating Conditions Voltage on Ag with may affect device reliability. Respect to Ground........... 0.6V to + 13.0V Vpp Supply Voltage with Respect to Ground During Programming ....0.6V to + 14V Voc Supply Voitage with Respect to Ground........ 0.6V to + 7.0V Operating Conditions Symbol Description Min Max Units Tc Case Temperature (Instant On) 55 +125 C Voc Digital Supply Voltage 4.50 5.50 Vv READ OPERATION D.C. CHARACTERISTICS (Over Specified Operating Conditions) Limits Symbol . Parameter Min Typ@) Max Units Comments lu Input Load Current 1 pA Vin = 5.5V ILo Output Leakage Current 1 pA Vout = 5.5V Ippy(2) Vpp Load Current Read 1 pA Vpp= 5.5V Isp Voc Current Standby 60 mA CE=Vin icco1@) Voc Current Active 200 mA CE=OE=Vi_ Vit Input Low Voltage -0.1 +0.8 Vv Vin Input High Voltage 2.0 Vect 1 Vv Vo Output Low Voltage 0.45 Vv lol =2.1mA Vou Output High Voltage 2.4 Vv lon= 400 pA A.C. CHARACTERISTICS (Over Specified Operating Conditions) Versions Veco + 10% M27210-20 M27210-25 Unit Symbol Characteristics Min Max Min Max tacc Address to Output Delay 200 250 ns toe CE to Output Delay 200 250 ns toe OE to Output Delay 80 100 ns tor(4) OE High to Output Float 0 60 0 60 ns tou Output Hold from 0 0 ns Addresses CE or OE Whichever Occurred First NOTES: 1. Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 2. The maximum current value is with Outputs Op to O15 unloaded. 3. Typical values are for Tc = 25C and nominal supply voltages. 4. Output Float is defined as the point where data is no longer drivensee timing diagram. 7-92intel M27210 CAPACITANCE Tg. = 25C, f = 1MHz Parameter T Max | Unit | Conditions 6 =0V 12 V =0V 25 Vpp = 0V A.C. TESTING INPUT/OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 1.3V 4 . 2 20 20 4NO14 > TEST POINTS < 3.3K0. 0.8 os 0.45 DEVICE 271050-3 UNDER out A.C. testing inputs are driven at 2.4V for a Logic 1 and 0.45V L= 100 DF for a Logic 0. Timing measurements are made at 2.0V for a L Logic 1 and 0.8V for a Logic 0. = CL = 100 pF 271650-4 C_ Includes Jig Capacitance A.C. WAVEFORMS C= ADDRESSES VALID vu eoee A vs , or tel! Vi TY oE Lot i] tog!!} >4 a tow . LLL rcwvurn wan uN" Wan z VALID OUTPUT ve NAW. 271050-5 NOTES: 1. apical values are for Tc = 25C and nominal supply voltages. 2 may be delayed up to tcetoe after the falling edge of CE without impact on tce. 7-93intel M27210 DEVICE OPERATION The modes of operation of the M27210 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels except for Vpp. Table 1. Modes Selection Pins CE | OE | PGM Ag Ao Vpp Vee Outputs Mode Read Vir | Vit X x(t) x xX 5.0V Dout Output Disable Vit | Vin X X X x 5.0V High Z Standby VIH X Xx X X X 5.0V High Z Programming Vic | Vin Vit X x (Note 4) | (Note 4) Din Program Verify Vir {| Vit Vin X x (Note 4) | (Note 4) Dout Program Inhibit Vin Xx x X x (Note 4) | (Note 4) High Z intgligent | Manufacturer(3) | Vit | Vit x VH@ | Vit Voc .0V 0089 H Identifier Device(3) Vit Vit Xx Vu) | Ving Voc 5.0V OOFFH NOTES: 1. X can be Vi_ or Vin 2. Vy = 12.0V +0.5V 3. Ay-Ag. A1o-A15 = VIL 4. See Table 2 for Voc and Vpp voltages. Read Mode The M27210 has two control functions, both of which must be logically active in order to obtain data at the outputs. Ghip Enable (CE) is the power control and should be used for device selection. Output En- able (OE) is the output control and should be used to gate data from the output pins, independent of device selection. Assuming that addresses are sta- ble, the address access time (tacc) is equa! to the delay from CE to output (ice). Data is available at the outputs after a delay of tog from the falling edge of OE, assuming that CE has been low and address- es have been stable for at least tacc-toe. Standby Mode EPROMs can be placed in standby mode which re- duces the maximum current of the device by apply- ing a TTL-high signal to the CE input. When in stand- by mode, the outputs are in a high impedance state, independent of the OE input. Two Line Output Control Because EPROMs are usually used in larger memo- ry arrays, Intel has provided 2 control lines which accommodate this multiple memory connection. The two control lines allow for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur To use these two control lines most efficiently, CE should be decoded and used as the primary device selecting function, while OE should be made a com- mon connection to all devices in the array and con- nected to the READ line from the system control bus. This assures that all deselected memory devices are in their jow power standby mode and that the output pins are active only when data is desired from a particular memory device. SYSTEM CONSIDERATIONS The power switching characteristics of EPROMs re- quire careful decoupling of the devices. The supply current, Icc, has three segments that are of interest to the system designerthe standby current level, the active current level, and the transient current peaks that are produced by the falling and rising edges of Chip Enable. The magnitude of these tran- sient current peaks is dependent on the output ca- pacitive and inductive loading of the device. The as- sociated transient voltage peaks can be suppressed by complying with Intels Two-Line Control, and by properly selected decoupling capacitors. It is recom- mended that a 0.1 zF ceramic capacitor be used on every device between Voc and GND. This should be a high frequency capacitor for low inherent induc- tance and should be placed as close to the device as possible. In addition, a 4.7 uF bulk electrolytic capacitor should be used between Voc and GND for every eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage droop caused by the inductive effect of PC board-traces.intel M27210 PROGRAMMING MODES Caution: Exceeding 14V on Vpp will permanently damage the device. Initially, and after each erasure, all bits of the EPROM are in the 1 state. Data is introduced by selectively programming Os into the desired bit lo- cations. Although only Os will be programmed, both 1s and Os can be present in the data word. The only way to change a 0 to a 4 is by ultravio- let light erasure (Cerdip EPROMs). The device is in the programming mode when Vpp is raised to its programming voltage (See Table 2) and CE and PGM are both at TTL low. The data to be programmed is applied 16 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. Program [nhibit Programming of multiple EPROMS in parallel with different data is easily accomplished by using the Program inhibit mode. A high-level CE or PGM input inhibits the other devices from being programmed. Except for CE, ail like inputs (including OE) of the parallel EPROMs may be. common. A TTL low-level pulse applied to the PGM input with Vpp at its pro- gramming voltage and TE at TTL-Low will program the selected device. Program Verify A verify should be performed on the programmed bits to determine that they have been correctly pro- grammed. The verify is performed with OE at Vi_, CE at Vi_, PGM at Vy and Vpp and Vcc at their pro- gramming voltages. INTEL EPROM PROGRAMMING SUPPORT TOOLS Intel offers a full line of EPROM Programmers pro- viding state-of-the-art programming for Intel pro- grammable devices. The modular architecture of Intels EPROM programmers allows you to add new support as it becomes available, with very low cost add-ons. For example, even the earliest users of the iUP-FAST 27/K module may take advantage of 7-95 Intels new Quick-Pulse Programming Algorithm, the fastest in the industry. Intel EPROM programmers may be controlled from a host computer using Intels PROM Programming software (iPPS). iPPS makes programming easy for a growing list of industry standard hosts, including the IBM PC, XT, AT and PCDOS compatibles, intel- lec Development Systems. Intels iPDS Personal De- velopment System, and the Intel Network Develop- ment System (iNDS-II). Stand-alone operation is also available, including device previewing, editing, programming, and download of programming data from any source over an RS232C port. For further details consult the EPROM Programming section of the Development Systems Handbook. ERASURE CHARACTERISTICS (FOR CERDIP EPROMS) The erasure characteristics are such that erasure begins to occur upon exposure to light with wave- lengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000A range. Data shows that constant expo- sure to room level fluorescent lighting could erase the EPROM in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. if the device is to be ex- posed to these types of lighting conditions for ex- tended periods of time, opaque labels should be placed over the window to prevent unintentional era- sure. The recommended erasure procedure is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (.e., UV intensity < exposure time) for erasure should be a minimum of 15 Wsec/cm?. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 W/cm? power rat- ing. The EPROM should be placed within 1 inch of the lamp tubes during erasure. The maximum inte- grated dose an EPROM can be exposed to without damage is 7258 Wsec/cm? (1 week @ 12000 pW/ cm2). Exposure of the device to high intensity UV light for longer periods may cause permanent dam- age.M27210 INCREMENT ADDRESS ADDRESS = FIRST LOCATION Voc = 6.25V Vpp = 12.75V DEVICE PASSED 271050-6 Figure 3. Quick-Pulse Programming Algorithm Quick-Pulse Programming Algorithm Intels M27210 EPROMs can be programmed using the Quick-Pulse Programming Algorithm, developed by Intel to substantially reduce the throughput time in the production programming environment. This al- gorithm allows these devices to be programmed in under sight seconds, almost a hundred fold improve- ment over previous algorithms. Actual programming time is a function of the PROM programmer being used. The Quick-Pulse Programming Algorithm uses initial pulses of 100 microseconds followed by a word veri- 7-96 fication to determine when the addressed word has been successfully programmed. Up to 25 100 us pulses per word are provided before a failure is rec- ognized. A flow chart of the Quick-Pulse Program- ming Algorithm is shown in Figure 3. For the Quick-Pulse Programming Algorithm, the en- tire sequence of programming pulses and word veri- fications is performed at Vcc = 6.25V and Vpp at 12.75V. When programming of the EPROM has been completed, all data words should be compared to the original data with Vcc = Vpp = 5.0V.intel M27210 D.C. PROGRAMMING CHARACTERISTICS Tg = 25C +5C Table 2 Limits Comments Symbol Parameter Min Max Unit (Note 1) Iu Input Leakage Current (All Inputs) 10 pA Vin = 6V ViL Input Low Level (All Inputs) 0.1 0.8 Vv Vin _{nput High Level 2.0 Vocot1 Vv Vo Output Low Voltage During Verify 0.45 Vv lo, = 2.1 mA Vou Output High Voltage During Verify 2.4 Vv lon = 400 nA Ioca') Voc Supply Current (Program & Verify) 160 mA CE = PGM = Vit Ipp2 Vpp Supply Current (Program) 50 mA CE = PGM = Vit Vpp Quick-Pulse Programming Algorithm 12.5 13.0 Vv Voc Quick-Pulse Programming Algorithm 6.0 6.5 Vv A.C. PROGRAMMING CHARACTERISTICS To = 25C +5C (See Table 2 for Voc and Vpp voltages.) Symbol Parameter Limits Comments Min | Typ | Max } Unit (Note 1) tas Address Setup Time 2 pS toes OE Setup Time 2 ps tps Data Setup Time 2 ps taH Address Hold Time 0 ps tou Data Hold Time 2 ps toe OE High to Output Float Delay ) 130 ns_ | (Note 2) typs Vpp Setup Time 2 ps tyvcs Voc Setup Time 2 ps tces CE Setup Time 2 BS tpw PGM Initial Program Pulse Width 95 100 105 ps | Quick-Pulse Programming topw PGM Overprogram Pulse Width | 2.85 | __ 78.75 | ms tor Data Valid from OE 150 ns *A.C. CONDITIONS OF TEST NOTES: 1. Voc must be applied simultaneously or before Vpp and Input Rise and Fall Times (10% to 90%)...... 20 ns Oris 2 Simultaneously or at ver is not 100% tested Input Pulse Levels .........--..--++- 0.45V to 2.4V Gutput Float is defined as the point where data is no long- Input Timing Reference Level ....... 0.8V and 2.0V er drivensee timing diagram. Output Timing Reference Level ...... 0.8V and 2,0V we, current value is with outputs Oo~O1s un- 7-97intel M27210 PROGRAMMING WAVEFORMS wa VERIFY Vv wo ADDRESSES x ADDRESS STABLE Mi massac Qs as tan Lo Vin HIGH Z f ~ DATA DATA IN STABLE DATA OUT VALIO pT viv ove tore + tos __pl Lae. FH pf > + + 12.75 1 y we Vep / 5.0v ture aa B.25 od Vee / ; 5.0 tyes Vin cE Mi we a tees ___g Vin a PGM Vi tow toes. tor Vin forpw age a, - \ / me 271050-8 NOTES: 1. The Input Timing Reference Level is 0.8V for Vi_ and 2V for a Viy. 2. toe and tprp are characteristics of the device but must be accommodated by the programmer. 3. When programming the M27210, a 0.1 yF capacitor is required across Vpp and ground to suppress spurious voltage transients which can damage the device. 7-98