AS7C4098A-20TI - Alliance Memory, Inc.

February 2006

AS7C4098A

5.0 V 256 K × 16 CMOS SRAM

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Features

• Pin compatible with AS7C4098

• Industrial and commercial temperature

• Organization: 262,144 words × 16 bits

• Center power and ground pins

• High speed

- 10/12/15/20 ns address access time

- 5/6 ns output enable access time

• Low power consumption: ACTIVE

- 990mW/max @ 10 ns

• Low power consumption: STANDBY

- 55mW/max CMOS

• Individual byte read/write controls

• Easy memory expansion with CE, OE inputs

• TTL- and CMOS-compatible, three-state I/O

• 44-pin JEDEC standard packages

- 400-mil SOJ

- TSOP 2

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Logic block diagram

1024 × 256 × 16

Array

(4,194,304)

WE Column decoder

Row Decoder

GND

A12

A10

A11

A14

A15

A16

A17

A13

Control circuit

I/O1–I/O8

I/O9–I/O16

I/O

buffer

Pin arrangement for SOJ and TSOP 2

I/O14

I/O13

GND

I/O12

I/O11

I/O10

I/O9

A14

A13

A12

A11

A10

I/O1

I/O2

I/O3

I/O4

GND

I/O5

I/O6

I/O7

I/O8

TSOP2

I/O16

I/O15

2A1 3A2

4A3

1A0

A16

A15

A17

44-pin (400 mil) SOJ

Selection guide

–10 –12 –15 –20 Unit

Maximum address access time 10 12 15 20 ns

Maximum output enable access time 5 6 6 6 ns

Maximum operating current 180 160 140 120 mA

Maximum CMOS standby current 10 10 10 10 mA

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Functional description

The AS7C4098A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as

262,144 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are

desired.

Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6 ns are ideal

for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory

systems.

When CE is high the device enters standby mode. The device is guaranteed not to exceed 55mW power consumption in CMOS

standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/

O1–I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices

should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip

drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or

write enable is active, output drivers stay in high-impedance mode.

The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be

written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.

All chip inputs and outputs are TTL- and CMOS-compatible, and operation is for 5.0V (AS7C4098A) supply. The device is

available in the JEDEC standard 400-mL, 44-pin SOJ, TSOP 2 packages.

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Absolute maximum ratings

Parameter Symbol Min Max Unit

Voltage on VCC relative to GND Vt1 –0.50 +7.0 V

Voltage on any pin relative to GND Vt2 –0.50 VCC +0.50 V

Power dissipation PD–1.5W

Storage temperature (plastic) Tstg –65 +150 °C

Ambient temperature with VCC applied Tbias –55 +125 °C

DC current into outputs (low) IOUT –±20mA

Truth table

CE WE OE LB UB I/O1–I/O8 I/O9–I/O16 Mode

HXXXX High Z High Z Standby (ISB, ISB1)

LHHXX

High Z High Z Output disable (ICC)

LXXHH

LHL

LH D

OUT High Z

Read (ICC)HL High Z D

OUT

LL D

OUT DOUT

LLX

LH D

IN High Z

Write (ICC)

HL High Z D

LL D

IN DIN

Key: X = Don’t care, L = Low, H = High.

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*VIH max = VCC + 1.5V for pulse width less than 5 nS.

**VIL min = –1.0V for pulse width less than 5 nS.

Recommended operating conditions

Parameter Symbol Min Typical Max Unit

Supply voltage VCC (10/12/15/20) 4.5 5.0 5.5 V

Input voltage VIH*2.2 – VCC + 0.5 V

VIL** –0.5 – 0.8 V

Ambient operating temperature commercial TA0– 70°C

industrial TA–40 – 85 °C

DC operating characteristics (over the operating range)1

Parameter Symbol Test conditions

–10 –12 –15 –20

Unit NotesMin Max Min Max Min Max Min Max

Input leakage

current |ILI|VCC = Max

VIN = GND to VCC

– 1– 1 –1–1µA

Output

leakage

current

|ILO|

VCC = Max

CE = VIH or OE = VIH

or WE = VIL

VI/O = GND to VCC

– 1– 1 –1–1µA

Operating

power supply

current

ICC

VCC = Max

CE < VIL, f = fmax, IOUT = 0 mA - 180 - 160 - 140 - 120 mA

Standby

power supply

current

ISB

VCC = Max

CE > VIH, f = Max -60-55-50-45mA

ISB1

VCC = Max

CE ≥ VCC – 0.2V, VIN ≥ VCC

– 0.2V or VIN ≤ 0.2V, f = 0

-10-10-10-10mA

Output

voltage

VOL

IOL = 6 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 V4

IOL = 8 mA, VCC = Min – 0.5 – 0.5 – 0.5 – 0.5

VOH IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – 2.4 – V 4

Capacitance (f = 1MHz, Ta = 25° C, VCC = NOMINAL)4

Parameter Symbol Signals Test conditions Max Unit

Input capacitance CIN A, CE, WE, OE, UB, LB VIN = 0V 6 pF

I/O capacitance CI/O I/O VIN = VOUT = 0V 8 pF

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Key to switching waveforms

Read waveform 1 (address controlled)5,6,8

Read cycle (over the operating range)2,8

Parameter Symbol

–10 –12 –15 –20

Unit NotesMin Max Min Max Min Max Min Max

Read cycle time tRC 10 – 12–15–20– ns

Address access time tAA – 10 –12–15–20ns

Chip enable (CE) access time tACE – 10 –12–15–20ns

Output enable (OE) access time tOE – 5 –6–6–6ns

Output hold from address change tOH 3 – 3–3–3–ns4

CE Low to output in low Z tCLZ 3 – 3–3–3–ns3, 4

CE High to output in high Z tCHZ – 5 –6–7–9ns3, 4

OE Low to output in low Z tOLZ 0 – 0–0–0–ns3, 4

OE High to output in high Z tOHZ – 5 –6–7–9ns3, 4

LB, UB access time tBA – 5 –6–7–8ns

LB, UB Low to output in low Z tBLZ 0 – 0–0–0–ns

LB, UB High to output in high Z tBHZ – 5 –6–7–9ns

Power up time tPU 0 – 0–0–0–ns4

Power down time tPD – 10 –12–15–20ns 4

Undefined/don’t careFalling inputRising input

Data

OUT

Address

Data validPrevious data valid

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Read waveform 2 (CE, OE, UB, LB controlled)5,7,8

Write cycle (over the operating range)9

Parameter Symbol

–10 –12 –15 –20

Unit NoteMin Max Min Max Min Max Min Max

Write cycle time tWC 10–12–15–20– ns

Chip enable (CE) to write end tCW 7–8–10–12–ns

Address setup to write end tAW 7–8–10–12–ns

Address setup time tAS 0–0–0–0–ns

Write pulse width (OE = High) tWP1 7–8–10–12–ns

Write pulse width (OE = Low) tWP2 10–12–15–20– ns

Write recovery time tWR 0–0–0–0–ns

Address hold from end of write tAH 0–0–0–0–ns

Data valid to write end tDW 5–6 7–9–ns

Data hold time tDH 0–0–0–0–ns3, 4

Write enable to output in High-Z tWZ 25262729ns3, 4

Output active from write end tOW 3–3–3–3–ns3, 4

Byte enable Low to write end tBW 7–8–10–12–ns3, 4

Data valid

BLZ

OLZ

OHZ

CHZ

BHZ

ACE

CLZ

Address

LB, UB

Data

OUT

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Write waveform 1(WE controlled)9

Write waveform 2 (CE controlled)9

Address

LB, UB

Data

OUT

Data undefined High Z

Data valid

Address

LB, UB

Data

Data valid

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Write waveform 3 9

AC test conditions

Notes

1During V

CC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.

2 For test conditions, see AC Test Conditions, Figures A and B.

CLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured ±500mV from steady-state voltage.

4 This parameter is guaranteed, but not tested.

5WE

is High for read cycle.

6CE

and OE are Low for read cycle.

7 Address valid prior to or coincident with CE transition Low.

8 All read cycle timings are referenced from the last valid address to the first transitioning address.

9 All write cycle timings are referenced from the last valid address to the first transitioning address.

10 C = 30 pF, except on High Z and Low Z parameters, where C = 5 pF.

Address

LB, UB

Data

OUT

Data undefined

High Z High Z

Data valid

- Output load: see Figure B.

- Input pulse level: GND to VCC - 0.5V. See Figure A.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

10%

90%

10%

90%

GND

VCC - 0.5V

2 ns

Figure A: Input pulse

255

Ω

480

Ω

OUT

GND

+5.0V

Figure B:5.0V Output load

168

Ω

OUT

+1.728V

Thevenin equivalent:

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Package dimensions

44-pin TSOP 2

Min (mm) Max (mm)

A1.2

A10.05 0.15

A20.95 1.05

b0.30 0.45

c0.12 0.21

d18.31 18.52

e10.06 10.26

He11.68 11.94

E0.80 (typical)

l0.40 0.60

1234567891011121314

44 43424140393837363534333231

1516

3029

1718 1920

272625

44-pin TSOP 2

0–5

44-pin SOJ 400 mils

Min(mils) Max(mils)

A0.128 0.148

A1 0.025 -

A2 0.105 0.115

B0.026 0.032

b0.015 0.020

c0.007 0.013

D1.120 1.130

E0.370 NOM

E1 0.395 0.405

E2 0.435 0.445

e0.050 NOM

Seating

Plane

44-pin SOJ

Pin 1

AA2

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Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts. (EX: AS7C4098A - 10TCN)

Ordering Codes

Package Version 10 ns 12 ns 15 ns 20 ns

SOJ 5.0V commercial AS7C4098A-10JC AS7C4098A-12JC AS7C4098A-15JC AS7C4098A-20JC

5.0V industrial AS7C4098A-10JI AS7C4098A-12JI AS7C4098A-15JI AS7C4098A-20JI

TSOP 2 5.0V commercial AS7C4098A-10TC AS7C4098A-12TC AS7C4098A-15TC AS7C4098A-20TC

5.0V industrial AS7C4098A-10TI AS7C4098A-12TI AS7C4098A-15TI AS7C4098A-20TI

Part numbering system

AS7C 4098A –XX J or T X X

SRAM prefix Device

number

Access

time

Packages:

J: SOJ 400 mil

T: TSOP 2

Temperature ranges:

C: Commercial, 0°C to 70°C

I: Industrial, –40°C to 85°C

N = Lead Free Parts

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Revision History

Rev. No. History Revised Date

v1.0 Initial release 11/08/04

v1.1 Included ICC, ISB & ISB1 parameters 05/27/05

Corrected the following: TOE, VIH, VOL & tWZ

v1.2 Removed the title “PRELIMINARY INFORMATION” 02/21/06

Alliance Semiconductor Corporation

2575, Augustine Drive,

Santa Clara, CA 95054

Tel: 408 - 855 - 4900

Fax: 408 - 855 - 4999

www.alsc.com

Part Number: AS7C4098A

Document Version: v 1.2

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AS7C4098A