19.0218, Fev 2 4496 ____ General Description The MAX680 Family of supervisory circuits reduce the complexity and number of components required for power supply monitoring and battery control functions in microprocessor systems. These include zP reset and backup-battery switchover, watchdog timer, CMOS RAM write protection, and power-failure warning. The MAX690 Family significantly improves system reliability and accuracy compared to that obtainable with separate ICs or discrete components. The MAX690, MAX692 and MAX694 are supplied in 8-pin packages and provide four functions: 1) A Reset output during power-up, power-down and brownout conditions. 2) Battery backup Switching for CMOS RAM, CMOS microprocessor or other low power logic. 3) A Reset pulse if the optiona! watchdog timer has not been toggled within a specified time. 4) A 1.3V threshold detector for power fail warning, low battery detection, or to monitor a power supply other than +5V. The MAX691, MAX693 and MAX695 are supplied in 16-pin packages and perform ali MAX690/692/694 functions, plus: 1) Write protection of CMOS RAM or EEPROM. 2) Adjustable reset and watchdog timeout periods. 3) Separate outputs for indicating a watchdog timeout, backup-battery switchover, and low Voc. Applications Computers Controllers Intelligent Instruments Automotive Systems Critical uP Power Monitoring _____(CSRPn- Crniguratticn MAALNVI Microprocessor Supervisory Circuits # Precision Voltage Monitor 4.65V In MAX690, MAX6$1, MAX694 and MAX695 4.40V in MAX692 and MAX633 @ Power OK/Reset Time Delay - 50, 200ms, or adjustable # Watchdog Timer - 100ms, 1.6 sec, or adjustable @ Minimum Compenent Count @ 1yA Standby Current @ Battery Backup Power Switching @ Onboard Gating of Chip Enable Signals Voltage Monitor for Power Fall or Low Battery Features Warning Ordering Information PART | _-TEMP.RANGE _~PIN-PACKAGE | MAXBHICPA OC to 470C 8 Lead Plastic DIP MAXGSOC/D OPC to +70C Dice | MAXGS0EPA 40C 10 485C 8 Lead Plastic DIP MAXBQ0EJA -A0C to +B5-C 8 Lead CERDIP | MAXGSOMJA 65C to+128C Lead CERDIP | MAX691CPE OCioz7C 16 Lead Plastic DIP MAX691CWE C 10 +70C 16 Load Wide SO [MAXBSC/O PC tO $+ FOP Dice* MAX69 IEPE -40C to +85C 16 Lead Plastic DIP MAXOSIEWE -40C to 485C 1S Lead Wide SO | MAXE9TEJE 40Cto 485C 16 Lead CERDIP | MAX6SIMJE SSP to +125C 16 Lead CERDIP_| Ordering Information contmued an last page. *Cantact factory tor dice specifications Typical Operating Circuit S6/6/6/Z6/1.6/O69XVW Top View Vout (8) Veart | AELAXx LAI Vee MAX690 7] RESET GND MAxeo2 [Ce] wal ~ (POWER TO uP pace] AXE FS oe sy io our CMOS RAM POWER f >] BATT = MARI ovo <= x690 Veart CJ [a] RESET aEREY vel op FERET Your Pe) RESET PFI PFD uP NMI Yee) Anaxinn woo woe | V6 SHO LE! yayeg [E) CE IN GND LIME BATT ONE] MAXeoS A CE OUT aE <I tow owe CE] MAX695 Ty yy = osc in 70] PFO . a MAX690 Typical Application osc see I rs) PF yp PP _ uN, - S/VIAXAL FI Maxim integrated Products 1 Call toll free 1-800-998-8800 for free samples or literature.MAX690/91/92/93/94/95 Microprocessor Supervisory Circuits ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect to GND) VOG - eee cree eee e teeta -0.3V to 6.0V VBATT cece e eee cece eee ee 0.3V to 6.0V All Other Inputs (Note 1) .. 0.3V to (VouT +0.5V) [a 200mA VBATT oe cece cece eee cece e teen es 50mA Dee cece eee eee 20mA Output Current VOUT cece eee ccc eee eee short circuit protected Ail Other Outputs .... 2.0... .0 000 ae 20mA Rate-of-Rise, Vaart, Veco 2... lees eee eee 100V/us Operating Temperature Range C suffix 0. eee eee oc to +70C E suffix... 0.0.20. cece 40C to +88C M suffix o. 0.0. eee S58C to +1268C Power Dissipation 8 Pin Plastic DIP {Derate 5mW/C above +70C} .......... 400mWw 8 Pin CEADIP (Derate BMW/C above +85C) .......... 500mWwW 16 Pin Plastic DIP (Derate 7mW/C above +70C) .......... 600mw 16 Pin Small Outline (Derate 7mW/C above +70C) .......... 600mW 16 Pin CERDIP (Derate iOMW/C above +85C) 1.00.2... 600mW Storage Temperature Range ..... 68C to +160C Lead Temperature (Soldering, 10 seconds) .... 300C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage ta Iie device. These are stress ratings only, and funchonal operation of the device at these or any ather conditions above those indicalad Jn the operational sections of the specifications 13 nat umphed. Exposure ta absolute maximum ratings conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Vcc = full operating range, Vaart = 2.84, Ta = 25C, unless otherwise noted.) PARAMETER | CONDITIONS MIN TYP MAX | UNITS | BATTERY BACKUP SWITCHING | Operating Voltage Range I MAX690, MAX691, MAX694, MAX695 Vic 4.75 5.5 MAX690, MAX691, MAXBS4, MAX695 Veary 2.0 4.26 v MAX692, MAX893 Voc 45 5.5 MAX692, MAX693 Veatr 2.0 4.0 lout = 1mA Veo-0 3 Ver -0.1 Vour Outpul Voltage lour = SOmA Vee- 0.8 Vog0.25 v | Your in Battery Backup Mode loin = 250A, Veco -. Vpat1-O.2V Voeat; O01 Voearr -0.02 Vv | loua = TMA 2 5 Supply Current (exeiudes lout) lour = 5OmA 365 10 mA Supply Current in Battery Backup Mode Veo = OV, Vaart = 2.8V 0.6 1 ua B.5V Veo = Veattt 1 Battery Standby Current Ta = 25C 01 10,02 BA (i Discharge, -- =: Charge) Ts = Full Operating Range 1,.0 +0.02 Batiery Switchover Threshold Power Up 70 inv Veo Vaatr Power Down 50 Battery Switchover Hysteresis 20 my BATT ON Output Voltage loin = 3.2mA j 04 BATT ON Qutput Short BATT ON - Vous = 4.5V Sink Current 25 mA Circuit Current BATT ON = OV Source Current 06 1 25 pA RESET AND WATCHDOG TIMER 4 Ta = Full Operating Range r | Reset Voltage Threshold MAX690, MAX691, MAX6S4, MAX695 45 4.65 4.75 v j MAX692, MAX693 4.25 4.4 45 Vv Note 1: The input voltage limits on PF) and WDI may be exceeded provided the input current is limited 10 less than 10mA. __ #/MAALVIELECTRICAL CHARACTERISTICS (continued) (Vcc = full operating range, Vaatr = 2.8, Ta = 25C, unless otherwise noted.} Microprocessor Supervisory Circuits [ PARAMETER CONDITIONS MIN TYP MAX UNITS | Reset Threshold Hysteresis 40 mv | Reset Timeout Delay (MAX690/91/92/63) Figure 6. OSC SELHIGH, Ven = 5V | 95 50 70 | ms Reset Timeout Delay (MAX694/95) Figure 6. OSC SEL HIGH, Voc =- 5V 140 200 "380 ms Watchdog Timeout Period, Internal Oscillator She ale 1 = ey e ; on ic ine Watchdog Timeout Period, External Glock ore aes ae 1025 Gules Minimum WDI Input Pulse Width : Von 0.4, Vin = G-8V ce 200 ns RESET and LOW LINE Qutput Voltage ete = eA Woe = 35 04 Vv RESET and WOO Output Voltage Se eA. Ver < 5V 35 o4 v | Qutput Short Circuit Current RESET, RESET, WOO, LOW LINE 1 3 35 pA WDI Input Threshaid Vee = 5V (Note 2) a ~ Logic Low 08 Vv Logic High 3.5 WO! Input current Wet = Nour 50 a 50 ua POWER FAIL DETECTOR PFi input Threshold Veo = +5V, Ta = Full 1.2 13 | Vv PFI Input Current +0.01 25 T- nA PFO Qutput Voltage ee = oe 35 G4 PFO Short Circuit Source Current PFI = Vi, PFO = OV 1 3 2 pA CHIP ENABLE GATING 7 CE IN Threshotds Ty vt a0 0.8 v ) GE IN Pullup Current 3 ua | _ Ise = 3.2mA a a 0.4 GE OUT Output Voltage lsounce = 3.0mA Vour 1.5 v lsournce = 1A, Veo = OV Vour0.05 [cE Propagation Delay Veo = 5V 50 200 ns | OSCILLATOR a a | | OSC IN Input Current _ 420 uA | | OSC SEL Input Pullup Current a 5 aA | | OSC IN Frequency Range "| O80 SEL = ov ~~ 0 250 kHz | OSC IN Frequency | ~~ | OSC SEL ov _ ~~ He with External Capacitor Cosc = 47pF 4 Note 1: The input voltage limits on PFI and WDI may be exceeded provided the input current is limited ta Jess than 10mA. Note 2: WDI is guaranteed to be in the mid-level (inactive) state if WDI is floating and Vcc is in the operating voltage range. WDlis internally biased to 38% of Voc with an impedance of approximately 125 kilohms. MAXIMA _ $6/06/E6/26/16/O69XVNMAX690/91/92/93/94/95 Microprocessor Supervisory Circuits CSP DeeSription TO ST Maxeoo/ | Maxey FUNCTION 92/604 693/695 a | 3 The +SVinput oO a 1 Backup battery input. Connect to Ground if a backup batlery is not used _ 4a 2 The higher of Veg oF Vaar, is internally switched to Voi Connect Vou1 to Ver if GND 3. | Von ur a and id Vrart are not used, Connect a 0 1pF or larger bypass capacitor to Vou. {ws Ground reference for ail signals. 5 RESET goes low whenever Vor falls below either the reset voltage threshold or the Vuatr input voltage. The reset threshald 1s typically 4.65V far the MAX690/ 691/694/695, and 4.4V for the MAX692 and MAX693. RESET remains low for 50ms after Voc returns to 5V, (except 200ms in MAX694/695). RESET alse goes low for 50ms if the Watchdog Timer is enabled but not Serviced within its timeout period. The RESET pulse width oc can be adjusted as shown in Table 1. PFI it The watchdog input, WO, is a three devel input. If WDL remains either high on ar law for ianger than the watchdog timeout period, RESET pulses low and WDO goes low, The Watchdog Timer is disabled when WDI is left floating or is driven to mid-supply. The timer resets with each transition at the Watchdog Timer Input. 9 PFI is the non-inverting input to the Power Fail Comparaior When PFI is is less than 1.3, PFO goes low. Connect PFI to GND or Vour when not used See Figure 1. 10 PFO is the output of the Power Fail Comparator. It goes 8s low W when PFlis less than | 1 13y, The comparator is turned off and PFO qoes low when Vcc 1s below Vaart. 14 The input to the CE gating circuit. Connect to GND or Vout if not used 12 CE OUT goes low only when CE IN is low and Vcc is above the reset threshald | (4.65V for MAX691 and MAX695, 4.4V for MAX693). See Figure 6. 5 BATT ON goes high when Vout $8 internally switched to the Vearr input. It goes low when Vour is internally switched to Vec. The output typically sinks 25mA and can directly drive the base of an external PNP transistor to increase the output current @ above the the 5OmA vA raling af af Your. _| 6 LOW LINE goes low when Ve ec falls below the reset threshold. It returns high as s | soon a8 Voc. rises above the reset threshold. See Figure 6, Reset Timing. 16 RESET is an active high output. It is the inverse of RESET 8 When OSC SEL is unconnected or driven high, the internal oscillator sets the reset time delay and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN, is enabled. OSC SEL nas a 3A internal pullup See Table 1. OSC iN 7 When OSC SEL is iow, OSC IN can be driven by an external clack to adjust both the rset delay and the watctidog timeout period The timing can alsa be adjusted by connecting an external capacitor lo this pin See Figure 8 When OSC SEL is high or floating, OSC IN selects between fast and slow Waichdog timeout periods i4 The Watchdog Output. WDO, goes low if WDI rmaing either high or low for longer than the Watchdog timeout period. WOO is sei high by the next transition at WDI. If WDI is unconnected or at mid-supply, WDO remains high. WDO alsa goes high when LOW LINE goes low. #AAXIM__ Typical Applications MAX69 1, MAX693 and MAX695 Atypical connection for the MAX691/693/695 is shown in Figure 1. CMOS RAM is powered from Vout. Your is internally connected to Voc when 5V power is present, or tO Vpa77 when Veo is less than the battery voltage. Voyr can supply 50mA from Vee, but if more current is required, an external P transistor can be added. When Vac is higher than Vestry, the BATT ON output goes low, providing 25mA of base drive for the external transistor. When Ver is lower than Vear7, an internal 2000 MOSFET connects the backup battery ta Vout. The quiescent current in the battery backup mode is vA maximum when Voc is between OV and Vaarr OOM. Reset Gutput A voltage detector monitors Vcc and generates a RESET output to held the microprocessors Reset line low when Vec is below 4.65V (4.4V for MAX693). An internal monostable holds RESET low for 50ms after Voc rises above 4.65V (4.4V for MAX693). This prevents repeated toggling of RESET even if the 5V power drops out and recovers with each power line cycle. The crystal oscillator normally used to generate the clock for microprocessors takes several milliseconds to start. Since mast_microprocessors need several clock cycles to reset, RESET must be held fow until the microprocessor clock oscillator has started. The "200ms for MAX695 Microprocessor Supervisory Circuits MAX680 Farnily power-up RESET pulse lasts 50ms* to allow for this oscillator start-up time. The manual reset switch and the 0.1uF capacitor connected to the reset bus can be omitted if manual reset is not needed. An inverted, active high, RESET cutput is also supplied. Power Fall Detector The MAX691/93/95 issues a non-maskable interrupt (NMi) to the microprocessor when a power failure occurs. The +5V power line is monitored via two external resistors connected to the Power Fail Input {PFi}. When the voltage at PFI falls below 1.3, the Power Fail Output (PFO) drives the processors NMI input low. If a Power Fail threshald of 4.8V is chosen, the microprocessor will have the time when Vcc fails from 4.8V to 4.65V to save data into RAM. An earlier power fail warning can be generated if the unregulated DC input of the 5V regulator is available for monitoring. RAM Write Protection The MAX691/93/95 CE OUT line drives the Chip Setect inputs of the CMOS RAM. CE OUT follows CE IN as long as Vec is above the 4.65V {4.4V for MAX693)_ reset threshold, if Vcc falls below the reset threshold, CE QUT goes high, independent of the logic level at CE IN. This prevants the microprocessor from writing erroneous data into RAM = during power-up, power-cown, brownouts, and momentary power interruptions. The LOW LINE output goes law when Vcc falls below 4.65 (4.4V for MAX693}. +5 Vee * ee eer weuT = Loe YL i t - 3 15 Lt | BATT ON I Year Vout = W $ . [12 | cmos BATTERY a CE OUT RAM PFI (13 [| aponess cE IN-] DecoDE AAMT + MAX891 " - * 4 ana MAX693 WOl p vo MO-ANS f MAX695 _}10 = ; PFO | NMI 4 ot IN __| 15 __ NO CONNECTION 8 RESET RESET |0se se ase t tow LINE woo L [ow MICROPROCESSOR 6 14 == | AUDIBLE ALARM OTHER SYSTEM RESET SOURCES SYSTEM STATUS INEXCATORS Figure 1. MAX691/693/595 Typical Application MAXXIS S$6/P6/6/Z6/16/O69XUNMAX690/91/92/93/94/95 Microprocessor Supervisory Circuits Watchdog Timer The microprocessor drives the WATCHDOG INPUT (WDH with an {1/0 line. When OSC IN and OSC SEL are unconnected, the microprocessor must toggle the WDI pin once every 1.6 seconds to verify proper software execution. If a hardware or software failure occurs such that WDI not toggled, the MAX691/93 will issue a 50ms* RESET pulse after 1.6 seconds. This typically restarts the microprocessor's power-up routine. A new RESET pulse is issued every 1.6 seconds until WDI is again strobed. The WATCHDOG OUTPUT (WOO) goes low if the watchdog timer is not serviced within its timeout period. Once WDO goes low it remains low until a transition occurs at WDI. The watchdog timer feature can be disabled by leaving WDI unconnected. OSC IN and OSC SEL also allow other watchdog timing options, as shown in Table 1 and Figure 8. MAX690, MAX6982 and MAX694 The 8 pin MAX690, MAX692 and MAX694 have most of the features of the MAX691, MAX693 and MAX695. "Z00ms for MAX6Q5 Figure 2 shows the MAX690/692/694 in a typical application. Operation is much the same as with the MAX691/693/695 (Figure 1} but in this case the Power Fail Input (PFI) monitors the unregulated input to the 7805 regulator. The MAX690/694 RESET guipul goes low when Vec falls below 4.65V, The RESET output of the MAX692 goes low when Vec drops below 4.4V. The current consumption of the battery-backed-up power bus must be less than 50mA. The MAX690/692/694 does not have a BATT ON output to drive an external transistor. The MAX690/92/94 also does not include chip enable gating circuitry that is available_on the MAX691/93/95, In many systems though, CE gating i$ Not needed since a low input to the microprocessor RESET line prevents the processor from writing to RAM during power-up and power-down transients. The MAX690/92/84 watchdog timer has a fixed 1.6 second timeout period. If WOLremains either low or high for more than 1.6 seconds, a RESET pulse is sent to the microprocessor. The watcthdag timer is disabled if WDI is left floating. +a +5 2 1 Olek T POWER = MICO. 7805 1 Vcc Your -~] 10 PROCESSOR 3-TERMINAL L cmos POWER REGULATOR AAAxLAA = | me :.> MAX690 Your | MAXBO2 aa eee = MICROPROGESSOR RESET 1 RESET Pri Pro 3 et WH 6 WOl - 41/0 LINE &ND BB Figure 2. MAX690/692/694 Typical Application 6 MAXIDetailed Description Battery-Switchover and Vour The battery switchover circuit compares Vac to the Vaarz input, and connects Your to whichever is higher. Switchover occurs when Vcc is 50mV greater than Veatt a8 Veo falls, and when Vcc is 7OmV more than Veatt 38 Voc rises (see Figure 4). The switchover comparator has 2OmV of hysteresis to prevent repeated, rapid switching if Vcc falls very slowly or remains nearly equai to the battery voltage. When Veco is higher than Vearr. oc is internally switched to Voy, via a low saturation PNP transistor. Vour has 50mA output current capability. Use an external PNP pass transistor in parallel with internal transistor if the output current requirement at Vouq exceeds 50mA or if a lower Vog-Vour voltage differen- tial is desired. The BATT ON output (MAX691/693/695. only) can directly drive the base of the external transistor. lt should be noted that the MAX690/91/92/93/94/95 need only supply the average current drawn by the CMOS RAM if there is adequate filtering. Many RAM data sheets specify a 75mA maximum supply current, but this peak current spike lasts only 100ns. A O.14F bypass capacitor at Vour supplies the high instantaneous current, while Vout need only supply the average load current, which is much less. A capacitance of O.1uF or greater must be connected to the Vout terminal to ensure stability. A 2000 MOSFET connects the Vaaz7 Input 0 Vout Microprocessor Supervisory Circuits during battery backup. This MOSFET has very low input- to-output differential (dropout voltage) at the low current levels required for battery backup of GMOS RAM or other low power CMOS circuitry, When Vcc equals Veatt the supply current is typically 124A. When Voc is between OV and (Veart700mvV} the typical supply current is only GOOnA typical, 14A maximum. The MAX6S0/MAX69 T/MAX6394/MAX695 operate with bat- tery voltages fram 2.0V to 4.25V while the MAX692/MAX693 operate with battery voltages from 2.GV to 4.0V. High value capacitors can also be used for short-term memory back- up. External circuitry is required to ensure that the capaci- tor voltage does not rise above the reset threshold, and that the charging resistor does not discharge the capacitor when in backup mode. Tne MAX691A and the MAx791 provide solulions requiring fewer external components. Asmatt charging current of typically 10nA (G.14A max) flows out of the Vearq terminal. This current varies with the amount of current that Is drawn from Vor but its polarity is such that the backup battery Is always slightly charged, and is never discharged while Ver is in its operating voltage range. This extends the shelf life of the backup battery by compensating for its self- discharge current. Also note that this current poses no problem when lithium batteries are used for backup since the maximum charging current (0.17A) is safe for even the smallest lithium cells. lf the battery-switchover section is not used, connect VeaTt to GND and connect Vout to Vc. Table 2 shows the state of the inputs and output in the low power battery backup mode. Veatt + 5 g BATT ON I 3 + Le Vout Vee ' l 2 B CHIP-ENABLE INPUT *4.4U (MAXG93] RESET GENERATOR 2 ff > CHIP ENABLE OUTPUT >> LW LINE b rae HESET | 7 RESET OSC IN OSC SEL > TIMEBASE FIR RESET AND WATCHDOE WATCHDOG N WATCHDOG INPUT WATCHDOG TRANSITION i deTECTOA 14 e WATCHIOG OUTPUT TIMER power FAIL 9 It m POWER FAIL OUTPUT INPUT o> 4 | GROUND Figure 3. MAX691/693/695 Block Diagram MAKI S$6/6/6/Z26/16/O69XVNMAX690/91/92/93/94/95 Microprocessor Supervisory Circuits Vee ee +5Y a K TO CMOS 14 RAM AND i ' t REALTIME UT u uf _ P CHANNEL Oar or MOSFET 1 BASE DRIVE = I | | I | BATT OW er (MAXGS1, MAXG3, MAXB9S ONLY) woo , BATTERY INPUT - INTERNAL my + oo LT Moe SHUTDOWN > SELECT SIGNAL WHEN Vaart > Ver + 0.7V Figure 4. Battery-Switchover Biock Diagram Reset Gutput RESET is an active low output which goes low whenever Voc falls below 4.5V (MAX690/691/694/695) or 4.25V (MAX692/693). It will remain iow until Vcc rises above 4.75V (MAX690/691/694/695) or 4.5V (MAX692/699) for 50 milliseconds*. See Figures 5 and 6. The guaranteed minimum and maximum thresholds of the MAX690/691/694/695 are 4.5V and 4.75V, while the guaranteed thresholds of the MAX692/693 are 4.25 and 4.5V. The MAX690/691/694/695 is compatible with 5V supplies with a +10%, 5% tolerance while the MAX692/693 is compatible with 5V+10% supplies. The reset threshold comparator has approximately 5OmV of hysteresis, with a nominal threshold of 4.65V in the MAX690/691/694/695, and 4.4 in the MAX692/693. The response time of the reset voltage comparator is about 100u8. Vcc should be bypassed to ensure that glitches do not activate the RESET output. RESET also goes low if the Watchdog Timer is enabled and WDI remains either high or low longer than the watchdog timeout period, RESET has an internal 3uA pullup, and can either connect to an open collector Reset bus or directly drive a CMOS gate without an external pullup resistor. *200ms for MAX69+ and MAX695 CE Gating and RAM Write Protection The MAX691, MAX693 and MAX695 use two pins to control the Chip Enable or Write inputs of CMOS RAMs. When Voc is + 5V, CE OUT is a buffered replica of CE IN, with a 50nS propagation delay. If Voc input falls below 4,65V (4.5V min, 4.75 max) an internal gate forces CE_OUT high, independent of CE IN. The MAX693 GCE OUT goes high whenever Vcc is below 4.4V (4.254 min, 4.5 max). The CE output of both devices is also forced high when Vcc is less than Veatr. (See Figure 5.) CE OUT typically drives the CE, CS, or Write input of battery backed up CMOS RAM. This ensures the integrity of the data in memory by preventing write Operations when Voc is at an invalid level. Similar protection of EEPROMS can be achieved by using the CE OUT to drive the Store or Write inputs of an EEPROM, EAROM, or NOVRAM. if the 50ns typical Propagation delay of CE OUT is tog long, connect CE IN to GND and use the resulting CE OUT to contrel a high speed external logic gate. A second alternative is to AND the LOW LINE output with the CE or WR signal. An external logic gate and the RESET output of the MAX690/692/694 can also be used for CMOS RAM write protection. VAXMicroprocessor Supervisory Circuits Yee WETAL 4 RESET Link TRIMMED RESISTORS RESET WATCHOQE FROM WATCHDOG TIMER 10 kHz CLOCK FROM TIMEBASE SECTION Figure 5. Aeset Block Diagram | I | Vee 47 4.6V 47y 4.6 | I | I ( | | ( I \ ' P| 3 | Oms* ! ' 5oms* , RESET ! QUTPUT and t | { \ ( I ( ( I | LOW LINE OUTPUT | iS Vaut ~ Ypatt *200ms lor MAX694 and MAX695 Figure 6. Reset Timing MAXAII 9 S6/6/E6/26/1L6/O69XVNMAX690/91/92/93/94/95 Microprocessor Supervisory Circuits L3V Comparator and Power Fail Warning The Power Fail Input (PFi) is compared to an internal 1.3V reference. The Power Fail Output (PFO) goes low when the voltage at PFI is less than 1.3V. Typically PFI ts driven by an external voltage divider which senses either the unregulated DC input to the system's 5V regulator or the regulated 5VY output. The voltage divider ratio can be chosen such that the voltage at PFI falls below 1.3V several milliseconds before the +5V supply falls below 4.75V. PFO is normally used to interrupt the microprocessor so that data can_be stored in RAM before Veco falls below 4.75V and the RESET output goes low (4.5V for MAX692/93). The Power Fail Detector can also monitor the backup battery to warn of a low battery condition. To conserve battery power,_the Power Fail Detector comparator is turned off and PFO is forced low when Vec is lower than the Vaart input voltage. Watchdog Timer and Oscillator The watchdog circuit monitors the activity of the microprocessor. If the microprocessor does not toggle the Watchdog Input (WDD within the selected timeout period, a 50 millisecond* RESET pulse is generated. Since many systems cannot service the watchdog timer immediately after a reset, the MAX691/693/695 has a langer timeout period after a reset is issued. The normal timeout period becomes effective following the first transition of WD! after RESET has gone high. The watchdog timer is restarted at the end of Reset, whether the Reset was caused by lack of activity on WDI or by Voc falling below the reset threshold. lf WDE remains either high or low, reset pulses will be issued every 1.6 secands. The watchdog monitor can be deactivated by floating the Watchdog Input (WDI). The Watchdog Output (WDO, MAX681/693/695 only) goes low if the watchdog timer times out and remains low until set high by the next transition on the watchdog input. WDO is also set high when Vcc goes below the reset threshold. The watchdog timeout period is fixed at 1.6 seconds and the reset pulse width is fixed at 50ms* on the &-pin MAX6S0, MAX692 and MAX694. The MAX691, MAX693 and MAX695 allow these times to be adjusted per Table 1. Figure 8 shows various oscillator configurations. The internal oscillator is enabled when OSC SEL is floating. In this mode, OSC IN selects between the 1.6 second and 100ms watchdag timeout periods. In either case. immediately after a reset the timeout period is 1.6 seconds. This gives the microprocessor time to re- initialize the system. If OSC IN is low, then the 100ms watchdog period becomes effective after the first transition of WDL. The software should be written such that the I/O port driving WD1is left in its power-up reset state until the initialization routines are completed and the microprocessor is able to toggle WDI at the minimum watchdog timeout period of 7Oms. *200ms for MAX694 WATCHOOG INFUT PREScALER | 10.24 kHz FROM INTERNAL OSCILLATOR Of EXTERNALLY SET FREQUENCY FROM 06 <j O50 IN PIN AL IF WATCHDOG INPUT 1S FLOATING WATCHDOG TIMEQUT SELECT tt RESET WATCHDOG WATCHDOG eOUNTER 4 > COUNTER | TIMEOUT pigf] SELECTOR grostz | a} LOGIC END OF WATCHDOG R 15 GOES HIGH AT THE R = OV TRANSITION t DETECTOR rf 5 | TIMEOUT PERIOD rf FOR EACH TRANSITION lL 3 LOW LINE RESET (HIF Voge < 4650) FLIP FLOP 0 9 ca aie 0 A 8 SHORT |igw] WATCHOOG LINE FAULT FF v S MG ed ' _ WATCHDOG OUTPUT Figure 7. Watehdog Timer Block Diagram 10 MAXALSVIMicroprocessor Supervisory Circuits EXTERWAL CLOCK OSC SEL 4 MAXI MAX691 MAX693 0 TO 250kHz MAX695 OSC IN INTERNAL OSCILLATOR 1.6 SECOND WATCHOOG NC. O80 SEL MAAK MAX691 MAX693 MAX695 W.. OSC IN EXTERNAL OSCILLATOR OSC SEL 4, MAXIM MAX69I MAX693 MAX695 OSG iN Ay (INTERNAL OSCILLATOR 100ms WATCHDOG N.C. O8C SEL MAKI MAX6OT MAX6S3 MAX695 Co OS IW &6/06/6/26/16/O069XVN Figure &. Oscillator Circuits Table 1. MAX691, MAX693 and MAX695 Reset Pulse Width and Watchdog Timeout Selections Watch i OSC SEL OSC IN atchdog Timeout Period 1 Reset Timeout Period 7 Normal After Reset MAX691/93 MAX695 Low External Clock Input 1024 clks 4096 clks 512 clks 2048 clks Low External Capacitor 400ms ,. c 1.6 sec ,, Cc 200MS 5 B00ms .. Cc 47pF 47pF 47pF 47pF Floating Low 100ms 1.6 sec 50ms 200ms Floating Fieating 1.6 sec 1.6 sec 50ms 200ms | Note 1: The MAX690/682/694 watchdog timeout period is fixed at 1 6 seconds nominal, the MAX690/692 reset pulse width is fixed at S0ms nominal and the MAX594 Is 200ms nominal Note 2: When the MAX691 OSC SEL pin is low. OSC IN can be driven by an exlernal clock signal or an external capacitor can be connected between OSC IN and GND The nomiral internal oscillator frequency is 6.55kHz. The nominal oscillator Ire- quency with capacitor is: 120,000 Faso(H7) = C(pF) Note 3: Sec Electrical Characteristics Table lor minimum and maximum timing values, SMA XL 1MAX690/91/92/93/94/95 Microprocessor Supervisory Circuits Application Hints Other Uses of the Power Fail Detector In Figure 9 the Power Fail Detector is used to initiate a system reset when Vcc falls to 4.85V. Since the threshold of the Power Fail Detector is not as accurate as the onboard Reset voltage detector, a trimpot must be used to adjust the voltage detection threshold. Both the PFO and RESET outputs have high sink current capability and only 10uzA of source current drive. This allows the two outputs to be connected directly to each other in a wired or fashion. The overvoltage detector circuit in Figure 10 resets the microprocessor whenever the nominal 5V Voc is above 5.6V. The battery monitor circuit (Figure 11} shows the status of the memory backup battery. !f desired, the CE OUT can be used to apply a test load to the battery. Since CE OUT is forced high during the battery backup mode, the test load will not be applied to the battery while it is in use, even if the microprocessor is not powered. Adding Hysteresis to the Power Fail Comparator Since the power fail comparator circuit is non-inverting, hysteresis can_be added by connecting a resistor betwean the PFO output and the PFI input as shown in Figure 12. When PFO is low, resistor R3 sinks current from the summing junction at the PFI pin. When PFO is high, the series combination of A3 and R4 source current into the PFl summing junction. Alternate Watchdog input Drive Circuits The Watchdog feature can be enabled and disabled under program control by driving WDI with a 3-state buffer (Figure 13). The drawback to this circuit is that a software fault may erroneously 3-state the buffer, thereby preventing the MAX690 from detecting that the microprocessor is no longer working. In most cases a better method is to extend the watchdog period rather than disabling the wateneee See Figure 14, When the contral input is high, the OSC SEL pin is low and the watchdog timeout is set by the external capacitor. A 0,01uF capacitor sets a watchdog timeout delay of 100 seconds. When the control input is low, the OSC SEL pin is driven high, selecting the internal oscillator, The 100ms or the 1.6 sec period is chosen, depending on which diode in Figure 14 is used. +5 +5V Voc < TO pP 4ka = v anaxian RESET RESET me MAX680 Td pP mn S pl MAXEST =e B5.7KO Maxi AESET RESET > MAX692 MAX6G0 IMPUT MAX693 MAXGOT | MA X604 wa PFI MAX692 10ko MAX693 PFO Hie W-CHANNEL GND MAX694 | MAX695 loka _ + Gnd + + Figure 9. Externally Achustable Voc Resel Threshotd Figure 70. Reset on Gvervollage or Uindervoltage 12 MAXIMicroprocessor Supervisory Circuits 7 - HV +5V +5Y > 7806 1 ec WAXD Sea MAX690 TL > 10ka MAX691 ge ok MAX692 mK FRO MAxX693 MAX694 Ver LOW BATTERY MAX695 T Vaart PFO -> SIGHAL TO aa | = wma MAK Vl pp |/0 PIN Pr aH =| + MAX690 "a I | pel = MAX697 Fe BB L =;3 MAX692 Taka = 4 & 10M MAX693 J MAX6G4 1 JP = MAKEOS _ Low = Lana GE OUT BE wy ee ae FROM Uy = D254 Wee ia fi. * - wm OnE eka ft BY = 130 A LOAD HYSTERESIS = 1.23 = AL _ GW - ae} AT L 10 BATTERY w= 130 (1+ gta (RS + Aaj HYSTERESIS = SW & fa ASSUMING Ra <<: RS Figure 1. Backup Battery Monitor with Optional Test Load Figure 12. Adding Hysteresis to the Power Fal Voltage Comparator +8 I Vee 4M AXA MAX690 MAX69I WATCHDOG STROBE wan Maxess MAX694 MAX695 WATCHDOG TISABLE GND I y LOW = INTERNAL WATCHDOG TIMEOUT Vice OSC SEL I 1 I | MAXIAA Hl = EXTERNAL 2 WATCHDOG =~ M MAXESI TIMEOUT ( MAX693 | CONNECT FOR | 10mm TIMEQUT ose wn WHEN INTERHAL TI SeECTED. I CONNECT FOR { = 16 sec INTERNAL == TIMEOUT Figure 13. Disabling the Watchdog Under Program Control MAAI/I Figure t4, Selecting internal or Externa! Watchdog Timeout 8 S6/%6/6/Z26/16/O69XUNMAX690/91/92/93/94/95 Microprocessor Supervisory Circuits Table 2. Input and Output Status In Battery Backup Mode Veatt, Your Veart is connected to Your via internal MOSFET. RESET Logic low RESET Logie high. The open circuit output voltage is equal to Vout. LOW LINE Logic low BATT ON Logic high WOI WDI is internally disconnected from its internal pullup and does not source or sink current as long as its input voltage is between GND and Vaur. The inpul voltage does not affect supply current. WDO Logic high PFI The Power Fail Comparator is turned off and the Power Fail input voltage has no effect on the Power Fail utput. PFO Logic low CE IN CE IN is internally disconnected from its internal pullup and dees not source or sink current as long as its input voltage is between GND and Vout. The input voltage does not affect supply currant. CE OUT Logic high OSC IN OSC IN is ignored. OSC SEL OSC SEL is ignored. Voc Approximately 122A is drawn frorn the Vaart input when Voc is between Vgarr +100mY and Vyatr 7O0mv. The supply current is 124 maximum when Voc is less than Vaart 700m. Package information gag Gate MAX 104 Have LEAD #1 025 0291 way Jae jn.3sy HAO aa) 0.060 + 1.005 0.020 - 0.070 (6.080) a age _f Rota MAX (0.508 - 1.778] 7a MIN ae A * Le 1 one - 0012 ano i fast 0306) [1 524) MAR rl I | OM x nod? er (L457 + 0.051) 0.100 + 2010 0386 + 0025 zed = 1254) (v7 = Lesa) 8 Lead CERDIP (JA) Oy, = 125C Ojo = 58C/W 14 vos __ sAAXIMRAAB RE Microprocessor Supervisory Circuits Package Information (continued) LEAD #1 i D.2ot-0799 0344-0964 _0.394-0.419 [7.390 - 7.959} (8.738- 9.245) (10.008 - 10.643) Hoewd i (1.270) 0.014-0.019 WU ree} Q.0a2-0.4h 1 2.642) bois (0.381) r* ey | al noe aaa - + arden) MAX. OBS ath 0.088 0.056 ae ia. alt east 248 (2280-308 16 Lead Small Outline, Wide (WE) 8), = 105C/W Bic = 60 CAV qe be-nsite mak LEAD #1 ss 0008 ee oh RAD 1.095 = 0.018 (0.535 = 0.381} oes 001s | 300 Treo 8128) a re ome ame ti ht ut oN ivy node - a01s ee TES +H asm gua Mm |e 0018 + 0.003 +2025 (eas? = 0.076) 100+ OLD 0.328 ROrB z5a= 78a] (az =26S5) MAXALSVI. 16 Lead Plastic DIP (PE) Bj, = 135C/W Osc = 65C/W 15 S6/6/E6/26/16/O069XVNMAX690/91/92/93/94/95 Microprocessor _ Supervisory Circuits LEAD aA ena wat 0.0050 - = $i) pa 00 pap, gms ans gue ome oll Package Information (continued) 785 [- Tica nooo foo -- CEAD #1 LOS i (RR) RAD rims | 1.050 DOUUNUOD a w= fe | fo ROD Ey A200 - 0.527 eS ea) ane joes 0308) tt oop afi an -aon' | ct | ode wnt =m oe iets aa ate 08 gi Le ears ceed * a ae jae 3 16 Lead CERDIP (JE) Lead Plastic DIP (PA) Oya = 100C AV Byq = 160C/AW Oye = 50C/W Bye = FSC/W _Ordering Information (continued) _____ Chip Topography [ani rep. Range pacrAGKAGE MAX692C/D OC to +70C Dice | Veo Your Years ee; MAX692CPA OC to +74C 8 Lead Plastic DIP 3 Ie 1 16 15 MAXG92EPA -40C to +85C 8 Lead Piastic DIP 7 MAX692EJA _-d0C to 486C BB Lead CERDIP _| MAXB92MJA, 56C lo +125C 8 Lead CERDIP MAX693C/D OC to 474C Dice MAX693CPE OC to +70C 16 Lead Plastic DIP M4 oe | MAX69SCWE OC ta +7OC 16 Lead Wide SO Bs wy MAXBOSEPE 40C to 485C _16 Lead Plastic DIP | : n MAX6O3EJE 40C to 485C 16 Leac CERDIP o.iz27 ji | GE OUT | MAX69SEWE -40C 10 485C TS Lead Wide SO (3.086 my } MAX693MJE "55C ta +125C 18 Lead CERDIP eno : | MAX694C/0 OC to +70" Dice MAXGS4CPA PC to F7OS 8 Lead Plaslic DIP a 5 MAXGQ4EPA -ADC to +85C 8 Lead Plastic DIP 7 | MAX694EJA -AD"C to +88C 8 Lead CERDIP = MAX694MIA 55C to+125C 8 Leact CERDIP A | MAX6S5C/D OC to + 70C Dice MAX695CPE WCtw+70C 6 Lead Plastic DIP | MAXGOSCWE OS 10 70C 16 Lead Wide SO 1 MAX695EPE -40C to 485C 16 Load Plastic BIP (6 7 [a [8 iil PMAXGSBEJE 40C to +85C 16 Lead CERDIP LOW LINE oer PA Pro wo! MAXBSSEWE _-40C to 485C 1G Lead Wide SO_ 0.086" | MAX695MJE 55C to +125C 16 Lead CERDIP (2.184 mm) Maxim cannot assure responsibly for use of aay ercuilly olner thar circuriry ontresty emoodied inva Maan produc! No crcud Patent tosanes are inpited, Vaxie reserves the agntto cnange ihe cieunry anc specications wihout qulee al any ime. 16 @ 1995 Maxim Integrated Products Printed USA Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 AAAMLAA 15 a registered tradernark of Mav Inlegrated Products