This is information on a product in full production.
March 2012 Doc ID 14557 Rev 5 1/27
1
M41T00CAP
Serial access real-time clock (RTC)
with integral backup battery and crystal
Datasheet − production data
Features
■Real-time clock (RTC) with backup battery
integrated into package
■Uses M41T00S enhanced RTC with precision
switchover reference
■400 kHz I2C serial interface
■Automatic switchover and deselect circuitry
with fixed reference voltage
–V
CC = 2.7 to 5.5 V operating voltage range
– 2.6 V (typ) power-fail deselect (switchover)
threshold
■Counters for seconds, minutes, hours, day,
date, month, year and century
■Software clock calibration
■Low operating current of 300 µA
■Oscillator stop detection
■Battery backup
■Operating temperature of 0 to 70 °C
■Self-contained battery and crystal in
CAPHAT™ DIP package
■RoHS compliant
– Lead-free second level interconnect
24
1
PCDIP24 (PC)
Battery/crystal CAPHATTM
www.st.com
Contents M41T00CAP
2/27 Doc ID 14557 Rev 5
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.8 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.9 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6 Initial power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
List of tables M41T00CAP
4/27 Doc ID 14557 Rev 5
List of tables
Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. TIMEKEEPER® register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Preferred default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package mechanical data . . . . . . . . . 23
Table 12. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
M41T00CAP List of figures
Doc ID 14557 Rev 5 5/27
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 23
Figure 16. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Description M41T00CAP
6/27 Doc ID 14557 Rev 5
1 Description
The M41T00CAP is a low-power serial real-time clock (RTC) with integral battery and
crystal in ST’s 24-pin CAPHAT™ package. It includes a crystal controlled, 32.768 kHz
oscillator and has a built-in power sense circuit which detects power failures and
automatically switches to the backup battery when a power failure occurs.
Eight registers comprise the clock/calendar function and are configured in binary-coded
decimal (BCD) format. Addresses and data are transferred serially via an industry standard,
two line, 400 kHz, bidirectional I2C interface. The built-in address register is incremented
automatically after each WRITE or READ data byte. The internal lithium coin cell contains
ample energy to sustain timekeeping operation for 10 years in the absence of system power.
The eight clock address locations contain the century, year, month, date, day, hour, minute,
and second in 24-hour BCD format. Corrections for the number of days in a month, including
leap year, are made automatically (leap year valid up to year 2100).
Figure 1. Logic diagram
SCL
VCC
M41T00CAP
VSS
SDA
FT/OUT
AI09165
M41T00CAP Pin settings
Doc ID 14557 Rev 5 7/27
2 Pin settings
2.1 Pin connection
Figure 2. DIP connections
1. DU is “don’t use”. Do not connect. Must be allowed to float. Do not connect to VCC or VSS.
2.2 Pin description
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
FT/OUT
NC
NC
NC
NC
NC
SCLNC
NC
DUVSS
SDA
NC
VCC
AI01028
M41T00CAP
8
1
2
3
4
5
6
7
9
10
11
12
16
15
24
23
22
21
20
19
18
17
14
13 (1)
Table 1. Pin description
Symbol Name and function
FT/OUT Frequency test / output driver (open drain)
SDA Serial data input/output
SCL Serial clock input
VCC Supply voltage
VSS Ground
DU(1)
1. DU is “don’t use”. Do not connect. Must be allowed to float. Do not connect to VCC or VSS.
Do not use. Do not connect. Reserved for factory use.
NC No connection
Pin settings M41T00CAP
8/27 Doc ID 14557 Rev 5
Figure 3. Block diagram
1. Open drain output
REAL TIME CLOCK
CALENDAR
RTC &
CALIBRATION
FREQUENCY TEST
OSCILLATOR FAIL
CIRCUIT
LOGIC OUTPUT
FT/OUT(1)
INTERNAL
POWER
FT
OUT
SDA
SCL
VCC
COMPARE
I2C
INTERFACE
32KHz
OSCILLATOR
VBAT
CRYSTAL
VSO
VPFD
AI09168
WRITE
PROTECT
M41T00CAP Operation
Doc ID 14557 Rev 5 9/27
3 Operation
The M41T00CAP clock operates as a slave device on the I2C serial bus. Access is obtained
by implementing a start condition followed by the correct slave address (D0h). The 8 bytes
contained in the device can then be accessed sequentially in the following order:
1. Seconds register
2. Minutes register
3. Century/hours register
4. Day register
5. Date register
6. Month register
7. Year register
8. Calibration register
The M41T00CAP clock continually monitors VCC for an out-of-tolerance condition. Should
VCC fall below VPFD, the device terminates an access in progress and resets the device
address counter. Inputs to the device will not be recognized at this time to prevent erroneous
data from being written to the device from a an out-of-tolerance system. Once VCC falls
below the switchover voltage (VSO), the device automatically switches over to the battery
and powers down into an ultra-low current mode of operation to prolong battery life. If VBAT
is less than VPFD, the device power is switched from VCC to VBAT when VCC drops below
VBAT
. If VBAT is greater than VPFD, the device power is switched from VCC to VBAT when VCC
drops below VPFD. Upon power-up, the device switches from battery to VCC at VSO. When
VCC rises above VPFD, the inputs will be recognized.
For more information on battery storage life refer to application note AN1012.
3.1 Wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a
bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must
be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●Data transfer may be initiated only when the bus is not busy.
●During data transfer, the data line must remain stable whenever the clock line is high.
●Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
3.2 Bus not busy
Both data and clock lines remain high.
Operation M41T00CAP
10/27 Doc ID 14557 Rev 5
3.3 Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
3.4 Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
3.5 Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
3.6 Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte that has been clocked out of the master
transmitter. The device that acknowledges has to pull down the SDA line during the
acknowledge clock pulse in such a way that the SDA line is a stable low during the high
period of the acknowledge related clock pulse. Of course, setup and hold times must be
taken into account. A master receiver must signal an end of data to the slave transmitter by
not generating an acknowledge on the last byte that has been clocked out of the slave. In
this case the transmitter must leave the data line high to enable the master to generate the
STOP condition.
M41T00CAP Operation
Doc ID 14557 Rev 5 11/27
Figure 4. Serial bus data transfer sequence
Figure 5. Acknowledgement sequence
3.7 READ mode
In this mode the master reads the M41T00CAP slave after setting the slave address (see
Figure 7). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the
word address 'An' is written to the on-chip address pointer. Next the START condition and
slave address are repeated followed by the READ mode control bit (R/W = 1). At this point
the master transmitter becomes the master receiver. The data byte which was addressed
will be transmitted and the master receiver will send an acknowledge bit to the slave
transmitter. The address pointer is only incremented on reception of an acknowledge clock.
The M41T00CAP slave transmitter will now place the data byte at address An+1 on the bus,
the master receiver reads and acknowledges the new byte and the address pointer is
incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 06h). The updating will resume upon a stop condition or when the
pointer increments to any non-clock address (07h).
Note: This is true both in READ mode and WRITE mode.
AI00587
DATA
CLOCK
DATA LINE
STABLE
DATA VALID
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00601
DATA OUTPUT
BY RECEIVER
DATA OUTPUT
BY TRANSMITTER
SCL FROM
MASTER
START
CLOCK PULSE FOR
ACKNOWLEDGEMENT
12 89
MSB LSB
Operation M41T00CAP
12/27 Doc ID 14557 Rev 5
An alternate READ mode may also be implemented whereby the master reads the
M41T00S slave without first writing to the (volatile) address pointer. The first address that is
read is the last one stored in the pointer (see Figure 8).
Figure 6. Slave address location
Figure 7. READ mode sequence
Figure 8. Alternative READ mode sequence
AI00602
R/W
SLAVE ADDRESS
STA R T A
0100011
MSB
LSB
AI00899
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+ 1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
S
START
R/W
SLAVE
ADDRESS
ACK
AI00895
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK STOP
STA R T
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
SLAVE
ADDRESS
M41T00CAP Operation
Doc ID 14557 Rev 5 13/27
3.8 WRITE mode
In this mode the master transmitter transmits to the M41T00CAP slave receiver. Bus
protocol is shown in Figure 9. Following the START condition and slave address, a logic '0'
(R/W=0) is placed on the bus and indicates to the addressed device that word address “An”
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The device slave receiver will
send an acknowledge clock to the master transmitter after it has received the slave address
and again after it has received the word address and after each data byte.
Figure 9. WRITE mode sequence
3.9 Data retention mode
With valid VCC applied, the M41T00CAP can be accessed as described above with READ
or WRITE cycles. Should the supply voltage decay, the power input will be switched from
the VCC pin to the battery when VCC falls below the battery backup switchover voltage
(VSO). At this time the clock registers will be maintained by the internal battery supply. On
power-up, when VCC returns to a nominal value, write protection continues for tREC after
VCC rises above VSO .
AI00591
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
ACK STOP
START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
Clock operation M41T00CAP
14/27 Doc ID 14557 Rev 5
4 Clock operation
The 8-byte register map (see Ta b l e 2 ) is used to both set the clock and to read the date and
time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are
contained within the first three registers. Bits D6 and D7 of clock register 02h (century/hours
register) contain the century enable bit (CEB) and the century bit (CB). Setting CEB to a '1'
will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century
(depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2
of Register 03h contain the Day (day of week). Registers 04h, 05h, and 06h contain the date
(day of month), month and years. The eighth clock register is the calibration register (this is
described in the clock calibration section). Bit D7 of register 00h contains the STOP bit (ST).
Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a
significant amount of time on the shelf, the oscillator may be stopped to reduce current
drain. When reset to a '0' the oscillator restarts within one second. The seven clock registers
may be read one byte at a time, or in a sequential block. The calibration register (address
location 07h) may be accessed independently. Provision has been made to ensure that a
clock update does not occur while any of the seven clock addresses are being read. If a
clock address is being read, an update of the clock registers will be halted. This will prevent
a transition of data during the READ.
Keys:
0 = must be set to '0'
CB = century bit
CEB = century enable bit
FT = frequency test bit
OF = oscillator fail bit
OUT = output level
S = sign bit
ST = stop bit
Table 2. TIMEKEEPER® register map
Addr Function/range BCD format
D7 D6 D5 D4 D3 D2 D1 D0
00h ST 10 seconds Seconds Seconds 00-59
01h OF 10 minutes Minutes Minutes 00-59
02h CEB CB 10 hours Hours (24-hour format) Century/hours 0-1/00-23
03h00000 Day of week Day 01-7
04h 0 0 10 date Date: day of month Date 01-31
05h 0 0 0 10M Month Month 01-12
06h 10 years Year Year 00-99
07h OUT FT S Calibration Calibration
M41T00CAP Clock operation
Doc ID 14557 Rev 5 15/27
4.1 Clock registers
The M41T00CAP has 8 internal registers which contain clock and calibration data. These
registers are memory locations which contain external (user accessible) and internal copies
of the data (usually referred to as BiPORT™ TIMEKEEPER cells). The external copies are
independent of internal functions except that they are updated periodically by the
simultaneous transfer of the incremented internal copy. The system-to-user transfer of clock
data will be halted whenever the address being read is a clock address (00h to 06h). The
update will resume either due to a stop condition or when the pointer increments to any non-
clock address (07h). Clock registers store data in BCD. The calibration register stores data
in binary format. The internal divider (or clock) chain will be reset upon the completion of a
WRITE to any clock address.
4.2 Calibrating the clock
The M41T00CAP is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested not to exceed ±23 ppm (parts per million) oscillator
frequency error at 25°C, which equates to about ±1 minute per month (see Figure 10).
When the Calibration circuit is properly employed, accuracy improves to better than ±2 ppm
at 25°C. The oscillation rate of crystals changes with temperature. The M41T00CAP design
employs periodic counter correction. The calibration circuit adds or subtracts counts from
the oscillator divider circuit at the divide by 256 stage, as shown in Figure 11. The number of
times pulses which are blanked (subtracted, negative calibration) or split (added, positive
calibration) depends upon the value loaded into the five calibration bits found in the
calibration register. Adding counts speeds the clock up, subtracting counts slows the clock
down. The calibration bits occupy the five lower order bits (D4-D0) in the calibration register
07h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is
a Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration
occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step
has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual
oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in the
calibration register (see Figure 11). Assuming that the oscillator is running at exactly 32,768
Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35
seconds per month which corresponds to a total possible adjustment range of +5.5 or –2.75
minutes per month.
Two methods are available for ascertaining how much calibration a given M41T00CAP may
require. The first involves setting the clock, letting it run for a month and comparing it to a
known accurate reference and recording deviation over a fixed period of time. Calibration
values, including the number of seconds lost or gained in a given period, can be found in
application note AN934, “TIMEKEEPER® calibration.” This allows the designer to give the
end user the ability to calibrate the clock as the environment requires, even if the final
product is packaged in a non-user serviceable enclosure. The designer could provide a
simple utility that accesses the calibration byte. The second approach is better suited to a
manufacturing environment, and involves the use of the FT/OUT pin. The pin will toggle at
512 Hz, when the stop bit (ST, D7 of 00h) is '0,' and the frequency test bit (FT, D6 of 07h) is
'1.' Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift
at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration byte
Clock operation M41T00CAP
16/27 Doc ID 14557 Rev 5
for correction. Note that setting or changing the calibration byte does not affect the
frequency test output frequency. The FT/OUT pin is an open drain output which requires a
pull-up resistor to VCC for proper operation. A 500-10 kΩ resistor is recommended in order
to control the rise time. The FT bit is cleared on power-down.
Figure 10. Crystal accuracy across temperature
Figure 11. Clock calibration
4.3 Century bit
Bits D7 and D6 of clock register 02h contain the century enable bit (CEB) and the century bit
(CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at
the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not
toggle.
AI07888
–160
0 10203040506070
Frequency (ppm)
Temperature °C
80–10–20–30–40
–100
–120
–140
–40
–60
–80
20
0
–20
= –0.036 ppm/°C2 ± 0.006 ppm/°C2
K
ΔF= K x (T – TO)2
F
TO = 25°C ± 5°C
AI00594B
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
M41T00CAP Clock operation
Doc ID 14557 Rev 5 17/27
4.4 Oscillator fail detection
If the oscillator fail bit (OF) is internally set to '1,' this indicates that the oscillator has either
stopped, or was stopped for some period of time and can be used to judge the validity of the
clock and date data. In the event the OF bit is found to be set to '1' at any time other than the
initial power-up, the STOP bit (ST) should be written to a '1,' then immediately reset to '0.'
This will restart the oscillator. The following conditions can cause the OF bit to be set:
●The first time power is applied (defaults to a '1' on power-up).
●The voltage present on VCC is insufficient to support oscillation.
●The ST bit is set to '1'.
●External interference of the crystal.
The OF bit will remain set to '1' until written to logic '0.' The oscillator must have started and
run for at least 4 seconds before attempting to reset the OF bit to '0.'
4.5 Output driver pin
When the FT bit is not set, the FT/OUT pin becomes an output driver that reflects the
contents of D7 of the calibration register. In other words, when D7 (OUT bit) and D6 (FT bit)
of address location 07h are '0's, then the FT/OUT pin will be driven low.
Note: The FT/OUT pin is an open drain which requires an external pull-up resistor.
4.6 Initial power-on default
Upon initial application of power to the device, the ST and FT bits are set to a '0' state, and
the OF and OUT bits will be set to a '1.' All other register bits will initially power on in a
random state (see Ta bl e 3 ).
Table 3. Preferred default values
Condition ST OUT FT OF
Initial power-up(1)
1. State of other control bits undefined.
0101
Subsequent power-up (with battery backup)(2)
2. UC = unchanged
UC UC 0 UC
Maximum ratings M41T00CAP
18/27 Doc ID 14557 Rev 5
5 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Caution: Negative undershoots below –0.3 volts are not allowed on any pin while in the battery
backup mode.
Table 4. Absolute maximum ratings
Sym Parameter Value Unit
TSTG Storage temperature (VCC off, oscillator off) –55 to 125 °C
VCC Supply voltage –0.3 to 7 V
TSLD(1)(2)
1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. In order to protect the lithium
battery, preheat temperatures must be limited such that the battery temperature does not exceed +85 °C.
Furthermore, the devices shall not be exposed to IR reflow.
2. For DIP packaged devices, ultrasonic vibrations should not be used for post-solder cleaning to avoid
damaging the crystal.
Lead solder temperature for 10 seconds 260 °C
VIO Input or output voltages –0.3 to VCC +0.3 V
IOOutput current 20 mA
PDPower dissipation 1 W
M41T00CAP DC and AC parameters
Doc ID 14557 Rev 5 19/27
6 DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in Ta bl e 5 :
Operating and AC measurement conditions. Designers should check that the operating
conditions in their projects match the measurement conditions when using the quoted
parameters.
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 12. AC measurement I/O waveform
Table 5. Operating and AC measurement conditions
Parameter M41T00CAP
Supply voltage (VCC) 2.7 to 5.5 V
Ambient operating temperature (TA) 0 to 70 °C
Load capacitance (CL)100 pF
Input rise and fall times ≤ 5 ns
Input pulse voltages 0.2 VCC to 0.8 VCC
Input and output timing ref. voltages 0.3 VCC to 0.7 VCC
Table 6. Capacitance
Symbol Parameter(1)(2)
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2. At 25 °C, f = 1 MHz.
Min Max Unit
CIN Input capacitance - 7 pF
COUT(3)
3. Outputs deselected.
Output capacitance - 10 pF
tLP Low-pass filter input time constant (SDA and SCL) - 50 ns
AI02568
0.8VCC
0.2VCC
0.7VCC
0.3VCC
DC and AC parameters M41T00CAP
20/27 Doc ID 14557 Rev 5
Figure 13. Power down/up mode AC waveforms
Table 7. DC characteristics
Sym Parameter Test condition(1)
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 2.7 to 5.5 V (except where noted).
Min Typ Max Unit
ILI Input leakage current 0V ≤ VIN ≤ VCC -±1µA
ILO Output leakage current 0V ≤ VOUT ≤ VCC -±1µA
ICC1 Supply current Switch freq = 400 kHz - 300 µA
ICC2 Supply current (standby)
SCL = 0 Hz
All inputs
≥ VCC – 0.2 V
≤ VSS + 0.2 V
-70µA
VIL Input low voltage –0.3 - 0.3 VCC V
VIH Input high voltage 0.7 VCC -VCC + 0.3 V
VOL
Output low voltage IOL = 3.0 mA -0.4V
Output low voltage
(open drain)(2)
2. For FT/OUT pin (open drain).
IOL = 10 mA -0.4V
Pull-up supply voltage
(open drain)(2) -5.5V
Table 8. Power down/up AC characteristics
Symbol Parameter(1)(2)
1. VCC fall time should not exceed 5 mV/µs.
2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 2.7 to 5.5 V (except where noted).
Min Typ Max Unit
tPD SCL and SDA at VIH before power down 0 - - nS
trec SCL and SDA at VIH after power up 10 - - µS
AI00596
VCC
tREC
tPD
VSO
SDA
SCL DON'T CARE
M41T00CAP DC and AC parameters
Doc ID 14557 Rev 5 21/27
Figure 14. Bus timing requirements sequence
Table 9. Power down/up trip points DC characteristics
Sym Parameter (1)(2) Min Typ Max Unit
VPFD
Power-fail deselect 2.5 2.6 2.7 V
Hysteresis 25 mV
VSO
Battery backup switchover voltage
VBAT < VPFD VBAT V
VBAT > VPFD VPFD V
Hysteresis 40 mV
tDR (3) Expected data retention time 10 Years
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.7 to 5.5 V (except where noted).
3. TA = 25°C, VCC = 0 V, oscillator on.
AI00589
SDA
P
tSU:STOtSU:STA
tHD:STA
Sr
SCL
tSU:DAT
tF
tHD:DAT
tR
tHIGH
tLOW
tHD:STAtBUF
SP
DC and AC parameters M41T00CAP
22/27 Doc ID 14557 Rev 5
Table 10. AC characteristics
Sym Parameter (1)
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 2.7 to 5.5 V (except where noted).
Min Typ Max Units
fSCL SCL clock frequency 0 - 400 kHz
tLOW Clock low period 1.3 - µs
tHIGH Clock high period 600 - ns
tRSDA and SCL rise time - 300 ns
tFSDA and SCL fall time - 300 ns
tHD:STA
START condition hold time
(after this period the first clock pulse is
generated)
600 - ns
tSU:STA START condition setup time
(only relevant for a repeated start condition)
600 - ns
tSU:DAT(2)
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling
edge of SCL.
Data setup time 100 - ns
tHD:DAT Data hold time 0 - µs
tSU:STO STOP condition setup time 600 - ns
tBUF Time the bus must be free before a new
transmission can start 1.3 - µs
M41T00CAP Package mechanical data
Doc ID 14557 Rev 5 23/27
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 15. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline
Note: Drawing is not to scale.
PCDIP
A2
A1
A
L
B1 B e1
D
E
N
1
C
eA
e3
Table 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package mechanical data
Symb mm inches
Ty p M i n M a x Ty p M i n M a x
A 8.89 9.65 0.350 0.380
A1 0.38 0.76 0.015 0.030
A2 8.38 8.89 0.330 0.350
B 0.38 0.53 0.015 0.021
B1 1.14 1.78 0.045 0.070
C 0.20 0.31 0.008 0.012
D 34.29 34.80 1.350 1.370
E 17.83 18.34 0.702 0.722
e1 2.29 2.79 0.090 0.110
e3 27.94 1.1
eA 15.24 16.00 0.600 0.630
L 3.05 3.81 0.120 0.150
N24 24
Part numbering M41T00CAP
24/27 Doc ID 14557 Rev 5
8 Part numbering
Table 12. Ordering information scheme
Example: M41T 00CAP PC 1
Device type
M41T
Supply voltage and write protect voltage
00CAP = VCC = 2.7 to 5.5 V
Package
PC = PCDIP24
Temperature range
1 = 0 °C to 70 °C
Shipping method
Blank = ECOPACK® package, tubes
M41T00CAP Environmental information
Doc ID 14557 Rev 5 25/27
9 Environmental information
Figure 16. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
Revision history M41T00CAP
26/27 Doc ID 14557 Rev 5
10 Revision history
Table 13. Document revision history
Date Revision Changes
28-Jun-2006 1 First release
20-Mar-2008 2 Document status upgraded to full datasheet; updated title and cover
page, Section 1, 3, 4, Figure 1, 2, 3, 4, Ta b l e 1 , 7, 8, 9, 10.
25-Mar-2009 3 Added Section 9: Environmental information; updated text in
Section 7: Package mechanical data.
27-May-2010 4 Updated Section 5, Ta b l e 1 1 ; reformatted document.
22-Mar-2012 5 Updated title of document; Section 9: Environmental information.
M41T00CAP
Doc ID 14557 Rev 5 27/27
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