SST39LF160-55-4C-BK - Silicon Storage Technology

Data Sheet

S71145-04-000 11/03 399

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

16 Mbit (x16) Multi-Purpose Flash

SST39LF160 / SST39VF160

FEATURES:

• Organized as 1M x16

• Single Voltage Read and Write Operations

– 3.0-3.6V for SST39LF160

– 2.7-3.6V for SST39VF160

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

(typical values at 14 MHz)

– Active Current: 12 mA (typical)

– Standby Current: 4 µA (typical)

– Auto Low Power Mode: 4 µA (typical)

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Fast Read Access Time

– 55 ns for SST39LF1 60

– 70 and 90 ns for SST39VF160

• Latched Address and Data

• Fast Erase and Word-Program

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Word-Program Time: 14 µs (typical)

– Chip Rewrite Time: 15 seconds (typical) for

SST39LF/VF160

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Availab le

– 48-lead TSOP (12mm x 20mm)

– 48-ball TFBGA (8mm x 10mm)

PRODUCT DESCRIPTION

The SST39LF/VF160 devices are 1M x16 CMOS Multi-

Purpose Flash (MPF) manufactured with SST’s propri-

etary, high performance CMOS SuperFlash technology.

The split-gate cell desig n and thick-oxide tunneling injec-

tor attain better reliability and manufacturability compared

with alternate approaches. The SST39LF160 write (Pro-

gram or Erase) with a 3.0-3.6V power supply. The

SST39VF160 write (Program or Erase) with a 2.7-3.6V

power supply. These devices conf orm to JEDEC standard

pinouts f or x16 memories.

Featuring high performance Word-Program, the

SST39LF/VF160 devices provide a typical Word-Program

time of 14 µsec. These devices use Toggle Bit or Data#

Polling to indicate the completion of Program operation.

To protect against inadvertent write, they have on-chip

hardware and Software Data Protection schemes.

Designed, manufactured, and tested for a wide spectrum

of applications, these devices are offered with a guaran-

teed typical endurance of 10,000 cycles. Data retention is

rated at greater than 100 years .

The SST39LF/VF160 devices are suited for applications

that require convenient and economical updating of pro-

gram, configuration, or data memory. For all system appli-

cations, they significantly improve performance and

reliability, while l ower ing power consumption. They inher-

ently use less energy during Erase and Program than

alternativ e flash t echnologies. The total ener gy consumed

is a function of the applied voltage, current, and time of

application. Since for any given voltage range, the Super-

Flash technology uses less curr ent to p rogram and has a

shorter erase time, the total energy consumed during any

Erase or Program operation is less than alter native flash

technologies. These devices also improve flexibility while

lowering the cost for program, data, and configuration

storage applications.

The SuperFlash technology pro vides fixed Erase and Pro-

gram t imes, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as

is necessary with alternative flash technologies, whose

Erase and Program times increase with accumulated

Erase/Program cycles.

To meet high density, surface mount requirements, the

SST39LF/VF160 are offered in a 48-lead TSOP and a

48-ball TFBGA package. See Figures 1 and 2 for pin

assignments.

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asse rtin g WE# low while keepi ng CE#

low. The address bus is latched on the falling edge of WE#

or CE#, whichever oc curs l ast. T he data bus is latc hed o n

the rising edge of WE# or CE#, whichev er occurs first.

SST39LF/VF1603.0 & 2.7V 16Mb (x16) MPF memories

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

The SST39LF/VF160 also have the Auto Low Power

mode whic h puts the device in a ne ar stand by mode aft er

data has been accessed with a valid Read operation. This

reduces the IDD active read current from typically 15 mA to

typically 4 µA. The Auto Low P ow er mode reduces the typi-

cal IDD active read current to the range of 1 mA/MHz of

read cycle time. The device exits the Auto Low Power

mode with any address transition or control signal transition

used to initiate another Read cycle, with no access time

penalty. Note that the device does not enter Auto Low

P o wer mo de afte r pow er-up w ith CE # held s teadily low unt il

the f irst a ddress t ransi tion or CE# is driv en high.

Read

The Read operation of the SST39LF/VF160 is controlled by

CE# and OE#, both ha ve to be low f or the system to obtain

data from the outputs. CE# is used for device selection.

When CE# is high, the chip is deselected and only standby

power is consumed. OE# is the output control and is used

to gate data from the output pins. The data bus is in high

impedance state when either CE# or OE# is high. Refer to

the Read cycle timing diagram for further details (Figure 3).

Word-Program Operation

The SST39LF/VF160 are programmed on a word-b y-word

basis. Before programming, the sector where the word

exists must be fully erased. The Program operation is

accomplished in three steps. The first step is the three-byte

load sequence for Software Data Protection. The second

step is to load word address and word data. During the

W ord-Program operation, the addresses are latched on the

falling edge o f either CE# or WE#, whicheve r occurs last.

The data is latched on the rising edge of either CE# or

WE#, wh ichever occurs first. The third step is the inter nal

Program operation which is initiated after the rising edge of

the fourth WE# or CE#, whichever occurs first. The Pro-

gram operation, once initiated, will be completed within 20

µs. See Figures 4 and 5 for WE# and CE# controlled Pro-

gram operation timing diagrams and Figure 16 for flow-

charts. Dur ing th e Program op eratio n, the on ly valid rea ds

are Data# Polling and Toggle Bit. During the internal Pro-

gr am ope rat ion , the host is fr ee to p erform additi onal task s .

Any comman ds is s ued during the i nte rnal Program ope ra-

tion are ignored.

Sector-/B loc k- Era se Opera tio n

The Sector- (or Block-) Erase operation allows the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST39LF/VF160 offer both Sector-Erase

and Blo ck-Erase mo des. The secto r architectu re is base d

on unif orm sector size of 2 KW ord. The Block-Erase mode

is based on uniform block size of 32 KWord. The Sector-

Erase operation is initiated by executing a six-byte com-

mand sequence with Sector-Erase command (30H) and

sector address (SA) in the last bus cycle. The Block-Erase

operation is initiated by executing a six-byte command

sequence with Block-Erase command (50H) and block

address (BA) in the last bus cycle. The sector or block

address is latched on the falling edge of the sixth WE#

pulse, whil e the command (30H or 50H) is latched on th e

rising edge of the sixth WE# pulse. The internal Erase

operation begins after the sixth WE# pulse. The End-of-

Erase operation can be determined using either Data#

P olling or Toggle Bit methods. See Figures 9 and 10 for tim-

ing wavefor ms. Any comman ds issued dur ing the Sector-

or Block-Erase operation are ignored.

Chip-Erase Operation

The SST39LF/VF160 provide a Chip-Erase operation,

which allows the user to erase the entire memory array to

the “1” state. This is useful when the entir e device must be

quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command (10H)

at address 5555H in the last byte sequence. The Erase

operation begins with the rising edge of the sixth WE# or

CE#, whichever occurs first. During the Erase operation,

the only v alid read is Toggle Bit or Data# P olling. See Table

4 for the command sequence, Figure 8 for timing diagram,

and Figure 19 for the flowchart. Any commands issued dur-

ing the Chip-Erase operation are ignored.

Write Opera ti on Status De te ct ion

The SST39LF/VF160 provide two software means to

detect the completion of a Write (Program or Erase) cycle,

in order to op timize the syste m Write cycle time. The soft-

ware detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write detection

mode is enabled after the rising edge of WE#, which ini-

tiates the internal Program or Erase operation.

The act ual co mple tion of the nonvolatile wr ite is as ynchr o-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ7 or DQ6. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

Data# Polling (DQ7)

When the SST39LF/VF160 are in the internal Program

operatio n, any attempt to r ead DQ7 will pro duce the co m-

plement of the true data. Once the Program operation is

completed, DQ7 will produce true data. Note that even

though D Q7 may have valid data immediately following the

completion of an internal Write operation, the remaining

data outputs may still be invalid: valid data on the entire

data bus will appear in subsequent successive Read

cycles after an interval of 1 µs. During internal Erase opera-

tion, any a ttempt to read DQ7 will pro duce a ‘ 0’. Once the

inter nal Erase operati on is completed, DQ 7 will produce a

‘1’. The Data# Polling is valid after the rising edge of fourth

WE# (or CE#) pulse for Program operation. For Sector-,

Block- or Chip-Erase, the Data# P olling is v alid after the ris-

ing edge of sixth WE# (or CE#) pulse. See Figure 6 for

Data# P olling timing diagram and Figure 17 for a flowchart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will p roduce alter nating 1s

and 0s, i.e., toggling between 1 and 0. When the inter nal

Program or Erase op eration is compl eted, the DQ6 bit will

stop toggling. The Toggle Bit is valid after the rising edge of

fourth WE# (or CE#) pulse for Program operation. For Sec-

tor-, Block- or Chip-Erase, the Toggle Bit is valid after the

risi ng edge of six th WE# ( or CE# ) pulse. Se e Figu re 7 for

Toggle Bit timing diagram and Figure 17 for a flowchart.

Data Protection

The SST39LF/VF160 provide both hardware and software

features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pu lse of less t han 5

ns will not ini tiate a w rite cycle .

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will in hi bit t he Writ e ope ration . T hi s prevents inadvert-

ent w rites durin g pow er-u p or po wer- dow n.

Software Data Protection (SDP)

The SST39LF/VF160 provide the JEDEC approved Soft-

ware Data P rotect ion s cheme for all data altera tion opera-

tions, i.e., Program and Erase. Any Program operation

requires the inclusion of the three-byte sequence. The

three-byte load sequence is used to initiate the Program

operation, providing optimal protection from inadvertent

Write operations, e.g., during the system power-up or

po w e r-d own. Any Er as e o pe r at i on req ui re s th e in cl usi o n of

six-byte sequence. These devices are shipped with the

Software Da ta Prote c tio n pe rman en tly ena bled. Se e Table

4 for the specific software command codes. During SDP

command sequence, invalid commands will abort the

device to Read mode within TRC. The contents of DQ15-

DQ8 can be VIL or VIH, but no other value, during any SDP

command sequence.

Common Flash Memory Interface (CFI)

The SST39LF/VF160 also contain the CFI information to

descr ibe the character i stics o f the device. In order to enter

the CFI Query mode, the system must load the three-byte

sequence, similar to the Software ID Entry command. The

last byte cycle of this command loads 98H (CFI Query

comman d) to addr ess 5555H. Onc e th e device enter s th e

CFI Query mode, the system can read CFI data at the

addresses given in Tables 5 through 7. The system must

wri te the CFI Exit co mmand t o retur n to Read mo de from

the CFI Query mode.

Product Identifica tion

The Product Identification mode identifies the devices as

the SST39LF/VF160 and manufacturer as SST. This mode

may be acces sed by software operati ons. Users m ay u se

the Software Pr o duc t Id ent ifi cati on opera ti on to id en tif y th e

par t (i.e., using the device ID) when using multiple manu-

facturers in the same socket. For details, see Table 4 for

software operation, Figure 11 f or the Software ID Entry and

Read timing diagram, and Figure 18 for the Software ID

Entry comman d sequen ce flo wchart.

TABLE 1: PRODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 0000H 00BFH

Device ID

SST39LF/VF160 0001H 2782H

T1.2 399

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

Product Identification Mode Exit/

CFI Mode Exit

In order to return to the standard Read mode, the Software

Produc t Ident ificati on mode must be exited. Exit is acco m-

plished by issuing the Software ID Exit command

sequence, which returns the device to the Read mode.

This command may also be used to reset the de vice to the

Read mode after any inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. Please note that the Software ID Exit/

CFI Exit command is ignored during an internal Program or

Erase operation. See Table 4 for software command

codes, Figu re 13 for timing waveform , and Fi gure 18 for a

flowchart.

FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP

Y-Decoder

I/O Buffers and Data Latches

399 ILL B1.1

Address Buffer & Latches

X-Decoder

DQ15 - DQ0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

FUNCTIONAL BLOCK DIAGRAM

A15

A14

A13

A12

A11

A10

A19

WE#

A18

A17

A16

VSS

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VDD

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

399 ILL F01.2

Standard Pinout

Top View

Die Up

SST39LF160/SST39VF160

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBG A

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

A19-A0Address Inputs To provide memory addresses. During Sector-Erase A19-A11 address lines will select the

sector. During Block-Erase, A19-A15 address line will select the block.

DQ15-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low

OE# Output Enable To gate the data output buffers

WE# Write Enable To control the Write operations

VDD Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF160

2.7-3.6V for SST39VF160

VSS Ground

NC No Connection Unconnected pins

T2.3 399

399 ILL F02a.0

A13

WE#

A12

A17

A14

A10

A18

A15

A11

A19

A16

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

A B C D E F G H

SST39LF/VF160

TOP VIEW (balls facing down)

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1Sector or Bl ock add ress,

XXH for Chip-Erase

Standby VIH XXHigh Z X

Write Inhibit X VIL XHigh Z/ D

OUT X

XXV

IH High Z/ DOUT X

Product Identification

Softw are Mode VIL VIL VIH See Table 4

T3.4 399

1. X can be VIL or VIH, but no other value

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

Sequence 1st Bus

Write Cycle 2nd Bus

Write Cycle 3rd Bus

Write Cycle 4th Bus

Write Cycle 5th Bus

Write Cycle 6th Bus

Write Cycle

Addr1

1. Address format A14-A0 (Hex), Addresse s A19-A15 can be VIL or VIH, but no other value, for Command sequence for SST39LF/VF160

Data2

2. DQ15 - DQ8 can be VIL or VIH, but no other value, fo r Comm and sequence

Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2

Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3

3. WA = Program word address

Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX4

4. SAX for Sector-Erase; uses A19-A11 address lines

BAX, for Block-Erase; uses A19-A15 address lines

30H

Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX450H

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Softw are ID Entry5,6

5. The device does not remain in Software Product ID mode if powered down.

6. With A19-A1 = 0;SST Manufacturer’s ID = 00BFH, is read with A0 = 0,

SST39LF/VF160 Device ID = 2782H, is read with A0 = 1

5555H AAH 2AAAH 55H 5555H 90H

CFI Query Entry55555H AAH 2AAAH 55H 5555H 98H

Software ID Exit7/

CFI Exit

7. Both Software ID Exit operations are equivalent

XXH F0H

Softw are ID Exit7/

CFI Exit 5555H AAH 2AAAH 55H 5555H F0H

T4.5 399

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR S ST 39LF /VF160

Address Data Data

10H 0051H Query Unique ASCII string “QRY”

11H 0052H

12H 0059H

13H 0001H Primary OEM command set

14H 0007H

15H 0000H Address for Primary Extended Table

16H 0000H

17H 0000H Alternate OEM command set (00H = none exists)

18H 0000H

19H 0000H Address for Alternate OEM extended Table (00H = none exits)

1AH 0000H T5.0 399

1. Refer to CFI publication 100 for more details.

TABLE 6: SYSTEM INTERFACE INFORMATION FOR SST39LF/ VF16 0

Address Data Data

1BH 0027H1

1. 0030H for SST39LF160 and 0027H for SST39VF160

VDD Min (Program/Erase)

0030H1DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1CH 0036H VDD Max (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH 0000H VPP min (00H = no VPP pin)

1EH 0000H VPP max (00H = no VPP pin)

1FH 0004H Typical time out for Word-Program 2N µs (24 = 16 µs)

20H 0000H Typical time out f or mi n size buf fer program 2N µs (00H = not supported)

21H 0004H Typical time out f or ind ividu al Sec tor/Bl ock-Erase 2N ms (24 = 16 ms)

22H 0006H Typical time out f or C hip -Er ase 2N ms (26 = 64 ms)

23H 0001H Maximum time out for Word-Program 2N times typical (21 x 24 = 32 µs)

24H 0000H Maximum time out for buffer program 2N times typical

25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)

26H 0001H Maximum time out for Chip-Erase 2N t imes typical (21 x 26 = 128 ms)

T6.2 399

TABLE 7: DEVICE GEOMETRY INFORMATION FOR SST39LF/V F160

Address Data Data

27H 0015H Device size = 2N Bytes (15H = 21; 221 = 2 MByte)

28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface

29H 0000H

2AH 0000H Maximum number of bytes in multi-byte write = 2N (00H = not supported)

2BH 0000H

2CH 0002H Number of Erase Sector/Block sizes supported by device

2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

2EH 0001H y = 155 + 1 = 512 sectors (01FFH = 511)

2FH 0010H

30H 0000H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)

31H 003FH Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H 0000H y = 31 + 1 = 32 blocks (001FH = 31)

33H 0000H

34H 0001H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256) T7.3 399

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may caus e per manent d amage to the device. This is a stres s rating only and funct ional operatio n

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Pac kage Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Curr ent1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shor ted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE: SST 39LF 160

Range Ambient Temp VDD

Commercial 0°C to +70°C 3.0-3.6V

OPERATING RANGE: SST 39VF1 60

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF for SST39LF160

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for SST39VF160

See Figu res 14 and 15

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

TABLE 8: DC OPERATING CHARACTERISTICS

VDD = 3.0-3.6V FOR SS T39L F16 0 AND 2 .7-3.6V FOR S ST39V F1601

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT, at f=1/TRC Min,

VDD=VDD Max

Read220 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

Program and Erase 30 mA CE#=WE#=VIL, OE# =VIH

ISB Standby VDD Current 20 µA CE#=VIHC, VDD=VDD Max

IALP Auto Low Power Current 20 µA CE#=VILC, VDD=VDD Max,

all inputs = VSS or VDD, WE#=VIHC

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltag e 0.8 V VDD=VDD Min

VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

VIH Input High Voltage 0.7 VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH = -100 µA, VDD=VDD Min

T8.8 399

1. Typical conditions for the Activ e Current shown on the front data sheet page are average values at 25°C

(room temperature), and VDD = 3V for VF devices or VDD = 5V for SF devices. Not 100% tested.

2. Values are for 70 ns conditions. See the

Multi-Purpose Flash Power Rating

application note fo r further information.

TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T9.0 399

TABLE 10: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T10.0 399

TABLE 11: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1,2

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a

higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T11.3 399

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

AC CHARACTERISTICS

TABLE 12: READ CYCLE TIMING PARAMETERS VDD = 3.0-3.6V FOR SST39LF160 AND 2.7-3.6V FOR SS T39 VF160

Symbol Parameter

SST39LF160-55 SST39VF160-70 SST39VF160-90

UnitsMin Max Min Max Min Max

TRC Read Cycle Time 55 70 90 ns

TCE Chip Enable Access Time 55 70 90 ns

TAA Address Access Time 55 70 90 ns

TOE Output Enable Access Time 30 35 45 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 0 0 ns

TOLZ1OE# Low to Active Output 0 0 0 ns

TCHZ1CE# High to High-Z Output 15 20 30 ns

TOHZ1OE# High to High-Z Output 15 20 30 ns

TOH1Output Hold from Address Change 0 0 0 ns

T12.2 399

TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TBP Word-Program Time 20 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 100 ms

T13.0 399

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

FIGURE 3: READ CYCLE TIMING DIAGRAM

FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

399 ILL F03.2

ADDRESS A19-0

DQ15-0

WE#

OE#

CE# TCE

TRC TAA

TOE

TOLZVIH

HIGH-Z TCLZ TOH TCHZ HIGH-Z

D ATA VALIDD ATA VALID

TOHZ

399 ILL F04.3

ADDRESS A19-0

DQ15-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS

CE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

WE#

TBP

Note: X can be V

or V

, but no other value

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

FIGURE 6: DATA# POLLING T IMING D IAGRAM

399 ILL F05.3

ADDRESS A19-0

DQ15-0

TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

CE#

TBP

Note: X can be V

or V

, but no other value

399 ILL F06.2

ADDRESS A19-0

DQ7DATA DATA# DATA# DATA

WE#

OE#

CE#

TOEH

TOE

TCE

TOES

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

FIGURE 7: TOGGLE BIT TIMING DIAGRAM

FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

399 ILL F07.2

ADDRESS A19-0

DQ6

WE#

OE#

CE#

TOETOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

399 ILL F08.3

ADDRESS A19-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX10XX55XXAA XX80 XXAA

5555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 13)

X can be V

or V

, but no other value

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM

FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

399 ILL F17.3

ADDRESS A19-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX50XX55XXAA XX80 XXAA

BAX

OE#

CE#

SIX-BYTE CODE FOR BLOCK-ERASE

TBE

TWP

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 13)

BAX = Block Address

X can be V

or V

, but no other value

399 ILL F18.3

ADDRESS A19-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX30XX55XXAA XX80 XXAA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 13)

SAX = Sector Address

X can be V

or V

, but no other value

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

FIGURE 11: SOFTWARE ID ENTRY AND READ

FIGU R E 12: CFI Q UERY AND READ

399 ILL F09.4

ADDRESS A14-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2

5555 2AAA 5555 0000 0001

OE#

CE#

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

TWP

TWPH TAA

00BF

Device ID

XX55XXAA XX90

Device ID = 2782H for SST39LF/VF160

Note: X can be V

or V

, but no other value

399 ILL F20.1

ADDRESS A14-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2

5555 2AAA 5555

OE#

CE#

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

TWP

TWPH TAA

XX55XXAA XX98

Note: X can be V

or V

, but no other value

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

FIGURE 13: SOFTWARE ID EXIT/CFI EXIT

399 ILL F10.1

ADDRESS A14-0

DQ15-0

TIDA

TWP

T WHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

XXAA XX55 XXF0

Note: X can be V

or V

, but no other value

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 15: A TEST LOAD EXAMPLE

399 ILL F11.1

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

A C test inputs are driven at VIHT (0.9 VDD) f or a logic “1” and VILT (0.1 VDD) f or a lo gic “0”. Mea surement re f erence poin ts

f or inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and f all times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Test

VOT - VOUTPUT Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

399 ILL F12.1

T O TESTER

TO DUT

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

FIGURE 16: WORD-PROGRAM ALGORITHM

399 ILL F13.3

Start

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XXA0H

Address: 5555H

Load W ord

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

Note: X can be V

or V

, but no other value

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

FIGURE 17: WAIT OPTIONS

399 ILL F14.0

W ait TBP,

TSCE, TSE

or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Yes

Program/Erase

Completed

Does DQ6

match?

Read same

word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read word

Is DQ7 =

true data?

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

FIGURE 18: SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS

399 ILL F15.2

Load data: XXAAH

Address: 5555H

Software Product ID Entry

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX90H

Address: 5555H

W ait TIDA

Read Software ID

Load data: XXAAH

Address: 5555H

CFI Query Entry

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX98H

Address: 5555H

W ait TIDA

Read CFI data

Load data: XXAAH

Address: 5555H

Software ID Exit/CFI Exit

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XXF0H

Address: 5555H

Load data: XXF0H

Address: XXH

Return to normal

operation

W ait TIDA

Return to normal

operation

Note: X can be V

or V

, but no other value

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

FIGURE 19: ERASE COMMAND SEQUENCE

399 ILL F16.2

Load data: XXAAH

Address: 5555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Load data: XXAAH

Address: 5555H

W ait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX30H

Address: SAX

Load data: XXAAH

Address: 5555H

W ait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 5555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX50H

Address: BAX

Load data: XXAAH

Address: 5555H

W ait TBE

Block erased

to FFFFH

Note: X can be V

or V

, but no other value

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

PRODUCT ORDERING INFORMATION

Valid combinations for SST39LF160

SST39LF160-55-4C-EK SST39LF160-55-4C-BK

SST39LF160-55-4C-EKE

Valid combinations for SST39VF160

SST39VF160-70-4C-EK SST39VF160-70-4C-BK

SST39VF160-70-4C-EKE

SST39VF160-90-4C-EK SST39VF160-90-4C-BK

SST39VF160-90-4C-EKE

SST39VF160-70-4I-EK SST39VF160-70-4I-BK

SST39VF160-70-4I-EKE

SST39VF160-90-4I-EK SST39VF160-90-4I-BK

SST39VF160-90-4I-EKE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Environmental Attribute

E = non-Pb

Package Modifier

K = 48 leads or balls

Package Type

E = TSOP (type 1, die up, 12mm x 20mm)

B = TFBGA (8mm x 10mm )

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

55 = 55 ns

70 = 70 ns

90 = 90 ns

Device Density

160 = 16 Mbit

Voltage

L = 3.0-3.6V

V = 2.7-3.6V

Product Serie s

39 = Multi-Purpose Flash

SST 39 VF 160 - 70 - 4C - EK E

XX XX XXX -XXX -XX-XXX X

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

PACKAGING DIAGRAMS

48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM

SST PACKAGE CODE: EK

1.05

0.95

0.70

0.50

18.50

18.30

20.20

19.80

0.70

0.50

12.20

11.80

0.27

0.17

0.15

0.05

48-tsop-EK-8

Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

0˚- 5˚

DETAIL

Pin # 1 Identifier

0.50

BSC

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Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 8MM X 10MM

SST PACKAGE CODE: BK

TABLE 14: REVISION HISTORY

Number Description Date

02 •2002 Data Book May 2002

03 •Removed B3K package

•Re-introduced BK package

•Changes to Tabl e 8 on page 9

– Added footnotes for MPF power usage and Typical conditions

– Clarified the Test Conditions for Power Supply Current and Read parameters

– Corr ected I DD Program and Erase Current parameter from 25 mA to 30 mA

– Corr ected I ALP Test Condition for CE# from VIHC to VILC

Mar 2003

04 •2004 Data Book

•Updated the BK package diagram

•Added non-Pb MPNs and removed footnote (See page 22)

Nov 2003

A1 CORNER

H G F E D C B A

A B C D E F G H

BOTTOM VIEWTOP VIEW

8.00 ± 0.20

0.30 ± 0.05

(48X)

A1 CORNER

10.00 ± 0.20

0.80

4.00

0.80

5.60

48-tfb

a-BK-8x10-300mic-14

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.08 mm

4. Ball opening size is 0.25 mm (± 0.05 mm)

1mm

SIDE VIEW

SEATING PLANE

0.21 ± 0.05

1.10 ± 0.10

0.08

Silicon Stor age Technol ogy, Inc. • 1171 Sonor a C ourt • Sunnyvale , CA 940 86 • Telephone 408-73 5-91 10 • Fax 408-735-90 36

www.SuperFlash.com or www.sst.com

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