Features
•Contactless Power Supply and Communication Interface
•Up to 10 kbaud Data Rate (R/O)
•Power Management for Contactless and Battery Power Supply
•Frequency Range 100 kHz to 150 kHz
•32 x 16-bit EEPROM
•Two-wire Serial Interface
•Shift Register Supported Bi-phase and Manchester Modulator Stage
•Reset I/O Line
•Field Clock Extractor
•Field and Gap Detection Output for Wake-up and Data Reception
•Field Modulator with Energy-saving Damping Stage
Applications
•Main Areas
– Access Control
– Telemetry
– Wireless Sensors
•Examples:
– Wireless Passive Access and Active Alarm Control for Protection of Valuables
– Contactless Position Sensors for Alignments of Machines
– Contactless Status Verification and/or Data Readout from Sensors
1. Description
The U3280M is a transponder interface for use in contactless ID systems, remote con-
trol systems, tag and sensor applications. It supplies the microcontroller with power
from an RF field via an LC-resonant circuit and it enables contactless bi-directional
data communication via this RF field. It includes power management that handles
switching between the magnetic field and a battery power supply. To store permanent
data like an identifier code and configuration data, the U3280M includes a 512-bit
EEPROM with a serial interface.
Transponder
Interface for
Microcontroller
U3280M
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U3280M
Figure 1-1. Block Diagram
Damping
stage
512-bit
EEPROM
memory
Coil 1
Coil 2
VSS
Low power
microcontroller
Rectifier
VDD
Field/gap
detect
VBatt
MOD
NGAP
Bi-phase
modulator
Serial
interface
Clock
extractor
FC
Power
management
>
_1
VField
regulator
SCL
SDA
Transmit data
Field clock
Data
Energy
NRST
Sensors, keys, displays, actuators
Receive data/field detected
U3280M Transponder Interface
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U3280M
2. Pin Configuration
Figure 2-1. Pinning
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VBatt
VDD
SCL
NRST
SDA
VSS
NC
FC
Coil 2
Coil 1
NC
NC
NC
NC
NGAP
MOD
Table 2-1. Pin Description
Pin Symbol Function
1 VBatt Power supply voltage input to connect a battery
2VDD
Power supply voltage for the microcontroller and EEPROM. At this pin a buffer capacitor (0.5 to 10 µF)
must be connected to buffer the voltage during field supply and to block the VDD of the microcontroller.
3 SCL Serial clock line
4 NRST Reset line bi-directional
5 SDA Serial data line
6 VSS Circuit ground
7 NC Not connected
8 FC Field clock output of the front-end clock extractor
9 MOD Modulation input
10 NGAP Gap and field detect output
11 NC Not connected
12 NC Not connected
13 NC Not connected
14 NC Not connected
15 Coil 1 Coil input 1. Use pin to connect a resonant circuitry for communication and field supply
16 Coil 2 Coil input 2. Use pin to connect a resonant circuitry for communication and field supply
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U3280M
3. Functional Description
3.1 Transponder Interface
The U3280M is a transponder interface IC that can operate microcontrollers using wireless tech-
nology and battery independently. Wireless data communication and the power supply are
handled via an electromagnetic field and the coil antenna of the transponder interface. The
U3280M consists of a rectifier stage for the antenna, power management to handle field and
battery power supplies, a damping modulator, and a field-gap detection stage for contactless
data communication. Furthermore, a field clock extraction and an EEPROM are on-chip.
The internal rectifier stage rectifies the AC from the LC-resonant circuit at the coil inputs and
supplies the U3280M device and an additional microcontroller device with power. It is also possi-
ble to supply the device via the VBatt input with DC from a battery. The power management
handles switching between battery supply (VBatt pin) and field supply automatically. It switches to
field supply if a field is applied at the coil, and it switches back to battery if the field is removed.
The voltage from the coil or the VBatt pin is output at the VDD pin to supply the microcontroller or
any other suited device. At the VDD pin a capacitor must be connected to smooth and buffer the
supply voltage. This capacitor is also necessary to buffer the supply voltage during communica-
tion (damping and gaps in the field).
For communication, the chip contains a damping stage and gap-detect circuitry. By means of the
damping stage the coil voltage can be modulated to transmit data via the field. It can be con-
trolled with the modulator input (MOD pin) via the microcontroller. The gap-detection circuitry
detects gaps in the field and outputs the gap/field signal at the gap-detect output (Pin NGAP).
To store data like keycodes, identifiers and configuration bits, a 512-bit EEPROM is available
on-chip. It can be read and written by the microcontroller via a two-wire serial interface.
The serial interface, the EEPROM and the microcontroller are supplied with the voltage at the
VDD pin. That means the microcontroller can read and write the EEPROM if the supply voltage at
VDD is in the operating range of the IC.
The U3280M has built-in operating modes to support a wide range of applications. These modes
can be activated via the serial interface with special mode control bytes.
To support applications with battery supply only, power management can be switched off by
software to disable the automatic switching to field supply.
An on-chip Bi-phase and Manchester modulator can be activated and controlled by the serial
interface. If this modulator is used, it modulates the serial data stream at the serial inputs SDA
and SCL into a Bi-phase or Manchester-coded signal for the damping stage.
3.2 Modulation
The transponder interface can modulate the magnetic field by its damping stage to transmit data
to a base station. It modulates the coil voltage by varying the coil’s load. The modulator can be
controlled via the MOD pin. A high level (“1”) increases the current into the coil and damps the
coil voltage. A low level (“0”) decreases the current and increases the coil voltage. The modula-
tor generates a voltage stroke of about 2 Vpp at the coil. A high level at the MOD pin makes the
maximum of the field energy available at VDD. During reset mode, a high level at the MOD pin
causes optimum conditions for starting the device and charging the capacitor at VDD after the
field has been applied at the coil.
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U3280M
3.2.1 Digital Input to Control the Damping Stage (MOD)
MOD = 0: coil not damped
MOD = 1: coil damped
VCMS = VCID: modulation voltage stroke at coil inputs
Note: If the automatic power management is disabled, the internal front-end VDD is limited at VDDC. In
this case the value VDDC must be used in the above formula.
3.3 Field Clock
The field clock extractor of the interface makes the field clock available for the microcontroller. It
can be used to supply timer inputs to synchronize modulation and demodulation with the field
clock.
3.4 Gap Detect
The transponder interface can also receive data. The base station modulates the data with short
gaps in the field. The gap-detection circuit detects these gaps in the magnetic field and outputs
the NGAP/field signal at the NGAP pin. A high level indicates that a field is applied at the coil
and a low level indicates a gap or that the field is off. The microcontroller must demodulate the
incoming data stream at one of its inputs.
Vcoil-peak VDD 2V
CMS VCU
=+×=
Vcoil-peak VDD 2×VCD
==
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U3280M
4. U3280M Signals and Timing
Figure 4-1. Modulation
Figure 4-2. GAP and Modulation Timing
4.1 Digital Output of the Gap-detection Stage (NGAP)
NGAP = 0: gap detected/no field Vcoil-peak = VFDoff
NGAP = 1: field detected Vcoil-peak = VFDon
Note: No amplifier is used in the gap-detection stage. A digital Schmitt trigger evaluates the rectified and
smoothed coil voltage.
4.2 Wake-up Signal
If a field is applied at the coil of the transponder interface, the microcontroller can be woken up
with the wake-up signal at the NGAP pin. For that purpose, the NGAP pin must be connected to
an interrupt input of the microcontroller. A high level at the NGAP output indicates an applied
field and can be used as a wake-up signal for the microcontroller via an interrupt. The wake-up
signal is generated if power management switches to field supply. The field-detection stage of
the power management has lowpass characteristics to avoid generating wake-up signals and
unnecessary switching between battery and field supply in case of interferences at the coil
inputs.
MOD
Coil inputs
V
CMS
V
CU
V
CD
t
FBS
t
BFS Coil supply if automatically power management is enabled
Battery
supply
Battery supply
Coil inputs
NGAP
Field clock FC
Power
management
1. edge used as wakeup signal
t
FGAP0
V
FDON
t
FGAP1
V
FDOFF
Gap detection and battery to field switching
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U3280M
4.3 Power Supply
The U3280M has a power management that handles two power supply sources. Normally, the
IC is supplied by a battery at the VBatt pin. If a magnetic field is applied at the LC-resonant circuit
of the device, the field detection circuit switches automatically from VBatt to field supply.
The VDD pin is used to connect a capacitor to smooth the voltage from the rectifier and to buffer
the power while the field is modulated by gaps and damping. The EEPROM and the connected
controller always operate with the voltage at the VDD pin.
Note: During field supply the maximum energy from the field is used if a high level is applied at the MOD
input.
4.3.1 Automatic Power Management
There are different conditions that cause a switch from the battery to field and back from field to
the battery.
The power management switches from battery to field if the rectified voltage (Vcoil) from the coil
inputs becomes higher than the field-on-detection voltage (VFDon), even if no battery voltage is
available (0 < VBatt < 1.8V). It switches back to battery if the coil voltage becomes lower than the
field-off-detection voltage (VFDoff).
The field detection stage of the power management has low pass characteristics to suppress
noise. An applied field needs a time delay tBFS (battery-to-field switch delay) to change the
power supply. If the field is removed from the coil, the power management will generate a reset
that can be connected to the microcontroller.
Figure 4-3. Switch Conditions for Power Management
Note: The rectified supply voltage from the coil is limited to VDDC (2.9V). During field supply, the battery
is switched off and VDD changes to VDDC.
4.3.2 Controlling Power Management via the Serial Interface
The automatic mode of the power management can be switched off and on by a command from
the microcontroller. If the automatic mode is switched off, the IC is always supplied by the bat-
tery up to the next power-on reset or to a switch-on command. The power management’s on and
off command must be transferred via the serial interface.
If the power management is switched off and the device is supplied from the battery, it can com-
municate via the field without loading the field. This mode can be used to realize applications
with battery supply if the field is too weak to supply the IC with power.
Battery
supply Field
supply
V
Coil
> V
FDon
for t > tBFS
V
Coil
< V
FDon
for t > tBFS
(V
Batt
)
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U3280M
4.3.3 Buffer Capacitor CB
The buffer capacitor connected at VDD is used to buffer the supply voltage for the microcontroller
and the EEPROM during field supply. It smoothes the rectified AC from the coil and buffers the
supply voltage during modulation and gaps in the field. The size of this capacitor depends on the
application. It must be of a dimension so that during modulation and gaps the ripple on the sup-
ply voltage is in the range of 100 mV to 300 mV. During gaps and damping the capacitor is used
to supply the device, which means the size of the capacitor depends on the length of the gaps
and damping cycles.
4.4 Serial Interface
The transponder interface has a serial interface to the microcontroller for read and write access
to the EEPROM. In a special mode, the serial interface can also be used to control the
Bi-phase/Manchester modulator or the power management of the U3280M.
The serial interface of the U3280M device must be controlled by a master device (normally the
microcontroller) which generates the serial clock and controls the access via the SCL and SDA
lines. SCL is used to clock the data in and out of the device. SDA is a bi-directional line and used
to transfer data into and out of the device. The following protocol is used for the data transfers.
4.4.1 Serial Protocol
• Data states on the SDA line change only when SCL is low.
• Changes in the SDA line while SCL is high will be interpreted as a START or STOP condition.
• A STOP condition is defined as a high-to-low transition on the SDA line while the SCL line is
high.
• Each data transfer must be initialized with a START condition and terminated with a STOP
condition. The START condition awakens the device from standby mode, and the STOP
condition returns the device to standby mode.
• A receiving device generates an acknowledge (A) after the reception of each byte. For that
purpose the master device must generate an extra clock pulse. If the reception was
successful, the receiving master or slave device pulls down the SDA line during that clock
cycle. If an acknowledge has not been detected (N) by the interface in transmit mode, it will
terminate further data transmissions and switch to receive mode. A master device must finish
its read operation by a not acknowledge and then issue a STOP condition to switch the
device to a known state.
Table 4-1. Example for a 350 µA Supply Current, 200 mV Ripple at VDD
No Field Supply During Necessary CB
250 µs 470 nF
500 µs 1000 nF
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U3280M
Figure 4-4. Serial Protocol
Control Byte Format
The control byte follows the START condition and consists of the 5-bit row address, 2 mode con-
trol bits and the read/not-write bit.
• After the STOP condition and before the START condition the device is in standby mode and
the SDA line is switched to an input with the pull-up resistor.
• The START condition follows a control byte that determines the following operation. Bit 0 of
the control byte is used to control the following transfer direction. A “0” defines a write access
and a “1” defines a read access.
EEPROM address Mode control
bits
Read/
NWrite
START A4 A3 A2 A1 A0 C1 C0 R/NW Ackn
Data Transfer Sequence
START Control byte Ackn Data byte Ackn Data byte Ackn STOP
START
condition Data
valid Data
change Data/
acknowledge
valid
STOP
condition
SCL
SDA
Stand-
by Stand-
by
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U3280M
5. EEPROM
The EEPROM has a size of 512 bits and is organized as a 32 × 16-bit matrix. To read and write
data to and from the EEPROM, the serial interface must be used. The interface supports one
and two-byte write access and one to n-byte read access to the EEPROM.
5.1 EEPROM Operating Modes
The operating modes of the EEPROM are defined by the control byte. The control byte contains
the row address, the mode control bits and the read/not-write bit that is used to control the direc-
tion of the following transfer. A “0” defines the write access and a “1” defines a read access. The
five address bits select one of the 32 rows of EEPROM memory to be accessed. For complete
access the complete 16-bit word of the selected row is loaded into a buffer. The buffer must be
read or overwritten via the serial interface. The two mode control bits C1 and C2 define in which
order the access to the buffer is performed: high byte – low byte or low byte – high byte. The
EEPROM also supports auto-increment and auto-decrement read operations. After sending the
START address with the corresponding mode, consecutive memory cells can be read row by
row without transmission of the row addresses.
5.2 Write Operations
The EEPROM allows for 8-bit and 16-bit write operations. A write access starts with the START
condition followed by writing a write control byte and one or two data bytes from the master. It is
completed with the STOP condition from the master after the acknowledge cycle.
When the EEPROM receives the control byte, it loads the addressed memory cell into a 16-bit
read/write buffer. The following data bytes overwrite the buffer. The internal EEPROM program-
ming cycle is started by a STOP condition after the first or second data byte. During the
programming cycle, the addressed EEPROM cells are cleared and the contents of the buffer is
written back to the EEPROM cells. The complete erase-write cycle takes about 10 ms.
5.2.1 Acknowledge Polling
If the EEPROM is busy with an internal write cycle, all inputs are disabled and the EEPROM will
not acknowledge until the write cycle is finished. This can be used to determine when the write
cycle is complete. The master must perform acknowledge polling by sending a START condition
followed by the control byte. If the device is still busy with the write cycle, it will not return an
acknowledge and the master has to generate a STOP condition or perform further acknowledge
polling sequences.
If the cycle is complete, the device returns an acknowledge and the master can proceed with the
next read or write cycle.
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U3280M
5.2.1.1 Write One Data Byte
5.2.1.2 Write Two Data Bytes
5.2.1.3 Write Control Byte Only
5.2.1.4 Write Control Bytes
5.2.2 Read Operations
The EEPROM allows byte-, word- and current address read operations. The read operations are
initiated in the same way as write operations. Each read access is initiated by sending the
START condition followed by the control byte which contains the address and the read mode.
When the device has received a read command, it returns an acknowledge, loads the addressed
word into the read/write buffer and sends the selected data byte to the master. The master has
to acknowledge the received byte to proceed with the read operation. If two bytes are read out
from the buffer, the device automatically increments or decrements the word address and loads
the buffer with the next word. The read mode bit determines if the low or high byte is read first
from the buffer and if the word address is incremented or decremented for the next read access.
When the memory address limit has been reached, the data word address will “roll over” and the
sequential read will continue. The master can terminate the read operation after every byte by
not responding with an acknowledge (N) and by issuing a STOP condition.
START Control byte A Data byte 1 A STOP
START Control byte A Data byte 1 A Data byte 2 A STOP
START Control byte A STOP
A → acknowledge
Write Low Byte First
MSB LSB
A4 A3 A2 A1 A0 C1 C0 R/NW
Row address 0 1 0
Byte Order
LB(R) HB(R)
Write High Byte First
MSB LSB
A4 A3 A2 A1 A0 C1 C0 R/NW
Row address 1 0 0
Byte Order
HB(R) LB(R)
HB: high byte; LB: low byte; R: row address
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U3280M
5.2.2.1 Read One Data Byte
5.2.2.2 Read Two Data Bytes
5.2.2.3 Read n Data Bytes
5.2.2.4 Read Control Bytes
5.2.3 Initialization after a Reset Condition
The EEPROM with the serial interface has reset circuitry on-chip. In systems with microcontrol-
lers that have their own reset circuitry for power-on reset, watchdog reset or brown-out reset, it
may be necessary to bring the U3280M into a known state independently of the internal reset.
This is performed by reading one byte without acknowledging and then generating a STOP
condition.
START Control byte A Data byte 1 N STOP
START Control byte A Data byte 1 A Data byte 2 N STOP
START Control byte A Data byte 1 A Data byte 2 A - - - - - - Data byte n N STOP
A → acknowledge, N → no acknowledge
Read Low Byte First, Address Increment
MSB LSB
A4 A3 A2 A1 A0 C1 C0 R/NW
Row address 0 1 1
Byte Order
LB(R) HB(R) LB(R+1) HB(R+1) - - - - LB(R+n) HB(R+n)
Read High Byte First, Address Decrement
MSB LSB
A4 A3 A2 A1 A0 C1 C0 R/NW
Row address 1 0 1
Byte Order
HB(R) LB(R) HB(R-1) LB(R-1) - - - - HB(R-n) LB(R-n)
HB: high byte; LB: low byte; R: row address
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U3280M
5.2.4 Special Modes
Data Transfer Sequence for Bi-phase and Manchester Modulation
By using special control bytes, the serial interface can control the modulator stage or the power
management. The EEPROM access and the serial interface are disabled in these modes until
the next STOP condition. If no START or STOP condition is generated, the SCL and SDA lines
can be used for the modulator stage. SCL is used for the modulator clock and SDA is used for
the data. In this mode, the same conditions for clock and data changing, as in normal mode, are
valid. The SCL and SDA lines can be used for continuous bit transfers, an acknowledge cycle
after 8 bits must not be generated.
Note: After a reset of the microcontroller it is not assured that the transponder interface has been reset
as well. It could still be in a receive or transmit cycle. To switch the device’s serial interface to a
known state, the microcontroller should read one byte from the device without acknowledge and
then generate a STOP condition.
5.2.5 Power-on Reset, NRST
The U3280M transponder front end starts working with the applied field. For the digital circuits
like the EEPROM serial interface and registers there is reset circuitry. A reset is generated by a
power-on condition at VDD, by switching back from field to battery supply and if a low signal is
applied at the NRST-pin.
The NRST-pin is a bi-directional pin and can also be used as a reset output to generate a reset
for the microcontroller if the circuit switches over from field to battery supply. This sets the micro-
controller in a well-defined state after the uncertain power supply condition during switching.
5.2.6 Antenna
For the transponder interface a coil must be used as an antenna. Air and ferrite cored coils can
be used. The achievable working distance (passive mode, not battery assisted) depends on the
minimum coupling factor of an application, the power consumption, and the size of the antennas
of the IC and the base station. With a power consumption of 150 µA, a minimum magnetic cou-
pling factor below 0.5% is within reach. For applications with a higher power consumption, the
coupling factor must be increased.
The Q-factor of the antenna coil should be in a range between 30 and 80 for read only applica-
tions and below 40 for bi-directional read-write applications.
Table 5-1. Control Byte Description
Control Byte Description
1100x111b Bi-phase modulation
1101x111b Manchester modulation
11xx0111b Switch power management off → disables switching from battery to field supply
11xx1111b Switch power management on → enables automatic switching between battery
and field supply
xxxxx110b Reserved
START Control byte Ackn Bit 1 Bit 2 Bit 3 - - - - - - - - - - - Bit n STOP
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U3280M
The antenna coil must be connected with a capacitor as a parallel LC resonant circuit to the Coil
1 and Coil 2 pins of the IC. The resonance frequency f0 of the antenna circuit should be in the
range of 100 kHz to 150 kHz.
The correct LC combination can be calculated with the following formula:
Figure 5-1. Antenna Circuit Connection
Example: Antenna frequency: f0 = 125 kHz, capacitor: CA = 2.2 nF
LA1
CA2π× f0
×()
2
×
------------------------------------------------=
LACA
Coil 1
Coil 2
LA1
2.2 nF 2 π× 125 kHz×()
2
×
--------------------------------------------------------------------------- 737 µH==
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U3280M
6. Absolute Maximum Ratings
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at any condition beyond those indicated in the operational section of these specification is not
implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. All inputs and outputs are
protected against high electrostatic voltages or electric fields. However, precautions to minimize build-up of electrostatic charges during
handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for
example, VDD).
Voltages are given relative to VSS
Parameter Symbol Value Unit
Supply voltage VDD, VBatt 0V to +7.0V with reverse protection V
Maximum current out of VSS pin ISS 15 mA
Maximum current into VBatt pin IBatt 15 mA
Input voltage (on any pin) VIN VSS –0.6 ≤VIN ≤VDD +0.6 V
Input/output clamp current (VSS > Vi/Vo > VDD)I
IK/IOK ±15 mA
Min. ESD protection (100 pF through 1.5 kΩ)±2kV
Operating temperature range Tamb -40 to +85 °C
Storage temperature range TSTG -40 to +125 °C
Soldering temperature (t ≤10s) TSD 260 °C
7. Thermal Resistance
Parameter Symbol Value Unit
Junction ambient RthJA 180 K/W
8. DC Characteristics
Supply voltage VDD = 1.8V to 6.5V, VSS = 0V, Tamb = –40°C to 85°C unless otherwise specified
Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit
Power Supply
Operating voltage at VBatt VBatt 2.0 6.5 V
Operating voltage at VDD during
battery supply VDDB VBatt –
VSD V
VDD-limiter voltage during coil
supply VDDC 2.6 2.9 3.2 V
Operating current during field
supply VDD > 2.0V IFi 40 80 µA
Sleep current ISl 0.4 µA
EEPROM
Operating current during
erase/write cycle
VDD = 2.0V
VDD = 6.5V
IWR
IWR 400 500
1200
µA
µA
Operating current during read
cycle
VDD = 2.0V
VDD = 6.5V
Peak current during 1/4 of read
cycle
IRdp
IRdp
300
350
µA
µA
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U3280M
Power Management
Field-on detection voltage VDD > 1.8V VFDon 2.3 2.5 2.9 V
Field-off detection voltage VDD > 1.8V VFDoff 0.8 V
Voltage drop at
power-supply switch
IS = 0.5 mA,
VBatt = 2 V VSD 150 mV
Coil Inputs: Coil 1 and Coil 2
Coil input current ICI 20 mA
Input capacitance CIN 30 pF
Coil voltage stroke during
modulation
VCU > 5V
Icoil = 3 to 20 mA VCMS 1.8 2.3 4.0 V
Pin MOD
Input LOW voltage VIL VIH 0.2 ×
VDD V
Input LOW voltage VIH 0.8 ×
VDD VDD V
Input leakage current IIleakage 10 nA
Pin NGAP/FC
Output LOW current VDD = 2.0V
VOL = 0.2 ×VDD IOL 0 . 0 8 0 . 2 0 . 3 m A
Output HIGH current VDD = 2.0V
VOH = 0.8 ×VDD IOH –0.06 –0.15 –0.25 m A
Serial Interface I/O Pins SCL and SDA
Input LOW voltage VIL VIH 0.3 ×
VDD V
Input HIGH voltage VIH 0.7 ×
VDD VDD V
Input leakage current IIleakage 10 nA
Output LOW current
VDD = 2.0V
VOL = 0.2VDD
VDD = 6.0V
IOL
0.7
2.8
0.9
3.5
1.1
4.2
mA
mA
Output HIGH current
VDD = 2.0V
VOH = 0.8 VDD
VDD = 6.0V
IOH
–0.5
–1.8
–0.6
–2.2
–0.7
–2.6
mA
mA
8. DC Characteristics (Continued)
Supply voltage VDD = 1.8V to 6.5V, VSS = 0V, Tamb = –40°C to 85°C unless otherwise specified
Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit
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U3280M
9. AC Characteristics
Supply voltage VDD = 1.8V to 6.5V, VSS = 0V, Tamb = –40°C to 85°C unless otherwise specified
Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit
Serial Interface Timing
SCL clock frequency fSCL 0 100 kHz
Clock low time tLOW 4.7 µs
Clock high time tHIGH 4.0 µs
SDA and SCL rise time tR1000 ns
SDA and SCL fall time tF300 ns
START condition setup time tSUSTA 4.7 µs
START condition hold time tHDSTA 4.0 µs
Data input setup time tSUDAT 250 ns
Data input hold time tHDDAT 0ns
STOP condition setup time tSUSTO 4.7 µs
Bus free time tBUF 4.7 µs
Input filter time tI100 ns
Data output hold time tDH 300 1000 ns
Coil Inputs
Coil frequency fCOIL 100 125 150 kHz
Gap Detection
Delay field off to GAP = 0 VcoilGap < 0.7 VDC TFGAP0 10 50 µs
Delay field on to GAP = 1 VcoilGap > 3 VDC TFGAP1 150µs
Power Management
Battery to field switch delay tBFS 1000 µs
Field to battery switch delay VBatt = 6.5V tFBS 51030ms
EEPROM
Endurance Erase/write cycles ED500000 Cycles
Data erase/write cycle time For 16-bit access tDEW 912ms
Data retention time Tamb = 25°Ct
DR 10 years
Power up to read operation tPUR 0.2 ms
Power up to write operation tPUw 0.2 ms
Reset
Power-on reset VDDrise = 0 to 2V trise 10 ms
NRST VIl < 0.2 VDD tres 1µs
18
4688D–RFID–03/07
U3280M
Figure 9-1. Typical Reset Delay After Switching VDD On
Figure 9-2. Typical Reset Delay After Switching VDD On
Figure 9-3. VDD Rise Time to Ensure Power-on Reset
0
100
200
300
400
500
600
1.0 2.0 3.0 4.0 5.0 6.0
V
DD
NRST
t
RESDEL
V
DD
(V)
t
RESDEL
(µs)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.0 2.0 3.0 4.0 5.0 6.0
V
DD
(V)
t
RESDEL
(ms)
V
DD
NRST
5 ms
t
RESDEL
0
1
2
3
4
5
6
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0
Not allowed
t
rise
(ms)
V
DD
(V)
19
4688D–RFID–03/07
U3280M
11. Package Information
10. Ordering Information
Extended Type Number Package Remarks
U3280M-NFBY SSO16 Tube, Pb-free
U3280M-NFBG3Y SSO16 Taped and reeled, Pb-free
20
4688D–RFID–03/07
U3280M
12. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No. History
4688D-RFID-03/07
• Put datasheet in a new template
• Pb-free logo on page 1 deleted
• Section 5.1 "EEPROM Operating Modes” on page 10 changed
4688C-RFID-09/05
• Put datasheet in a new template
• Pb-free logo on page 1 added
• Table “Ordering Information” on page 19 changed
4688B-RFID-12/04
• Page 10: Data Transfer Sequence: Text changed
• Page 13: Antenna: Text changed
• Page 16: Ordering Information table changed
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4688D–RFID–03/07
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