12/9/10
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HEXFET® Power MOSFET
IRFB4321PbF
S
D
G
TO-220AB
D
S
D
G
GDS
Gate Drain Source
Benefits
lLow RDSON Reduces Losses
lLow Gate Charge Improves the Switching
Performance
lImproved Diode Recovery Improves Switching &
EMI Performance
l30V Gate Voltage Rating Improves Robustness
lFully Characterized Avalanche SOA
Applications
l Motion Control Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l Hard Switched and High Frequency Circuits
VDSS 150V
RDS(on) typ. 12m:
max. 15m:
ID85A
Absolute Maximum Ratings
Symbol Parameter Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
IDM Pulsed Drain Current d
PD @TC = 25°C Maximum Power Dissipation W
Linear Derating Factor W/°C
VGS Gate-to-Source Voltage V
EAS (Thermally limited) Single Pulse Avalanche Energy emJ
TJ Operating Junction and °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case g––– 0.43
RθCS Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W
RθJA Junction-to-Ambient g––– 62
350
Max.
85 c
60
330
-55 to + 175
2.3
10lbxin (1.1Nxm)
300
±30
120
PD - 97103B
IRFB4321PbF
2www.irf.com
S
D
G
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.095mH
RG = 25Ω, IAS = 50A, VGS =10V. Part not recommended for use
above this value.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
Rθ is measured at TJ approximately 90°C
Static @ T
J
= 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
V
(BR)DSS
Drain-to-Source Breakdown Voltage 150 ––– ––– V
ΔV
(BR)DSS
/
ΔT
J
Breakdown Voltage Temp. Coefficient ––– 150 ––– mV/°C
R
DS(on)
Static Drain-to-Source On-Resistance ––– 12 15 mΩ
V
GS(th)
Gate Threshold Voltage 3.0 ––– 5.0 V
I
DSS
Drain-to-Source Leakage Current ––– ––– 20 μA
––– ––– 1.0 mA
I
GSS
Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
R
G(int)
Internal Gate Resistance ––– 0.8 ––– Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
gfs Forward Transconductance 130 ––– ––– S
Q
g
Total Gate Charge ––– 71 110 nC
Q
gs
Gate-to-Source Charge ––– 24 –––
Q
gd
Gate-to-Drain ("Miller") Charge ––– 21 –––
t
d(on)
Turn-On Delay Time ––– 18 ––– ns
t
r
Rise Time ––– 60 –––
t
d(off)
Turn-Off Delay Time ––– 25 –––
t
f
Fall Time ––– 35 –––
C
iss
Input Capacitance ––– 4460 ––– pF
C
oss
Output Capacitance ––– 390 –––
C
rss
Reverse Transfer Capacitance ––– 82 –––
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units
I
S
Continuous Source Current ––– ––– 85
c
A
(Body Diode)
I
SM
Pulsed Source Current ––– ––– 330 A
(Body Diode)
d
V
SD
Diode Forward Voltage ––– ––– 1.3 V
t
rr
Reverse Recovery Time ––– 89 130 ns I
D
= 50A
Q
rr
Reverse Recovery Charge ––– 300 450 nC V
R
= 128V,
I
RRM
Reverse Recovery Current ––– 6.5 ––– A di/dt = 100A/μs
f
t
on
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Conditions
V
DS
= 25V, I
D
= 50A
I
D
= 50A
V
GS
= 20V
V
GS
= -20V
V
DS
= V
GS
, I
D
= 250μA
V
DS
= 150V, V
GS
= 0V
V
DS
= 150V, V
GS
= 0V, T
J
= 125°C
MOSFET symbol
V
DS
= 75V
Conditions
V
GS
= 10V
f
V
GS
= 0V
V
DS
= 50V
ƒ = 1.0MHz
Conditions
V
GS
= 0V, I
D
= 250μA
Reference to 25°C, I
D
= 1mA
d
V
GS
= 10V, I
D
= 33A
f
V
GS
= 10V
f
V
DD
= 98V
T
J
= 25°C, I
S
= 50A, V
GS
= 0V
f
integral reverse
p-n junction diode.
showing the
I
D
= 50A
R
G
= 2.5Ω
IRFB4321PbF
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Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature
Fig 2. Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage
3.0 4.0 5.0 6.0 7.0 8.0 9.0
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current
(Α)
VDS = 25V
≤ 60μs PULSE WIDTH
TJ = 25°C
TJ = 175°C
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 50A
VGS = 10V
110 100
VDS, Drain-to-Source Voltage (V)
0
1000
2000
3000
4000
5000
6000
7000
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0 20406080100120
QG Total Gate Charge (nC)
0
4
8
12
16
20
VGS, Gate-to-Source Voltage (V)
VDS= 120V
VDS= 75V
VDS= 30V
ID= 50A
0.1 110 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
≤ 60μs PULSE WIDTH
Tj = 25°C
5.0V
VGS
TOP 15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
BOTTOM 5.0V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
≤ 60μs PULSE WIDTH
Tj = 175°C
5.0V
VGS
TOP 15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
BOTTOM 5.0V
IRFB4321PbF
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 11. Typical COSS Stored Energy
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
0.20.40.60.81.01.21.4
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
140
150
160
170
180
190
V(BR)DSS , Drain-to-Source Breakdown Voltage
020 40 60 80 100 120 140 160
VDS, Drain-to-Source Voltage (V)
0.0
1.0
2.0
3.0
4.0
5.0
Energy (μJ)
25 50 75 100 125 150 175
Starting TJ, Junction Temperature (°C)
0
100
200
300
400
500
EAS, Single Pulse Avalanche Energy (mJ)
I D
TOP 13A
20A
BOTTOM 50A
1 10 100 1000
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100μsec
DC
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
10
20
30
40
50
60
70
80
90
ID , Drain Current (A)
LIMITED BY PACKAGE
IRFB4321PbF
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Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Typical Avalanche Current vs.Pulsewidth
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
Thermal Response ( Z
thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W)
τι (sec)
0.085239 0.000052
0.18817 0.00098
0.176912 0.008365
τ
J
τ
J
τ
1
τ
1
τ
2
τ
2
τ
3
τ
3
R
1
R
1
R
2
R
2
R
3
R
3
τ
τ
C
Ci= τi/Ri
Ci= τi/Ri
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
100
120
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = 50A
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
IRFB4321PbF
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Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt
Fig. 20 - Typical Stored Charge vs. dif/dt
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temperature ( °C )
1.0
2.0
3.0
4.0
5.0
6.0
VGS(th), Gate threshold Voltage (V)
ID = 1.0A
ID = 1.0mA
ID = 250μA
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
0
10
20
30
40
IRRM - (A)
IF = 33A
VR = 128V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
0
10
20
30
40
IRRM - (A)
IF = 50A
VR = 128V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
0
400
800
1200
1600
2000
2400
2800
3200
QRR - (nC)
IF = 33A
VR = 128V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
0
400
800
1200
1600
2000
2400
2800
3200
QRR - (nC)
IF = 50A
VR = 128V
TJ = 125°C
TJ = 25°C
IRFB4321PbF
www.irf.com 7
Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
VGS
VDS
90%
10%
td(on) td(off)
trtf
VGS
Pulse Width < 1μs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Inductor Current
1K
VCC
DUT
0
L
IRFB4321PbF
8www.irf.com
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/10
TO-220AB packages are not recommended for Surface Mount Application.
TO-220AB Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Part Marking Information
LOT CODE 1789
EXAMPLE: T HIS IS AN IRF 1010
Note: "P" in as sembly line pos ition
i ndicates " L ead - F r ee"
IN THE ASSEMBLY LINE "C"
AS S E MBLED ON WW 19, 2000
INTERNATIONAL PART NUMBER
RECT IFIER
LOT CODE
AS S E MB L Y
LOGO
YEAR 0 = 2000
DAT E CODE
WE E K 19
LINE C
