CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x HX3 USB 3.0 Hub HX3 USB 3.0 Hub General Description HX3 is a family of USB 3.0 hub controllers compliant with the USB 3.0 specification revision 1.0. HX3 supports SuperSpeed (SS), Hi-Speed (HS), Full-Speed (FS), and Low-Speed (LS) on all the ports. It has integrated termination, pull-up, and pull-down resistors, and supports configuration options through pin-straps to reduce the overall BOM of the system. HX3 includes the following Cypress-proprietary features: Shared LinkTM: Enables extra downstream (DS) ports for on-board connections in embedded applications Ghost ChargeTM: Enables charging of devices connected to the DS ports when no host is connected on the upstream (US) port HX3 USB 3.0 Hub Features USB-IF Certified Hub, TID# 330000060, 30000074 Supports up to Four USB 3.0-Compliant DS ports All ports support SS (5 Gbps), and are backward-compatible with HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) SS and USB 2.0 Link Power Management (LPM) Dedicated Hi-Speed Transaction Translators (Multi-TT) LED status indicators - suspend, SS, and USB 2.0 operation Shared LinkTM for Embedded Applications Each DS port can simultaneously connect to an embedded SS device and a removable USB 2.0 device Enables up to eight device connections Enhanced Battery Charging Each DS port complies with the USB Battery Charging v1.2 (BC v1.2) specification Ghost ChargeTM: Each DS port can emulate a Dedicated Charging Port (DCP) when the host is not connected to the US port Accessory Charger Adapter Dock (ACA-Dock): Enables charging and simultaneous data transfer for a smart phone or a tablet acting as a host compliant to BC v1.2 Apple charging supported on all DS ports Integrated ARM(R) CortexTM-M0 CPU 16 KB RAM, 32 KB ROM Configure GPIOs for overcurrent protection, power enable, and LEDs 2 Upgrade firmware using (a) I C EEPROM or (b) an external I2C master Cypress Semiconductor Corporation Document Number: 001-73643 Rev. *S * Vendor-Command Support to Implement a USB-to-I2C Bridge Firmware upgrade of an external ASSP connected to HX3 through USB In-System Programming (ISP) of the EEPROM connected to HX3 through USB Extensive Configuration Support Pin-strap configuration for the following functions: * Vendor ID (VID) * Charging support for each DS port * Number of active ports * Number of non-removable devices * Ganged or individual power switch enables for DS ports * Power switch polarity selection 2 Custom configuration modes supported with eFuse, I C 2 EEPROM, or I C slave * SS and USB 2.0 PHY parameters * Product ID (PID)/VID, manufacturer, and product string descriptors * Swap DP/DM signals for flexible PCB routing Software Features Microsoft WHQL-certified for Windows XP/Vista/7/8/8.1 Compatible with Mac OS 10.9 and Linux kernel version 3.11 Customize configuration parameters with the easy-to-use Cypress's "Blaster Plus" software tool Flexible Packaging Options 68-pin QFN (8 x 8 x 1.0 mm) 88-pin QFN (10 x 10 x 1.0 mm) 100-ball BGA (6 x 6 x 1.0 mm) Industrial temperature range (-40 C to +85 C) 198 Champion Court * San Jose, CA 95134-1709 * +1-408-943-2600 Revised March 13, 2019 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Block Diagram SS PHY VBUS SSRxP/M DP DM USB 2.0 PHY SSTxP/M US Port USB 2.0 SS ARM Cortex-M0 VBUS Detect RAM USB 2.0 Controller SS Controller PHY Interface US Port Control Routing Hub Controller Hub Controller Repeater Four Transaction Translators ROM I2C 1.2 V US Buffers DS Buffers DS Port 1 Document Number: 001-73643 Rev. *S DS Port 2 DS Port 3 Port Control PWR OVR LED SSTxP/M SS PHY SSRxP/M USB 2.0 PHY DP DM Port Control PWR OVR LED SS PHY SSTxP/M USB 2.0 PHY SSRxP/M Port Control PWR OVR LED SSTxP/M SS PHY SSRxP/M USB 2.0 PHY DP DM PWR OVR LED SSTxP/M SSRxP/M DP DM Port Control 26 MHz Buffer and Routing Logic DP DM Routing Logic SS PHY I2C_CLK 3.3 V PLL USB 2.0 PHY I2C_DATA DS Port 4 Page 2 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Contents Architecture Overview ..................................................... 4 SS Hub Controller ....................................................... 4 USB 2.0 Hub Controller ............................................... 4 CPU ............................................................................. 4 I2C Interface ................................................................ 4 Port Controller ............................................................. 4 Applications ...................................................................... 4 HX3 Product Options ....................................................... 5 Product Features .............................................................. 6 Shared Link ................................................................. 6 Ghost Charge .............................................................. 6 Vendor-Command Support ......................................... 7 ACA-Dock Support ...................................................... 7 Pin Information ................................................................. 8 System Interfaces ........................................................... 24 Upstream Port (US) ................................................... 24 Downstream Ports (DS1, 2, 3, 4) .............................. 24 Communication Interfaces (I2C) ................................ 24 Oscillator ................................................................... 24 GPIOs ........................................................................ 24 Power Control ............................................................ 24 Reset ......................................................................... 24 Configuration Mode Select ........................................ 24 Configuration Options ................................................ 25 Document Number: 001-73643 Rev. *S EMI ................................................................................... 33 ESD .................................................................................. 33 Absolute Maximum Ratings .......................................... 34 Electrical Specifications ................................................ 34 DC Electrical Characteristics ..................................... 34 Power Consumption .................................................. 35 Ordering Information ...................................................... 36 Ordering Code Definitions ......................................... 37 Packaging ........................................................................ 38 Package Diagrams .......................................................... 39 Acronyms ........................................................................ 41 Reference Documents .................................................... 41 Document Conventions ................................................. 41 Units of Measure ....................................................... 41 Silicon Revision History ................................................ 42 Method of Identification ............................................. 42 Document History Page ................................................. 43 Sales, Solutions, and Legal Information ...................... 45 Worldwide Sales and Design Support ....................... 45 Products .................................................................... 45 PSoC(R) Solutions ...................................................... 45 Cypress Developer Community ................................. 45 Technical Support ..................................................... 45 Page 3 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Architecture Overview The Block Diagram on page 2 shows the HX3 architecture. HX3 consists of two independent hub controllers (SS and USB 2.0), the Cortex-M0 CPU subsystem, an I2C interface, and port controller blocks. SS Hub Controller This block supports the SS hub functionality based on the USB 3.0 specification. The SS hub controller supports the following: SS link power management (U0, U1, U2, U3 states) Full-duplex data transmission USB 2.0 Hub Controller This block supports the LS, FS, and HS hub functionalities. It includes the repeater, frame timer, and four transaction translators. The USB 2.0 hub controller block supports the following: I2C Interface The I2C interface in HX3 supports the following: I2C Slave, Master, and Multi-master configurations 2 2 Configure HX3 by an external I C master in I C slave mode 2 Configure HX3 from an I C EEPROM 2 Multi-master mode to share EEPROM with other I C masters In-System Programming of the I2C EEPROM from HX3's US port Port Controller The port controller block controls DS port power to comply with the BC v1.2 and USB 3.0 specifications. This block also controls the US port power in the ACA-Dock mode. Control signals for external power switches are implemented within the chip. HX3 controls the external power switches at power-on to reduce in-rush current. The port controller block supports the following: Overcurrent detection USB 2.0 link power management (L0, L1, L2, L3 states) SS and USB 2.0 port indicators for each DS port Suspend, resume, and remote wake-up signaling Ganged and individual power control modes Multi-TT (one TT for each DS port) Automatic port numbering based on active ports CPU Applications The ARM Cortex-M0 CPU subsystem is used for the following functions: Standalone hubs PC and tablet motherboards Docking station Hand-held cradles Monitors Digital TVs Set-top boxes Printers System configuration and initialization Battery charging control Vendor-specific commands for the USB-to-I2C bridge String-descriptor support Suspend status indicator Shared Link support in embedded systems Document Number: 001-73643 Rev. *S Page 4 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x HX3 Product Options Table 1. HX3 Product Options Features CYUSB3302 CYUSB3304 CYUSB3312 CYUSB3314 CYUSB3324 CYUSB3326 CYUSB3328 CYUSB2302 CYUSB2304 8 (4 SS, 4 USB 2.0) 2 (USB 2.0) 4 (USB 2.0) 2 (USB 3.0) 4 (USB 3.0) 2 (USB 3.0) 4 (USB 3.0) 4 (USB 3.0) 6 (2 USB 3.0, 2 SS, 2 USB 2.0) 0 0 0 0 0 2[1] 4 0 0 BC v1.2 Yes Yes Yes Yes Yes Yes Yes Yes Yes ACA-Dock No No No No Yes No Yes No No Ganged Ganged Individual and Ganged Individual and Ganged Individual and Ganged Individual Individual Ganged Ganged No No Yes Yes Yes Yes Yes No No I C Yes Yes Yes Yes Yes Yes Yes Yes Yes Vendor command Yes Yes Yes Yes Yes Yes Yes Yes Yes Number of DS ports Number of Shared Link ports External Power Switch Control Pin-Strap support 2 Port indicators Packages [2] Temperature range No No Yes Yes Yes No No No No 68-QFN, 100-ball BGA 68-QFN, 100-ball BGA 88-QFN, 100-ball BGA 88-QFN, 100-ball BGA 88-QFN, 100-ball BGA 88-QFN, 100-ball BGA 88-QFN, 100-ball BGA 68-QFN, 100-ball BGA 68-QFN, 100-ball BGA Industrial and Commercial Industrial and Commercial Industrial and Commercial Industrial and Commercial Industrial and Commercial Industrial and Commercial Industrial (88-QFN only) and Commercial Industrial and Commercial Industrial and Commercial Notes 1. DS1 and DS2 are Shared link Ports. 2. BGA Industrial Grade packages are limited to 1 W of active power. For power calculations refer to Table 12 on page 35. Document Number: 001-73643 Rev. *S Page 5 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Product Features Shared Link Figure 1. Application of Shared Link in a Notebook Example: Shared Link Provides Six USB Ports in a Notebook USB 2.0 2 USB 3.0 6 DS4 6 HX3 Internal SS Port USB 3.0 2 D+ D- 4 USB 3.0 SSTX+ SSTX- 6 SS (internal) 6 SSRX+ USB 3.0 6 SSRX- DS3 Standard USB 2.0 Port DS1 4 US PC Chipset USB 3.0 Host SS (internal) USB 3.0 Port Split Into SS Port and Standard USB 2.0 Port USB 2.0 WiFi Module USB 3.0 Camera DS2 Notebook PC Motherboard USB 2.0 HX3 USB 3.0 Port USB 3.0 Card Reader Shared Link is a Cypress-proprietary feature that enables a USB 3.0 port to be split into an embedded SS port and a standard USB 2.0 port. Shared Link enables a maximum of eight DS ports from a four-port USB 3.0 hub. DSx_PWREN is another output signal generated by HX3 and controls VBUS for the removable USB 2.0 device. For example, when an overcurrent condition occurs, DSx_PWREN turns off the port power. For example, if one of the DS ports is connected to an embedded SS device, such as a USB 3.0 camera, HX3 enables the system designer to reuse the USB 2.0 signals of that specific port to connect to a standard USB 2.0 port. Figure 1 shows how Shared Link can be used in an application. Ghost Charge HX3 Ghost Charge is a Cypress-proprietary feature for charging USB devices on the DS port when the US port is not connected to a host. For example, in a docking station with HX3 as shown in Figure 3, when the laptop is undocked, HX3 will emulate a dedicated charging port (DCP) to provide charge to a phone connected on a DS port. USB 3.0 DS Port Figure 3. Ghost Charge Figure 2. DS Port VBUS Control in Shared Link Embedded SuperSpeed Device Power to Smartphone (HX3's Downstream Port) DSx_PWREN DM USB 2.0 PHY DP SSTXP/M SSRXP/M VBUS DSx_VBUSEN_SL SuperSpeed PHY VBUS Removable USB 2.0 Device The Shared Link mode requires a separate VBUS control for the removable USB 2.0 device and the embedded SS device. Figure 2 shows the VBUS control implementation. USB Cable HX3 Notebook PC Undocked Charge a smartphone without docking the notebook To ensure that the embedded SS device does not fall back to USB 2.0 operation, an external power switch is required. This switch is controlled by HX3, which generates an output signal called DSx_VBUSEN_SL. This signal controls the VBUS for the embedded device. Document Number: 001-73643 Rev. *S Page 6 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x When the US port is disconnected from the host, HX3 detects if any of the DS ports are connected to a device requesting charging. It determines the charging method and then switches to the appropriate signaling based on the detected charging specification as shown in Figure 4. The hub either emulates a USB-compliant dedicated charging port by connecting DP and DM (see the BC v1.2 specification) or other supported proprietary charging schemes. Figure 4. Ghost Charge Implementation in HX3 HX3 DS PORT Other Charging Scheme BC v1.2 Scheme Figure 5 shows the ACA-Dock system. If the ACA-Dock feature is enabled, HX3 turns on the external power switch to drive VBUS on the US port. To inform the OTG host that it is connected to an ACA-Dock, the ID pin is tied to ground using a resistor RID_A,3 as shown in Figure 5. The ACA-Dock feature can be disabled using the Configuration Options on page 25. 5V Power Switch VBUS DSx_OVRCURR Figure 5. ACA-Dock Support DSx_PWREN DM In traditional USB topologies, the host provides VBUS to enable and charge the connected devices. For OTG hosts, however, an ACA-Dock provides VBUS and a method to charge the host. HX3 supports the ACA-Dock standard (see BC v1.2 specification) by integrating the functions of the adapter controller. For example, a BC v1.2 compliant phone such as a Sony Xperia (neo V) can be docked to a HX3-based ACA-Dock system. The phone acts as an OTG host and the ACA-Dock charges the phone connected to the US port while also powering the four DS ports. Charging Scheme Detector DP ACA-Dock Support VBUS Power Source 5V Wall Charger Detector Battery Charger Power Switch US_PWREN HX3 USB Battery-Powered Device Ghost Charge is enabled by default and can be disabled through configuration. Refer to Configuration Options on page 25. Vendor-Command Support VBUS To US OTG Enabled Device ID RID_A VBUS Micro A Plug PCB HX3 supports vendor-specific requests and can also enumerate as a vendor-specific device. The vendor-specific request can be used to (a) bridge USB and I2C and (b) configure HX3. This feature can be used for the following applications: Firmware upgrade of an external ASSP connected to HX3 through USB In-System programming (ISP) of an EEPROM connected to HX3 through USB Note 3. 124 k is the recommended RID_A value as per BC v1.2 specification, but some portable devices use custom RID_A values. Document Number: 001-73643 Rev. *S Page 7 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Pin Information 57 56 55 54 AVDD12 60 59 58 AVDD12 XTL_OUT 62 61 XTL_IN 63 AVDD33 DS2_DM DS2_DP 64 US_DP NC 65 US_DM NC 66 DS1_DM AVDD33 67 DS1_DP NC 68 AVDD33 NC Figure 6. HX3 68-Pin QFN 2-Port Pinout 53 52 DVDD12 1 51 DS1_RXP RREF_USB2 2 50 DS1_RXM DVDD12 3 49 DVDD12 AVDD33 4 48 DS1_TXM US_TXM 5 47 DS1_TXP US_TXP 6 46 AVDD12 DVDD12 7 45 DS2_RXP US_RXM 8 44 DS2_RXM US_RXP 9 AVDD12 10 42 DS2_TXM NC 11 41 DS2_TXP NC 12 40 GND DVDD12 13 39 NC NC 14 38 NC NC 15 37 DVDD12 AVDD12 16 36 NC VBUS_US 17 35 NC 43 DVDD12 21 22 23 24 25 26 27 28 29 30 31 32 33 34 RESERVED2 MODE_SEL[0] MODE_SEL[1] NC RREF_SS DVDD12 VDD_IO PWR_EN OVRCURR RESETN I2C_CLK I2C_DATA AVDD12 VDD_EFUSE Document Number: 001-73643 Rev. *S 20 SUSPEND 19 RESERVED1 18 VBUS_DS 68-Pin QFN Page 8 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x 57 56 55 54 AVDD12 60 59 58 AVDD12 XTL_OUT 62 61 XTL_IN DS2_DP 63 AVDD33 DS2_DM 64 US_DP DS3_DM 65 US_DM DS3_DP 66 DS1_DM AVDD33 67 DS1_DP DS4_DP 68 AVDD33 DS4_DM Figure 7. HX3 68-Pin QFN 4-Port Pinout 53 52 DVDD12 1 51 DS1_RXP RREF_USB2 2 50 DS1_RXM DVDD12 3 49 DVDD12 AVDD33 4 48 DS1_TXM US_TXM 5 47 DS1_TXP US_TXP 6 46 AVDD12 DVDD12 7 45 DS2_RXP US_RXM 8 44 DS2_RXM US_RXP 9 AVDD12 10 42 DS2_TXM DS4_TXP 11 41 DS2_TXP DS4_TXM 12 40 GND DVDD12 13 39 DS3_TXM DS4_RXM 14 38 DS3_TXP DS4_RXP 15 37 DVDD12 AVDD12 16 36 DS3_RXM VBUS_US 17 35 DS3_RXP 43 DVDD12 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VBUS_DS VDD_EFUSE SUSPEND RESERVED1 RESERVED2 MODE_SEL[0] MODE_SEL[1] NC RREF_SS DVDD12 VDD_IO PWR_EN OVRCURR RESETN I2C_CLK I2C_DATA AVDD12 68-Pin QFN Document Number: 001-73643 Rev. *S Page 9 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Figure 8. HX3 100-Ball BGA Pinout for CYUSB3302 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 NC NC NC AVDD33 DS2_DM DS2_DP AVDD33 US_DM US_DP AVDD12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 NC NC NC VDD_IO VSS AVDD33 NC NC NC DVDD12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 US_TXM NC NC NC NC VSS DS1_DP DS1_DM AVDD12 DS1_RXM D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 US_TXP NC NC DVDD12 VSS DVDD12 VSS DVDD12 VSS DS1_RXP E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 DVDD12 RREF_US B2 NC NC XTL_IN XTL_OUT VDD_IO DS1_TXM VSS DVDD12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 DVDD12 OVRCUR R RESETN DS1_TXP AVDD12 DS2_RXP G5 G6 G7 G8 G9 G10 VDD_IO PWR_EN I2C_DATA VSS DS2_RXM US_RXM VSS AVDD33 MODE_SE L[1] G1 G2 G3 G4 US_RXP VBUS_DS SUSPEND H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 AVDD12 VBUS_US VDD_EFU SE RESERVE D2 RREF_SS VSS DS2_TXM DS2_TXP NC AVDD12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 VSS AVDD12 VSS GPIO NC I2C_CLK NC NC VSS NC K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 NC NC DVDD12 NC NC NC NC NC DVDD12 NC Document Number: 001-73643 Rev. *S RESERVE MODE_SE D1 L[0] Page 10 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Figure 9. HX3 100-Ball BGA Pinout for CYUSB3304 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 NC DS4_DM DS4_DP AVDD33 DS2_DM DS2_DP AVDD33 US_DM US_DP AVDD12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 NC NC NC VDD_IO VSS AVDD33 NC NC NC DVDD12 C1 C2 C3 C4 C5 C6 C7 C8 C9 10 US_TXM NC NC DS3_DP DS3_DM VSS DS1_DP DS1_DM AVDD12 DS1_RXM D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 US_TXP NC NC DVDD12 VSS DVDD12 VSS DVDD12 VSS DS1_RXP E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 DVDD12 RREF_US B2 NC NC XTL_IN XTL_OUT VDD_IO DS1_TXM VSS DVDD12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 DVDD12 OVRCUR R RESETN DS1_TXP AVDD12 DS2_RXP G5 G6 G7 G8 G9 G10 VDD_IO PWR_EN I2C_DATA VSS DS2_RXM US_RXM VSS AVDD33 MODE_SE L[1] G1 G2 G3 G4 US_RXP VBUS_DS SUSPEND H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 AVDD12 VBUS_US VDD_EFU SE RESERVE D2 RREF_SS VSS DS2_TXM DS2_TXP NC AVDD12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 VSS AVDD12 VSS GPIO NC I2C_CLK NC NC VSS DS3_RXM K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 DS4_TXP DS4_TXM DVDD12 DS4_RXP DS4_RXM NC DS3_TXP DS3_TXM DVDD12 DS3_RXP Document Number: 001-73643 Rev. *S RESERVE MODE_SE D1 L[0] Page 11 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 2. 68-Pin QFN, 100-Ball BGA Pinout for CYUSB3302 and CYUSB3304 Pin Name Type 68-QFN Pin# 100-BGA Ball # US_RXP I 9 G1 SuperSpeed receive plus US_RXM I 8 F1 SuperSpeed receive minus US_TXP O 6 D1 SuperSpeed transmit plus US_TXM O 5 C1 SuperSpeed transmit minus CYUSB3302 CYUSB3304 Description US Port US_DP I/O 57 A9 USB 2.0 data plus US_DM I/O 58 A8 USB 2.0 data minus DS1 Port DS1_RXP I 51 D10 SuperSpeed receive plus DS1_RXM I 50 C10 SuperSpeed receive minus DS1_TXP O 47 F8 SuperSpeed transmit plus DS1_TXM O 48 E8 SuperSpeed transmit minus DS1_DP I/O 60 C7 USB 2.0 data plus DS1_DM I/O 59 C8 USB 2.0 data minus DS2_RXP I 45 F10 SuperSpeed receive plus DS2_RXM I 44 G10 SuperSpeed receive minus DS2_TXP O 41 H8 SuperSpeed transmit plus DS2 Port DS2_TXM O 42 H7 SuperSpeed transmit minus DS2_DP I/O 62 A6 USB 2.0 data plus DS2_DM I/O 63 A5 USB 2.0 data minus DS3 Port NC DS3_RXP I 35 K10 SuperSpeed receive plus NC NC DS3_RXM I 36 J10 SuperSpeed receive minus DS3_TXP O 38 K7 SuperSpeed transmit plus NC DS3_TXM O 39 K8 SuperSpeed transmit minus NC DS3_DP I/O 65 C4 USB 2.0 data plus NC DS3_DM I/O 64 C5 USB 2.0 data minus DS4 Port NC DS4_RXP I 15 K4 SuperSpeed receive plus NC DS4_RXM I 14 K5 SuperSpeed receive minus NC DS4_TXP O 11 K1 SuperSpeed transmit plus NC DS4_TXM O 12 K2 SuperSpeed transmit minus NC DS4_DP I/O 67 A3 USB 2.0 data plus NC DS4_DM I/O 68 A2 USB 2.0 data minus OVRCURR I 30 F6 Ganged overcurrent input PWR_EN I/O 29 G7 Ganged power enable output Document Number: 001-73643 Rev. *S Page 12 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 2. 68-Pin QFN, 100-Ball BGA Pinout for CYUSB3302 and CYUSB3304 (continued) Pin Name Type 68-QFN Pin# 100-BGA Ball # NC I/O 25 NA NC RESERVED1 21 22 G4 This pin must be pulled HIGH using a 10 k to VDD_IO. RESERVED2 I/O I H4 This pin must be pulled HIGH using a 10 k to VDD_IO. MODE_SEL[0] I 23 G5 Device operation mode select bit 0; refer to Table 5 on page 24 MODE_SEL[1] I 24 F4 Device operation mode select bit 1; refer to Table 5 on page 24 XTL_OUT A 54 E6 Crystal out CYUSB3302 CYUSB3304 Description Mode Select, Clock, and Reset XTL_IN A 55 E5 Crystal in RESETN I 31 F7 Active LOW reset input I2C_CLK I/O 32 J6 I2C clock I2C_DATA I/O 33 G8 I2C data SUSPEND I/O 20 G3 Hub suspend status indicator. This pin is asserted if both the SS and USB 2.0 hubs are in the suspend state and is de-asserted when either of the hubs comes out of the suspend state. Power and Ground VDD_EFUSE PWR 19 AVDD12 PWR 10, 16, 34, 46, 52, 53 GND PWR 40 DVDD12 PWR 1, 3, 7, 13, 27, 37, 43, 49, VBUS _US PWR 17 VBUS_DS PWR 18 AVDD33 PWR 4, 56, 61, 66 VDD_IO PWR 28 H3 1.2 V normal operation, 2.5 V for programming. Customers should connect to 1.2 V. A10, C9, F9, 1.2 V analog supply H1, H10, J2 B5, C6, D5, D7, D9, E9, F2, G9, GND pin H6, J1, J3, J9 B10, D4, D6, D8, E1, E10, 1.2 V core supply F5, K3, K9 H2 This pin must be connected to VBUS from US port G2 This pin is used to power the Apple-charging circuit in HX3. For normal operation, connect pin to local 5 V supply to enable Apple charging and BC v1.2 charging modes (enable multi-charger mode). For BC v1.2 compliance testing or when Apple charging is not required, connect pin to GND to enable BC v1.2 charging mode (disable multi-charger mode). A4, A7, B6, F3 3.3 V analog supply B4, E7, G6 3.3 V I/O supply USB Precision Resistors RREF_USB2 A 2 E2 Connect pin to a precision resistor (6.04 k1%) to generate a current reference for USB 2.0 PHY. RREF_SS A 26 H5 Connect pin to a precision resistor (200 1%) for SS PHY termination impedance calibration. Note 4. These pins are Do Not Use (DNU); they must be left floating. Document Number: 001-73643 Rev. *S Page 13 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 3. 68-Pin QFN, 100-Ball BGA Pinout for CYUSB2302 and CYUSB2304 Pin Name Type 68-QFN Pin# 100-BGA Ball # NC I 9 G1 SuperSpeed receive plus NC I 8 F1 SuperSpeed receive minus NC O 6 D1 SuperSpeed transmit plus NC O 5 C1 SuperSpeed transmit minus CYUSB2302 CYUSB2304 Description US Port US_DP I/O 57 A9 USB 2.0 data plus US_DM I/O 58 A8 USB 2.0 data minus DS1 Port NC I 51 D10 SuperSpeed receive plus NC I 50 C10 SuperSpeed receive minus NC O 47 F8 SuperSpeed transmit plus NC O 48 E8 SuperSpeed transmit minus DS1_DP I/O 60 C7 USB 2.0 data plus DS1_DM I/O 59 C8 USB 2.0 data minus NC I 45 F10 SuperSpeed receive plus NC I 44 G10 SuperSpeed receive minus NC O 41 H8 SuperSpeed transmit plus DS2 Port NC O 42 H7 SuperSpeed transmit minus DS2_DP I/O 62 A6 USB 2.0 data plus DS2_DM I/O 63 A5 USB 2.0 data minus DS3 Port NC I 35 K10 SuperSpeed receive plus NC NC I 36 J10 SuperSpeed receive minus NC NC O 38 K7 SuperSpeed transmit plus NC NC O 39 K8 SuperSpeed transmit minus NC DS3_DP I/O 65 C4 USB 2.0 data plus NC DS3_DM I/O 64 C5 USB 2.0 data minus NC DS4 Port NC NC I 15 K4 SuperSpeed receive plus NC NC I 14 K5 SuperSpeed receive minus NC NC O 11 K1 SuperSpeed transmit plus NC NC O 12 K2 SuperSpeed transmit minus NC DS4_DP I/O 67 A3 USB 2.0 data plus NC DS4_DM I/O 68 A2 USB 2.0 data minus OVRCURR I 30 F6 Ganged overcurrent input PWR_EN I/O 29 G7 Ganged power enable output Document Number: 001-73643 Rev. *S Page 14 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 3. 68-Pin QFN, 100-Ball BGA Pinout for CYUSB2302 and CYUSB2304 (continued) Pin Name Type 68-QFN Pin# 100-BGA Ball # NC I/O 25 NA NC RESERVED1 21 22 G4 This pin must be pulled HIGH using a 10 k to VDD_IO. RESERVED2 I/O I H4 This pin must be pulled HIGH using a 10 k to VDD_IO. MODE_SEL[0] I 23 G5 Device operation mode select bit 0; refer to Table 5 on page 24 MODE_SEL[1] I 24 F4 Device operation mode select bit 1; refer to Table 5 on page 24 XTL_OUT A 54 E6 Crystal out CYUSB2302 CYUSB2304 Description Mode Select, Clock, and Reset XTL_IN A 55 E5 Crystal in RESETN I 31 F7 Active LOW reset input I2C_CLK I/O 32 J6 I2C clock I2C_DATA I/O 33 G8 I2C data SUSPEND I/O 20 G3 Hub suspend status indicator. This pin is asserted if both the SS and USB 2.0 hubs are in the suspend state and is de-asserted when either of the hubs comes out of the suspend state. Power and Ground VDD_EFUSE PWR 19 AVDD12 PWR 10, 16, 34, 46, 52, 53 GND PWR 40 DVDD12 PWR 1, 3, 7, 13, 27, 37, 43, 49, VBUS _US PWR 17 VBUS_DS PWR 18 AVDD33 PWR 4, 56, 61, 66 VDD_IO PWR 28 H3 1.2 V normal operation, 2.5 V for programming. Customers should connect to 1.2 V. A10, C9, F9, 1.2 V analog supply H1, H10, J2 B5, C6, D5, D7, D9, E9, F2, G9, GND pin H6, J1, J3, J9 B10, D4, D6, D8, E1, E10, 1.2 V core supply F5, K3, K9 H2 This pin must be connected to VBUS from US port G2 This pin is used to power the Apple-charging circuit in HX3. For normal operation, connect pin to local 5 V supply to enable Apple charging and BC v1.2 charging modes (enable multi-charger mode). For BC v1.2 compliance testing or when Apple charging is not required, connect pin to GND to enable BC v1.2 charging mode (disable multi-charger mode). A4, A7, B6, F3 3.3 V analog supply B4, E7, G6 3.3 V I/O supply USB Precision Resistors RREF_USB2 A 2 E2 Connect pin to a precision resistor (6.04 k1%) to generate a current reference for USB 2.0 PHY. RREF_SS A 26 H5 Connect pin to a precision resistor (200 1%) for SS PHY termination impedance calibration. Document Number: 001-73643 Rev. *S Page 15 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x VDD_IO DS3_PWREN DS2_PWREN DS3_AMBER DS2_LED_SS DVDD12 NC NC AVDD33 NC NC DS2_DM DS2_DP AVDD33 DS1_DP DS1_DM US_DM US_DP AVDD33 XTL_IN XTL_OUT AVDD12 Figure 10. HX3 88-Pin QFN 2-Port Pinout 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 DS2_OVRCURR 1 66 VDD_IO DS1_AMBER 2 65 DS3_OVRCURR DS1_GREEN 3 64 DS3_GREEN DS1_LED_SS 4 63 DS3_LED_SS DS2_AMBER 5 62 AVDD12 DS2_GREEN 6 61 DS1_RXP RREF_USB2 7 60 DS1_RXM DVDD12 8 59 DVDD12 AVDD33 9 58 DS1_TXM US_TXM 10 57 DS1_TXP US_TXP 11 DVDD12 12 US_RXM 13 54 US_RXP 14 53 DVDD12 AVDD12 15 52 DS2_TXM NC 16 51 DS2_TXP NC 17 50 GND DVDD12 18 49 NC NC 19 48 NC NC 20 47 DVDD12 AVDD12 21 46 NC VBUS_US 22 45 NC 56 88-Pin QFN 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 VBUS_DS VDD_EFUSE SUSPEND DS4_LED_SS RESERVED1 MODE_SEL[0] MODE_SEL[1] DS4_AMBER US_PWREN RREF_SS DVDD12 VDD_IO DS4_PWREN/PWR_EN4 DS4_OVRCURR RESETN DS1_PWREN US_OVRCURR I2C_CLK I2C_DATA DS1_OVRCURR DS4_GREEN AVDD12 55 DS2_RXP 23 Document Number: 001-73643 Rev. *S AVDD12 DS2_RXM Page 16 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x VDD_IO DS3_PWREN DS2_PWREN DS3_AMBER DS2_LED_SS DVDD12 DS4_DM DS4_DP AVDD33 DS3_DP DS3_DM DS2_DM DS2_DP AVDD33 DS1_DP DS1_DM US_DM US_DP AVDD33 XTL_IN XTL_OUT AVDD12 Figure 11. HX3 88-Pin QFN 4-Port Pinout 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 DS2_OVRCURR 1 66 VDD_IO DS1_AMBER 2 65 DS3_OVRCURR DS1_GREEN 3 64 DS3_GREEN DS1_LED_SS 4 63 DS3_LED_SS DS2_AMBER 5 62 AVDD12 DS2_GREEN 6 61 DS1_RXP RREF_USB2 7 60 DS1_RXM DVDD12 8 59 DVDD12 AVDD33 9 58 DS1_TXM US_TXM 10 57 DS1_TXP US_TXP 11 DVDD12 12 US_RXM 13 54 US_RXP 14 53 DVDD12 AVDD12 15 52 DS2_TXM DS4_TXP 16 51 DS2_TXP DS4_TXM 17 50 GND DVDD12 18 49 DS3_TXM DS4_RXM 19 48 DS3_TXP DS4_RXP 20 47 DVDD12 AVDD12 21 46 DS3_RXM VBUS_US 22 45 DS3_RXP 56 88-Pin QFN 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 VBUS_DS VDD_EFUSE SUSPEND DS4_LED_SS RESERVED1 MODE_SEL[0] MODE_SEL[1] DS4_AMBER US_PWREN RREF_SS DVDD12 VDD_IO DS4_PWREN/PWR_EN4 DS4_OVRCURR RESETN DS1_PWREN US_OVRCURR I2C_CLK I2C_DATA DS1_OVRCURR DS4_GREEN AVDD12 55 DS2_RXP 23 Document Number: 001-73643 Rev. *S AVDD12 DS2_RXM Page 17 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Figure 12. HX3 100-Ball BGA Pinout for CYUSB3312 A1 A2 DS3_PWR NC EN B1 B2 DS2_OVR DS2_PWR CURR EN C1 C2 DS1_AMBE US_TXM R D1 D2 DS1_LED_ US_TXP SS E1 E2 RREF_USB DVDD12 2 F1 F2 US_RXM G1 US_RXP H1 AVDD12 J1 VSS K1 NC A3 A4 A5 A6 A7 A8 A9 A10 NC AVDD33 DS2_DM DS2_DP AVDD33 US_DM US_DP AVDD12 B3 B4 B5 B6 B7 B8 B9 DS3_AMBE DS3_OVR DS3_GREE DS3_LED_ VDD_IO VSS AVDD33 R CURR N SS C3 C4 C5 C6 C7 C8 C9 DS2_LED_ NC NC VSS DS1_DP DS1_DM AVDD12 SS D3 D4 D5 D6 D7 D8 D9 DS1_GREE DVDD12 VSS DVDD12 VSS DVDD12 VSS N E3 E4 E5 E6 E7 E8 E9 DS2_GREE DS2_AMBE XTL_IN XTL_OUT VDD_IO DS1_TXM VSS N R F3 F4 F5 F6 F7 F8 F9 MODE_SE DS4_OVR VSS AVDD33 DVDD12 RESETN DS1_TXP AVDD12 L[1] CURR G2 G3 G4 G5 G6 G7 G8 G9 RESERVE MODE_SE DS4_PWR VBUS_DS SUSPEND VDD_IO I2C_DATA VSS D1 L[0] EN H2 H3 H4 H5 H6 H7 H8 H9 VDD_EFUS DS4_LED_ DS4_GREE VBUS_US RREF_SS VSS DS2_TXM DS2_TXP E SS N J2 J3 J4 J5 J6 J7 J8 J9 DS4_AMBE US_PWRE DS1_PWR DS1_OVR AVDD12 VSS I2C_CLK VSS R N EN CURR K2 K3 K4 K5 K6 K7 K8 K9 US_OVRC NC DVDD12 NC NC NC NC DVDD12 URR Document Number: 001-73643 Rev. *S B10 DVDD12 C10 DS1_RXM D10 DS1_RXP E10 DVDD12 F10 DS2_RXP G10 DS2_RXM H10 AVDD12 J10 NC K10 NC Page 18 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Figure 13. HX3 100-Ball BGA Pinout for CYUSB3314, CYUSB332x A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 DS3_PWR EN DS4_DM DS4_DP AVDD33 DS2_DM DS2_DP AVDD33 US_DM US_DP AVDD12 B4 B5 B6 B7 B8 B9 B10 DS3_GRE EN DS3_LED _SS DVDD12 B1 B2 B3 DS2_OVR CURR DS2_PWR EN DS3_AMB ER VDD_IO VSS AVDD33 DS3_OVR CURR C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 US_TXM DS1_AMB ER DS2_LED _SS DS3_DP DS3_DM VSS DS1_DP DS1_DM AVDD12 DS1_RXM D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 US_TXP DS1_LED _SS DS1_GRE EN DVDD12 VSS DVDD12 VSS DVDD12 VSS DS1_RXP E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 DVDD12 RREF_US B2 DS2_GRE EN DS2_AMB ER XTL_IN XTL_OUT VDD_IO DS1_TXM VSS DVDD12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 DVDD12 DS4_OVR CURR RESETN DS1_TXP AVDD12 DS2_RXP G5 G6 G7 G8 G9 G10 VDD_IO DS4_PWR EN I2C_DATA VSS DS2_RXM H6 H7 H8 H9 H10 AVDD12 US_RXM VSS AVDD33 MODE_SE L[1] G1 G2 G3 G4 US_RXP VBUS_DS SUSPEND H1 H2 H3 H4 AVDD12 VBUS_US VDD_EFU SE DS4_LED _SS RREF_SS VSS DS2_TXM DS2_TXP DS4_GRE EN J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 VSS AVDD12 VSS DS4_AMB ER US_PWR EN I2C_CLK DS1_PWR EN DS1_OVR CURR VSS DS3_RXM K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 DS4_RXM US_OVRC URR DS3_TXP DS3_TXM DVDD12 DS3_RXP DS4_TXP DS4_TXM DVDD12 Document Number: 001-73643 Rev. *S RESERVE MODE_SE D1 L[0] DS4_RXP H5 Page 19 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 4. 88-Pin QFN, 100-Ball BGA Pinout for CYUSB331X and CYUSB332X Pin Name CYUSB3314 CYUSB3312 CYUSB3324 Type Pin# Ball# Description CYUSB3326 CYUSB3328 US Port US_RXP I 14 G1 SuperSpeed receive plus US_RXM I 13 F1 SuperSpeed receive minus US_TXP O 11 D1 SuperSpeed transmit plus US_TXM O 10 C1 SuperSpeed transmit minus US_DP I/O 71 A9 USB 2.0 data plus US_DM I/O 72 A8 USB 2.0 data minus K6 CYUSB3324/3328: Overcurrent detect input for US port in ACA-Dock mode. If ACA-Dock mode is disabled using Configuration Options on page 25, this pin must be pulled HIGH using a 10 k to VDD_IO. Other part numbers: This pin must be pulled HIGH using a 10 k to VDD_IO. US_OVRCURR US_PWREN[5] I I/O 39 31 J5 PWR_SW_POL[6] CYUSB3324/3328: VBUS power enable output for US port in ACA-Dock mode. If ACA-Dock mode is disabled using Configuration Options on page 25, this pin can be left floating if Pin-Strap is not enabled. Other part numbers: This pin can be left floating if Pin-Strap (Pin# 63) is not enabled. This pin is called PWR_SW_POL in pin-strap configuration mode. DS1 Port DS1_RXP I 61 D10 SuperSpeed receive plus DS1_RXM I 60 C10 SuperSpeed receive minus DS1_TXP O 57 F8 SuperSpeed transmit plus DS1_TXM O 58 E8 SuperSpeed transmit minus DS1_DP I/O 74 C7 USB 2.0 data plus DS1_DM I/O 73 C8 USB 2.0 data minus DS1_OVRCURR I 42 J8 Overcurrent detect input for DS1 port I/O 38 J7 VBUS power enable output for DS1 port. When the port is disabled, this pin is in tristate. DS1_PWREN[5] DS1_CDP_EN[6] DS1_AMBER[5] ACA_DOCK[6] This pin is called DS1_CDP_EN in pin-strap configuration mode. I/O 2 C2 DS1_GREEN[5] DS1_VBUSEN_SL[5] PORT_DISABLE[1][6] This pin is called ACA-DOCK in pin-strap configuration mode. CYUSB3312/3314/3324: LED_GREEN output for DS1 port I/O 3 D3 PORT_DISABLE[0][6] DS1_LED_SS[5] LED_AMBER output for DS1 port CYUSB3326/3328: VBUS power enable output for SS port 1 This pin is called PORT_DISABLE[0] in pin-strap configuration mode. I/O 4 D2 LED_SS output for DS1 port This pin is called PORT_DISABLE[1] in pin-strap configuration mode. Notes 5. This pin can be configured as a GPIO using custom firmware. For information contact www.cypress.com/support. 6. For pin-strap configuration details, refer to Table 6 on page 26. Document Number: 001-73643 Rev. *S Page 20 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 4. 88-Pin QFN, 100-Ball BGA Pinout for CYUSB331X and CYUSB332X (continued) Pin Name CYUSB3314 CYUSB3312 CYUSB3324 Type Pin# Ball# Description CYUSB3326 CYUSB3328 DS2 Port DS2_RXP I 55 F10 SuperSpeed receive plus DS2_RXM I 54 G10 SuperSpeed receive minus DS2_TXP O 51 H8 SuperSpeed transmit plus DS2_TXM O 52 H7 SuperSpeed transmit minus DS2_DP I/O 76 A6 USB 2.0 data plus DS2_DM I/O 77 A5 USB 2.0 data minus DS2_OVRCURR I 1 B1 Overcurrent detect input for DS2 port B2 VBUS power enable output for DS2 port. When the port is disabled, this pin is in tristate. DS2_PWREN[7] DS2_CDP_EN[8] DS2_AMBER[7] NON_REMOVABLE[0][8] I/O 86 This pin is called DS2_CDP_EN in the pin-strap configuration mode. I/O 5 E4 I/O 6 E3 DS2_GREEN[7] DS2_VBUSEN_SL[7] PWR_EN_SEL[8] This pin is called NON_REMOVABLE[0] in the pin-strap configuration mode. CYUSB3312/3314/3324: LED_GREEN output for DS2 port NON_REMOVABLE[1][8] DS2_LED_SS[7] LED_AMBER output for DS2 port CYUSB3326/3328: VBUS power enable output for SS port 2 This pin is called NON_REMOVABLE[1] in the pin-strap configuration mode. I/O 84 C3 LED_SS output for DS2 port This pin is called PWR_EN_SEL in the pin-strap configuration mode. DS3 Port NC DS3_RXP I 45 K10 SuperSpeed receive plus NC DS3_RXM I 46 J10 SuperSpeed receive minus NC DS3_TXP O 48 K7 SuperSpeed transmit plus NC DS3_TXM O 49 K8 SuperSpeed transmit minus NC DS3_DP I/O 79 C4 USB 2.0 data plus NC DS3_DM I/O 78 C5 USB 2.0 data minus I 65 B7 CYUSB3314/3324/3326/3328: Overcurrent detect input for DS3 port CYUSB3312: This pin must be pulled HIGH using a 10 k to VDD_IO. I/O 87 A1 DS3_OVRCURR DS3_PWREN[7] DS3_CDP_EN[8] DS3_AMBER[7] VID_SEL[2][8] VBUS power enable output for DS3 port. When the port is disabled, this pin is in tristate. This pin is called DS3_CDP_EN in the pin-strap configuration mode. I/O 85 B3 LED_AMBER output for DS3 port This pin is called VID_SEL[2] in the pin-strap configuration mode. Notes 7. This pin can be configured as a GPIO using custom firmware. For information contact www.cypress.com/support. 8. For pin-strap configuration details, refer to Table 6 on page 26. Document Number: 001-73643 Rev. *S Page 21 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 4. 88-Pin QFN, 100-Ball BGA Pinout for CYUSB331X and CYUSB332X (continued) Pin Name CYUSB3314 CYUSB3312 CYUSB3324 Type Pin# Ball# Description CYUSB3326 CYUSB3328 DS3_GREEN[9] DS3_VBUSEN_SL[9] CYUSB3312/3314/3324: LED_GREEN output for DS3 port I/O 64 B8 VID_SEL[1][10] DS3_LED_SS[9] PIN_STRAP[10] CYUSB3328: VBUS power enable output for SS port 3 This pin is called VID_SEL[1] in the pin-strap configuration mode. For pin-strap configuration details, refer to Table 6 on page 26. LED_SS output for DS3 port I/O 63 B9 This pin is called PIN_STRAP in pin-strap configuration mode. When connected to VDD_IO through a 10-k resistor, this pin enables pin-strap configuration mode for HX3. DS4 Port NC DS4_RXP I 20 K4 SuperSpeed receive plus NC DS4_RXM I 19 K5 SuperSpeed receive minus NC DS4_TXP O 16 K1 SuperSpeed transmit plus NC DS4_TXM O 17 K2 SuperSpeed transmit minus NC DS4_DP I/O 81 A3 USB 2.0 data plus NC DS4_DM I/O 82 A2 USB 2.0 data minus I 36 F6 CYUSB3314/3324/3326/3328: Overcurrent detect input for DS4 port. CYUSB3312: This pin must be pulled HIGH using a 10 k to VDD_IO. DS4_OVRCURR DS4_PWREN/PWR_EN4 I/O 35 G7 DS4_CDP_EN[10] DS4_AMBER[9] I2C_DEV_ID[10] This pin is called DS4_CDP_EN in the pin-strap configuration mode. I/O 30 J4 I/O 43 H9 DS4_GREEN[9] DS4_VBUSEN_SL VBUS power enable output for DS4 port. This pin is also used as power enable output when configured in ganged power mode using the Blaster Plus tool. When the port is disabled, this pin is in tristate. LED_AMBER output for DS4 port This pin is called I2C_DEV_ID in the pin-strap configuration mode. CYUSB3312/3314/3324: LED_GREEN output for DS4 port VID_SEL[0][10] CYUSB3328: VBUS power enable output for SS port 4 This pin is called VID_SEL[0] in the pin-strap configuration mode. DS4_LED_SS I/O 26 H4 LED_SS output for DS4 port. The LED must be connected to GND as shown in Figure 16 on page 25. If LED is not used, this pin must be pulled HIGH using a 10 k to VDD_IO. RESERVED1 I 27 G4 This pin must be pulled HIGH using a 10 k to VDD_IO. Mode Select, Clock, and Reset MODE_SEL[0] I 28 G5 Device operation mode select bit 0; refer to Table 5 on page 24 MODE_SEL[1] I 29 F4 Device operation mode select bit 1; refer to Table 5 on page 24 XTL_OUT A 68 E6 Crystal out XTL_IN A 69 E5 Crystal in RESETN I 37 F7 Active LOW reset input I2C_CLK I/O 40 J6 I2C clock I2C_DATA I/O 41 G8 I2C data Notes 9. This pin can be configured as a GPIO using custom firmware. For information contact www.cypress.com/support. 10. For pin-strap configuration details, refer to Table 6 on page 26. Document Number: 001-73643 Rev. *S Page 22 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 4. 88-Pin QFN, 100-Ball BGA Pinout for CYUSB331X and CYUSB332X (continued) Pin Name CYUSB3314 CYUSB3312 CYUSB3324 Type Pin# Ball# Description 25 G3 Hub suspend status indicator. This pin is asserted if both the SS and USB 2.0 hubs are in the suspend state and is de-asserted when either of the hubs comes out of the suspend state. H3 1.2 V normal operation, 2.5 V for programming. Customers should connect to 1.2 V CYUSB3326 CYUSB3328 SUSPEND I/O Power and Ground VDD_EFUSE AVDD12 GND DVDD12 VBUS _US PWR 24 A10, 15, 21, C9, F9, 1.2 V analog supply PWR 44, 56, H1, 62, 67 H10, J2 PWR 50 B5, C6, D5, D7, D9, E9, GND pin F2, G9, H6, J1, J3, J9 B10, 8, 12, D4, D6, 18, 33, D8, E1, 1.2 V core supply PWR 47, 53, E10, 59, 83 F5, K3, K9 PWR 22 23 H2 CYUSB3324/3328: Connect the VBUS_US pin to the local 5 V supply. If ACA-Dock mode is disabled using Configuration Options on page 25, this pin must be connected to VBUS from US port. Other part numbers: This pin must be connected to VBUS from US port. G2 This pin is used to power the Apple-charging circuit in HX3. For normal operation, connect pin to local 5 V supply to enable Apple charging and BC v1.2 charging modes (enable multi-charger mode). For BC v1.2 compliance testing or when Apple charging is not required, connect pin to GND to enable BC v1.2 charging mode (disable multi-charger mode). VBUS_DS PWR AVDD33 PWR 9, 70, A4, A7, 3.3 V analog supply 75, 80 B6, F3 VDD_IO PWR 34, 66, B4, E7, 3.3 V I/O supply 88 G6 USB Precision Resistors RREF_USB2 A 7 E2 Connect pin to a precision resistor (6.04 k 1%) to generate a current reference for USB 2.0 PHY. RREF_SS A 32 H5 Connect pin to a precision resistor (200 1%) for SS PHY termination impedance calibration. Document Number: 001-73643 Rev. *S Page 23 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x System Interfaces switches for DS port power and monitor overcurrent conditions. The power switch polarity and the power control mode (individual and ganged) can be changed using the configuration options. Upstream Port (US) This port is compliant with the USB 3.0 specification and includes an integrated 1.5 k pull-up and termination resistors. It also supports ACA-Dock to enable charging an OTG host connected on the US port. Downstream Ports (DS1, 2, 3, 4) DS ports are compliant with the USB 3.0 specification and integrate 15 k pull-down and termination resistors. Ports can be disabled or enabled, and can be set to removable or non-removable options. BC v1.2 charging is enabled by default and can be disabled on each DS port using the configuration options (see Configuration Options). Communication Interfaces (I2C) Reset HX3 operates with two external power supplies, 3.3 V and 1.2 V. There is no power sequencing requirement between these two supplies. However, the RESETN pin should be held LOW until both these supplies become stable. The RESETN pin can be tied to VDD_IO through an external resistor and to ground (GND) through an external capacitor (minimum 5 ms time constant), as shown in Figure 15. This creates a clean reset signal for power-on reset (POR). HX3 does not support internal brown-out detection. If the system requires this feature, an external reset should be provided on the RESETN pin when supplies are below their valid operating ranges. The interface follows the Inter-IC Bus specification, version 3.0, with support for the standard mode (100 kHz) and the fast mode (400 kHz) frequencies. HX3 supports I2C in the slave and master modes. The I2C interface supports the multi-master mode of operation. Both the SCL and SDA signals require external pull-up resistors based on the specification. VDD_IO for HX3 is 3.3 V and it is expected that the I2C pull-up resistors will be connected to the same supply. Figure 15. Reset Connection VDD_IO 10 k RESETN Oscillator 1.5 F HX3 requires an external crystal with a frequency of 26 MHz and an accuracy of 150 ppm in parallel resonant, fundamental mode. The crystal drive circuit is capable of a low-power drive level (<200 W). The crystal connection to the XTL_OUT and XTL_IN pins is shown in Figure 14. Figure 14. Crystal Connection 26 MHz XTL_IN 10 pF XTL_OUT 10 pF Configuration Mode Select Configuration options are selected through the MODE_SEL pins and the pin-strap enable pin (PIN_STRAP). After power-up, these pins are sampled by an on-chip bootloader to determine the configuration options (see Table 5). Table 5. HX3 Boot Sequence GPIOs HX3 GPIOs are used for overcurrent sensing, controlling external power switches, and driving LEDs. These pins can sink up to 4 mA current each. GPIOs also enable pin-straps for input configuration. Refer to Table 6 for more details. Power Control * MODE SEL[1] MODE SEL[0] 0 0 Reserved. Do not use this mode. 1 1 Internal ROM configuration 0 1 I2C Master, read configuration from I2C EEPROM* 1 0 I2C Slave, configure from an external I2C Master* HX3 Configuration Modes Download Cypress-provided firmware from www.cypress.com/hx3. The PWR_EN[1-4] and OV_CURR[1-4] pins interface HX3 to external power switches. These pins are used to control power Document Number: 001-73643 Rev. *S Page 24 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Configuration Options HX3 can be configured by using one of the following: eFuse (one-time programmable memory) Pin-Strap (read configuration from dedicated pins at power on) External I2C slave such as an EEPROM External I2C master The I2C master/slave configuration overrides the pin-strap configuration. Pin-straps override the eFuse configuration, and the eFuse configuration overrides the internal ROM configuration. eFuse Configuration HX3 contains eFuses, which are OTP elements on the chip that can be electrically blown. The eFuses are read by the bootloader to determine the customer-specific configurations. eFuse programming is supported only at factory and distributor locations where programming conditions can be controlled. eFuse programming is supported under the following conditions: Temperature range of 25 C-70 C and programming voltage of 2.5 V-2.7 V. the GPIOs need to be connected if pin-strap and LED connection are required or only pin-strap is required. HX3 samples pin-strap GPIOs at power-up. Floating straps are considered as invalid and the default configuration is used. If PIN_STRAP (Pin #63 of 88-pin QFN) is floating, all strap inputs are considered invalid. A GPIO is considered strapped "1" or "0" when connected with a weak pull-up (10 k) or pull-down (10 k) respectively. After the initial sampling at power-up and reset, the GPIOs are used in their normal functions. Figure 16. Pin-Strap With LED or LED-Only Connection To GPIO VDD_IO 10 k 800 - 1 k 800 - 1 k 10 k VSS To GPIO Pin-Strap HIGH with LED Pin-Strap LOW with LED Figure 17. Pin-Strap Connection VDD_IO To GPIO Pin-Strap Configuration Pin-straps are supported for select product options (see Table 1 on page 5) to provide reconfigurability without an additional EEPROM. The pin-strap configuration is enabled by pulling the Pin #63 of 88-pin QFN HIGH. Table 6 on page 26 shows the configuration options supported through pin-straps and the GPIOs used for this purpose. Figure 16 and Figure 17 show how Document Number: 001-73643 Rev. *S 10 k To GPIO Pin-Strap HIGH 10 k VSS Pin-Strap LOW Page 25 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 6. Pin-Strap Configuration 88-pin QFN Pin # Pin-Strap Name Strapped `0'[11] Strapped `1'[11] 30 I2C_DEV_ID[12] ID 0: HX3 I2C slave address (7 bits) is 0x60. This is also the default I2C slave address for ID 1: HX3 I2C slave address (7 bits) is 0x58 the 68-pin QFN package. 31 PWR_SW_POL Power enable and overcurrent will be active Power enable and overcurrent will be active LOW HIGH 2 ACA_DOCK 84 PWR_EN_SEL Individual Gang 63 PIN_STRAP[13] No pin-strapping Pin-strapping configuration enabled 4 PORT_DISABLE[1] 3 PORT_DISABLE[0] 6 NON_REMOVABLE[1][14] NON_REMOVABLE[1:0] = b'00: DS1, DS2, DS3, DS4 removable b'01: DS1, DS2, DS3 removable NON_REMOVABLE[0][14] b'10: DS1, DS2 removable b'11: DS1 removable 5 85 VID[2] 64 VID[1] 43 VID[0] 38 DS1_CDP_EN[15] 86 Disabled Enabled PORT_DISABLE[1:0] = b'00: DS1, DS2, DS3, DS4 active b'01: DS1, DS2, DS3 active b'10: DS1, DS2 active b'11: DS1 active Pin-straps cannot enable ports disabled by factory setting. Reserved. If PIN_STRAP is enabled and CY VID is required, strap VID[2:0] to `1'. strapped `0' strapped `1' strapped `0' strapped `1' DS1 CDP enabled DS1 CDP disabled DS1 CDP disabled DS1 CDP enabled DS2_CDP_EN[15] DS2 CDP enabled DS2 CDP disabled DS2 CDP disabled DS2 CDP enabled 87 DS3_CDP_EN[15] DS3 CDP enabled DS3 CDP disabled DS3 CDP disabled DS3 CDP enabled 35 DS4_CDP_EN[15] DS4 CDP enabled DS4 CDP disabled DS4 CDP disabled DS4 CDP enabled Notes 11. See Figure 16 on page 25 and Figure 17 on page 25. 12. I2C_DEV_ID is valid only when HX3 is in I2C slave mode. 13. VID, PORT_DISABLE, NON_REMOVABLE are group straps. If one of the pins in a group strap is floating (INVALID), that group input will be INVALID and the default will not be overwritten. 14. These DS ports are exposed ports and the connected devices can be removed. 15. DSx_CDP_EN will be active LOW input when PWR_SW_POL is set to active LOW; similarly DSx_CDP_EN will be active HIGH input when PWR_SW_POL is set to active HIGH. Document Number: 001-73643 Rev. *S Page 26 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x I2C Configuration Read the configuration settings from the EEPROM. These settings are displayed in the Blaster Plus GUI. Modify settings as required. Write back the updated settings on to the EEPROM. In addition, an image file can be created for external use. I2C When enabled for configuration through the MODE_SEL pins (See Table 5 on page 24), HX3 can be configured as an I2C master or as an I2C slave. HX3's configuration data is a maximum of 197 bytes and HX3's firmware is 10 KB. Note that HX3's firmware also includes configuration settings. HX3 as I2C Master HX3 reads configurations from an external I2C EEPROM with sizes ranging from 16 to 64 KB. An example of a supported EEPROM is 24LC128. Based on the contents of the bSignature and bImageType fields in Table 8 on page 27, HX3 performs one of the following actions: Loads custom configuration settings from the EEPROM when bSignature is "CY" and bImageType is 0xD4. Loads the Cypress-provided firmware from the EEPROM when bSignature is "CY" and bImageType is 0xB0. This firmware also includes configuration settings. If bSignature "CY", HX3 enumerates in the vendor-specific mode. The contents of the EEPROM can be updated with the easy-to-use Cypress Blaster Plus tool. Blaster Plus is a GUI-based tool to configure HX3. This tool allows to do the following: Download the Cypress-provided firmware from a PC via HX3's US port and store it on an EEPROM connected to HX3's I2C port. The EEPROM addresses for small and large EEPROM is shown in Table 7. Small EEPROM refers to one-byte address I2C EEPROM with size ranging from 128-byte to 2K-byte while Large EEPROM refers to two-byte address I2C EEPROM with size ranging from 4K-byte to 256K-byte. Table 7. EEPROM Addresses EEPROM Type EEPROM Address Blaster Plus I2C Address Small EEPROM 0x50 0xA0 Large EEPROM 0x51 0xA2 The Blaster Plus tool, user guide, and the Cypress-provided firmware are available at www.cypress.com/hx3. HX3 as I2C Slave An external I2C master can program the configuration settings into HX3 according to the EEPROM map in Table 8. Alternatively, the HX3 firmware (<10 KB), which includes configuration settings, can also be programmed. It is recommended to use the Blaster Plus tool to create the HX3 firmware or configuration image file. HX3's I2C slave address needs to be provided while creating the image file. Refer to Table 6 on page 26 for HX3's I2C slave address. Table 8. EEPROM Map I2C Offset Bits Name 0 7:0 bSignature LSB ("C") Default 0x43 1 7:0 bSignature MSB ("Y") 0x59 2 7:6 bImageCTL 5:4 I2C Speed b'00 3:1 bImageCTL 0 bImageCTL b'000 0 7:0 bImageType 0xD4 3 Document Number: 001-73643 Rev. *S b'11 Description The first byte of the 2-byte signature initialized with "CY" ASCII text. When the signature is not valid, the hub enumerates as a vendor-specific device. The second byte of the 2-byte signature initialized with "CY" ASCII text. When the signature is not valid, the hub enumerates as a vendor-specific device. Reserved b'01: 400 kHz b'11: 100 kHz Reserved 0: Execution binary file 1: Data file 0xD4: Load only configuration 0xB0: Load firmware boot image All other bImageType will return an error code. Page 27 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 8. EEPROM Map (continued) I2C Offset Bits 4 7:0 bD4Length Name 5 6 7 8 7:0 7:0 7:0 7:0 VID [7:0] VID [15:8] PID [7:0] PID [15:8] 9 7:0 DID [7:0] 10 11 12 7:0 DID [15:8] 7:0 Reserved 7:4 SHARED_LINK_EN 3:0 SHC_ACTIVE_PORTS [3:0] Default 40 0xB4 0x04 0x04 0x65 00 - 88-pin QFN, 10 - 68-pin QFN 50 0 b'0000 b'1111 13 7:0 POWER_ON_TIME 14 7:4 REMOVABLE_PORTS [3:0] b'1111 3:0 UHC_ACTIVE_PORTS [3:0] b'1111 Document Number: 001-73643 Rev. *S 0x32 Description bD4Length is defined in bytes as the length from offset 5. I2C offset bytes 0-4 are the header bytes. bD4Length = 6: Only update VID, PID, and DID bD4Length = 18: Configuration options (no PHY trim) bD4Length = 40: Configuration options with PHY trim options bD4Length > 40: User must provide valid string descriptors bD4Length > 192: Error Custom Vendor ID - LSB Custom Vendor ID - MSB Custom Product ID (PID) Default: 0x6504 If separate PID is used for USB 2.0, the USB 2.0 PID will be read from offset 35 and 36. Else, USB 2.0 PID = PID+2; Default: 0x6506 Refer to Table 9 on page 33 for other default PID values for different parts. Custom Device ID - revision - LSB Custom Device ID - revision - MSB Reserved Enable Shared Link on DS port bit[7:4]=DS4, DS3, DS2, DS1 0: Shared Link not enabled 1: Shared Link enabled Indicates if a SuperSpeed port is active. bit[3:0] = DS4, DS3, DS2, DS1 0: Not active 1: Active Time (in 2-ms intervals) from the time the power-on sequence begins on a port until power is good on that port (bPwron2PwrGood) Indicates if the port is removable. bit[7:4]=DS4, DS3, DS2, DS1 0: Non-removable 1: Removable Indicates if a USB 2.0 port is active. bit[3:0]=DS4, DS3, DS2, DS1 0: Not active 1: Active Page 28 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 8. EEPROM Map (continued) I2C Offset Bits Name 15 7 SS_LED_PIN_CONTROL 6 GREEN_LED_PIN_CONTROL 0 5 AMBER_LED_PIN_CONTROL 0 4 PORT_INDICATORS 1 3 COMPOUND_HUB 0 2:1 Reserved 0 GANG 16 7 18 0 0 6 SUSPEND_INDICATOR_ DISABLE SS_US_DISABLE 0 5 PWR_EN_POLARITY 0 4:0 PORT_POLARITY 17 Default 0 7:5 Reserved 4 BC_ENABLE 0 b'00000 0 1 3 2 ACA_DOCK APPLE_XA 0 0 1 0 Reserved GHOST_CHARGE_EN 0 1 7:4 CDP_EN[3:0] b'1111 3:0 DCP_EN[3:0] b'0000 Document Number: 001-73643 Rev. *S Description Port 1-4: SS LED disable 0: DS[1:4]_LED_SS are LEDs. The LED glows when the SS port is active and not in disabled state. 1: DS[1:4]_LED_SS are not LEDs Port 1-4: USB 2.0 Green LED disable 0: DS[1:4]_GREEN are LEDs 1: DS[1:4]_GREEN are not LEDs Port 1-4: USB 2.0 Amber LED disable 0: DS[1:4]_AMBER are LEDs 1: DS[1:4]_AMBER are not LEDs Port indicators supported 0: Port indicators are not supported on its DS-facing ports and the USB 2.0 PORT_INDICATOR request has no effect. 1: Port indicators are supported on its DS-facing ports and the USB 2.0 PORT_INDICATOR request controls the indicators. Identifies a compound device. 0: Hub is not part of a compound device. 1: Hub is part of a compound device. Reserved 1: Ganged power switch enable for all DS ports 0: Individual port power switch enable for each DS port 0: Suspend indicator enabled 1: Suspend indicator disabled Hub mode of operation (USB 3.0 or USB 2.0) 0: USB 3.0 hub and USB 2.0 hub enabled 1: USB 3.0 hub disabled and USB 2.0 hub enabled Power switch control output polarity 0: Active LOW 1: Active HIGH USB 2.0 DP and DM swapped bit[4:0]=DS4, DS3, DS2, DS1, US 1: Port polarity swapped 0: Port polarity not swapped Reserved 0: BC v1.2 disabled 1: BC v1.2 enabled If this bit is set, enable ACA-Dock on the US port 0: Max limit for Apple charging 2.1 A 1: Max limit for Apple charging 1 A Reserved 0: Ghost Charging disabled 1: Ghost Charging enabled Per-port charging setting bit[7:4]=DS4, DS3, DS2, DS1 0: CDP disabled 1: CDP enabled Per-port charging setting bit[3:0]=DS4, DS3, DS2, DS1 0: DCP disabled 1: DCP enabled Page 29 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 8. EEPROM Map (continued) I2C Offset Bits Name 19 7 EMBEDDED_HUB 6 ILLEGAL_DESCRIPTOR 1 5 4 Reserved OC_POLARITY 1 0 3:0 OC_TIMER 20 21 22 23 24 Default 0 b'1000 7:0 Reserved 7:4 Reserved 3 STRING_DESCRIPTOR_ ENABLE[16] 0 0 2:0 Reserved 0 7:0 7:6 5:4 3:2 1:0 7:6 5:2 Reserved HS_AMPLITUDE_DS4 HS_AMPLITUDE_DS3 HS_AMPLITUDE_DS2 HS_AMPLITUDE_DS2 HS_AMPLITUDE_US HS_SLOPE 1:0 HS_TX_VREF 0 0 b'00 b'00 b'00 b'00 b'00 b'0100 b'10 Description If this bit is set, the US is as an embedded port and VBUS connected to VBUS_US pin is ignored. If this bit is set, the USB 2.0 hub controller will accept both 0x00 and 0x29 as valid descriptor types. If '0', only 0x29 will be accepted as a valid descriptor type. Reserved Overcurrent input polarity 0: Active LOW 1: Active HIGH Time in milliseconds for which the overcurrent inputs will be filtered Reserved Reserved 0: String descriptor support is disabled 1: String descriptor support is enabled When string descriptors are not supported, the hub controller returns a non-zero index (compile-time programmable) for each string which is supported, and 0x00 for each string not supported, as indicated by this field. Reserved Reserved HS driver amplitude control; HS driver current: +0% to +7.5% b'00: Default b'01: +2.5% b'10: +5% b'11: +7.5% HS driver slope control for all ports b'0000: +15% b'0001: +5% b'0100: Default b'0101: -5% b'1111: -7.5% Reference voltage for HS squelch (transmission envelope detector) for all ports b'00: 96 mV b'01: 108 mV b'10: 120 mV b'11: 132 mV Note 16. When the string descriptor supports LangID, Manufacturer, Product and Serial Number, the serial number must be unique for each device. Document Number: 001-73643 Rev. *S Page 30 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 8. EEPROM Map (continued) I2C Offset Bits Name 25 7:3 HS_PREEMP_EN[4:0] 26 2 HS_PREEMP_DEPTH_DS4[17] 1 0 7 6 5 4:1 HS_PREEMP_DEPTH_DS3[17] HS_PREEMP_DEPTH_DS2[17] HS_PREEMP_DEPTH_DS1[17] HS_PREEMP_DEPTH_US[17] Reserved PCS_TX_DEEMPH_DS4 Default b'00000 0 0 0 0 0 1 0x6 0 Reserved 7:4 PCS_TX_DEEMPH_DS3 0 0x6 3:0 7:4 3:0 7 6 5:0 PCS_TX_DEEMPH_DS2 PCS_TX_DEEMPH_DS1 PCS_TX_DEEMPH_US Reserved Reserved PCS_TX_SWING_FULL_DS4 0x6 0x6 0x6 0 1 0x29 30 7:6 Reserved 5:0 PCS_TX_SWING_FULL_DS3 0 0x29 31 7:6 Reserved 5:0 PCS_TX_SWING_FULL_DS2 0 0x29 32 7:6 Reserved 5:0 PCS_TX_SWING_FULL_DS1 0 0x29 27 28 29 Description HS driver pre-emphasis enable - for ports DS4, DS3, DS2, DS1, and US 0: pre-emphasis is disabled 1: pre-emphasis is enabled HS driver pre-emphasis depth 0: +10% 1: +20% Reserved USB 3.0 Tx driver de-emphasis value 0x3: -2.75 dB 0x6: -3.4 dB (Default) 0x9: -4.0 dB Reserved USB 3.0 Tx driver de-emphasis value 0x3: -2.75 dB 0x6: -3.4 dB (Default) 0x9: -4.0 dB Reserved Reserved Adjust launch amplitude of the transmitter 0x1F - 0.9 V 0x29 - 1.0 V (Default) 0x35 - 1.1 V 0x3F - 1.2 V Reserved Adjust launch amplitude of the transmitter 0x1F - 0.9 V 0x29 - 1.0 V (Default) 0x35 - 1.1 V 0x3F - 1.2 V Reserved Adjust launch amplitude of the transmitter 0x1F - 0.9 V 0x29 - 1.0 V (Default) 0x35 - 1.1 V 0x3F - 1.2 V Reserved Adjust launch amplitude of the transmitter 0x1F - 0.9 V 0x29 - 1.0 V (Default) 0x35 - 1.1 V 0x3F - 1.2 V Note 17. HS_PREEMP_DEPTH is valid only when corresponding HS_PREEMP_EN is set for that port. Document Number: 001-73643 Rev. *S Page 31 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 8. EEPROM Map (continued) I2C Offset Bits Name 33 7:6 Reserved 5:0 PCS_TX_SWING_FULL_US 34 35 36 37-44 45 46 47 48 49 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 Reserved UHC_PID [7:0]_LSB UHC_PID [15:8]_MSB Reserved bLength: LangID DescType LangID - MSB LangID - LSB bLength: Manufacturer (X) 50 51 7:0 DescType 7:0 bString: Manufacturer 49 + X 7:0 bLength: Product (Y) 50 + X 51 + X 7:0 DescType 7:0 bString: Product 49 + X + Y 7:0 bLength: Serial Number (Z) 50 + X + Y 7:0 DescType 51 + X + Y 7:0 bString: Serial Number Document Number: 001-73643 Rev. *S Default 0 0x29 0 0x06 0x65 0 4 3 9 4 54 Description Reserved Adjust launch amplitude of the transmitter 0x1F - 0.9 V 0x29 - 1.0 V (Default) 0x35 - 1.1 V 0x3F - 1.2 V Reserved USB 2.0 PID. If bD4Length 40, USB 2.0 PID will be read from this location. Eight bytes reserved for future expansion Size of LangID (defined by spec as N+2) String descriptor type (constant value) String language ID - MSB of wLangID String language ID - MSB of wLangID Manufacturer string length ("bLength: LangID + bLength: Manufacturer + bLength: Product + bLength: Serial Number" should be less than or equal to 152 bytes). X 66. String descriptor type (constant value) 3 `2', 0, `0', 0, `1', 0, `4', Manufacturer string: UNICODE UTF-16LE per USB 2.0 0, ` ', 0, `C', 0, `y', 0, specification: "2014 Cypress Semiconductor" `p', 0, `r', 0, `e', 0, `s', 0, `s', 0, ` `, 0, `S', 0, `e', 0, `m', 0, `i', 0, `c', 0, `o', 0, `n', 0, `d', 0, `u', 0, `c', 0, `t', 0, `o', 0, `r', 0 22 Product string length ("bLength: LangID + bLength: Manufacturer + bLength: Product + bLength: Serial Number" should be less than or equal to 152 bytes). Y 66. 3 String descriptor type (constant value) `C', 0, `Y', 0, `-', 0, `H', Product string: UNICODE UTF-16LE per USB 2.0 specifi0, `X', 0, `3', 0, ` ', 0, cation: "CY-HX3 HUB" `H', 0, `U', 0, `B', 0 22 Serial number string length ("bLength: LangID + bLength: Manufacturer + bLength: Product + bLength: Serial Number" should be less than or equal to 152 bytes). Z 66. 3 String descriptor type (constant value) `1', 0, `2', 0, `3', 0, `4', Serial number string: UNICODE UTF-16LE per USB 2.0 0, `5', 0, `6', 0, `7', 0, specification: "123456789A" `8', 0, `9', 0, `A', 0 Page 32 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 9 contains example values of PID for different parts. Table 9. PID Values VID PID (USB 3.0) PID (USB 2.0) Vendor Mode PID (USB 2.0) CYUSB3304-68LTXC, CYUSB3302-68LTXC Part Number 0x04B4 0x6500 0x6502 0x6503 CYUSB3314-88LTXC, CYUSB3312-88LTXC 0x04B4 0x6504 0x6506 0x6503 CYUSB3328-88LTXC, CYUSB3326-88LTXC 0x04B4 0x6508 0x650A 0x6507 Note: In I2C Master boot mode, if the connected EEPROM contains invalid signature or is blank, the hub will come up in Vendor mode in 2.0 configuration with a default Vendor Mode PID as mentioned in Table 9. EMI ESD HX3 meets the EMI requirements outlined by FCC 15B (USA) and EN55022 (Europe) for consumer electronics. HX3 tolerates EMI conducted by aggressors outlined by the above specifications and continues to function as expected. HX3 has a built-in ESD protection on all pins. The ESD protection level provided on these ports is 2.2 kV Human Body Model (HBM) based on the JESD22-A114 specification. Document Number: 001-73643 Rev. *S Page 33 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Electrostatic discharge voltage ................................. 2200 V Oscillator or crystal frequency ................. 26 MHz 150 ppm Storage temperature................................... -65 C to +150 C I/O voltage supply ...............................................3 V to 3.6 V Operating temperature .............................. -40 C to +85 C Maximum input sink current per I/O .............................. 4 mA Electrical Specifications HX3 meets all USB-IF Electrical Compliance specifications. DC Electrical Characteristics Table 10. DC Electrical Characteristics Parameter DVDD12 Description Conditions Min - 1.14 1.2 1.26 V 1.14 1.2 1.26 V 1.2 V core supply VDD_EFUSE eFuse supply AVDD12 1.2 V analog supply Normal operation Programming - Typ Max Units 2.5 2.6 2.7 V 1.14 1.2 1.26 V VDD_IO 3.3 V I/O supply - 3 3.3 3.6 V AVDD33 3.3 V analog supply - 3 3.3 3.6 V VIH Input HIGH voltage - 0.7 x VDD_IO - VDD_IO V VIL Input LOW voltage - 0 - 0.3 x VDD_IO V VOH Output HIGH voltage Output HIGH voltage at IOH +4 mA 2.4 - - V VOL Output LOW voltage Output LOW voltage at IOL -4 mA - - 0.4 V IOS Input sink current LED GPIO usage - - 4 mA IIX Input leakage current All I/O signals held at VDD_IO or GND -1 - 1 A IOZ Output HI-Z leakage current - - - 10 A ICC 1.2 V supplies combined operating current - - 410 526 mA ICC 3.3 V supplies combined operating current - - 260 286 mA VRAMP Voltage ramp rate on core and I/O Voltage ramp must be monotonic supplies 0.2 - 50 V/ms VN Noise level permitted on core and Max p-p noise level permitted on all I/O supplies supplies except AVDD - - 100 mV VN_USB Noise level permitted on AVDD12 Max p-p noise level permitted USB and AVDD33 supply supply - - 20 mV Document Number: 001-73643 Rev. *S Page 34 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Power Consumption Table 11 provides the power consumption estimates for HX3 under different conditions. Table 12 summarizes the power consumption for various combinations of devices connected to DS ports. For example, to calculate the HX3 power consumption for three SS devices connected to DS ports (and no device connected to one DS port), and a US port connected to a USB 3.0 host: Power consumption = [a] + 2*[g] = 492.5 + 2*76 = 644 mW [a] is the active power consumption for the US port connected to a USB 3.0 host and the SS device connected to the DS port. [g] is the incremental power consumption for an additional SS device connected to the DS port. Table 11. Power Consumption Estimates for Various Usage Scenarios Typical Consumption Number and Speed of DS Ports Connected Device Condition Suspend [18] Active power with USB 3.0 host [19] Active power with USB 2.0 host [19, 20] Incremental active power for additional DS port Supply Current (mA) Power (mW) Comments 1.2 V 3.3 V NA 12.0 7.1 37.8 - 1 SS 204.1 75.0 492.5 [a] 1 HS 51.2 45.2 210.7 [b] 1 FS 51.2 34.0 173.7 [c] 1 SS + 1 HS 218.0 103.4 602.9 [d] 1 HS 51.2 45.2 210.7 [e] 1 FS 51.2 34.0 173.7 [f] SS 39.4 8.7 76.0 [g] HS 7.0 19.8 73.7 [h] 7.0 14.2 55.2 [i] 10.6 9.6 44.4 [j] FS Active power saving per disabled DS port[21] - Table 12. Power Consumption Under Various Configurations Number of DS Devices Connected With Data Transfer Configuration Typical Consumption Supply Current (mA) 1.2 V 3.3 V Power (mW) Comments USB 3.0 4-Port Hub (USB 3.0 host) 4 SS devices 322 101 720 [a] + 3*[g] 3 SS + 1 HS devices 297 121 755 [d] + 2*[g] 3 SS devices 283 92 644 [a] + 2*[g] USB 3.0 4-Port Hub with one port disabled (USB 3.0 host) 3 SS devices 272 83 600 [a] + 2*[g] - [j] 2 SS + 1 HS devices 247 103 634 [d] + [g] - [j] Shared Link with eight DS ports 4 SS + 4 HS devices 357 189 1052 [d] + 3*([g] + [h]) USB 2.0 4-Port Hub (USB 2.0 host) 4 HS devices 72 105 432 [e] + 3*[h] 3 HS + 1 FS devices 72 99 413 [e] + 2*[h] + [i] Notes 18. US port in low-power state (SS in U3 and USB 2.0 in L2). 19. All four DS ports are enabled. 20. US SS disabled using configuration options. Refer to Table 8 on page 27 for I2C configuration options. 21. Power saving applicable only with a USB 3.0 host. DS ports can be disabled through configuration options. Refer to Table 6 on page 26 for pin-strapping and Table 8 on page 27 for I2C configuration options. Document Number: 001-73643 Rev. *S Page 35 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Ordering Information Table 13 lists HX3's ordering information. The table contains only the part numbers that are currently available for order. Additional part numbers for industrial temperature range can be made available on request. For more information, visit the Cypress website or contact the local sales representative. Table 13. Ordering Information Serial No. Ordering Part Number Number of DS Ports Number of Ghost ACAShared Link Charge Dock Temperature Ports Package 1. CYUSB3302-68LTXC 2 (USB 3.0) 0 Yes No 0 C-70 C 68-pin QFN 2. CYUSB3302-68LTXI 2 (USB 3.0) 0 Yes No -40 C-85 C 68-pin QFN 3. CYUSB3304-68LTXC 4 (USB 3.0) 0 Yes No 0 C-70 C 68-pin QFN 4. CYUSB3304-68LTXI 4 (USB 3.0) 0 Yes No -40 C-85 C 68-pin QFN 5. CYUSB3312-88LTXC 2 (USB 3.0) 0 Yes No 0 C-70 C 88-pin QFN 6. CYUSB3312-88LTXCT 2 (USB 3.0) 0 Yes No 0 C-70 C 88-pin QFN 7. CYUSB3312-88LTXI 2 (USB 3.0) 0 Yes No -40 C-85 C 88-pin QFN 8. CYUSB3312-88LTXIT 2 (USB 3.0) 0 Yes No -40 C-85 C 88-pin QFN 9. CYUSB3314-88LTXC 4 (USB 3.0) 0 Yes No 0 C-70 C 88-pin QFN 10. CYUSB3314-88LTXCT 4 (USB 3.0) 0 Yes No 0 C-70 C 88-pin QFN 11. CYUSB3314-88LTXI 4 (USB 3.0) 0 Yes No -40 C-85 C 88-pin QFN 12. CYUSB3314-88LTXIT 4 (USB 3.0) 0 Yes No -40 C-85 C 88-pin QFN 13. CYUSB3324-88LTXC 4 (USB 3.0) 0 Yes Yes 0 C-70 C 88-pin QFN 14. CYUSB3324-88LTXCT 4 (USB 3.0) 0 Yes Yes 0 C-70 C 88-pin QFN 15. CYUSB3324-88LTXI 4 (USB 3.0) 0 Yes Yes -40 C-85 C 88-pin QFN 16. CYUSB3324-88LTXIT 4 (USB 3.0) 0 Yes Yes -40 C-85 C 88-pin QFN 17. CYUSB3326-88LTXC 6 (2 USB 3.0, 2 SS, 2 USB 2.0) 2 Yes No 0 C-70 C 88-pin QFN 18. CYUSB3326-88LTXCT 6 (2 USB 3.0, 2 SS, 2 USB 2.0) 2 Yes No 0 C-70 C 88-pin QFN 19. CYUSB3326-88LTXI 6 (2 USB 3.0, 2 SS, 2 USB 2.0) 2 Yes No -40 C-85 C 88-pin QFN 20. CYUSB3326-88LTXIT 6 (2 USB 3.0, 2 SS, 2 USB 2.0) 2 Yes No -40 C-85 C 88-pin QFN 21. CYUSB3328-88LTXC 8 (4 SS, 4 USB 2.0) 4 Yes Yes 0 C-70 C 88-pin QFN 22. CYUSB3328-88LTXCT 8 (4 SS, 4 USB 2.0) 4 Yes Yes 0 C-70 C 88-pin QFN 23. CYUSB3328-88LTXI 8 (4 SS, 4 USB 2.0) 4 Yes Yes -40 C-85 C 88-pin QFN 24. CYUSB3328-88LTXIT 8 (4 SS, 4 USB 2.0) 4 Yes Yes -40 C-85 C 88-pin QFN 25. CYUSB3302-BVXC 2 (USB 3.0) 0 Yes No 0 C-70 C 100-ball BGA 26. CYUSB3302-BVXI 2 (USB 3.0) 0 Yes No -40-85 C 100-ball BGA 27. CYUSB3304-BVXC 4 (USB 3.0) 0 Yes No 0 C-70 C 100-ball BGA 28. CYUSB3304-BVXI 4 (USB 3.0) 0 Yes No 29. CYUSB3312-BVXC 2 (USB 3.0) 0 Yes No 30. CYUSB3312-BVXI 2 (USB 3.0) 0 Yes No 31. CYUSB3314-BVXC 4 (USB 3.0) 0 Yes No 32. CYUSB3314-BVXI 4 (USB 3.0) 0 Yes No 33. CYUSB3324-BVXC 4 (USB 3.0) 0 Yes Yes 34. CYUSB3324-BVXI 4 (USB 3.0) 0 Yes Yes Document Number: 001-73643 Rev. *S -40 C-85 C 100-ball BGA 0 C-70 C 100-ball BGA -40 C-85 C 100-ball BGA 0 C-70 C 100-ball BGA -40 C-85 C 100-ball BGA 0 C-70 C 100-ball BGA -40 C-85 C 100-ball BGA Page 36 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 13. Ordering Information (continued) Serial No. Ordering Part Number Number of DS Ports Number of Ghost ACAShared Link Charge Dock Temperature Ports No 0 C-70 C Package 35. CYUSB3326-BVXC 6 (2 USB 3.0, 2 SS, 2 USB 2.0) 2 Yes 100-ball BGA 36. CYUSB3326-BVXI 6 (2 USB 3.0, 2 SS, 2 USB 2.0) 2 Yes No 37. CYUSB3328-BVXC 8 (4 SS, 4 USB 2.0) 4 Yes Yes 0 C-70 C 100-ball BGA 38. CYUSB2302-68LTXI 2 (USB 2.0) 0 Yes No -40 C-85 C 68-pin QFN 39. CYUSB2304-68LTXI 4 (USB 2.0) 0 Yes No -40 C-85 C 68-pin QFN -40 C-85 C 100-ball BGA Ordering Code Definitions CY USB X 3 X X - XXXX X X X X = blank or T blank = Tube; T = Tape and Reel Temperature Range: X = C or I C= Commercial; I= Industrial Pb-free Package Type: XXXX = 68LT or 88LT or BV 68LT = 68-pin QFN 88LT = 88-pin QFN BV = 100-ball BGA Number of Ports Feature list: X = 0 or 1 or 2 0 = Basic, 1 = Intermediate, 2 = Advanced Hub Family USB speed: X = 3 or 2 3 = USB 3.0; 2 = USB 2.0 Marketing Code: USB Company ID: CY = Cypress Document Number: 001-73643 Rev. *S Page 37 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Packaging Table 14. Package Characteristics Min Typ Max Units TA Parameter Operating ambient temperature Description -40 - 85 C TJ Operating junction temperature -40 - 125 C TJA Package JA (68-pin QFN) - 16.2 - C/W TJA Package JA (88-pin QFN) - 15.7 - C/W TJA Package JA (100-ball BGA) - 35 - C/W TJC Package JC (68-pin QFN) - 23.8 - C/W TJC Package JC (88-pin QFN) - 18.9 - C/W TJC Package JC (100-ball BGA) - 12 - C/W Table 15. Solder Reflow Peak Temperature Package Maximum Peak Temperature Maximum Time at Peak Temperature 68-pin QFN 260 C 30 seconds 88-pin QFN 260 C 30 seconds 100-ball BGA 260 C 30 seconds Table 16. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package MSL 68-pin QFN MSL 3 88-pin QFN MSL 3 100-ball BGA MSL 3 Document Number: 001-73643 Rev. *S Page 38 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Package Diagrams Figure 18. 68-pin QFN (8 x 8 x 1.0 mm) LT68B 5.1 x 5.1 mm EPAD (Sawn) Package Outline NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED PAD 2. REFERENCE JEDEC#: MO-220 001-78925 *B 3. ALL DIMENSIONS ARE IN MILLIMETERS Figure 19. 88-pin QFN (10 x 10 x 1.0 mm) LT88B 5.3 x 5.3 EPAD (Sawn) Package Outline 001-76569 *B Document Number: 001-73643 Rev. *S Page 39 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Figure 20. 100-Ball BGA (6.0 x 6.0 x 1.0 mm) BZ100 Package Outline E1 2X 0.10 C E B (datum B) A1 CORNER A 10 9 8 7 6 5 4 3 2 1 7 A1 CORNER A B C D E F G H J K 6 SD D 0.10 C 2X eD 6 D1 (datum A) eE SE TOP VIEW BOTTOM VIEW DETAIL A 0.10 C A1 0.08 C A C 100XOb 5 SIDE VIEW O0.15 M C A B O0.05 M C DETAIL A NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS SYMBOL MIN. NOM. MAX. A - - 1.00 A1 0.16 - - 2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. 3. "e" REPRESENTS THE SOLDER BALL GRID PITCH. 4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. D 6.00 BSC SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. E 6.00 BSC N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX D1 4.50 BSC E1 4.50 BSC MD 10 ME 10 N 100 b 0.25 0.30 eD 0.50 BSC eE 0.50 BSC SD 0.25 BSC SE 0.25 BSC SIZE MD X ME. 5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. 0.35 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW "SD" OR "SE" = 0. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2. 7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK METALIZED MARK, INDENTATION OR OTHER MEANS. 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER BALLS. 9. JEDEC SPECIFICATION NO. REF. : MO-195C. 51-85209 *F Document Number: 001-73643 Rev. *S Page 40 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Acronyms Reference Documents Table 17. Acronyms Used in this Document USB 2.0 Specification Acronym Description USB 3.0 Specification ACA Accessory Charging Adapter Battery Charging Specification ASSP Application-Specific Standard Product Document Conventions BC Battery Charging CDP Charging Downstream Port DS DownStream DCP Dedicated Charging Port DNU Do Not Use DWG Device Working Group EEPROM Electrically Erasable Programmable Read-Only Memory FS Full-Speed FW FirmWare GND GrouND GPIO General-Purpose Input/Output HS Hi-Speed ISP In-System Programming I/O Input/Output LS Low-Speed NC No Connect OTG On-The-Go PID Product ID POR Power-On Reset ROM Read-Only Memory SCL Serial CLock SDA Serial DAta SS SuperSpeed TT Transaction Translator US UpStream VID Vendor ID Document Number: 001-73643 Rev. *S Units of Measure Table 18. Units of Measure Symbol Unit of Measure C degree celsius ohm Gbps gigabit per second KB kilobyte kHz kilohertz k kiloohm Mbps megabit per second MHz megahertz A microampere mA milliampere ms millisecond mW milliwatt ns nanosecond ppm parts per million V volt Page 41 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Silicon Revision History This datasheet is applicable for the USB-IF certified (TID# 330000060) HX3 Rev. *D and Rev. *C Silicon. Rev. *D: This Silicon revision improves the yield of HX3, and is drop-in compatible for all the part numbers. There is no need to change the board design or layout to use the HX3 Rev. *D Silicon. Products are completely compatible with the HX3 Rev. *C Silicon. Rev. *C: This Silicon revision fixes the errata applicable to the Rev. *A Silicon. The following table defines the changes between Rev. *A, Rev. *C, and Rev. *D Silicon. No. Items Part Numbers Rev. *A Rev. *C Rev. *D 1 USB-IF Compliance All Requires firmware on external EEPROM No external EEPROM required No external EEPROM required 2 FS-only hub or host connected to HX3 Upstream Port All Not supported Supported Supported 3 Suspend Power All 90 mW 37.8 mW 37.8 mW Method of Identification Markings on row 3 of the HX3 package differentiate Rev. *D Silicon from Rev. *C Silicon and Rev. *A Silicon as indicated in the example below. Cypress maintains traceability of product to wafer level, including wafer fabrication location, through the lot number marked on the package. HX3 REV *A SILICON Document Number: 001-73643 Rev. *S HX3 REV *C SILICON HX3 REV *D SILICON Page 42 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Document History Page Document Title: CYUSB330x/CYUSB331x/CYUSB332x/CYUSB230x, HX3 USB 3.0 Hub Document Number: 001-73643 Revision ECN Orig. of Change Submission Date *E 4271496 MURT 02/21/2014 Changed status from Preliminary to Final. *F 4291210 MURT 02/25/2014 Post to external web. *G 4308926 MURT 03/14/2014 Updated System Interfaces: Updated Configuration Options: Updated HX3 as I2C Slave: Updated Table 8. *H 4463533 MURT 08/01/2014 Updated Features: Updated TID#. Updated Electrical Specifications: Updated Power Consumption: Updated Table 11: Updated details corresponding to suspend power. Removed Errata. *I 4483117 RAJM 08/22/2014 Added Silicon Revision History. *J 4499514 RAJM 09/15/2014 Added 100-ball BGA package information in all instances across the document. Updated Ordering Information: Updated Table 13: Updated part numbers. Updated Package Diagrams: Added spec 51-85209 Rev. *D. *K 4582512 PRJI 11/28/2014 Updated HX3 Product Options: Updated Table 1. Updated Pin Information: Updated Table 4. *L 4632890 HBM 01/20/2015 Updated Pin Information: Updated Figure 12. Updated Figure 13. Updated Table 4. Added Packaging. Updated Package Diagrams: spec 51-85209 - Changed revision from *D to *E. *M 4669639 HBM 02/24/2015 No technical updates. Completing Sunset Review. *N 4764583 HBM 05/13/2015 Updated Package Diagrams: spec 001-76569 - Changed revision from *A to *B. Updated Silicon Revision History. Updated Method of Identification. *O 4941772 HBM 11/25/2015 Updated HX3 Product Options: Updated Table 1: Included CYUSB2302-68LTXI and CYUSB2304-68LTXI part numbers related information. Updated Ordering Information: Updated Table 13: Updated part numbers. Document Number: 001-73643 Rev. *S Description of Change Page 43 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Document History Page (continued) Document Title: CYUSB330x/CYUSB331x/CYUSB332x/CYUSB230x, HX3 USB 3.0 Hub Document Number: 001-73643 Revision ECN Orig. of Change Submission Date *P 5466603 HBM 10/20/2016 Updated Features: Replaced "USB 3.0-Certified Hub, TID# 330000060" with "USB-IF Certified Hub, TID# 330000060, 30000074". Updated Package Diagrams: spec 51-85209 - Changed revision from *E to *F. Updated to new template. Completing Sunset Review. *Q 5725383 GNKK 05/03/2017 Updated Cypress Logo and Copyright. *R 6045135 HBM 01/25/2018 Updated HX3 Product Options: Updated Table 1: Replaced "CYUSB2302-68LTXI" with "CYUSB2302" in column heading. Replaced "CYUSB2304-68LTXI" with "CYUSB2304" in column heading. Updated Ordering Information: Updated Table 13: Updated part numbers. Updated Ordering Code Definitions. Updated to new template. *S 6288337 MKRS 03/13/2019 Updated Pin Information: Updated Table 2. Updated Table 3. Updated Table 4. Updated System Interfaces: Updated Configuration Options: Updated HX3 as I2C Master: Updated description. Added Table 7. Updated HX3 as I2C Slave: Updated description. Updated Table 8. Added Table 9. Document Number: 001-73643 Rev. *S Description of Change Page 44 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-73643 Rev. *S Ghost ChargeTM and Shared LinkTM are trademarks of Cypress Semiconductor Corporation. Revised March 13, 2019 Page 45 of 45