DC1703A-A - Linear Technology

LTC2655

2655f

BLOCK DIAGRAM

FEATURES DESCRIPTION

Quad I2C 16-/12-Bit

Rail-to-Rail DACs with

10ppm/°C Max Reference

The LTC

2655 is a family of Quad I2C 16-/12-Bit Rail-to-

Rail DACs with integrated 10ppm/°C max reference. The

DACs have built-in high performance, rail-to-rail, output

buffers and are guaranteed monotonic. The LTC2655-L

has a full-scale output of 2.5V with the integrated refer-

ence and operates from a single 2.7V to 5.5V supply.

The LTC2655-H has a full-scale output of 4.096V with

the integrated reference and operates from a 4.5V to

5.5V supply. Each DAC can also operate with an external

reference, which sets the full-scale output to 2 times the

external reference voltage.

The parts use the 2-wire I2C compatible serial interface.

The LTC2655 operates in both the standard mode (maxi-

mum clock rate of 100kHz) and the fast mode (maximum

clock rate of 400kHz). The LTC2655 incorporates a

power-on reset circuit that is controlled by the PORSEL

pin. If PORSEL is tied to GND the DACs power-on reset to

zero-scale. If PORSEL is tied to VCC, the DACs power-on

reset to mid-scale.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 5396245, 6891433 and 7671770.

INL Curve

APPLICATIONS

n Integrated Reference 10ppm/°C Max

n Maximum INL Error: ±4LSB at 16 Bits

n Guaranteed Monotonic Over Temperature

n Selectable Internal or External Reference

n 2.7V to 5.5V Supply Range (LTC2655-L)

n Integrated Reference Buffers

n Ultralow Crosstalk Between DACs (<1nV•s)

n Power-On-Reset to Zero-Scale/Mid-Scale

n Asynchronous DAC Update Pin

n Tiny 20-Lead 4mm × 4mm QFN and

16-Lead Narrow SSOP packages

n Mobile Communications

n Process Control and Industrial Automation

n Instrumentation

n Automatic Test Equipment

n Automotive

2655 BD

GND

VOUTA

VOUTB

SCL

CA2

LDAC

REFLO

CA1

CA0

REFIN/OUT

REFCOMP

VCC

VOUTD

VOUTC

PORSEL

SDA

INTERNAL REFERENCE

DAC A

POWER-ON

RESET

DAC B

DAC D

DAC C

32-BIT SHIFT REGISTER

2-WIRE INTERFACE

REGISTERREGISTER

CODE

128

INL (LSB)

–2

–1

–3

–4 32768 4915216384

2655 TA01b

65535

VCC = 5V

LTC2655

2655f

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (VCC) ................................... –0.3V to 6V

SCL, SDA, LDAC, REFLO .............................. –0.3V to 6V

VOUTA to VOUTD ................–0.3V to Min (VCC + 0.3V, 6V)

REFIN/OUT, REFCOMP .....–0.3V to Min (VCC + 0.3V, 6V)

PORSEL, CA0, CA1, CA2 ..–0.3V to Min (VCC + 0.3V, 6V)

(Notes 1, 2)

GN PACKAGE

16-LEAD PLASTIC SSOP

TOP VIEW

REFLO

VOUTA

REFCOMP

VOUTB

REFIN/OUT

LDAC

CA2

SCL

GND

VCC

VOUTD

VOUTC

PORSEL

CA0

CA1

SDA

TJMAX = 150°C, θJA = 110°C/W

20 19 18 17 16

6 7 8

TOP VIEW

GND

UF PACKAGE

20-LEAD (4mm s 4mm) PLASTIC QFN

9 10

VOUTA

REFCOMP

VOUTB

REFIN/OUT

LDAC

DNC

VOUTD

VOUTC

PORSEL

CA0

REFLO

GND

VCC

DNC

CA2

SCL

DNC

SDA

CA1

TJMAX = 150°C, θJA = 37°C/W

EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB

PIN CONFIGURATION

Operating Temperature Range

LTC2655C ................................................ 0°C to 70°C

LTC2655I .............................................–40°C to 85°C

Maximum Junction Temperature .......................... 150°C

Storage Temperature Range ......................–65 to 150°C

Lead Temperature, GN Only (Soldering, 10 sec)....300°C

LTC2655

2655f

ORDER INFORMATION

LTC2655 BC UF –L 16 #TR PBF

LEAD FREE DESIGNATOR

TAPE AND REEL

TR = Tape and Reel

RESOLUTION

16 = 16-Bit

12 = 12-Bit

FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE

L = 2.5V

H = 4.096V

PACKAGE TYPE

UF = 20-Lead (4mm × 4mm) Plastic QFN

GN = 16-Lead Narrow SSOP

TEMPERATURE GRADE

C = Commercial Temperature Range (0°C to 70°C)

I = Industrial Temperature Range (–40°C to 85°C)

ELECTRICAL GRADE (OPTIONAL)

B = ±4LSB Maximum INL (16-Bit)

PRODUCT PART NUMBER

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts. Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

LTC2655

2655f

PRODUCT SELECTION GUIDE

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION

TEMPERATURE

RANGE

MAXIMUM

INL

LTC2655BCGN-L16#PBF LTC2655BCGN-L16#TRPBF 655L16 16-Lead Narrow SSOP 0°C to 70°C ±4

LTC2655BIGN-L16#PBF LTC2655BIGN-L16#TRPBF 655L16 16-Lead Narrow SSOP –40°C to 85°C ±4

LTC2655BCUF-L16#PBF LTC2655BCUF-L16#TRPBF 55L16 20-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C ±4

LTC2655BIUF-L16#PBF LTC2655BIUF-L16#TRPBF 55L16 20-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C ±4

LTC2655BCGN-H16#PBF LTC2655BCGN-H16#TRPBF 655H16 16-Lead Narrow SSOP 0°C to 70°C ±4

LTC2655BIGN-H16#PBF LTC2655BIGN-H16#TRPBF 655H16 16-Lead Narrow SSOP –40°C to 85°C ±4

LTC2655BCUF-H16#PBF LTC2655BCUF-H16#TRPBF 55H16 20-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C ±4

LTC2655BIUF-H16#PBF LTC2655BIUF-H16#TRPBF 55H16 20-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C ±4

LTC2655CGN-L12#PBF LTC2655CGN-L12#TRPBF 655L12 16-Lead Narrow SSOP 0°C to 70°C ±1

LTC2655IGN-L12#PBF LTC2655IGN-L12#TRPBF 655L12 16-Lead Narrow SSOP –40°C to 85°C ±1

LTC2655CUF-L12#PBF LTC2655CUF-L12#TRPBF 55L12 20-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C ±1

LTC2655IUF-L12#PBF LTC2655IUF-L12#TRPBF 55L12 20-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C ±1

LTC2655CGN-H12#PBF LTC2655CGN-H12#TRPBF 655H12 16-Lead Narrow SSOP 0°C to 70°C ±1

LTC2655IGN-H12#PBF LTC2655IGN-H12#TRPBF 655H12 16-Lead Narrow SSOP –40°C to 85°C ±1

LTC2655CUF-H12#PBF LTC2655CUF-H12#TRPBF 55H12 20-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C ±1

LTC2655IUF-H12#PBF LTC2655IUF-H12#TRPBF 55H12 20-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C ±1

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

LTC2655

2655f

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2655B-L16/ LTC2655-L12 (Internal Reference=1.25V)

SYMBOL PARAMETER CONDITIONS

LTC2655-12 LTC2655B-16

UNITSMIN TYP MAX MIN TYP MAX

DC Performance

Resolution l12 16 Bits

Monotonicity (Note 3) l12 16 Bits

DNL Differential Nonlinearity (Note 3) l±0.1 ±0.5 ±0.3 ±1 LSB

INL Integral Nonlinearity (Note 3) VCC = 5.5V, VREF = 2.5V l±0.5 ±1 ±2 ±4 LSB

Load Regulation VCC = 5V ±10%, Internal Reference,

Mid-Scale, –15mA ≤ IOUT ≤ 15mA

l0.04 0.125 0.6 2 LSB/mA

VCC = 3V ±10%, Internal Reference,

Mid-Scale, –7.5mA ≤ IOUT ≤ 5mA

l0.06 0.25 1 4 LSB/mA

ZSE Zero-Scale Error l13 13 mV

VOS Offset Error VREF = 1.25V (Note 4) l±1 ±2 ±1 ±2 mV

VOS Temperature Coefﬁ cient 5 5 µV/°C

GE Gain Error l±0.02 ±0.1 ±0.02 ±0.1 %FSR

Gain Temperature Coefﬁ cient 1 1 ppm/°C

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOUT DAC Output Span Internal Reference

External Reference = VEXTREF

0 to 2.5

0 to 2•VEXTREF

PSR Power Supply Rejection VCC ±10% –80 dB

ROUT DC Output Impedance VCC = 5V ±10%, Internal Reference, Mid-Scale,

–15mA ≤ IOUT ≤ 15mA

VCC = 3V ±10%, Internal Reference, Mid-Scale,

–7.5mA ≤ IOUT ≤ 7.5mA

0.04

0.15



DC Crosstalk (Note 5) Due to Full-Scale Output Change

Due to Load Current Change

Due to Powering Down (per Channel)

±1.5

±2

±1

µV

µV/mA

µV

ISC Short-Circuit Output Current (Note 6) VCC = 5.5V VEXTREF = 2.8V

Code: Zero-Scale; Forcing Output to VCC

Code: Full-Scale; Forcing Output to GND

VCC = 2.7V VEXTREF = 1.4V

Code: Zero-Scale; Forcing Output to VCC

Code: Full-Scale; Forcing Output to GND

LTC2655

2655f

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2655B-L16/LTC2655-L12 (Internal Reference = 1.25V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Reference

Reference Output Voltage 1.248 1.25 1.252 V

Reference Temperature Coefﬁ cient (Note 7) ±2 ±10 ppm/°C

Reference Line Regulation VCC ±10% –80 dB

Reference Short-Circuit Current VCC = 5.5V, Forcing REFIN/OUT to GND l35 mA

REFCOMP Pin Short-Circuit Current VCC = 5.5V, Forcing REFCOMP to GND l65 200 µA

Reference Load Regulation VCC = 3V±10% or 5V±10%, IOUT = 100µA Sourcing 40 mV/mA

Reference Output Voltage Noise Density CREFCOMP = CREFIN/OUT = 0.1µF, at f = 1kHz 30 nV/√Hz

Reference Input Range External Reference Mode (Note 14) l0.5 VCC/2 V

Reference Input Current l0.001 1 µA

Reference Input Capacitance (Note 9) 20 pF

Power Supply

VCC Positive Supply Voltage For Speciﬁ ed Performance l2.7 5.5 V

ICC Supply Current (Note 8) VCC = 5V, Internal Reference On

VCC = 5V, Internal Reference Off

VCC = 3V, Internal Reference On

VCC = 3V, Internal Reference Off

1.7

1.3

1.6

1.2

2.5

2.2

1.7

ISD Supply Current in Shutdown Mode (Note 8) VCC = 5V l3µA

Digital I/O

VIL Low Level Input Voltage (SDA and SCL) l0.3VCC V

VIH High Level Input Voltage (SDA and SCL) l0.7VCC V

VIL(LDAC)Low Level Input Voltage (LDAC) VCC = 4.5V to 5.5V l0.8 V

VCC = 2.7V to 4.5V l0.6 V

VIH(LDAC)High Level Input Voltage (LDAC) VCC = 3.6V to 5.5V l2.4 V

VCC = 2.7V to 3.6V l2V

VIL(CA) Low Level Input Voltage (CA0 to CA2) See Test Circuit 1 l0.15VCC V

VIH(CA) High Level Input Voltage (CA0 to CA2) See Test Circuit 1 l0.85VCC V

RINH Resistance from CA

(

= 0,1,2)

to VCC to Set CA

= VCC

See Test Circuit 2 l10 k

RINL Resistance from CAn (

= 0,1,2)

to GND to Set CA

= GND

See Test Circuit 2 l10 k

RINF Resistance from CA

(

= 0,1,2)

to VCC or GND to Set Ca

= FLOAT

See Test Circuit 2 l2M

VOL Low Level Output Voltage Sink Current =3mA l0 0.4 V

tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX),

CB = 10pF to 400pF (Note 13)

20+0.1CB250 ns

tSP Pulse Width of Spikes Suppressed by Input

Filter

l050ns

IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l1µA

CIN I/O Pin Capacitance (Note 9) l10 pF

CBCapacitance Load for Each Bus Line l400 pF

CCA

External Capacitive Load on Address Pins

CA0, CA1 and CA2

l10 pF

LTC2655

2655f

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2655B-H16/LTC2655-H12 (Internal Reference = 2.048V)

SYMBOL PARAMETER CONDITIONS

LTC2655-12 LTC2655B-16

UNITSMIN TYP MAX MIN TYP MAX

DC Performance

Resolution l12 16 Bits

Monotonicity (Note 3) l12 16 Bits

DNL Differential Nonlinearity (Note 3) l±0.1 ±0.5 ±0.3 ±1 LSB

INL Integral Nonlinearity (Note 3) VCC = 5.5V, VREF = 2.5V l±0.5 ±1 ±2 ±4 LSB

Load Regulation VCC = 5V ±10%, Internal Reference,

Mid-Scale, –15mA ≤ IOUT ≤ 15mA

l0.04 0.125 0.6 2 LSB/mA

ZSE Zero-Scale Error l13 13 mV

VOS Offset Error VREF = 2.048V (Note 4) l±1 ±2 ±1 ±2 mV

VOS Temperature Coefﬁ cient 5 5 µV/°C

GE Gain Error l±0.02 ±0.1 ±0.02 ±0.1 %FSR

Gain Temperature Coefﬁ cient 1 1 ppm/°C

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOUT DAC Output Span Internal Reference

External Reference = VEXTREF

0 to 4.096

0 to 2•VEXTREF

PSR Power Supply Rejection VCC ±10% –80 dB

ROUT DC Output Impedance VCC = 5V ±10%, Internal Reference, Mid-Scale,

–15mA ≤ IOUT ≤ 15mA

l0.04 0.15 

DC Crosstalk Due to Full Scale Output Change

Due to Load Current Change

Due to Powering Down (per Channel)

±1.5

±2

±1

µV

µV/mA

µV

ISC Short-Circuit Output Current (Note 4) VCC = 5.5V VEXTREF = 2.8V

Code: Zero-Scale; Forcing Output to VCC

Code: Full-Scale; Forcing Output to GND

LTC2655

2655f

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2655B-H16/LTC2655-H12 (Internal Reference = 2.048V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Reference

Reference Output Voltage 2.044 2.048 2.052 V

Reference Temperature Coefﬁ cient (Note 7) ±2 ±10 ppm/°C

Reference Line Regulation VCC ±10% –80 dB

Reference Short-Circuit Current VCC = 5.5V, Forcing REFIN/OUT to GND l35 mA

REFCOMP Pin Short-Circuit Current VCC = 5.5V, Forcing REFCOMP to GND l65 200 µA

Reference Load Regulation VCC = 5V±10%, IOUT = 100µA Sourcing 40 mV/mA

Reference Output Voltage Noise Density CREFCOMP = CREFIN/OUT = 0.1µF, at f = 1kHz 35 nV/√Hz

Reference Input Range External Reference Mode (Note 14) l0.5 VCC/2 V

Reference Input Current l0.001 1 µA

Reference Input Capacitance (Note 9) l20 pF

Power Supply

VCC Positive Supply Voltage For Speciﬁ ed Performance l4.5 5.5 V

ICC Supply Current (Note 8) VCC = 5V, Internal Reference On

VCC = 5V, Internal Reference Off

1.9

1.5

2.5

ISD Supply Current in Shutdown Mode (Note 8) VCC = 5V l3µA

Digital I/O

VIL Low Level Input Voltage (SDA and SCL) l0.3VCC V

VIH High Level Input Voltage (SDA and SCL) l0.7VCC V

VIL(LDAC)Low Level Input Voltage (LDAC)V

CC = 4.5V to 5.5V l0.8 V

VIH(LDAC)High Level Input Voltage (LDAC)V

CC = 4.5V to 5.5V l2.4 V

VIL(CA) Low Level Input Voltage (CA0 to CA2) See Test Circuit 1 l0.15VCC V

VIH(CA) High Level Input Voltage (CA0 to CA2) See Test Circuit 1 l0.85VCC V

RINH Resistance from CAn (

= 0,1,2)

to VCC to Set CA

= VCC

See Test Circuit 2 l10 k

RINL Resistance from CA

(

= 0,1,2)

to GND to Set CA

= GND

See Test Circuit 2 l10 k

RINF Resistance from CA

(

= 0,1,2)

to VCC or GND to Set CA

= FLOAT

See Test Circuit 2 l2M

VOL Low Level Output Voltage Sink Current = 3mA l0 0.4 V

tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX),

CB = 10pF to 400pF (Note 13)

l20+0.1CB250 ns

tSP Pulse Width of Spikes Suppressed by Input

Filter

l050ns

IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l1µA

CIN I/O Pin Capacitance (Note 9) l10 pF

CBCapacitance Load for Each Bus Line l400 pF

CCA

External Capacitive Load on Address Pins

CA0, CA1 and CA2

l10 pF

LTC2655

2655f

ELECTRICAL CHARACTERISTICS

LTC2655B-L16/LTC2655-L12/LTC2655B-H16/LTC2655-H12

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

AC Performance

tsSettling Time ( Note 10) ±0.024%(±1LSB at 12 Bits)

±0.0015%(±1LSB at 16 Bits)

3.9

9.1

µs

Settling Time for 1LSB Step ±0.024%(±1LSB at 12 Bits)

±0.0015%(±1LSB at 16 Bits)

2.4

4.5

µs

Voltage Output Slew Rate 1.8 V/µs

Capacitive Load Driving 1000 pF

Glitch Impulse (Note 11) At Mid-Scale Transition, -L Option 4 nV•s

At Mid-Scale Transition, -H Option 7 nV•s

DAC to DAC Crosstalk (Note 12) CREFCOMP = CREFIN/OUT = 0.22µF 0.5 nV•s

Multiplying Bandwidth 150 kHz

enOutput Voltage Noise Density At f = 1kHz

At f = 10kHz

nV/√Hz

Output Voltage Noise 0.1Hz to 10Hz, Internal Reference (-L Options)

0.1Hz to 10Hz, Internal Reference (-H Options)

0.1Hz to 200KHz, Internal Reference (-L Options)

0.1Hz to 200KHz, Internal Reference (-H Options)

400

450

µVP-P

TIMING CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V to 5.5V (LTC2655B-L16/LTC2655-L12), VCC = 4.5V to 5.5V (LTC2655B-H16,

LTC2655-H12), VOUT unloaded unless otherwise speciﬁ ed.

LTC2655B-L16/LTC2655-L12/LTC2655B-H16/LTC2655-H12 (see Figure 1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSCL SCL Clock Frequency l0 400 kHz

tHD(STA) Hold Time (Repeated) Start Condition l0.6 µs

tLOW Low Period of the SCL Clock Pin l1.3 µs

tHIGH High Period of the SCL Clock Pin l0.6 µs

tSU(STA) Set-Up Time for a Repeated Start Program l0.6 µs

tHD(DAT) Data Hold Time l0 0.9 µs

tSU(DAT) Data Set-Up Time l100 ns

tr Rise Time of Both SDA and SCL Signals (Note 13) l20+0.1CB300 ns

tf Fall Time of Both SDA and SCL Signals (Note 13) l20+0.1CB300 ns

tSU(STO) Set-Up Time for Stop Condition l0.6 µs

tBUF Bus Free Time Between a Stop and Start Condition l1.3 µs

t1 Falling edge of the 9th Clock of the 3rd Input Byte

to LDAC High or Low Transition

l400 ns

t2 LDAC Low Pulse Width l20 ns

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V to 5.5V (LTC2655B-L16/LTC2655-L12), VCC = 4.5V to 5.5V

(LTC2655B-H16, LTC2655-H12), VOUT unloaded unless otherwise speciﬁ ed.

LTC2655

2655f

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltages are with respect to GND.

Note 3: Linearity and monotonicity are deﬁ ned from code kL to code 2N–1,

where N is the resolution and kL is the lower end code for which no output

limiting occurs. For VREF = 2.5V and N = 16, kL = 128 and linearity is

deﬁ ned from code 128 to code 65535. For VREF = 2.5V and N = 12, kL =8

and linearity is deﬁ ned from code 8 to code 4095.

Note 4: Inferred from measurement at code 128 (LTC2655-16), or code 8

(LTC2655-12).

Note 5: DC Crosstalk is measured with VCC = 5V and using internal

reference, with the measured DAC at mid-scale.

Note 6: This IC includes current limiting that is intended to protect the

device during momentary overload conditions. Junction temperature can

exceed the rated maximum during current limiting. Continuous operation

above the speciﬁ ed maximum operating junction temperature may impair

device reliability.

Note 7: Temperature coefﬁ cient is calculated by dividing the maximum

change in output voltage by the speciﬁ ed temperature range. Maximum

temperature coefﬁ cient is guaranteed for C-grade only.

Note 8: Digital inputs at 0V or VCC.

Note 9: Guaranteed by design and not production tested.

Note 10: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale

and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.

Note 11: VCC = 5V (-H Options) or VCC = 3V (-L Options), internal

reference mode. DAC is stepped ±1 LSB between half-scale and

half-scale – 1. Load is 2k n parallel with 200pF to GND.

Note 12: DAC to DAC Crosstalk is the glitch that appears at the output

of one DAC due to a full scale change at the output of another DAC. It is

measured with VCC = 5V and using internal reference, with the measured

DAC at mid-scale.

Note 13: CB = Capacitance of one bus line in pF.

Note 14: Gain error speciﬁ cation may be degraded for reference input

voltages less than 1V. See Gain Error vs Reference Input Curve in the

Typical Performance Characteristics section.

ELECTRICAL CHARACTERISTICS

LTC2655

2655f

DNL vs Temperature

REFIN/OUT Output Voltage

vs Temperature

Settling to ±1LSB Rising Settling to ±1LSB Falling

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

INL vs Temperature

CODE

128

INL (LSB)

–2

–3

–1

–4 32768 4915216384

2655 G01

65535

VCC = 3V

CODE

128

DNL (LSB)

1.0

–0.5

0.5

–1.0 32768 4915216384

2655 G02

65535

VCC = 3V

TEMPERATURE (°C)

–50

INL (LSB)

–2

–1

–3

–4 503010 1109070–10–30

2655 G03

130

VCC = 3V

INL(POS)

INL(NEG)

TEMPERATURE (°C)

–50

DNL (LSB)

1.0

–0.5

0.5

–1.0 503010 1109070–30 –10

2655 G04

130

VCC = 3V

DNL(POS)

DNL(NEG)

TEMPERATURE (°C)

–50

VREF (V)

1.253

1.248

1.249

1.252

1.251

1.250

1.247 503010 1109070–30 –10

2655 G05

130

VCC = 3V

2µs/DIV

VOUT

250µV/DIV

SCL

3V/DIV

2655 G06

9TH CLOCK OF

3RD DATA BYTE

7.8µs

1/4 SCALE TO

3/4 SCALE STEP

VCC = 3V, VFS = 2.50V

2µs/DIV

VOUT

200µV/DIV

SCL

3V/DIV

2655 G07

9TH CLOCK OF

3RD DATA BYTE

7.3µs

3/4 SCALE TO

1/4 SCALE STEP

VCC = 3V, VFS = 2.50V

RL = 2k, CL = 200pF

AVERAGE OF 2048 EVENTS

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C unless otherwise noted.

LTC2655-L16

LTC2655

2655f

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C unless otherwise noted.

LTC2655-H16

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

CODE

128

INL (LSB)

–2

–1

–3

–4 32768 4915216384

2655 G08

65535

VCC = 5V

CODE

128

DNL (LSB)

1.0

–0.5

0.5

–1.0 32768 4915216384

2655 G09

65535

VCC = 5V

Settling to ±1LSB Rising Settling to ±1LSB Falling

2µs/DIV

VOUT

250µV/DIV

SCL

5V/DIV

2655 G13

9TH CLOCK OF

3RD DATA BYTE

7.9µs

1/4 SCALE TO

3/4 SCALE STEP

VCC = 5V, VFS = 4.096V

RL = 2k, CL = 200pF

2µs/DIV

VOUT

250µV/DIV

SCL

5V/DIV

2655 G14

9TH CLOCK OF

3RD DATA BYTE

5.5µs

3/4 SCALE TO

1/4 SCALE STEP

VCC = 5V, VFS = 4.096V

RL = 2k, CL = 200pF

INL vs Temperature DNL vs Temperature

Reference Output Voltage

vs Temperature

TEMPERATURE (°C)

–50

INL (LSB)

–2

–1

–3

–4 503010 1109070–10–30

2655 G10

130

VCC = 3V

INL(POS)

INL(NEG)

TEMPERATURE (°C)

–50

DNL (LSB)

1.0

–0.5

0.5

–1.0 503010 1109070–30 –10

2655 G11

130

VCC = 3V

DNL(POS)

DNL(NEG)

TEMPERATURE (°C)

–50

VREF (V)

2.054

2.044

2.046

2.052

2.050

2.048

2.042 503010 1109070–30 –10

2655 G12

130

VCC = 5V

LTC2655

2655f

TYPICAL PERFORMANCE CHARACTERISTICS

Current Limiting Headroom at Rails

vs Output Current

Offset Error vs Temperature

Integral Nonlinearity (INL) Differential Nonlinearity (INL) Settling to ±1LSB Falling

Load Regulation

CODE

INL (LSB)

1.0

–0.5

0.5

–1.0 2048 30721024

2655 G15

4095

VCC = 5V

VREF = 2.048V

CODE

DNL (LSB)

1.0

–0.5

0.5

–1.0 2048 30721024

2655 G16

4095

VCC = 3V

VREF = 1.25V

2µs/DIV

VOUT

1mV/DIV

SCL

3V/DIV

2655 G17

4.0µs

3/4 TO 1/4 SCALE STEP

VCC = 3V, VFS = 2.5V

RL = 2k, CL = 200pF

AVERAGE OF 2048 EVENTS

IOUT (mA)

–50

$VOUT (mV)

–6

–8

–4

–2

–10 0–10–20 30 402010–40 –30

2655 G18

INTERNAL REF

CODE = MID-SCALE

VCC = 5V (LTC2655-H)

VCC = 3V (LTC2655-L)

IOUT (mA)

–50

∆VOUT (V)

0.20

–0.10

–0.15

–0.05

0.15

0.10

0.05

–0.20 0–10–20 30 402010–40 –30

2655 G19

INTERNAL REF

CODE = MID-SCALE

VCC = 5V (LTC2655-H)

VCC = 3V (LTC2655-L)

IOUT (mA)

VOUT (V)

5.0

1.0

0.5

1.5

2.0

4.5

4.0

3.5

3.0

2.5

0543897612

2655 G20

5V (LTC2655-H) SOURCING

3V (LTC2655-L) SOURCING

5V (LTC2655-H) SINKING

3V (LTC2655-L) SINKING

TEMPERATURE (°C)

–50

OFFSET ERROR (mV)

–2

–1

–3 503010 1109070–30 –10

2655 G21

130

TA = 25°C unless otherwise noted.

LTC2655-12

LTC2655

Zero-Scale Error vs Temperature Gain Error vs Temperature

TEMPERATURE (°C)

–50

ZERO-SCALE ERROR (mV)

3.0

2.0

0.5

2.5

1.5

1.0

0503010 1109070–30 –10

2655 G22

130

TEMPERATURE (°C)

–50

GAIN ERROR (LSB)

–48

–32

–16

–64 503010 1109070–30 –10

2655 G23

130

LTC2655-16

LTC2655

2655f

TYPICAL PERFORMANCE CHARACTERISTICS

Offset Error vs Reference Input

REFERENCE VOLTAGE (V)

0.5

OFFSET ERROR (mV)

2.0

–1.0

–1.5

–0.5

1.5

1.0

0.5

–2 21 1.5

2655 G24

2.5

VCC = 5V

OFFSET ERROR OF 4 CHANNELS

TA = 25°C unless otherwise noted.

LTC2655

Supply Current vs Temperature ICC Shutdown vs Temperature

Multiplying Bandwidth

TEMPERATURE (°C)

–50

SUPPLY CURRENT (mA)

3.0

2.0

2.5

1.5

1.0 503010 1109070–30 –10

2655 G28

130

LTC2655-H

VCC = 5V, CODE = MS

INTERNAL REFERENCE

LTC2655-L

VCC = 3V, CODE = MS

INTERNAL REFERENCE

TEMPERATURE (°C)

–50

ICC SHUTDOWN (µA)

0503010 1109070–30 –10

2655 G29

130

LTC2655-H

VCC = 5V

LTC2655-L

VCC = 3V

FREQUENCY (Hz)

AMPLITUDE (dB)

2655 G30

–2

–4

–6

–8

–10

–121k 100k 1M10k

VS = 5V

VREF(DC) = 2V

VREF(AC) = 0.2VP-P

CODE = FULL-SCALE

Gain Error vs Reference Input ICC Shutdown vs VCC

Supply Current vs Logic Voltage

REFERENCE VOLTAGE (V)

0.5

GAIN ERROR (LSB)

–32

–48

–16

–64 21 1.5

2655 G25

2.5

LTC2655-16

VCC = 5.5V

GAIN ERROR OF 4 CHANNELS

VCC (V)

2.5

ICC (nA)

450

150

100

200

400

350

300

250

053.53 4.54

2655 G26

5.5

LOGIC VOLTAGE (V)

ICC (mA)

2.6

1.6

2.4

2.2

2.0

1.8

1.4 2143

2655 G27

SWEEP SCL AND SDA

BETWEEN

0V AND VCC

VCC = 3V

(LTC2655-L)

VCC = 5V

(LTC2655-H)

Large-Signal Response Mid-Scale Glitch Impulse

2µs/DIV

VOUT

1V/DIV

2655 G31

VCC = 5V, VREF = 2.048V

ZERO-SCALE TO FULL-SCALE

2µs/DIV

VOUT

5mV/DIV

SCL

5V/DIV

2655 G32

LTC2655-H16, VCC = 5V

7nV-s TYP

LTC2655-L16, VCC = 3V

4nV-s TYP

9TH CLOCK OF

3RD DATA BYTE

LTC2655

2655f

TYPICAL PERFORMANCE CHARACTERISTICS

DAC Output 0.1Hz to

10Hz Voltage Noise

Reference 0.1Hz to

10Hz Voltage Noise

DAC to DAC Crosstalk (Dynamic) Power-On Reset Glitch

Power-On Reset to Mid-Scale Noise Voltage vs Frequency

2µs/DIV

VOUT

0.5mV/DIV

ONE DAC

SWITCH 0-FS

1V/DIV

2655 G33

LTC2655-L16, VCC = 5V, 0.4nV•s TYP

CREFCOMP = CREFOUT = 0.22µF

200µs/DIV

VOUT

10mV/DIV

VCC

2V/DIV

2655 G34

ZERO-SCALE

1ms/DIV

VOUT

1V/DIV

VCC

2V/DIV

2655 G35

LTC2655-L

FREQUENCY (Hz)

NOISE VOLTAGE (nV/√Hz)

2655 G36

400

300

200

100

010 100 100k 1M10k1k

VCC = 5V

CODE = MID-SCALE

INTERNAL REF

CREFCOMP = CREFOUT = 0.1µF

LTC2655-H

LTC2655-L

1s/DIV

5µV/DIV

2655 G37

VCC = 5V, LTC2655-H

CODE = MID-SCALE

INTERNAL REF

CREFCOMP = CREFOUT = 0.1µF

1s/DIV

2µV/DIV

2655 G38

VREFOUT = 2.048V

CREFCOMP = CREFOUT = 0.1µF

TA = 25°C unless otherwise noted.

LTC2655

2655f

PIN FUNCTIONS

REFLO (Pin 1/Pin 20): Reference Low. The voltage at this

pin sets the zero-scale voltage of all DACs. This pin should

be tied to GND.

VOUTA to VOUTD (Pins 2,4,13,14/Pins 1, 3, 13, 14): DAC

Analog Voltage Outputs. The output range is 0V to 2 times

the voltage at the REFIN/OUT pin.

REFCOMP (Pin 3/Pin 2): Internal Reference Compensation.

For low noise and reference stability, tie 0.1µF capacitor

to GND. Connect to GND to use an external reference at

start-up. Command 0111b must still be issued to turn off

internal reference.

REFIN/OUT (Pin 5/Pin 4): This pin acts as the internal

reference output in internal reference mode and acts as

the reference input pin in external reference mode. When

acting as an output the nominal voltage at this pin is

1.25V for -L options and 2.048V for -H options. For low

noise and reference stability tie a capacitor from this pin

to GND. Capacitor value must be ≤ CREFCOMP. In external

reference mode, the allowable reference input voltage

range is 0.5V to VCC/2.

LDAC (Pin 6/Pin 5): Asynchronous DAC Update. A fall-

ing edge on this input after four bytes have been written

into the part, immediately updates the DAC register with

the contents of the input register. A low on this input

without a complete 32-bit (four bytes including the slave

address) data write transfer to the part does not update

the DAC output. Software power-down is disabled when

LDAC is low.

CA2 (Pin 7/Pin 6): Chip Address Bit 2. Tie this pin to VCC,

GND or leave it ﬂ oating to select an I2C slave address for

the part (Table 2).

SCL (Pin 8/Pin 7): Serial Clock Input. Data is shifted

into the SDA pin at the rising edges of the clock. This

high impedance pin requires a pull-up resistor or current

source to VCC.

SDA (Pin 9/Pin 9): Serial Data Bidirectional. Data is shifted

into the SDA pin and acknowledged by the SDA pin. This is

a high impedance pin while data is shifted in. It is an open-

drain N-channel output during acknowledgement. This pin

requires a pull-up resistor or current source to VCC.

CA1 (Pin 10/Pin 10): Chip Address Bit 1. Tie this pin to

VCC, GND or leave it ﬂ oating to select an I2C slave address

for the part (Table 2).

CA0 (Pin 11/Pin 11): Chip Address Bit 0. Tie this pin to

VCC, GND or leave it ﬂ oating to select an I2C slave address

for the part (Table 2).

PORSEL (Pin 12/Pin 12): Power-On-Reset Select. If tied

to GND, the part resets to zero-scale at power-up, if tied

to VCC, the part resets to mid-scale.

VCC (Pin 15/Pin 18): Supply Voltage Input. For -L options,

2.7V ≤ VCC ≤ 5.5V, and for -H options, 4.5V ≤ VCC ≤ 5.5V.

Bypass to ground with a 0.1µF capacitor placed as close

to pin as possible.

GND (Pin 16/Pin 19, Exposed Pad Pin 21): Ground. Must

be soldered to PCB Ground.

DNC (NA/Pins 8, 15, 16, 17): Do not connect these

pins.

(GN/UF)

LTC2655

2655f

BLOCK DIAGRAM

2655 BD

GND

VOUTA

VOUTB

SCL

CA2

LDAC

REFLO

CA1

CA0

REFIN/OUT

REFCOMP

VCC

VOUTD

VOUTC

PORSEL

SDA

INTERNAL REFERENCE

DAC A

POWER-ON

RESET

DAC B

DAC D

DAC C

32-BIT SHIFT REGISTER

2-WIRE INTERFACE

REGISTERREGISTER

LTC2655

2655f

TIMING DIAGRAM

Figure 1

VIH(CAn)/VIL(CAn)

CAn

100

2655 TC01

GND

RINH/RINL/RINF

VDD

2655 TC02

Test Circuit 1

Test Circuit 2

TEST CIRCUITS

SDA

tLOW

tHD(STA)

ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS

tHD(DAT)

tSU(DAT)

tSU(STA)

tHD(STA)

tSU(STO)

tSP tBUF

tHIGH

SCL

S P S

2655 F01

9TH CLOCK

OF 3RD

DATA BYTE

SCL

LDAC

LTC2655

2655f

The LTC2655 is a family of quad voltage output DACs in

20-lead 4mm × 4mm QFN and in 16-lead narrow SSOP

packages. Each DAC can operate rail-to-rail in external

reference mode, or with its full-scale voltage set by an

integrated reference. Four combinations of accuracy (16-bit

and 12-bit), and full-scale voltage (2.5V or 4.096V) are

available. The LTC2655 is controlled using a 2-wire I2C

compatible interface.

Power-On Reset

The LTC2655-L/LTC2655-H clear the output to zero-scale

if PORSEL pin is tied to GND, when power is ﬁ rst applied,

making system initialization consistent and repeatable. For

some applications, downstream circuits are active during

DAC power-up, and may be sensitive to nonzero outputs

from the DAC during this time. The LTC2655 contains

circuitry to reduce the power-on glitch. The analog outputs

typically rise less than 10mV above zero-scale during power

on if the power supply is ramped to 5V in 1ms or more.

In general, the glitch amplitude decreases as the power

supply ramp time is increased. See Power-On Reset Glitch

in the Typical Performance Characteristics section.

Alternatively, if PORSEL pin is tied to VCC, The LTC2655-L/

LTC2655-H set the output to mid-scale when power is

ﬁ rst applied.

Power Supply Sequencing and Start-Up

For the LTC2655 family of parts, the internal reference is

powered up at start-up by default. If an external reference

is to be used, REFCOMP (Pin 3/Pin 2, GN/UF) must be

hardwired to GND. This conﬁ guration allows the use of an

external reference at start-up and converts the REFIN/OUT

pin to an input. However, the internal reference will still be

ON and draw supply current. In order to use an external

reference, command 0111b should be used to turn the

internal reference off (see Table 1).

The voltage at REFIN/OUT (Pin 5/Pin 4, GN/UF) should be

kept within the range – 0.3V ≤ REFIN/OUT ≤ VCC + 0.3V

(see the Absolute Maximum Ratings section). Particular

care should be taken to observe these limits during power

supply turn-on and turn-off sequences, when the voltage

at VCC (Pin 15/Pin 18, GN/UF) is in transition.

Transfer Function

The digital-to-analog transfer function is

OUT(IDEAL) = 2 • k/2N [VREF – REFLO] + REFLO

where k is the decimal equivalent of the binary DAC input

code, N is the resolution, and VREF is the voltage at the

REFIN/OUT Pin. The resulting DAC output span is 0V to

2•VREF, as it is necessary to tie REFLO to GND. VREF is

nominally 1.25V for LTC2655-L and 2.048V for LTC2655-H,

in internal reference mode.

Table 1

COMMAND*

C3 C2 C1 C0

0 0 0 0 Write to Input Register

0 0 0 1 Update (Power-Up) DAC Register

0 0 1 0 Write to Input Register

, Update (Power-Up) All

0 0 1 1 Write to and Update (Power-Up)

0 1 0 0 Power-Down

0 1 0 1 Power-Down Chip (All DAC’s and Reference)

0 1 1 0 Select Internal Reference (Power-Up Reference)

0 1 1 1 Select External Reference (Power-Down Reference)

1 1 1 1 No Operation

ADDRESS (

A3 A2 A1 A0

0 0 0 0 DAC A

0 0 0 1 DAC B

0 0 1 0 DAC C

0 0 1 1 DAC D

1 1 1 1 All DACs

* Command and address codes not shown are reserved and should not

be used.

Serial Interface

The LTC2655 communicates with a host using the stan-

dard 2-wire I2C interface. The Timing Diagram (Figure 1)

shows the timing relationship of the signals on the bus.

The two bus lines, SDA and SCL, must be high when the

bus is not in use. External pull-up resistors or current

sources are required on these lines. The value of these

pull-up resistors is dependent on the power supply and

can be obtained from the I2C speciﬁ cations. For an I2C

bus operating in the fast mode, an active pull-up will be

OPERATION

LTC2655

2655f

necessary if the bus capacitance is greater than 200pF.

The LTC2655 is a receive-only (slave) device. The master

can write to the LTC2655. The LTC2655 does not respond

to a read command from the master.

The START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be high.

A bus master signals the beginning of a communication

to a slave device by transmitting a START condition (see

Figure 1). A START condition is generated by transitioning

SDA from high to low while SCL is high. When the master

has ﬁ nished communicating with the slave, it issues a STOP

condition. A STOP condition is generated by transitioning

SDA from low to high while SCL is high. The bus is then

free for communication with another I2C device.

Acknowledge

The Acknowledge signal is used for handshaking between

the master and the slave. An Acknowledge (active LOW)

generated by the slave lets the master know that the lat-

est byte of information was received. The Acknowledge

related clock pulse is generated by the master. The master

releases the SDA line (HIGH) during the Acknowledge

clock pulse. The slave-receiver must pull down the SDA

bus line during the Acknowledge clock pulse so that it

remains a stable LOW during the HIGH period of this clock

pulse. The LTC2655 responds to a write by a master in

this manner. The LTC2655 does not acknowledge a read

(retains SDA HIGH during the period of the Acknowledge

clock pulse).

Chip Address

The state of CA0, CA1 and CA2 decides the slave address

of the part. The pins CA0, CA1 and CA2 can be each set

to any one of three states: VCC, GND or ﬂ oat. This results

in 27 selectable addresses for the part. The slave address

assignments are shown in Table 2.

In addition to the address selected by the address pins,

the parts also respond to a global address. This address

allows a common write to all LTC2655 parts to be accom-

plished with one 3-byte write transaction on the I2C bus.

The global address is a 7-bit on-chip hardwired address

and is not selectable by CA0, CA1 and CA2. The addresses

corresponding to the states of CA0, CA1 and CA2 and

the global address are shown in Table 2. The maximum

capacitive load allowed on the address pins (CA0, CA1

and CA2) is 10pF, as these pins are driven during address

detection to determine if they are ﬂ oating.

Table 2. Slave Address Map

CA2 CA1 CA0 A6 A5 A4 A3 A2 A1 A0

GND GND GND 0 0 1 0 0 0 0

GND GND FLOAT 0 0 1 0 0 0 1

GND GND VCC 0010010

GND FLOAT GND 0 0 1 0 0 1 1

GND FLOAT FLOAT 0 1 0 0 0 0 0

GND FLOAT VCC 0100001

GND VCC GND 0 1 0 0 0 1 0

GND VCC FLOAT 0 1 0 0 0 1 1

GND VCC VCC 0110000

FLOAT GND GND 0 1 1 0 0 0 1

FLOAT GND FLOAT 0 1 1 0 0 1 0

FLOAT GND VCC 0110011

FLOAT FLOAT GND 1 0 0 0 0 0 0

FLOAT FLOAT FLOAT 1 0 0 0 0 0 1

FLOAT FLOAT VCC 1000010

FLOAT VCC GND 1 0 0 0 0 1 1

FLOAT VCC FLOAT 1 0 1 0 0 0 0

FLOAT VCC VCC 1010001

VCC GND GND 1 0 1 0 0 1 0

VCC GND FLOAT 1 0 1 0 0 1 1

VCC GND VCC 1100000

VCC FLOAT GND 1 1 0 0 0 0 1

VCC FLOAT FLOAT 1 1 0 0 0 1 0

VCC FLOAT VCC 1100011

VCC VCC GND 1 1 1 0 0 0 0

VCC VCC FLOAT 1 1 1 0 0 0 1

VCC VCC VCC 1110010

GLOBAL ADDRESS 1 1 1 0 0 1 1

OPERATION

LTC2655

2655f

OPERATION

Write Word Protocol

The master initiates communication with the LTC2655

with a START condition and a 7-bit slave address followed

by the Write bit (W) = 0. The LTC2655 acknowledges by

pulling the SDA pin low at the 9th clock if the 7-bit slave

address matches the address of the part (set by CA0, CA1

and CA2) or the global address. The master then transmits

three bytes of write data. The LTC2655 acknowledges each

byte of data by pulling the SDA line low at the 9th clock of

each data byte transmission. After receiving three com-

plete bytes of data, the LTC2655 executes the command

speciﬁ ed in the 24-bit input word. If more than three data

bytes are transmitted after a valid 7-bit slave address, the

LTC2655 does not acknowledge the extra bytes of data

(SDA is high during the 9th clock). The ﬁ rst byte of the

input word consists of the 4-bit command followed by

the 4-bit address. The next two bytes consist of the 16-bit

data word. The 16-bit data word consists of the 16-bit, or

12-bit input code, MSB to LSB, followed by 0 or 4 don’t

care bits (LTC2655-16 and LTC2655-12 respectively). A

typical LTC2655 write transaction is shown in Figure 2.

The command (C3-C0) and address (A3-A0) assignments

are shown in Table 1. The ﬁ rst four commands in the table

consist of write and update operations. A write operation

loads a 16-bit data word from the 32-bit shift register into

the input register. In an update operation, the data word

is copied from the input register to the DAC register and

converted to an analog voltage at the DAC output. The

update operation also powers up the DAC if it had been in

power-down mode. The data path and registers are shown

in the Block Diagram.

Power-Down Mode

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever less

than four outputs are needed. When in power-down, the

buffer ampliﬁ ers, bias circuits and integrated reference

circuits are disabled, and draw essentially zero current.

The DAC outputs are put into a high-impedance state, and

the output pins are passively pulled to ground through

individual 80k resistors. Input- and DAC-register contents

are not disturbed during power-down.

Any channel or combination of channels can be put into

power-down mode by using command 0100b in combina-

tion with the appropriate DAC address, (

). The integrated

reference is automatically powered down when external

reference mode is selected using command 0111b. In ad-

dition, all the DAC channels and the integrated reference

together can be put into power-down mode using the

Power-Down Chip command 0101b. For all power-down

commands the 16-bit data word is ignored, but still required

in order to complete a full communication cycle.

Normal operation resumes by executing any command

which includes a DAC update, in software as shown in

Table 1 or using the asynchronous LDAC pin. The selected

DAC is powered up as its voltage output is updated. When

a DAC which is in a powered-down state is powered up and

updated, normal settling is delayed. If less than four DACs

are in a powered-down state prior to the update command,

the power-up delay time is approximately 12s. If on the

other hand, all four DACs and the integrated reference

are powered down, then the main bias generation circuit

block has been automatically shut down in addition to the

individual DAC ampliﬁ ers and the integrated reference.

LTC2655

2655f

In this case, the power-up delay time is approximately

14s. The power-up of the integrated reference depends

on the command that powered it down. If the reference is

powered down using the Select External Reference com-

mand (0111b), then it can only be powered back up by

sending the Select Internal Reference command (0110b).

However if the reference was powered down by sending

the Power-Down Chip command (0101b), then in addition

to the Select Internal Reference command (0110b), any

command that powers up the DACs will also power-up

the integrated reference.

Reference Modes

For applications where an accurate external reference is

not available, the LTC2655 has a user-selectable, inte-

grated reference. The LTC2655-L has a 1.25V reference

that provides a full-scale output of 2.5V. The LTC2655-H

has a 2.048V reference that provides a full-scale output

of 4.096V. Both references exhibit a typical temperature

drift of 2ppm/°C. Internal reference mode can be selected

by using command 0110b, and is the power-on default. A

buffer is needed if the internal reference is required to drive

external circuitry. For reference stability and low noise, it

is recommended that a 0.1µF capacitor be tied between

REFCOMP and GND. In this conﬁ guration, the internal

reference can drive up to 0.1µF capacitive load without any

stability problems. In order to ensure stable operation, the

capacitive load on the REFIN/OUT pin should not exceed

the capacitive load on the REFCOMP pin.

The DAC can also operate in external reference mode using

command 0111b. In this mode, the REFIN/OUT pin acts

as an input that sets the DAC’s reference voltage. This

input is high impedance and does not load the external

reference source. The acceptable voltage range at this

pin is 0.5V ≤ REFIN/OUT ≤ VCC/2. The resulting full-scale

output voltage is 2•VREFIN/OUT. For using external refer-

ence at start-up, see the Power Supply Sequencing and

Start-Up Sections.

Integrated Reference Buffers

Each of the four DACs in LTC2655 has its own integrated

high performance reference buffer. The buffers have very

high input impedance and do not load the reference volt-

age source. These buffers shield the reference voltage

from glitches caused by DAC switching and thus minimize

DAC-to-DAC dynamic crosstalk. By tying 0.22F capacitors

between REFCOMP and GND, and also between REFIN/OUT

and GND, the crosstalk can be reduced to less than 1nV•s.

See the curve DAC-to-DAC Crosstalk (Dynamic) in the

Typical Performance Characteristics section.

Voltage Outputs

Each of the four rail-to-rail ampliﬁ ers contained in LTC2655

has guaranteed load regulation when sourcing or sinking

up to 15mA at 5V (7.5mA at 3V).

Load regulation is a measure of the ampliﬁ er’s ability to

maintain the rated voltage accuracy over a wide range of

load conditions. The measured change in output voltage

per milliampere of forced load current change is expressed

in LSB/mA.

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change in

units from LSB/mA to ohms. The ampliﬁ ers’ DC output

impedance is 0.040 when driving a load well away from

the rails.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by

the 30 typical channel resistance of the output devices;

e.g., when sinking 1mA, the minimum output voltage =

30 • 1mA = 30mV. See the graph Headroom at Rails vs

Output Current in the Typical Performance Characteristics

section.

The ampliﬁ ers are stable driving capacitive loads of up

to 1000pF.

OPERATION

LTC2655

2655f

Board Layout

The excellent load regulation and DC crosstalk performance

of these devices is achieved in part by keeping signal and

power grounds separate.

The PC board should have separate areas for the analog

and digital sections of the circuit. This keeps digital signals

away from sensitive analog signals and facilitates the use

of separate digital and analog ground planes which have

minimal capacitive and resistive interaction with each

other.

Digital and analog ground planes should be joined at only

one point, establishing a system star ground as close to

the device’s ground pin as possible. Ideally, the analog

ground plane should be located on the component side of

the board, and should be allowed to run under the part to

shield it from noise. Analog ground should be a continuous

and uninterrupted plane, except for necessary lead pads

and vias, with signal traces on another layer.

The GND pin functions as a return path for power supply

currents in the device and should be connected to analog

ground. The REFLO pin should be connected to system

star ground. Resistance from the REFLO pin to system

star ground should be as low as possible.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is limited

to voltages within the supply range.

Since the analog outputs of the device cannot go below

ground, they may limit for the lowest codes as shown in

Figure 3b. Similarly, limiting can occur in external refer-

ence mode near full scale when the REFIN/OUT pin is at

VCC/2. If VREFIN/OUT = VCC/2 and the DAC full-scale error

(FSE) is positive, the output for the highest codes limits

at VCC as shown in Figure 3c. No full-scale limiting can

occur if VREFIN/OUT ≤ (VCC – FSE)/2.

Offset and linearity are deﬁ ned and tested over the region

of the DAC transfer function where no output limiting can

occur.

OPERATION

LTC2655

2655f

OPERATION

Figure 2. Typical LTC2655 Input Waveform—Programming DAC Output for Full-Scale

ACK ACK

123456789123456789123456789123456789

2655 F02

ACK

START STOP

FULL-SCALE

VOLTAGE

ZERO-SCALE

VOLTAGE

SDA SA6 SA5 SA4 SA3 SA2 SA1 SA0

SCL

VOUT

C2C3

C3 C2 C1 C0 A3 A2 A1 A0

C1 C0 A3 A2 A1 A0 ACK

COMMAND

D15 D14 D13 D12 D11 D10 D9 D8

MS DATA

D7 D6 D5 D4 D3 D2 D1 D0

LS DATA

SA6 SA5 SA4 SA3 SA2 SA1 SA0 WR

SLAVE ADDRESS

LTC2655

2655f

OPERATION

2655 F03

INPUT CODE

(b)

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

32, 7680 65, 535

INPUT CODE

OUTPUT

VOLTAGE

(a)

VREF = VCC

(c)

INPUT CODE

OUTPUT

VOLTAGE

POSITIVE

FSE

Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function,

(b) Effect of Negative Offset for Codes Near Zero-Scale, (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale

LTC2655

2655f

PACKAGE DESCRIPTION

GN Package

16-Lead Plastic SSOP

(Reference LTC DWG # 05-08-1641)

GN16 (SSOP) 0204

345678

.229 – .244

(5.817 – 6.198)

.150 – .157**

(3.810 – 3.988)

16 15 14 13

.189 – .196*

(4.801 – 4.978)

12 11 10 9

.016 – .050

(0.406 – 1.270)

.015 ± .004

(0.38 ± 0.10) × 45°

0° – 8° TYP

.007 – .0098

(0.178 – 0.249)

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

.004 – .0098

(0.102 – 0.249)

.0250

(0.635)

BSC

.009

(0.229)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 – .165

.0250 BSC.0165 ±.0015

.045 ±.005

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

LTC2655

2655f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

UF Package

20-Lead (4mm × 4mm) Plastic QFN

(Reference LTC DWG # 05-08-1710 Rev A)

4.00 ± 0.10

NOTE:

1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220

VARIATION (WGGD-1)—TO BE APPROVED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

2019

BOTTOM VIEW—EXPOSED PAD

2.00 REF

2.45 ± 0.10

0.75 ± 0.05 R = 0.115

TYP

R = 0.05

TYP

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UF20) QFN 01-07 REV A

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

0.25 ±0.05

0.50 BSC

2.00 REF 2.45 ± 0.05

3.10 ± 0.05

4.50 ± 0.05

PACKAGE OUTLINE

PIN 1 NOTCH

R = 0.20 TYP

OR 0.35 × 45°

CHAMFER

2.45 ± 0.10

2.45 ± 0.05

LTC2655

2655f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0710 • PRINTED IN USA

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2655 TA02

LDAC

GND GND REFLO

LTC2655IUF-L16*

PORSEL

*PIN NUMBERS SHOWN ARE FOR THE QFN PACKAGE.

VCC REFCOMP REFIN/OUT DNC DNC

DNC DNC

SCL

SDA

CA0

CA1

CA2

518 171624

MICROCONTROLLER

VOUTA

VOUTB

VOUTC

VOUTD

+5V

0.1µF

–

450k

150k

450k

50k

450k

4pF

450k

VOUT

±5V

4pF

–12V

+12V

LT1991

–

LTC6240IS5

+5V

19 21 20 12 8 15

VCC

VEE REF

±5V Bipolar Output DAC