The following document contains information on Cypress products. Although the document is marked with the name "Broadcom", the company that originally developed the specification, Cypress will continue to offer these products to new and existing customers. CONTINUITY OF SPECIFICATIONS There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. Future revisions will occur when appropriate, and changes will be noted in a document history page. CONTINUITY OF ORDERING PART NUMBERS Cypress continues to support existing part numbers. To order these products, please use only the Cypress Ordering Part Number listed in the table. Broadcom Ordering Part Number BCM20738A1KFBG BCM20738A2KML3G BCM20738A2KML3GT BCM20738A1KFBGT Cypress Ordering Part Number CYW20738A1KFBG CYW20738A2KML3G CYW20738A2KML3GT CYW20738A1KFBGT FOR MORE INFORMATION Please visit our website at www.cypress.com or contact your local sales office for additional information about Cypress products and services. OUR CUSTOMERS Cypress is for true innovators - in companies both large and small. Our customers are smart, aggressive, out-of-the-box thinkers who design and develop game-changing products that revolutionize their industries or create new industries with products and solutions that nobody ever thought of before. ABOUT CYPRESS Founded in 1982, Cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, home automation and appliances, consumer electronics and medical products. Cypress's programmable systems-on-chip, general-purpose microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and engineering resources on the planet enabling innovators and out-of-the-box thinkers to disrupt markets and create new product categories in record time. To learn more, go to www.cypress.com. Cypress Semiconductor Corporation Document Number: 002-14891 Rev. *B 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised October 17, 2016 Data Sheet BCM20738 Single-Chip Bluetooth Transceiver for Wireless Input Devices GE NE R AL DE S C RI PT ION (R) The Broadcom BCM20738 is a Bluetooth low energy compliant, stand-alone baseband processor with an integrated 2.4 GHz transceiver. It is ideal for wireless input device applications including game controllers, keyboards, remote controls, gestural input devices, and sensor devices. Built-in firmware adheres to the Bluetooth Human Interface Device (HID) profile and Bluetooth Device ID profile specifications. The BCM20738 radio has been designed to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with Bluetooth Low Energy Radio Specification. The single-chip Bluetooth transceiver is a monolithic component implemented in a standard digital CMOS process and requires minimal external components to make a fully compliant Bluetooth device. The BCM20738 is available in two package options: a 40pin, 6 mm x 6 mm QFN and a 64-pin, 7 mm x 7 mm BGA. F E A T U RE S * * * * * * * * * * * * * * * * A P P LIC AT IO N S * * * * * * Wireless pointing devices: mice, trackballs, gestural controls Wireless keyboards Remote controls Game controllers Point-of-sale (POS) input devices Remote sensors * * On-chip support for common keyboard and mouse interfaces eliminates external processor Programmable keyscan matrix interface, up to 8 x 20 key-scanning matrix 3-axis quadrature signal decoder Infrared modulator IR learning Supports Adaptive Frequency Hopping Excellent receiver sensitivity Bluetooth HID Over GATT profile 10-bit auxiliary ADC with 28 analog channels On-chip support for serial peripheral interface (master and slave modes) Broadcom Serial Communications (BSC) interface (compatible with Philips(R) (now NXP) I2C slaves) Integrated ARM CortexTM-M3 based microprocessor core On-chip power-on reset (POR) Support for EEPROM and serial flash interfaces Integrated low-dropout regulator (LDO) On-chip software controlled power management unit Two package types are available: - 40-pin QFN package (6 mm x 6 mm) - 64-pin BGA package (7 mm x 7 mm) RoHS compliant 20738-DS102-R 5300 California Avenue * Irvine, CA 92617 * Phone: 949-926-5000 * Fax: 949-926-5203 November 16, 2015 BCM20738 Data Sheet Revision History Figure 1: Functional Block Diagram Muxed on GPIO UART_TXD UART_RXD Tx RTS_N Rx CTS_N 1.2V VDD_CORE Domain WDT Processing Unit (ARM -CM3) SDA/ MOSI Test UART Periph 320K UART ROM 1.2V SCL/ SCK MISO BSC/SPI Master Interface (BSC is I2C compable) 60K RAM VDD_CORE VSS, VDDO, VDDC 28 ADC Inputs 1.2V 1.2V POR CT ADC 1.2V LDO 1.425V to 3.6V MIA POR System Bus 1.62V to 3.6V 32 kHz LPCLK Peripheral Interface Block hclk (24 MHz to 1 MHz) RF Control and Data 2.4 GHz Radio T/R Switch VDD_IO Domain I/O Ring Bus Bluetooth Baseband Core 24 MHz RF I/O I/O Ring Control Registers Volt. Trans GPIO Control/ Status Registers IR Mod. and Learning SPI M/S Keyboard Matrix Scanner w/FIFO 3 -Axis Mouse Signal Controller Frequency Synthesizer 1.2V VDD_RF Domain IR I/O 8 x 20 Scan Matrix 6 Quadrature Inputs (3 pair) + High Current Driver Controls 28 ADC Inputs 24 MHz Ref Xtal Power WAKE 40 GPIO AutoCal PMU PWM 40 GPIO on the 64-pin BGA (22 GPIO on the 40-pin QFN) 32 kHz LPCLK 128 kHz LPO 128 kHz LPCLK /4 32 kHzyZZ 1.62V to 3.6V VDD_IO Broadcom(R) November 16, 2015 * 20738-DS102-R Page 2 BROADCOM CONFIDENTIAL Revision History Revision Date Change Description 20738-DS102-D1 11/11/15 20738-DS101-R 05/21/14 20738-DS100-R 01/27/14 Updated: * Section 5: "Ordering Information," on page 49. Updated: * Unit in Equivalent series resistance in Table 5 on page 9. * Values in Table 14 on page 9. * RX sensitivity typical value in Table 16 on page 10. * "SPI Timing" on page 10 * Part number in Table 26: "Ordering Information," on page 10. * Removed: * IR_TX from Table 5: "Reference Crystal Electrical Specifications," on page 9. Initial release. Broadcom Corporation 5300 California Avenue Irvine, CA 92617 (c) 2015 by Broadcom Corporation All rights reserved Printed in the U.S.A. Broadcom(R), the pulse logo, Connecting everything(R), and the Connecting everything logo are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high-risk application. BROADCOM PROVIDES THIS DATA SHEET "AS-IS," WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. BCM20738 Data Sheet Revision History Broadcom(R) November 16, 2015 * 20738-DS102-R Page 4 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Table of Contents Table of Contents About This Document .................................................................................................................................. 9 Purpose and Audience ............................................................................................................................ 9 Acronyms and Abbreviations................................................................................................................... 9 References .............................................................................................................................................. 9 Technical Support ........................................................................................................................................ 9 Section 1: Functional Description ................................................................................... 10 Keyboard Scanner...................................................................................................................................... 10 Theory of Operation .............................................................................................................................. 10 Idle ................................................................................................................................................. 10 Scan ............................................................................................................................................... 10 Scan End........................................................................................................................................ 11 Mouse Quadrature Signal Decoder........................................................................................................... 11 Theory of Operation .............................................................................................................................. 11 Infrared Modulator...................................................................................................................................... 12 Infrared Learning ........................................................................................................................................ 12 Bluetooth Baseband Core ......................................................................................................................... 13 Frequency Hopping Generator.............................................................................................................. 13 E0 Encryption ........................................................................................................................................ 13 Link Control Layer ................................................................................................................................. 14 Adaptive Frequency Hopping ................................................................................................................ 14 Bluetooth Low Energy ........................................................................................................................... 14 Test Mode Support................................................................................................................................ 14 ADC Port...................................................................................................................................................... 14 Serial Peripheral Interface ......................................................................................................................... 15 Microprocessor Unit................................................................................................................................... 17 EEPROM Interface................................................................................................................................ 18 Serial Flash Interface ............................................................................................................................ 18 Internal Reset ........................................................................................................................................ 18 External Reset....................................................................................................................................... 19 Integrated Radio Transceiver .................................................................................................................... 19 Transmitter Path.................................................................................................................................... 19 Digital Modulator ............................................................................................................................ 19 Power Amplifier .............................................................................................................................. 19 Receiver Path........................................................................................................................................ 20 Digital Demodulator and Bit Synchronizer ..................................................................................... 20 Receiver Signal Strength Indicator................................................................................................. 20 Local Oscillator...................................................................................................................................... 20 Broadcom(R) November 16, 2015 * 20738-DS102-R Page 5 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Table of Contents Calibration ............................................................................................................................................. 20 Internal LDO Regulator ......................................................................................................................... 20 Peripheral Transport Unit .......................................................................................................................... 21 Broadcom Serial Communications Interface ......................................................................................... 21 UART Interface...................................................................................................................................... 21 Clock Frequencies...................................................................................................................................... 21 Crystal Oscillator ................................................................................................................................... 22 HID Peripheral Block...................................................................................................................... 22 32 kHz Crystal Oscillator................................................................................................................ 23 GPIO Port .................................................................................................................................................... 23 Port 0-Port 1, Port 8-Port 23, and Port 28-Port 38.............................................................................. 23 Port 26-Port 29 ..................................................................................................................................... 24 PWM............................................................................................................................................................. 24 Power Management Unit............................................................................................................................ 25 RF Power Management ........................................................................................................................ 25 Host Controller Power Management ..................................................................................................... 25 BBC Power Management...................................................................................................................... 26 Section 2: Pin Assignments ............................................................................................. 27 Pin Descriptions ......................................................................................................................................... 27 Ball Maps..................................................................................................................................................... 35 Section 3: Specifications .................................................................................................. 37 Electrical Characteristics........................................................................................................................... 37 RF Specifications ....................................................................................................................................... 40 Timing and AC Characteristics ................................................................................................................. 42 UART Timing......................................................................................................................................... 42 SPI Timing............................................................................................................................................. 42 BSC Interface Timing ............................................................................................................................ 45 Section 4: Mechanical Information .................................................................................. 46 Tape Reel and Packaging Specifications.............................................................................................. 48 Section 5: Ordering Information ...................................................................................... 49 Appendix A: Acronyms and Abbreviations .................................................................... 50 Broadcom(R) November 16, 2015 * 20738-DS102-R Page 6 BROADCOM CONFIDENTIAL BCM20738 Data Sheet List of Figures List of Figures Figure 1: Functional Block Diagram................................................................................................................... 2 Figure 2: Infrared TX ........................................................................................................................................ 12 Figure 3: Infrared RX ....................................................................................................................................... 13 Figure 4: Internal Reset Timing........................................................................................................................ 18 Figure 5: External Reset Timing ...................................................................................................................... 19 Figure 6: Recommended Oscillator Configuration--12 pF Load Crystal ........................................................ 22 Figure 7: 32 kHz Oscillator Block Diagram ...................................................................................................... 23 Figure 8: PWM Channel Block Diagram .......................................................................................................... 25 Figure 9: 40-pin QFN Ball Map ........................................................................................................................ 35 Figure 10: 64-pin BGA Ball Map ...................................................................................................................... 36 Figure 11: UART Timing .................................................................................................................................. 42 Figure 12: SPI Timing Diagram........................................................................................................................ 43 Figure 13: BSC Interface Timing Diagram ....................................................................................................... 45 Figure 14: 40-pin QFN Package ...................................................................................................................... 46 Figure 15: 64-pin FBGA Package .................................................................................................................... 47 Figure 16: Pin 1 Orientation ............................................................................................................................. 48 Broadcom(R) November 16, 2015 * 20738-DS102-R Page 7 BROADCOM CONFIDENTIAL BCM20738 Data Sheet List of Tables List of Tables Table 1: ADC Modes........................................................................................................................................ 14 Table 2: BCM20738 First SPI Set (Master Mode) ........................................................................................... 15 Table 3: BCM20738 Second SPI Set (Master Mode) ...................................................................................... 15 Table 4: BCM20738 Second SPI Set (Slave Mode) ........................................................................................ 16 Table 5: Reference Crystal Electrical Specifications ....................................................................................... 22 Table 6: XTAL Oscillator Characteristics ......................................................................................................... 23 Table 7: Pin Descriptions ................................................................................................................................. 27 Table 8: GPIO Pin Descriptions ....................................................................................................................... 29 Table 9: Maximum Electrical Rating ................................................................................................................ 37 Table 10: Power Supply................................................................................................................................... 37 Table 11: LDO Regulator Electrical Specifications .......................................................................................... 38 Table 12: ADC Specifications .......................................................................................................................... 38 Table 13: Digital Level ..................................................................................................................................... 39 Table 14: Current Consumption ...................................................................................................................... 39 Table 15: ESD Tolerance................................................................................................................................. 39 Table 16: Receiver RF Specifications .............................................................................................................. 40 Table 17: Transmitter RF Specifications .......................................................................................................... 41 Table 18: UART Timing Specifications ............................................................................................................ 42 Table 19: SPI1 Timing Values--SCLK = 12 MHz and VDDM = 3.2V ............................................................. 43 Table 20: SPI1 Timing Values--SCLK = 6 MHz and VDDM = 1.62V ............................................................. 44 Table 21: SPI2 Timing Values--SCLK = 12 MHz and VDDM = 3.2V ............................................................. 44 Table 22: SPI2 Timing Values--SCLK = 6 MHz and VDDM = 1.62V ............................................................. 44 Table 23: BSC Interface Timing Specifications................................................................................................ 45 Table 24: BCM20738 6 x 6 x 1 mm QFN, 40-Pin Tape Reel Specifications ................................................... 48 Table 25: BCM20738 7 x 7 x 0.8 mm WFBGA, 64-Pin Tape Reel Specifications .......................................... 48 Table 26: Ordering Information ........................................................................................................................ 49 Broadcom(R) November 16, 2015 * 20738-DS102-R Page 8 BROADCOM CONFIDENTIAL BCM20738 Data Sheet About This Document About This Document Purpose and Audience This data sheet provides a description of the major blocks, interfaces, pin assignments, and specifications of the BCM20738 single-chip Bluetooth transceiver. This is a required document for designers responsible for adding the BCM20738 Bluetooth transceiver to wireless input device applications including game controllers, keyboards, remote controls, gestural input devices, and sensor devices. Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. Acronyms and abbreviations in this document are also defined in Appendix A: "Acronyms and Abbreviations," on page 50. For a comprehensive list of acronyms and other terms used in Broadcom documents, go to: http://www.broadcom.com/press/glossary.php. References The references in this section may be used in conjunction with this document. Note: Broadcom provides customer access to technical documentation and software through its Customer Support Portal (CSP) and Downloads & Support site (see Technical Support). For Broadcom documents, replace the "x" in the document number with the largest number available in the repository to ensure that you have the most current version of the document. Document Name Number Broadcom Items [1] Single-Chip Bluetooth(R) Transceiver and Baseband Processor 20702-DS10x-R Technical Support Broadcom provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates through its customer support portal (https://support.broadcom.com). For a CSP account, contact your Sales or Engineering support representative. In addition, Broadcom provides other product support through its Downloads & Support site (http://www.broadcom.com/support/). Broadcom(R) November 16, 2015 * 20738-DS102-R Page 9 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Functional Description Section 1: Functional Description Keyboard Scanner The keyboard scanner is designed to autonomously sample keys and store them into buffer registers without the need for the host microcontroller to intervene. The scanner has the following features: * Ability to turn off its clock if no keys pressed. * Sequential scanning of up to 160 keys in an 8 x 20 matrix. * Programmable number of columns from 1 to 20. * Programmable number of rows from 1 to 8. * 16-byte key-code buffer (can be augmented by firmware). * 128 kHz clock - allows scanning of full 160-key matrix in about 1.2 ms. * N-key rollover with selective 2-key lockout if ghost is detected. * Keys are buffered until host microcontroller has a chance to read it, or until overflow occurs. * Hardware debouncing and noise/glitch filtering. * Low-power consumption. Single-digit A-level sleep current. Theory of Operation The key scan block is controlled by a state machine with the following states: Idle The state machine begins in the idle state. In this state, all column outputs are driven high. If any key is pressed, a transition occurs on one of the row inputs. This transition causes the 128 kHz clock to be enabled (if it is not already enabled by another peripheral) and the state machine to enter the scan state. Also in this state, an 8-bit row-hit register and an 8-bit key-index counter is reset to 0. Scan In the scan state, a row counter counts from 0 up to a programmable number of rows minus 1. Once the last row is reached, the row counter is reset and the column counter is incremented. This cycle repeats until the row and column counters are both at their respective terminal count values. At that point, the state machine moves into the Scan-End state. As the keys are being scanned, the key-index counter is incremented. This counter is the value compared to the modifier key codes stored, or in the key-code buffer if the key is not a modifier key. It can be used by the microprocessor as an index into a lookup table of usage codes. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 10 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Mouse Quadrature Signal Decoder Also, as the n-th row is scanned, the row-hit register is ORed with the current 8-bit row input values if the current column contains two or more row hits. During the scan of any column, if a key is detected at the current row, and the row-hit register indicates that a hit was detected in that same row on a previous column, then a ghost condition may have occurred, and a bit in the status register is set to indicate this. Scan End This state determines whether any keys were detected while in the scan state. If yes, the state machine returns to the scan state. If no, the state machine returns to the idle state, and the 128 kHz clock request signal is made inactive. The microcontroller can poll the key status register. Mouse Quadrature Signal Decoder The mouse signal decoder is designed to autonomously sample two quadrature signals commonly generated by optomechanical mouse apparatus. The decoder has the following features: * Three pairs of inputs for X, Y, and Z (typical scroll wheel) axis signals. Each axis has two options: - For the X axis, choose P2 or P32 as X0 and P3 or P33 as X1. - For the Y axis, choose P4 or P34 as Y0 and P5 or P35 as Y1. - For the Z axis, choose P6 or P36 as Z0 and P7 or P37 as Z1. * Control of up to four external high current GPIOs to power external optoelectronics: - Turn-on and turn-off time can be staggered for each HC-GPIO to avoid simultaneous switching of high currents and having multiple high-current devices on at the same time. - Sample time can be staggered for each axis. - Sense of the control signal can be active high or active low. - Control signal can be tristated for off condition or driven high or low, as appropriate. Theory of Operation The mouse decoder block has four 16-bit PWMs for controlling external quadrature devices and sampling the quadrature inputs at its core. The GPIO signals may be used to control such items as LEDs, external ICs that may emulate quadrature signals, photodiodes, and photodetectors. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 11 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Infrared Modulator Infrared Modulator The BCM20738 includes hardware support for infrared TX. The hardware can transmit both modulated and unmodulated waveforms. For modulated waveforms, hardware inserts the desired carrier frequency into all IR transmissions. IR TX can be sourced from firmware-supplied descriptors, a programmable bit, or the peripheral UART transmitter. If descriptors are used, they include IR on/off state and the duration between 1-32767 sec. The BCM20738 IR TX firmware driver inserts this information in a hardware FIFO and makes sure that all descriptors are played out without a glitch due to underrun. See Figure 2. Figure 2: Infrared TX VCC R1 62 INFRARED-LD D1 U1 R2 20738 IR TX 2.4K Q1 MMBTA42 Infrared Learning The BCM20738 includes hardware support for infrared learning. The hardware can detect both modulated and unmodulated signals. For modulated signals, the BCM20738 can detect carrier frequencies between 10 kHz and 500 kHz and the duration that the signal is present or absent. The BCM20738 firmware driver supports further analysis and compression of learned signal. The learned signal can then be played back through the BCM20738 IR TX subsystem. See Figure 3. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 12 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Bluetooth Baseband Core Figure 3: Infrared RX VCC U3 D2 PHOTODIODE 20738 IR RX Bluetooth Baseband Core The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high performance Bluetooth operation. The BBC manages the buffering, segmentation, and data routing for all connections. It also buffers data that passes through it, handles data flow control, schedules ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it independently handles HCI event types and HCI command types. The following transmit and receive functions are also implemented in the BBC hardware to increase TX/RX data reliability and security before sending over the air: * Receive Functions: symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), data decryption, and data dewhitening. * Transmit Functions: data framing, FEC generation, HEC generation, CRC generation, link key generation, data encryption, and data whitening. Frequency Hopping Generator The frequency hopping sequence generator selects the correct hopping channel number depending on the link controller state, Bluetooth clock, and device address. E0 Encryption The encryption key and the encryption engine are implemented using dedicated hardware to reduce software complexity and provide minimal processor intervention. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 13 BROADCOM CONFIDENTIAL BCM20738 Data Sheet ADC Port Link Control Layer The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the Link Control Unit (LCU). This layer consists of the Command Controller, which takes software commands, and other controllers that are activated or configured by the Command Controller to perform the link control tasks. Each task performs a different Bluetooth link controller state. STANDBY and CONNECTION are the two major states. In addition, there are five substates: page, page scan, inquiry, inquiry scan, and sniff. Adaptive Frequency Hopping The BCM20738 gathers link quality statistics on a channel-by-channel basis to facilitate channel assessment and channel map selection. The link quality is determined by using both RF and baseband signal processing to provide a more accurate frequency hop map. Bluetooth Low Energy The BCM20738 supports the Bluetooth Low Energy (BLE) operating mode. Test Mode Support The BCM20738 fully supports Bluetooth Test mode, as described in the Bluetooth Low Energy specification. ADC Port The BCM20738 contains a 16-bit ADC (effective number of bits is 10). Additionally: * There are 29 analog input channels in the 64-pin package, and 13 analog input channels in the 40-pin package. All channels are multiplexed on various GPIOs. * The conversion time is 10 s. * There is a built-in reference with supply- or band-gap based reference modes. * The maximum conversion rate is 187 kHz. * There is a rail-to-rail input swing. The ADC consists of an analog ADC core that performs the actual analog-to-digital conversion and digital hardware that processes the output of the ADC core into valid ADC output samples. Directed by the firmware, the digital hardware also controls the input multiplexers that select the ADC input signal Vinp and the ADC reference signals Vref. Table 1: ADC Modes Mode ENOB (Typical) Maximum Sampling Rate (kHz) Latencya (s) 0 13 5.859 171 1 12.6 11.7 85 Broadcom(R) November 16, 2015 * 20738-DS102-R Page 14 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Serial Peripheral Interface Table 1: ADC Modes (Cont.) Mode ENOB (Typical) Maximum Sampling Rate (kHz) Latencya (s) 2 12 46.875 21 3 11.5 93.75 11 4 10 187 5 a. Settling time after switching channels. Serial Peripheral Interface The BCM20738 has two independent SPI interfaces. One is a master-only interface and the other can be either a master or a slave. Each interface has a 16-byte transmit buffer and a 16-byte receive buffer. To support more flexibility for user applications, the BCM20738 has optional I/O ports that can be configured individually and separately for each functional pin, as shown in Table 2. The BCM20738 acts as an SPI master device that supports 1.8V to 3.3V SPI slaves, as shown in Table 2. The BCM20738 can also act as an SPI slave device that supports a 1.8V to 3.3V SPI master using the second SPI interface, as shown in Table 2. Table 2: BCM20738 First SPI Set (Master Mode) Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CSa Configuration set 1 SCL SDA P24 - Configuration set 2 SCL SDA P26 - Configuration set 3 SCL (Default for serial flash) SDA P32 P33 Configuration set 4 SDA P39 - SCL a. Any GPIO can be used as SPI_CS when SPI is in master mode. Table 3: BCM20738 Second SPI Set (Master Mode) Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CSa Configuration set 1 P3 P0 P1 - Configuration set 2 P3 P0 P5 - Configuration set 3 P3 P2 P1 - Configuration set 4 P3 P2 P5 - Configuration set 5 P3 P4 P1 - Configuration set 6 P3 P4 P5 - Configuration set 7 P3 P27 P1 - Configuration set 8 P3 P27 P5 - Configuration set 9 P3 P38 P1 - Configuration set 10 P3 P38 P5 - Configuration set 11 P7 P0 P1 - Configuration set 12 P7 P0 P5 - Broadcom(R) November 16, 2015 * 20738-DS102-R Page 15 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Serial Peripheral Interface Table 3: BCM20738 Second SPI Set (Master Mode) (Cont.) Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CSa Configuration set 13 P7 P2 P1 - Configuration set 14 P7 P2 P5 - Configuration set 15 P7 P4 P1 - Configuration set 16 P7 P4 P5 - Configuration set 17 P7 P27 P1 - Configuration set 18 P7 P27 P5 - Configuration set 19 P7 P38 P1 - Configuration set 20 P7 P38 P5 - Configuration set 21 P24 P0 P25 - Configuration set 22 P24 P2 P25 - Configuration set 23 P24 P4 P25 - Configuration set 24 P24 P27 P25 - Configuration set 25 P24 P38 P25 - Configuration set 26 P36 P0 P25 - Configuration set 27 P36 P2 P25 - Configuration set 28 P36 P4 P25 - Configuration set 29 P36 P27 P25 - Configuration set 30 P36 P38 P25 - a. Any GPIO can be used as SPI_CS when SPI is in master mode. Table 4: BCM20738 Second SPI Set (Slave Mode)a Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CS Configuration set 1 P3 P0 P1 P2 Configuration set 2 P3 P0 P5 P2 Configuration set 3 P3 P4 P1 P2 Configuration set 4 P3 P4 P5 P2 Configuration set 5 P7 P0 P1 P2 Configuration set 6 P7 P0 P5 P2 Configuration set 7 P7 P4 P1 P2 Configuration set 8 P7 P4 P5 P2 Configuration set 9 P3 P0 P1 P6 Configuration set 10 P3 P0 P5 P6 Configuration set 11 P3 P4 P1 P6 Configuration set 12 P3 P4 P5 P6 Configuration set 13 P7 P0 P1 P6 Configuration set 14 P7 P0 P5 P6 Configuration set 15 P7 P4 P1 P6 Configuration set 16 P7 P4 P5 P6 Broadcom(R) November 16, 2015 * 20738-DS102-R Page 16 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Microprocessor Unit Table 4: BCM20738 Second SPI Set (Slave Mode)a Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CS Configuration set 17 P24 P27 P25 P26 Configuration set 18 P24 P33 P25 P26 Configuration set 19 P24 P38 P25 P26 Configuration set 20 P36 P27 P25 P26 Configuration set 21 P36 P33 P25 P26 Configuration set 22 P36 P38 P25 P26 Configuration set 23 P24 P27 P25 P32 Configuration set 24 P24 P33 P25 P32 Configuration set 25 P24 P38 P25 P32 Configuration set 26 P36 P27 P25 P32 Configuration set 27 P36 P33 P25 P32 Configuration set 28 P36 P38 P25 P32 Configuration set 29 P24 P27 P25 P39 Configuration set 30 P24 P33 P25 P39 Configuration set 31 P24 P38 P25 P39 Configuration set 32 P36 P27 P25 P39 Configuration set 33 P36 P33 P25 P39 Configuration set 34 P36 P38 P25 P39 a. Additional configuration sets are available upon request. Microprocessor Unit The BCM20738 microprocessor unit (PU) executes software from the link control (LC) layer up to the application layer components that ensure adherence to the Bluetooth Human Interface Device (HID) profile. The microprocessor is based on an ARM CortexTM-M3, 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The PU has 320 KB of ROM for program storage and boot-up, 60 KB of RAM for scratchpad data, and patch RAM code. The internal boot ROM provides power-on reset flexibility, which enables the same device to be used in different Bluetooth HID over GATT applications with an external serial EEPROM or with an external serial flash memory for application and patch storage. At power-up, the lowest layer of the protocol stack is executed from the internal ROM memory. External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes and feature additions. The device can also support the integration of user applications. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 17 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Microprocessor Unit EEPROM Interface The BCM20738 provides a Broadcom Serial Control (BSC) master interface. The BSC is programmed by the CPU to generate four types of BSC bus transfers: read-only, write-only, combined read/write, and combined write/read. BSC supports both low-speed and fast mode devices. The BSC is compatible with a Philips(R) (now NXP) I2C slave device, except that master arbitration (multiple I2C masters contending for the bus) is not supported. The EEPROM can contain customer application configuration information including: application code, configuration data, patches, pairing information, BD_ADDR, and file system information used for code. Native support for the Microchip(R) 24LC128, Microchip 24AA128, and ST Micro(R) M24128-BR is included. Serial Flash Interface The BCM20738 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB slave interface, transmit and receive FIFOs, and the SPI core PHY logic. Devices natively supported include the following: * Atmel(R) AT25DF011-MAHN Internal Reset Figure 4: Internal Reset Timing VDDO POR delay ~ 2 ms VDDO VDDO POR threshold VDDO POR VDDC POR threshold VDDC VDDC POR delay ~ 2 ms VDDC POR Baseband Reset Crystal warm-up delay: ~ 5 ms Start reading EEPROM and firmware boot Crystal Enable Broadcom(R) November 16, 2015 * 20738-DS102-R Page 18 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Integrated Radio Transceiver External Reset The BCM20738 has an integrated power-on reset circuit that completely resets all circuits to a known power-on state. An external active low reset signal, RESET_N, can be used to put the BCM20738 in the reset state. The RESET_N pin has an internal pull-up resistor and, in most applications, it does not require that anything be connected to it. RESET_N should only be released after the VDDO supply voltage level has been stabilized. Figure 5: External Reset Timing Pulse width >50 s RESET_N Crystal warm-up delay: ~ 5 ms Baseband Reset Start reading EEPROM and firmware boot Crystal Enable Integrated Radio Transceiver The BCM20738 has an integrated radio transceiver that is optimized for 2.4 GHz Bluetooth(R) wireless systems. It has been designed to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with Bluetooth Low Energy Radio Specification and meets or exceeds the requirements to provide the highest communication link quality of service. Transmitter Path The BCM20738 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band. Digital Modulator The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal. Power Amplifier The BCM20738 has an integrated power amplifier (PA) that can transmit up to +4 dBm for class 2 operation. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 19 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Integrated Radio Transceiver Receiver Path The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order, on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation, enables the BCM20738 to be used in most applications without off-chip filtering. Digital Demodulator and Bit Synchronizer The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm. Receiver Signal Strength Indicator The radio portion of the BCM20738 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power. Local Oscillator The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 40 maximum available channels. The BCM20738 uses an internal loop filter. Calibration The BCM20738 radio transceiver features a self-contained automated calibration scheme. No user interaction is required during normal operation or during manufacturing to provide optimal performance. Calibration compensates for filter, matching network, and amplifier gain and phase characteristics to yield radio performance within 2% of what is optimal. Calibration takes process and temperature variations into account, and it takes place transparently during normal operation and hop setting times. Internal LDO Regulator The BCM20738 has an integrated 1.2V LDO regulator that provides power to the digital and RF circuits. The 1.2V LDO regulator operates from a 1.425V to 3.63V input supply with a 30 mA maximum load current. Note: Always place the decoupling capacitors near the pins as closely together as possible. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 20 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Peripheral Transport Unit Peripheral Transport Unit Broadcom Serial Communications Interface The BCM20738 provides a 2-pin master BSC interface, which can be used to retrieve configuration information from an external EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse devices. The BSC interface is compatible with I2C slave devices. The BSC does not support multimaster capability or flexible wait-state insertion by either master or slave devices. The following transfer clock rates are supported by the BSC: * 100 kHz * 400 kHz * 800 kHz (Not a standard I2C-compatible speed.) * 1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed.) The following transfer types are supported by the BSC: * Read (Up to 16 bytes can be read.) * Write (Up to 16 bytes can be written.) * Read-then-Write (Up to 16 bytes can be read and up to 16 bytes can be written.) * Write-then-Read (Up to 16 bytes can be written and up to 16 bytes can be read.) Hardware controls the transfers, requiring minimal firmware setup and supervision. The clock pin (SCL) and data pin (SDA) are both open-drain I/O pins. Pull-up resistors external to the BCM20738 are required on both the SCL and SDA pins for proper operation. UART Interface The UART is a standard 2-wire interface (RX and TX) and has adjustable baud rates from 9600 bps to 1.5 Mbps. The baud rate can be selected via a vendor-specific UART HCI command. The interface supports the Bluetooth 3.0 UART HCI (H5) specification. The default baud rate for H5 is 115.2 kbaud. Both high and low baud rates can be supported by running the UART clock at 24 MHz. The BCM20738 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within 5%. Clock Frequencies The BCM20738 is set with crystal frequency of 24 MHz. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 21 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Clock Frequencies Crystal Oscillator The crystal oscillator requires a crystal with an accuracy of 20 ppm as defined by the Bluetooth specification. Two external load capacitors in the range of 5 pF to 30 pF are required to work with the crystal oscillator. The selection of the load capacitors is crystal dependent. Table 5 on page 22 shows the recommended crystal specification. Figure 6: Recommended Oscillator Configuration--12 pF Load Crystal 22 pF XIN Crystal XOUT 20 pF Table 5: Reference Crystal Electrical Specifications Parameter Conditions Minimum Typical Maximum Unit Nominal frequency - - 24.000 - MHz Oscillation mode - Fundamental Frequency tolerance @25C - 10 - - ppm Tolerance stability over temp @0C to +70C - 10 - ppm Equivalent series resistance - - - 50 Load capacitance - - 12 - pF Operating temperature range - 0 - +70 C Storage temperature range - -40 - +125 C Drive level - - - 200 W Aging - - - 10 ppm/year Shunt capacitance - - - 2 pF HID Peripheral Block The peripheral blocks of the BCM20738 all run from a single 128 kHz low-power RC oscillator. The oscillator can be turned on at the request of any of the peripherals. If the peripheral is not enabled, it shall not assert its clock request line. The keyboard scanner is a special case in that it may drop its clock request line even when enabled and then reassert the clock request line if a keypress is detected. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 22 BROADCOM CONFIDENTIAL BCM20738 Data Sheet GPIO Port 32 kHz Crystal Oscillator Figure 7 shows the 32 kHz crystal (XTAL) oscillator with external components and Table 6 on page 23 lists the oscillator's characteristics. It is a standard Pierce oscillator using a comparator with hysteresis on the output to create a single-ended digital output. The hysteresis was added to eliminate any chatter when the input is around the threshold of the comparator and is ~100 mV. This circuit can be operated with a 32 kHz or 32.768 kHz crystal oscillator or be driven with a clock input at similar frequency. The default component values are: R1 = 10 M, C1 = C2 = ~10 pF. The values of C1 and C2 are used to fine-tune the oscillator. Figure 7: 32 kHz Oscillator Block Diagram C2 32.768 kHz XTAL R1 C1 Table 6: XTAL Oscillator Characteristics Parameter Symbol Conditions Minimum Typical Maximum Unit Output frequency Foscout - - 32.768 - kHz Frequency tolerance - Crystal dependent - 100 - ppm Start-up time Tstartup - - - 500 ms XTAL drive level Pdrv For crystal selection 0.5 - - W XTAL series resistance Rseries For crystal selection - - 70 k XTAL shunt capacitance Cshunt For crystal selection - - 1.3 pF GPIO Port The BCM20738 has 22 GPIOs in the 40-pin package, and 40 GPIOs in the 64-pin package. All GPIOs support programmable pull-up and pull-down resistors, and all support a 2 mA drive strength except P26, P27, P28, and P29, which provide a 16 mA drive strength at 3.3V supply. Port 0-Port 1, Port 8-Port 23, and Port 28-Port 38 All of these pins can be programmed as ADC inputs. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 23 BROADCOM CONFIDENTIAL BCM20738 Data Sheet PWM Port 26-Port 29 P[26:29] consists of four pins. All pins are capable of sinking up to 16 mA for LED. These pins also have the PWM function, which can be used for LED dimming. PWM The BCM20738 has four internal PWM channels. The PWM module consists of the following: * PWM1-4 * Each of the four PWM channels, PWM1-4, contains the following registers: - 10-bit initial value register (read/write) - 10-bit toggle register (read/write) - 10-bit PWM counter value register (read) * The PWM configuration register is shared among PWM1-4 (read/write). This 12-bit register is used: - To configure each PWM channel. - To select the clock of each PWM channel - To change the phase of each PWM channel Figure 8 shows the structure of one PWM channel. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 24 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Power Management Unit Figure 8: PWM Channel Block Diagram pwm_cfg_adr register pwm#_init_val_adr register pwm#_togg_val_adr register enable clk_sel o_flip 10 10 pwm#_cntr_adr 10 cntr value is CM3-readable pwm_out Example: PWM cntr w/ pwm#_init_val = 0 (dashed line) PWM cntr w/ pwm#_init_val = x (solid line) 10'H3FF pwm_togg_val_adr 10'Hx 10'H000 pwm_out Power Management Unit The Power Management Unit (PMU) provides power management features that can be invoked by software through power management registers or packet-handling in the baseband core. RF Power Management The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz transceiver, which then processes the power-down functions accordingly. Host Controller Power Management Power is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls the disabling of the on-chip regulator when in deep Sleep mode. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 25 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Power Management Unit BBC Power Management There are several low-power operations for the BBC: * Physical layer packet handling turns RF on and off dynamically within packet TX and RX. * Bluetooth-specified low-power connection mode. While in these low-power connection modes, the BCM20738 runs on the Low Power Oscillator and wakes up after a predefined time period. The BCM20738 automatically adjusts its power dissipation based on user activity. The following power modes are supported: * Active mode * Idle mode * Sleep mode * HIDOFF mode The BCM20738 transitions to the next lower state after a programmable period of user inactivity. Busy mode is immediately entered when user activity resumes. In HIDOFF mode, the BCM20738 baseband and core are powered off by disabling power to LDOOUT. The VDDO domain remains powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chip power consumption and is intended for long periods of inactivity. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 26 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Pin Assignments Section 2: Pin Assignments Pin Descriptions Table 7: Pin Descriptions Pin Number 40-pin QFN 64-pin BGA Pin Name I/O Power Domain Description 8 F1 RF I/O VDD_RF RF antenna port RF Power Supplies 6 D1 VDDIF I VDD_RF IFPLL power supply 7 E1 VDDFE I VDD_RF RF front-end supply 9 H1 VDDVCO I VDD_RF VCO, LOGEN supply 10 H2 VDDPLL I VDD_RF RFPLL and crystal oscillator supply VDDC I N/A Baseband core supply Power Supplies 13 H6 - D4, E2, E5, VSS F2, G1, G2 I N/A Ground 34 A6, D7 VDDO I VDDO I/O pad and core supply 16 - VDDM I VDDM I/O pad supply Clock Generator and Crystal Interface 11 H3 XTALI I VDD_RF Crystal oscillator input. See "Crystal Oscillator" on page 22 for options. 12 G3 XTALO O VDD_RF Crystal oscillator output. 40 A3 XTALI32K I VDDO Low-power oscillator (LPO) input is used. Alternative Function: * P11 in 40-QFN only * P39 in 64-BGA only 39 B3 XTALO32K O VDDO Low-power oscillator (LPO) output. Alternative Function: * P12 in 40-QFN only * P38 in 64-BGA only 20 G8 RESET_N I/O PU VDDO Active-low system reset with open-drain output & internal pull-up resistor 19 G7 TMC I VDDO Test mode control High: test mode Connect to GND if not used. Core Broadcom(R) November 16, 2015 * 20738-DS102-R Page 27 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Pin Descriptions Table 7: Pin Descriptions (Cont.) Pin Number 40-pin QFN 64-pin BGA Pin Name I/O Power Domain 14 H5 UART_RXD I VDDMa 15 G5 UART_TXD O, PU VDDMa F7 SDA I/O, PU Description UART UART serial input - Serial data input for the HCI UART interface. Leave unconnected if not used. Alternative function: * GPIO3 UART serial output - Serial data output for the HCI UART interface. Leave unconnected if not used. Alternative Function: * GPIO2 BSC 17 18 E8 SCL I/O, PU VDDMa a VDDM Data signal for an external I2C device. Alternative function: * SPI_1: MOSI (master only) * GPIO0 * CTS Clock signal for an external I2C device. Alternative function: * SPI_1: SPI_CLK (master only) * GPIO1 * RTS LDO Regulator Power Supplies 4 B1 LDOIN I LDO Battery input supply for the LDO 5 C1 LDOOUT O LDO LDO output a. VDDO for 64-pin package. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 28 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Pin Descriptions Table 8: GPIO Pin Descriptionsa Pin Number 40-pin 64-pin Default After QFN BGA Pin Name Direction POR Power Domain Alternate Function Description 21 F6 P0 Input Floating VDDO * * * * * * * * GPIO: P0 Keyboard scan input (row): KSI0 A/D converter input Peripheral UART: puart_tx SPI_2: MOSI (master and slave) IR_RX 60 Hz_main Not available during TMC=1 22 G6 P1 Input Floating VDDO * * * * * * GPIO: P1 Keyboard scan input (row): KSI1 A/D converter input Peripheral UART: puart_rts SPI_2: MISO (master and slave) IR_TX 24 H8 P2 Input Floating VDDO * * * * * * GPIO: P2 Keyboard scan input (row): KSI2 Quadrature: QDX0 Peripheral UART: puart_rx SPI_2: SPI_CS (slave only) SPI_2: SPI_MOSI (master only) 23 F8 P3 Input Floating VDDO * * * * * GPIO: P3 Keyboard scan input (row): KSI3 Quadrature: QDX1 Peripheral UART: puart_cts SPI_2: SPI_CLK (master and slave) 25 H7 P4 Input Floating VDDO * * * * * * GPIO: P4 Keyboard scan input (row): KSI4 Quadrature: QDY0 Peripheral UART: puart_rx SPI_2: MOSI (master and slave) IR_TX 26 E6 P5 Input Floating VDDO * * * * * GPIO: P5 Keyboard scan input (row): KSI5 Quadrature: QDY1 Peripheral UART: puart_tx SPI_2: MISO (master and slave) Broadcom(R) November 16, 2015 * 20738-DS102-R Page 29 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Pin Descriptions Table 8: GPIO Pin Descriptionsa (Cont.) Pin Number 40-pin 64-pin Default After QFN BGA Pin Name Direction POR Power Domain Alternate Function Description 27 F5 P6 PWM2 Input Floating VDDO * * * * * * GPIO: P6 Keyboard scan input (row): KSI6 Quadrature: QDZ0 Peripheral UART: puart_rts SPI_2: SPI_CS (slave only) 60Hz_main 28 C5 P7 Input Floating VDDO * * * * * GPIO: P7 Keyboard scan input (row): KSI7 Quadrature: QDZ1 Peripheral UART: puart_cts SPI_2: SPI_CLK (master and slave) 29 F4 P8 Input Floating VDDO * * * * GPIO: P8 Keyboard scan output (column): KSO0 A/D converter input External T/R switch control: ~tx_pd 3 A1 P9 Input Floating VDDO * * * * GPIO: P9 Keyboard scan output (column): KSO1 A/D converter input External T/R switch control: tx_pd 2 D2 P10 PWM3 Input Floating VDDO * * * GPIO: P10 Keyboard scan output (column): KSO2 A/D converter input 40 C2 P11 Input Floating VDDO * * * * GPIO: P11 Keyboard scan output (column): KSO3 A/D converter input XTALI32K (40-QFN only) 39 B2 P12 Input Floating VDDO * * * * GPIO: P12 Keyboard scan output (column): KSO4 A/D converter input XTALO32K (40-QFN only) 35 F3 P13 PWM3 Input Floating VDDO * * * * GPIO: P13 Keyboard scan output (column): KSO5 A/D converter input Alternative Function: P28 37 D3 P14 PWM2 Input Floating VDDO * * * GPIO: P14 Keyboard scan output (column): KSO6 A/D converter input Broadcom(R) November 16, 2015 * 20738-DS102-R Page 30 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Pin Descriptions Table 8: GPIO Pin Descriptionsa (Cont.) Pin Number 40-pin 64-pin Default After QFN BGA Pin Name Direction POR Power Domain Alternate Function Description 38 A2 P15 Input Floating VDDO * * * * * * GPIO: P15 Keyboard scan output (column): KSO7 A/D converter input IR_RX 60Hz_main Alternative Function: P26 - C8 P16 Input Floating VDDO * * GPIO: P16 Keyboard scan output (column): KSO8 - H4 P17 Input Floating VDDO * * * GPIO: P17 Keyboard scan output (column): KSO9 A/D converter input - C7 P18 Input Floating VDDO * * * GPIO: P18 Keyboard scan output (column): KSO10 A/D converter input - B8 P19 Input Floating VDDO * * * GPIO: P19 Keyboard scan output (column): KSO11 A/D converter input - A8 P20 Input Floating VDDO * * * GPIO: P20 Keyboard scan output (column): KSO12 A/D converter input - C6 P21 Input Floating VDDO * * * GPIO: P21 Keyboard scan output (column): KSO13 A/D converter input - G4 P22 Input Floating VDDO * * * GPIO: P22 Keyboard scan output (column): KSO14 A/D converter input - E3 P23 Input Floating VDDO * * * GPIO: P23 Keyboard scan output (column): KSO15 A/D converter input 33 A7 P24 Input Floating VDDO * * * * * GPIO: P24 Keyboard scan output (column): KSO16 SPI_2: SPI_CLK (master and slave) SPI_1: MISO (master only) Peripheral UART: puart_tx 32 B7 P25 Input Floating VDDO * * * * GPIO: P25 Keyboard scan output (column): KSO17 SPI_2: MISO (master and slave) Peripheral UART: puart_rx Broadcom(R) November 16, 2015 * 20738-DS102-R Page 31 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Pin Descriptions Table 8: GPIO Pin Descriptionsa (Cont.) Pin Number 40-pin 64-pin Default After QFN BGA Pin Name Direction POR Power Domain Alternate Function Description 38 A4 P26 PWM0 Input Floating VDDO * * * * * * * GPIO: P26 Keyboard scan output (column): KSO18 SPI_2: SPI_CS (slave only) SPI_1: MISO (master only) Optical control output: QOC0 Current: 16 mA Alternative function: P15 1 B4 P27 PWM1 Input Floating VDDO * * * * * GPIO: P27 Keyboard scan output (column): KSO19 SPI_2: MOSI (master and slave) Optical control output: QOC1 Current: 16 mA 35 B5 P28 PWM2 Input Floating VDDO * * * * * * GPIO: P28 Optical control output: QOC2 A/D converter input LED1 Current: 16 mA Alternative function: P13 - A5 P29 PWM3 Input Floating VDDO * * * * * GPIO: P29 Optical control output: QOC3 A/D converter input LED2 Current: 16 mA - E4 P30 Input Floating VDDO * * * * GPIO: P30 A/D converter input Pairing button pin in default FW Peripheral UART: puart_rts - E7 P31 Input Floating VDDO * * * * GPIO: P31 A/D converter input EEPROM WP pin in default FW Peripheral UART: puart_tx 31 D6 P32 Input Floating VDDO * * * * * * * GPIO: P32 A/D converter input Quadrature: QDX0 SPI_2: SPI_CS (slave only) SPI_1: MISO (master only) Auxiliary clock output: ACLK0 Peripheral UART: puart_tx Broadcom(R) November 16, 2015 * 20738-DS102-R Page 32 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Pin Descriptions Table 8: GPIO Pin Descriptionsa (Cont.) Pin Number 40-pin 64-pin Default After QFN BGA Pin Name Direction POR Power Domain Alternate Function Description 30 D8 P33 Input Floating VDDO * * * * * * GPIO: P33 A/D converter input Quadrature: QDX1 SPI_2: MOSI (slave only) Auxiliary clock output: ACLK1 Peripheral UART: puart_rx - B6 P34 Input Floating VDDO * * * * * GPIO: P34 A/D converter input Quadrature: QDY0 Peripheral UART: puart_rx External T/R switch control: tx_pd - D5 P35 Input Floating VDDO * * * * GPIO: P35 A/D converter input Quadrature: QDY1 Peripheral UART: puart_cts - C4 P36 Input Floating VDDO * * * * * * * GPIO: P36 A/D converter input Quadrature: QDZ0 SPI_2: SPI_CLK (master and slave) Auxiliary Clock Output: ACLK0 Battery detect pin in default FW External T/R switch control: ~tx_pd 36 C3 P37 Input Floating VDDO * * * * * * GPIO: P37 A/D converter input Quadrature: QDZ1 SPI_2: MISO (slave only) Auxiliary clock output: ACLK1 Alternative function: P38, P39 36 B3 P38 Input Floating VDDO * * * * * * GPIO: P38 A/D converter input SPI_2: MOSI (master and slave) IR_TX XTALO32K (64-BGA only) Alternate functions: P37, P39 Broadcom(R) November 16, 2015 * 20738-DS102-R Page 33 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Pin Descriptions Table 8: GPIO Pin Descriptionsa (Cont.) Pin Number 40-pin 64-pin Default After QFN BGA Pin Name Direction POR 36 A3 P39 Input Power Domain Alternate Function Description Floating VDDO * * * * * * * * GPIO: P39 SPI_2: SPI_CS (slave only) SPI_1: MISO (master only) Infrared control: IR_RX External PA ramp control: PA_Ramp XTALI32K (64-BGA only) 60Hz_main Alternative function: P37, P38 a. During Power-On Reset, all inputs are disabled. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 34 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Ball Maps Ball Maps XTALI32K/P11 XTALO32K/P12 P15/P26/PWM0 P14 P37/P38/P39 P13/P28 VDDO P24 P25 P32 Figure 9: 40-pin QFN Ball Map 40 39 38 37 36 35 34 33 32 31 28 P7 LDOIN 4 27 P6 LDOOUT 5 26 P5 VDDIF 6 25 P4 VDDFE 7 24 P2 RF 8 23 P3 VDDVCO 9 22 P1 VDDPLL 10 21 P0 11 12 13 14 15 16 17 18 19 20 RESET_N 3 TMC P9 SCL P8 SDA 29 VDDM 2 UART_TXD P10 UART_RXD P33 VDDC 30 XTALO 1 XTALI P27/PWM1 Broadcom(R) November 16, 2015 * 20738-DS102-R Page 35 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Ball Maps Figure 10: 64-pin BGA Ball Map 1 2 3 4 5 6 7 8 A P9 P15 P39/ XTALI32K P26/ PWM0 P29/ PWM3 VDDO P24 P20 A B LDOIN P12 P38/ XTALO32 K P27/ PWM1 P28/ PWM2 P34 P25 P19 B C LDOOUT P11 P37 P36 P7 P21 P18 P16 C D VDDIF P10 P14 VSS P35 P32 VDDO P33 D E VDDF E VSS P23 P30 VSS P5 P31 SCL E F RF VSS P13 P8 P6 P0 SDA P3 F G VSS VSS XTAL O P22 UART _TXD P1 TMC RESE T_N G H VDDVCO VDDPLL XTALI P17 UART_ RXD VDDC P4 P2 H 1 2 3 4 5 6 7 8 Broadcom(R) November 16, 2015 * 20738-DS102-R Page 36 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Specifications Section 3: Specifications Electrical Characteristics Table 9 shows the maximum electrical rating for voltages referenced to VDD pin. Table 9: Maximum Electrical Rating Rating Symbol Value Unit DC supply voltage for RF domain DC supply voltage for core domain DC supply voltage for VDDM domain (UART/I2C) DC supply voltage for VDDO domain DC supply voltage for VR3V DC supply voltage for VDDFE Voltage on input or output pin Operating ambient temperature range Storage temperature range - - - - - - - Topr Tstg 1.4 1.4 3.8 3.8 3.8 1.4 VSS - 0.3 to VDD + 0.3 0 to +70 -40 to +125 V V V V V V V C C Table 10 shows the power supply characteristics for the range TJ = 0 to 125C. Table 10: Power Supply Parameter Minimuma Typical Maximuma Unit DC supply voltage for RF DC supply voltage for Core DC supply voltage for VDDM (UART/I2C) DC supply voltage for VDDO DC supply voltage for LDOIN DC supply voltage for VDDFE Supply noise for VDDO (peak-to-peak) Supply noise for LDOIN (peak-to-peak) 1.14 1.14 1.62 1.62 1.425 1.14 - - 1.2 1.2 - - - 1.2b - - 1.26 1.26 3.63 3.63 3.63 1.26 100 100 V V V V V V mV mV a. Overall performance degrades beyond minimum and maximum supply voltages. b. 1.2V for Class 2 output with internal VREG. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 37 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Electrical Characteristics Table 12 shows the digital level characteristics for (VSS = 0V). Table 11: LDO Regulator Electrical Specifications Parameter Conditions Min Typ Max Unit Input voltage range - 1.425 - 3.63 V Default output voltage - - 1.2 - V Output voltage Range 0.8 - 1.4 V Step size - 40 or 80 - mV Accuracy at any step -5 - +5 % Load current - - - 30 mA Line regulation Vin from 1.425 to 3.63V, Iload = 30 mA -0.2 - 0.2 %VO/V Load regulation Iload from 1 A to 30 mA, Vin = 3.3V, Bonding R = 0.3 - 0.1 0.2 %VO/mA Quiescent current No load @Vin = 3.3V Note: Current limit enabled - 6 - A Power-down current Vin = 3.3V, worst @ 70C - 5 200 nA Table 12: ADC Specifications Parameter Symbol Conditions Min Typ Max Unit - - - 28 - - Channel switching rate fch - - - 133.33 kch/s Input signal range - 0 - 3.63 V Reference settling time - Changing refsel 7.5 - - s Input resistance Rinp Effective, single-ended - 500 - k ADC Characteristics Number of Input channels Vinp Input capacitance Cinp - - - 5 pF Conversion rate fC - 5.859 - 187 kHz Conversion time TC - 5.35 - 170.7 s Resolution R - - 16 - bits Effective number of bits - - - See - Table 1 on page 14 Absolute voltage measurement error - Using on-chip ADC firmware driver - 2 - % Current I Iavdd1p2 + Iavdd3p3 - - 1 mA Power P - - 1.5 - mW Leakage current Ileakage T = 25C - - 100 nA Power-up time Tpowerup - - - 200 s INL - -1 - 1 LSBa DNL - -1 - 1 LSBa Integral nonlinearity3 Differential nonlinearitya Broadcom(R) November 16, 2015 * 20738-DS102-R Page 38 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Electrical Characteristics a. LSBs are expressed at the 10-bit level. Table 13: Digital Levela Characteristics Symbol Min Typ Max Unit Input low voltage VIL - - 0.4 V Input high voltage VIH 0.75 x VDDO - - V Input low voltage (VDDO = 1.62V) VIL - - 0.4 V Input high voltage (VDDO = 1.62V) VIH 1.2 - - V Output low voltageb VOL - - 0.4 V Output high voltageb VOH VDDO - 0.4 - - V Input capacitance (VDDMEM domain) CIN - - pF 0.12 a. This table is also applicable to VDDMEM domain. b. At the specified drive current for the pad. Table 14: Current Consumption a Operational Mode Conditions Receive Typ Max Unit Receiver and baseband are both operating, 100% 26.8 ON. - mA Transmit Transmitter and baseband are both operating, 100% ON. 26.87 - mA Sleep Internal LPO is in use. 35.0 - A 1.5 - A HIDOFF (Deep Sleep) - a. Current consumption measurements are taken at VBAT with the assumption that VBAT is connected to VDDIO and LDOIN. Caution! This device is susceptible to permanent damage from electrostatic discharge (ESD). Proper precautions are required during handling and mounting to avoid excessive ESD. Table 15: ESD Tolerance Model Tolerance Human Body Model (HBM) 2000V Charged Device Model (CDM) 400V Machine Model (MM) 150V Broadcom(R) November 16, 2015 * 20738-DS102-R Page 39 BROADCOM CONFIDENTIAL BCM20738 Data Sheet RF Specifications RF Specifications Table 16: Receiver RF Specifications Parameter Mode and Conditions Min Typ Max Unit Frequency range - 2402 - 2480 MHz RX sensitivity GFSK, 0.1%BER, 1 Mbps - -93 - dBm Input IP3 - -16 - - dBm Maximum input - -10 - - dBm GFSK, 0.1%BERa - - 21.0 dB GFSK, 0.1%BER a - - 15.0 dB C/I 2 MHz adjacent channel GFSK, 0.1%BER a - - -17.0 dB C/I 3 MHz adjacent channel GFSK, 0.1%BERb - - -27.0 dB a - - -9.0 dB a - - -15.0 dB Receiver Section Interference Performance C/I cochannel C/I 1 MHz adjacent channel C/I image channel C/I 1 MHz adjacent to image channel GFSK, 0.1%BER GFSK, 0.1%BER Out-of-Band Blocking Performance (CW)b 30 MHz to 2000 MHz 0.1%BERc - -30.0 - dBm 2000 MHz to 2399 MHz 0.1%BERd - -35 - dBm 2498 MHz to 3000 MHz 0.1%BERd - -35 - dBm 3000 MHz to 12.75 GHz 0.1%BERe - -30.0 - dBm 30 MHz to 1 GHz - - - -57.0 dBm 1 GHz to 12.75 GHz - - - -55.0 dBm Spurious Emissions a. b. c. d. e. 30.8% PER. Desired signal is 3 dB above the reference sensitivity level (defined as -70 dBm). Measurement resolution is 10 MHz. Measurement resolution is 3 MHz. Measurement resolution is 25 MHz. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 40 BROADCOM CONFIDENTIAL BCM20738 Data Sheet RF Specifications Table 17: Transmitter RF Specifications Parameter Min Typ Max Unit Frequency range 2402 - 2480 MHz Output power adjustment range -20.0 - 4.0 dBm Default output power - 4.0 - dBm Output power variation - 2.0 - dB 20 dB bandwidth - - - kHz |M - N| = 2 - - -20 dBm |M - N| 3 - - -30 dBm 30 MHz to 1 GHz - - -36.0 dBm 1 GHz to 12.75 GHz - - -30.0 dBm 1.8 GHz to 1.9 GHz - - -47.0 dBm 5.15 GHz to 5.3 GHz - - -47.0 dBm - - 150 kHz Transmitter Section Adjacent Channel Power Out-of-Band Spurious Emission LO Performance Initial carrier frequency tolerance Frequency Drift Frequency drift - - 50 kHz Drift rate - - 20 kHz/50 s Average deviation in payload (sequence used is 00001111) 225 - 275 kHz Maximum deviation in payload (sequence used is 10101010) 185 - - kHz Channel spacing - 2 - MHz Frequency Deviation Broadcom(R) November 16, 2015 * 20738-DS102-R Page 41 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Timing and AC Characteristics Timing and AC Characteristics In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams. UART Timing Table 18: UART Timing Specifications Reference Characteristics Min Max Unit 1 Delay time, UART_CTS_N low to UART_TXD valid - 24 Baud out cycles 2 Setup time, UART_CTS_N high before midpoint of stop bit - 10 ns 3 Delay time, midpoint of stop bit to UART_RTS_N high - 2 Baud out cycles Figure 11: UART Timing SPI Timing The SPI interface supports clock speeds up to 12 MHz with VDDIO 2.2V. The supported clock speed is 6 MHz when 2.2V VDDIO 1.62V. Figure 12 shows the timing diagram. SPI timing values for different values of SCLK and VDDM are shown in Table 19, Table 20 on page 44, Table 21 on page 44, Table 22 on page 44. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 42 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Timing and AC Characteristics Figure 12: SPI Timing Diagram CS 3 4 SCLK Mode 1 SCLK Mode 3 2 1 MOSI MISO Invalid bit MSB LSB MSB LSB Table 19: SPI1 Timing Values--SCLK = 12 MHz and VDDM = 3.2Va Reference Characteristics Symbol Min Typicalb Max Unit 1 Output setup time, from MOSI Tds_mo data valid to sample edge of SCLK - 20 - ns 2 Output hold time, from sample Tdh_mo edge of SCLK to MOSI data update - 63 - ns 3c Time from CS assert to first SCLK edge Tsu_cs 1/2 SCLK period - 1 - - ns 4c Time from first SCLK edge to CS deassert Thd_cs 1/2 SCLK period - - ns a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The speed can be adjusted to as low as 400 Hz by configuring the firmware. b. Typical timing based on 20 pF/1 M load and SCLK = 12 MHz. c. CS timing is firmware controlled. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 43 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Timing and AC Characteristics Table 20: SPI1 Timing Values--SCLK = 6 MHz and VDDM = 1.62Va Reference Characteristics Symbol Min Typicalb Max Unit 1 Output setup time, from MOSI data valid Tds_mo to sample edge of SCLK - 41 - ns 2 Output hold time, from sample edge of SCLK to MOSI data update - 120 - ns 3c Time from CS assert to first SCLK edge Tsu_cs 1/2 SCLK period - 1 - - ns 4c Time from first SCLK edge to CS deassert 1/2 SCLK period - ns Tdh_mo Thd_cs - a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The speed can be adjusted to as low as 400 Hz by configuring the firmware. b. Typical timing based on 20 pF/1 M load and SCLK = 6 MHz. c. CS timing is firmware controlled. Table 21: SPI2 Timing Values--SCLK = 12 MHz and VDDM = 3.2Va Reference Characteristics Symbol Min Typicalb Max Unit 1 Output setup time, from MOSI data valid to sample edge of SCLK Tds_mo - 26 - ns 2 Output hold time, from sample edge of SCLK to MOSI data update Tdh_mo - 56 - ns 3c Time from CS assert to first SCLK edge Tsu_cs 1/2 SCLK period - 1 - - ns 4c Time from first SCLK edge to CS deassert 1/2 SCLK period - ns Thd_cs - a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The speed can be adjusted to as low as 400 Hz by configuring the firmware. b. Typical timing based on 20 pF//1 M load and SCLK = 12 MHz. c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode. Table 22: SPI2 Timing Values--SCLK = 6 MHz and VDDM = 1.62Va Reference Characteristics 1 Symbol Min Typicalb Max Unit - 50 - ns - 120 - ns 3c Output setup time, from MOSI Tds_mo data valid to sample edge of SCLK Output hold time, from sample Tdh_mo edge of SCLK to MOSI data update Time from CS assert to first SCLK edge Tsu_cs 1/2 SCLK period - 1 - - ns 4c Time from first SCLK edge to CS deassert Thd_cs 1/2 SCLK period - - ns 2 a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The speed can be adjusted to as low as 400 Hz by configuring the firmware. b. Typical timing based on 20 pF//1 M load and SCLK = 6 MHz. c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode. Broadcom(R) November 16, 2015 * 20738-DS102-R Page 44 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Timing and AC Characteristics BSC Interface Timing Table 23: BSC Interface Timing Specifications Reference Characteristics Min Max Unit 1 Clock frequency - 100 kHz 400 800 1000 2 START condition setup time 3 START condition hold time 4 Clock low time 5 Clock high time 6 Data input hold timea 650 - ns 280 - ns 650 - ns 280 - ns 0 - ns 7 Data input setup time 100 - ns 8 STOP condition setup time 280 - ns 9 Output valid from clock - 400 ns 10 timeb 650 - ns Bus free a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions. b. Time that the cbus must be free before a new transaction can start. Figure 13: BSC Interface Timing Diagram Broadcom(R) November 16, 2015 * 20738-DS102-R Page 45 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Mechanical Information Section 4: Mechanical Information Figure 14: 40-pin QFN Package Broadcom(R) November 16, 2015 * 20738-DS102-R Page 46 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Mechanical Information Figure 15: 64-pin FBGA Package Broadcom(R) November 16, 2015 * 20738-DS102-R Page 47 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Mechanical Information Tape Reel and Packaging Specifications Table 24: BCM20738 6 x 6 x 1 mm QFN, 40-Pin Tape Reel Specifications Parameter Value Quantity per reel 4000 pieces Reel diameter 13 inches Hub diameter 4 inches Tape width 16 mm Tape pitch 12 mm Table 25: BCM20738 7 x 7 x 0.8 mm WFBGA, 64-Pin Tape Reel Specifications Parameter Value Quantity per reel 2500 pieces Reel diameter 13 inches Hub diameter 4 inches Tape width 16 mm Tape pitch 12 mm The top left corner of the BCM20738 package is situated near the sprocket holes, as shown in Figure 16. Figure 16: Pin 1 Orientation Pin 1: Top left corner of package toward sprocket holes Broadcom(R) November 16, 2015 * 20738-DS102-R Page 48 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Ordering Information Section 5: Ordering Information Table 26: Ordering Information Part Number Package Ambient Operating Temperature BCM20738A2KML3G 40-pin QFN 0C to 70C BCM20738A1KFBG 64-pin BGA 0C to 70C Broadcom(R) November 16, 2015 * 20738-DS102-R Page 49 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Acronyms and Abbreviations Appendix A: Acronyms and Abbreviations The following list of acronyms and abbreviations may appear in this document. Term Description ADC analog-to-digital converter AFH adaptive frequency hopping AHB advanced high-performance bus APB advanced peripheral bus APU audio processing unit ARM7TDMI-STM Acorn RISC Machine 7 Thumb instruction, Debugger, Multiplier, Ice, Synthesizable BSC Broadcom Serial Control BTC Bluetooth controller COEX coexistence DFU device firmware update DMA direct memory access EBI external bus interface HCI Host Control Interface HV high voltage IDC initial digital calibration IF intermediate frequency IRQ interrupt request JTAG Joint Test Action Group LCU link control unit LDO low drop-out LHL lean high land LPO low power oscillator LV LogicVisionTM MIA multiple interface agent PCM pulse code modulation PLL phase locked loop PMU power management unit POR power-on reset PWM pulse width modulation QD quadrature decoder RAM random access memory RF radio frequency ROM read-only memory RX/TX receive, transmit SPI serial peripheral interface Broadcom(R) November 16, 2015 * 20738-DS102-R Page 50 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Acronyms and Abbreviations Term Description SW software UART universal asynchronous receiver/transmitter UPI -processor interface WD watchdog Broadcom(R) November 16, 2015 * 20738-DS102-R Page 51 BROADCOM CONFIDENTIAL BCM20738 Data Sheet Broadcom(R) Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. (R) Broadcom Corporation 5300 California Avenue Irvine, CA 92617 (c) 2015 by BROADCOM CORPORATION. All rights reserved. 20738-DS102-R November 16, 2015 Phone: 949-926-5000 Fax: 949-926-5203 E-mail: info@broadcom.com Web: www.broadcom.com