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X9119
Single Digitally-Controlled (XDCP
™
) Potentiometer
FEATURES
• 1024 Resistor Taps – 10-Bit Resolution
• 2-Wire Serial Interface for write, read, and
transfer operations of the potentiometer
• Wiper Resistance, 40
Ω
Typical @ V
CC
= 5V
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on
Power Up.
• Standby Current < 3µA Max
•V
CC
: 2.7V to 5.5V Operation
• 100K
Ω
End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes Per Bit Per
Register
• 14-Lead TSSOP, xx-Lead XBGA
• Low Power CMOS
• Single Supply version of the X9118
DESCRIPTION
The X9119 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 1023 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-wire bus interface. The potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and a
four non-volatile Data Registers that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the
contents of the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
Single Supply / Low Power / 1024-tap / 2-Wire bus
A
PPLICATION
N
OTES
AND
D
EVELOPMENT
S
YSTEM
A V A I L A B L E
AN99 • AN115 • AN124 •AN133 • AN134 • AN135
FUNCTIONAL DIAGRAM
RH
RL
Bus
RW
Interface &
Control
POT
VCC
VSS
2-Wire
Bus
Address
Data
Status
Write
Read
Wiper
1024-taps
Transfer
NC NC
100KΩ
Power On Recall
Wiper Counter
Register (WCR)
Data Registers
(DR0-DR3)
Control
Interface
Preliminary Information
X9119
– Preliminary Information
Characteristics subject to change without notice.
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CIRCUIT LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF
wireless systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
DETAILED FUNCTIONAL DIAGRAM
SCL
A1
SDA
A2
WP
Interface
and
Control
Circuitry
VCC
VSS
DR0 DR1
DR2 DR3
Wiper
Counter
Register
(WCR)
RH
RL
Data
RW
1024-taps
100KΩ
Control
Power On
Recall
A0
X9119
– Preliminary Information
Characteristics subject to change without notice.
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PIN CONFIGURATION
PIN ASSIGNMENTS
Pin
(TSSOP)
Pin
(XBGA) Symbol Function
1 NC No Connect
2 A0 Device Address for 2-wire bus
3 NC No Connect
4 A2 Device Address for 2-wire bus
5 SCL Serial Clock for 2-wire bus
6 SDA Serial Data Input/Output for 2-wire bus
7V
SS
System Ground
8WP
Hardware Write Protect
9 A1 Device Address for 2-wire bus
10 NC No Connect
11 R
W
Wiper terminal of the Potentiometer
12 R
H
High terminal of the Potentiometer
13 R
L
Low terminal of the Potentiometer
14 V
CC
System Supply Voltage
VCC
RL
VSS
1
2
3
4
5
6
78
14
13
12
11
10
9
NC
RW
A2
A1
TSSOP
RH
X9119
XBGA
A0
NC
SDA
NC
SCL
X9119
WP
X9119 – Preliminary Information
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PIN DESCRIPTIONS
Bus Interface Pins
S
ERIAL
D
ATA
I
NPUT
/O
UTPUT
(SDA)
The SDA is a bidirectional serial data input/output pin
for a 2-wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of the
serial clock SCL.
It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor.
For selecting typical values, refer to the guidelines for
calculating typical values on the bus pull-up resistors
graph.
S
ERIAL
C
LOCK
(SCL)
This input is used by 2-wire master to supply 2-wire
serial clock to the X9119.
D
EVICE
A
DDRESS
(A
2
–A
0
)
The Address inputs are used to set the least significant
3 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9119. A maximum of 4 devices may occupy the 2-
wire serial bus.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
R
W
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
S
YSTEM
S
UPPLY
V
OLTAGE
(V
CC
)
AND
S
UPPLY
G
ROUND
(V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin
is the system ground.
Other Pins
N
O
C
ONNECT
No connect pins should be left open. These pins are
used for Xicor manufacturing and testing purposes.
PRINCIPLES OF OPERATION
The X9119 is an integrated microcircuit incorporating a
resistor array and its associated registers and counters
and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometer. This section provides detail
description of the following:
– Resistor Array Description
– Serial Interface Description
– Instruction and Register Description
Resistor Array Description
The X9119 is comprised of a resistor array. The array
contains, in effect, 1023 discrete resistive segments
that are connected in series (see Figure 1). The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
H
and R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R
W
) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
10-bits of the WCR (WCR[9:0]) are decoded to select,
and enable, one of 1024 switches.
The WCR may be written directly. The Data Registers
and the WCR can be read and written by the host
system.
X9119 – Preliminary Information
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Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
From Interface
Register 0
Serial
Bus
Input
Parallel
Bus
Input
Counter
Register
RH
RL
RW
10 10
C
O
U
N
T
E
R
D
E
C
O
D
E
If WCR = 000[HEX] then RW = RL
If WCR = 3FF[HEX] then RW = RH
Wiper
(WCR)
(DR0)
Circuitry
Register 1
(DR1)
Register 2
(DR2)
Register 3
(DR3)
Serial Interface Description
S
ERIAL
I
NTERFACE
The X9119 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9119 will be considered a
slave device in all applications.
C
LOCK
AND
D
ATA
C
ONVENTIONS
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 3.
S
TART
C
ONDITION
All commands to the X9119 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9119 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is met.
See Figure 3.
S
TOP
C
ONDITION
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 3.
A
CKNOWLEDGE
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9119 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9119 will respond with a final acknowledge.
See Figure 2.
X9119 – Preliminary Information
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Figure 2. Acknowledge Response from Receiver
SCL from
Master
Data Output
from Transmitter
189
START ACKNOWLEDGE
Data Output
from Receiver
ACKNOWLEDGE POLLING
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9119
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9119 is still busy with the write operation no ACK
will be returned. If the X9119 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
FLOW 1. ACK Polling Sequence
Nonvolatile Write
Command Completed
EnterACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Further
Operation?
Issue
Instruction Issue STOP
No
Yes
Yes
Proceed
Issue STOP
No
Proceed
X9119 – Preliminary Information
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Instruction and Register Description
DEVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A)
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier. The ID[3:0] bits is the device id for the
X9119; this is fixed as 0101[B] (refer to Table 1).
The A2–A0 bits in the ID byte is the internal slave
address. The physical device address is defined by the
state of the A2–A0 input pins. The slave address is
externally specified by the user. The X9119 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for
the X9119 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A2–A0 inputs can
be actively driven by CMOS input signals or tied to VCC
or VSS. The R/W bit is the LSB and is be used to
program the device for read or write operations.
INSTRUCTION BYTE AND REGISTER SELECTION
The next byte sent to the X9119 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (IOP[2:0]). The RB and RA bits point to one of
the four registers. The format is shown below in
Table 2.
Table 3 provides a complete summary of the
instruction set opcodes.
Table 1. Identification Byte Format
Table 2. Instruction Byte Format
Register Selected RB RA
DR0 0 0
DR1 0 1
DR2 1 0
DR3 1 1
ID3 ID2 ID1 ID0 A2 A1 A0 R/W
0101
(MSB) (LSB)
Device Type
Identifies
Internal Slave
Address Read or
Write Bit
I2 I1 I0 0 RB RA 0 0
(MSB) (LSB)
Instruction
Opcode
Register
Selection
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Table 3. Instruction Set
Note: (1) 1/o = data is one or zero.
Instruction
Instruction Set
OperationR/W I2I1I00RBRA 0 0
Read Wiper Counter
Register
1 1 0 0 0 0 0 0 0 Read the contents of the Wiper Counter
Register
Write Wiper Counter
Register
0 1 0 1 0 0 0 0 0 Write new value to the Wiper Counter
Register
Read Data Register 1 1 0 1 0 1/0 1/0 0 0 Read the contents of the Data Register
pointed to RB-RA.
Write Data Register 0 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register
pointed to RB-RA.
XFR Data Register to
Wiper Counter Register
1 1 1 0 0 1/0 1/0 0 0 Transfer the contents of the Data Register
pointed to by RB-RA.to the Wiper Counter
Register
XFR Wiper Counter
Register to Data Regis-
ter
0 1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter
Register to the Data Register pointed to by
RB-RA.
Instruction and Register Description
DEVICE ADDRESSING
WIPER COUNTER REGISTER (WCR)
The X9119 contains a Wiper Counter Registers (see
Table 4) for the XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of 1024
switches along its resistor array. The contents of the
WCR can be altered in one of three ways: (1) it may be
written directly by the host via the write wiper counter
register instruction (serial load); (2) it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR data register; (3)
it is loaded with the contents of its data register zero
(R0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9119 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down. Power-
up guidelines are recommended to ensure proper
loadings of the DR0 value into the WCR.
DATA REGISTERS (DR0 TO DR3)
The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the Wiper Counter Register.
All operations changing data in one of the data
registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bit 9–Bit 0 are used to store one of the 1024 wiper
position (0 ~1023).
X9119 – Preliminary Information
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Table 4. Wiper Control Register, WCR (10-bit), WCR9–WCR0: Used to store the current wiper position (Volatile, V)
Table 5. Data Register, DR (10-bit), Bit 9–Bit 0: Used to store wiper positions or data (Non-Volatile, NV)
WCR9 WCR8 WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
VVVVVVVVVV
(MSB) (LSB)
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
NV NV NV NV NV NV NV NV NV NV
MSB LSB
Four of the six instructions are four bytes in length.
These instructions are:
–Read Wiper Counter Register – read the current
wiper position of the selected potentiometer,
–Write Wiper Counter Register – change current
wiper position of the selected potentiometer,
–Read Data Register – read the contents of the
selected Data Register;
–Write Data Register – write a new value to the
selected Data Register.
The basic sequence of the four byte instructions is
illustrated in Figure 3. These four-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a data register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers.
Two instructions (see Figure 4) require a two-byte
sequence to complete. These instructions transfer data
between the host and the X9119; either between the
host and one of the data registers or directly between
the host and the Wiper Counter Register. These
instructions are:
–XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the Wiper Counter Register.
–XFR Wiper Counter Register to Data Register –
This transfers the contents of the Wiper Counter
Register to the specified Data Register.
See Instruction format for more details.
POWER UP AND DOWN REQUIREMENTS
There are no restrictions on the power-up condition of
Vcc and the voltages applied to the potentiometer pins
provided that the Vcc is always more positive than or
equal to the voltages at RH, RL, and RW, i.e. VCC ≥ RH,
RL, RW. There are no restrictions on the power-down
condition. However, the datasheet parameters for the
DCP do not apply until 1milisecond after VCC reaches
its final value.
Figure 3. Two-Byte Instruction Sequence
S
T
A
R
T
01 0 1
A2 A1 A0 R/W A
C
K
I2 I1
I0 0 RBRA0 A
C
K
SCL
SDA
S
T
O
P
000
ID3 ID2 ID1 ID0
Device ID Internal Instruction
Opcode
Address
Register
Address
X9119 – Preliminary Information
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Figure 4. Four-Byte Instruction Sequence (Write or Read for WCR or Data Registers)
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
Register
Addresses S
A
C
K
Wiper Position
(Sent by Slave on SDA) M
A
C
K
Wiper Position
(Sent by Slave on SDA) M
A
C
K
S
T
O
P
0101A2A1A0
R / W = 1
10000000 XXXXXX
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
Register
Addresses S
A
C
K
Wiper Position
(Sent by Master on SDA) S
A
C
K
Wiper Position
(Sent by Master on SDA) S
A
C
K
S
T
O
P
0101A2A1A0
R / W = 0
10100000 XXXXXX
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
Register
Addresses S
A
C
K
Wiper Position
(Sent by Slave on SDA) M
A
C
K
wiper position or data
(Sent by Slave on SDA) M
A
C
K
S
T
O
P
0101A2A1A0
R / W = 1
1010RBRA00 XXXXXX
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
A
C
K
A
C
K
SCL
SDA
A
C
K
S
T
O
P
A
C
K
ID3 ID2 ID1 ID0 A2 A1 A0 R/W I2 0
00XX0 0XX X
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
I1 I0 0RB RA
0101 XX X
Device ID Internal
Address
Instruction
Opcode
Register
Address
Wiper or Data
Position
X9119 – Preliminary Information
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Write Data Register (DR)
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Notes: (1) “A2 ~ A0”: stand for the device addresses sent by the master.
(2) WCRx refers to wiper position data in the Wiper Counter Register
S
T
A
R
T
Device Type
Identifier
Device
Addresses
S
A
C
K
Instruction
Opcode
Register
Addresses
S
A
C
K
Wiper Position or Data
(Sent by Master on SDA)
S
A
C
K
Wiper Position or Data
(Sent by Master on SDA)
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0101A2A1A0
R / W = 0
1100RBRA00 XXXXXX
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
Register
Addresses S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0101A2A1A0
R / W = 0
1110RBRA00
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
Register
Addresses S
A
C
K
S
T
O
P
0101A2A1A0
R / W = 1
1100RBRA00
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ABSOLUTE MAXIMUM RATINGS
Temperature under bias.................... –65°C to +135°C
Storage temperature......................... –65°C to +150°C
Voltage on SCL, SDA, or any address input
with respect to VSS ................................. –1V to +7V
∆V = | (VH–VL) | ......................................................5V
Lead temperature (soldering, 10 seconds) ........ 300°C
IW (10 seconds) ..................................................±6mA
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
ANALOG CHARACTERISTICS (Over recommended industrial (2.7V) operation conditions unless otherwise stated.)
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 1023 or (RH – RL) / 1023, single pot
(4) Parameters not guaranteed until 1 msec after VCC reachs its final values .
(5) n = 0, 1, 2, …,1023; m =0, 1, 2, …, 1022.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Units
RTOTAL End to End Resistance 100 kΩ
End to End Resistance Tolerance ±20 %
Power Rating 50 mW 25°C, each pot
IW Wiper Current ±3 mA
RWWiper Resistance 150 500 ΩWiper Current = ± 3mA, VCC = 3V
RWWiper Resistance 40 100 ΩIW = ± 3mA, VCC = 5V
VTERM Voltage on any RH or RL Pin VSS 5VV
SS = 0V
Noise -120 dBV Ref: 1V
Resolution 0.1 %
Absolute Linearity(1) ±1 MI(3) Rw(n)(actual) – Rw(n)(expected),
where n=8 to 1006
±1.5 MI(3) Rw(n)(actual) – Rw(n)(expected)(5)
Relative Linearity(2) ±0.5 MI(3) Rw(m + 1) – [Rw(m) + MI], where
m=8 to 1006
±1 MI(3) Rw(m + 1) – [Rw(m) + MI](5)
Temperature Coefficient of RTOTAL ±300 ppm/°C
Ratiometric Temp. Coefficient 20 ppm/°C
CH/CL/CWPotentiometer Capacitancies 10/10/25 pF See Macro model
RECOMMENDED OPERATING CONDITIONS
Temp Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Device Supply Voltage (VCC) Limits(4)
X9119 5V ±10%
X9119-2.7 2.7V to 5.5V
X9119 – Preliminary Information
Characteristics subject to change without notice. 13 of 22
REV 1.1.5 11/10/00 www.xicor.com
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
Notes: (6) This parameter is not 100% tested.
(7) tPUR and tPUW are the delays required from the time the (last) power supply (Vcc-) is stable until the specific instruction can be
issued. These parameters are not 100% tested.
(8) This is not a tested or guaranteed parameter and should be used only as a guideline.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Units
ICC1 VCC supply current
(active)
3mAf
SCL = 400KHz; VCC = +5.5V;
SDA = Open; (for 2-wire, Active, Read and
Volatile Write States only)
ICC2 VCC supply current
(nonvolatile write)
5mAf
SCL = 400KHz; VCC = +5.5V;
SDA = Open; (for 2-wire, Active,
Non-volatile Write State only)
ISB VCC current (standby) 3 µAV
CC = +5.5V; VIN = VSS or VCC; SDA = VCC;
(for 2-wire, Standby State only)
ILI Input leakage current 10 µAV
IN = VSS to VCC
ILO Output leakage
current
10 µAV
OUT = VSS to VCC
VIH Input HIGH voltage VCC x 0.7 VCC + 1 V
VIL Input LOW voltage –1 VCC x 0.3 V
VOL Output LOW voltage 0.4 V IOL = 3mA
VOH Output HIGH voltage
Parameter Min. Units
Minimum Endurance 100,000 Data changes per bit per register
Data Retention 100 years
Symbol Test Max. Units Test Conditions
CIN/OUT(6) Input/Output capacitance (SI) 8 pF VOUT = 0V
CIN(6) Input capacitance (SCL, WP, A1 and A0) 6 pF VIN = 0V
Symbol Parameter Min. Max. Units
tr VCC(6) VCC Power-up Rate 0.2 50 V/ms
tPUR(7) Power-up to Initiation of read operation 1 ms
tPUW(7) Power-up to Initiation of write operation 50 ms
X9119 – Preliminary Information
Characteristics subject to change without notice. 14 of 22
REV 1.1.5 11/10/00 www.xicor.com
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
AC TIMINGHIGH-VOLTAGE WRITE CYCLE TIMING
Input pulse levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
Symbol Parameter Min. Max. Units
fSCL Clock Frequency 400 kHz
tCYC Clock Cycle Time 2500 ns
tHIGH Clock High Time 600 ns
tLOW Clock Low Time 1300 ns
tSU:STA Start Setup Time 600 ns
tHD:STA Start Hold Time 600 ns
tSU:STO Stop Setup Time 600 ns
tSU:DAT SDA Data Input Setup Time 100 ns
tHD:DAT SDA Data Input Hold Time 0 ns
tRSCL and SDA Rise Time 300 ns
tF SCL and SDA Fall Time 300 ns
tAA SCL Low to SDA Data Output Valid Time 250 ns
tDH SDA Data Output Hold Time 0 ns
TINoise Suppression Time Constant at SCL and SDA inputs 50 ns
tBUF Bus Free Time (Prior to Any Transmission) 1300 ns
tSU:WPA A0, A1, A2 Setup Time 0 ns
tHD:WPA A0, A1, A2 Hold Time 0 ns
RH
10pF
CLCL
RW
RTOTAL
CW
25pF
10pF
RL
SPICE Macromodel
5V
1533Ω
100pF
SDA OUTPUT
3V
867Ω
100pF
SDA OUTPUT
X9119 – Preliminary Information
Characteristics subject to change without notice. 15 of 22
REV 1.1.5 11/10/00 www.xicor.com
HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
SYMBOL TABLE
Symbol Parameter Typ. Max. Units
tWR High-voltage write cycle time (store instructions) 5 10 ms
Symbol Parameter Min. Max. Units
tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs
tWRL Wiper response time after instruction issued (all load
instructions)
510µs
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
X9119 – Preliminary Information
Characteristics subject to change without notice. 16 of 22
REV 1.1.5 11/10/00 www.xicor.com
TIMING DIAGRAMS
Start and Stop Timing
Input Timing
Output Timing
tSU:STA tHD:STA tSU:STO
SCL
SDA
tR
(START) (STOP)
tF
tRtF
SCL
SDA
tHIGH
tLOW
tCYC
tHD:DAT
tSU:DAT tBUF
SCL
SDA
tDH
tAA
X9119 – Preliminary Information
Characteristics subject to change without notice. 17 of 22
REV 1.1.5 11/10/00 www.xicor.com
XDCP Timing (for All Load Instructions)
Write Protect and Device Address Pins Timing
.
SCL
SDA
RW
(STOP)
LSB
tWRL
SDA
SCL ...
...
...
WP
A0, A1, A2
tSU:WPA tHD:WPA
(START) (STOP)
(Any Instruction)
X9119 – Preliminary Information
Characteristics subject to change without notice. 18 of 22
REV 1.1.5 11/10/00 www.xicor.com
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
Application Circuits
VR
RW
+VR
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Noninverting Amplifier Voltage Regulator
Offset Voltage Adjustment Comparator with Hysterisis
+
–
VS
VO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
100KΩ
10KΩ10KΩ
10KΩ
-12V+12V
TL072
+
–
VSVO
R2
R1
}
}
X9119 – Preliminary Information
Characteristics subject to change without notice. 19 of 22
REV 1.1.5 11/10/00 www.xicor.com
Application Circuits (Continued)
Attenuator Filter
Inverting Amplifier Equivalent L-R Circuit
+
–
VS
VO
R3
R1
VO = G VS
-1/2 ≤ G ≤ +1/2
GO = 1 + R2/R1
fc = 1/(2πRC)
+
–
VS
VO
R2
R1
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
+
–
VS
Function Generator
R2
R4R1 = R2 = R3 = R4 = 10kΩ
+
–
VS
R2
R1
R
C
}
}
VO = G VS
G = - R2/R1
R2
C1
R1
R3
ZIN
+
–R2
+
–
R1
}
}
RA
RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
C
VO
X9119 – Preliminary Information
Characteristics subject to change without notice. 20 of 22
REV 1.1.5 11/10/00 www.xicor.com
a
b
Top View (Bump Side Down)
Side View (Bump Side Down)
Bottom View (Bump Side Up)
c
d
e
f
k
a
j
b
Note: Drawing not to scale
= Die Orientation mark
Symbol
Millimeters Inches
Min Nom. Max Min Nom. Max
Package Body Dimension X a
Package Body Dimension Y b
Package Height c
Package Body Thickness d
Ball Height e
Ball Diameter f
Total Ball Count g
Ball Count X Axis h
Ball Count Y Axis i
Pins Pitch XAxis j
Pins Pitch Y Axis k
Edge to Ball Center (Corner)
Distance Along X l
Edge to Ball Center (Corner)
Distance Along Y m
l
m
XX-ball BGA (X9119xxxxxxx)
X9119 – Preliminary Information
Characteristics subject to change without notice. 21 of 22
REV 1.1.5 11/10/00 www.xicor.com
PACKAGING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14-Lead Plastic, TSSOP, Package Type V
See Detail “A”
.031 (.80)
.041 (1.05)
.169 (4.3)
.177 (4.5) .252 (6.4) BSC
.025 (.65) BSC
.193 (4.9)
.200 (5.1)
.002 (.05)
.006 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
0° – 8 °
.010 (.25)
.019 (.50)
.029 (.75)
Gage Plane
Seating Plane
Detail A (20X)
X9119 – Preliminary Information
Characteristics subject to change without notice. 22 of 22
REV 1.1.5 11/10/00 www.xicor.com
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
©Xicor, Inc. 2000 Patents Pending
ORDERING INFORMATION
Device VCC Limits
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
V14 = 14-Lead TSSOP
xxx = xxx-Lead XBGA
Potentiometer Organization
Pot
T = 100KΩ
X9119 P T VY
PART MARK CONVENTION
xx Lead XBGA Top Mark
X9119xxxx-2.7
X9119xxxx xx
X9119 xxxx
X9119xxxxx I-2.7
