Dual, 10-Bit nanoDAC
with 2 ppm/°C Reference, SPI Interface
Data Sheet AD5313R
Rev. B Document Feedback
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Technical Support www.analog.com
FEATURES
Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
Low power: 3.3 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The AD5313R, a member of the nanoDAC® family, is a low power,
dual, 10-bit buffered voltage output digital-to-analog converter
(DAC). The device includes a 2.5 V, 2 ppm/°C internal reference
(enabled by default) and a gain select pin giving a full-scale output
of 2.5 V (gain = 1) or 5 V (gain = 2). The AD5313R operates
from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by
design, and exhibits less than 0.1% FSR gain error and 1.5 mV
offset error performance. The device is available in a 3 mm ×
3 mm LFCSP package and a TSSOP package.
The AD5313R also incorporates a power-on reset circuit and
a RSTSEL pin that ensures that the DAC outputs power up to
zero scale or midscale and remain there until a valid write occurs.
The part contains a per channel power-down feature that reduces
the current consumption of the device to 4 μA at 3 V while in
power-down mode.
The AD5313R employs a versatile serial peripheral interface
(SPI) that operates at clock rates up to 50 MHz, and the device
contains a VLOGIC pin that is intended for 1.8 V/3 V/5 V logic.
Table 1. Related Devices
Interface Reference 12-Bit 10-Bit
SPI Internal AD5687R N/A
External AD5687 AD53131
I2C Internal AD5697R AD5338R1
External N/A AD53381
1 The AD5313R and the AD5313 are not pin-to-pin or software compatible;
likewise, the AD5338R and the AD5338 are not pin-to-pin or software compatible.
PRODUCT HIGHLIGHTS
1. Precision DC Performance.
Total unadjusted error: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
SCLK
V
LOGIC
SYNC
SDIN
SDO
INPUT
REGISTER
DAC
REGISTER STRING
DAC A
BUFFER
V
OUT
A
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
V
OUT
B
V
REF
GND
V
DD
POWER-
DOWN
LOGIC
POWER-ON
RESET
GAIN =
×1/×2
INTERFACE LOGIC
RSTSEL GAINLDAC RESET
AD5313R
2.5V
REFERENCE
11254-001
AD5313R Data Sheet
Rev. B | Page 2 of 26
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Characteristics ........................................................................ 4
Timing Characteristics ................................................................ 5
Daisy-Chain and Readback Timing Characteristics ............... 6
Absolute Maximum Ratings ............................................................ 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 17
Digital-to-Analog Converter (DAC) ....................................... 17
Transfer Function ....................................................................... 17
DAC Architecture ....................................................................... 17
Serial Interface ............................................................................ 18
Standalone Operation ................................................................ 19
Write and Update Commands .................................................. 19
Daisy-Chain Operation ............................................................. 19
Readback Operation .................................................................. 20
Power-Down Operation ............................................................ 20
Load DAC (Hardware LDAC Pin) ........................................... 21
LDAC Mask Register ................................................................. 21
Hardware Reset (RESET) .......................................................... 22
Reset Select Pin (RSTSEL) ........................................................ 22
Internal Reference Setup ........................................................... 22
Solder Heat Reflow ..................................................................... 22
Long-Term Temperature Drift ................................................. 22
Thermal Hysteresis .................................................................... 23
Applications Information .............................................................. 24
Microprocessor Interfacing ....................................................... 24
AD5313R to ADSP-BF531 Interface ....................................... 24
AD5313R to SPORT Interface .................................................. 24
Layout Guidelines....................................................................... 24
Galvanically Isolated Interface ................................................. 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
4/2017—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to VLOGIC Parameter, Table 2 ............................................ 4
Changes to Table 4 ............................................................................ 5
Changes to Table 5 and Figure 4 ..................................................... 6
Changes to Figure 5 .......................................................................... 7
Changes to Table 6 ............................................................................ 8
Changes to RESET Description, Table 7 ........................................ 9
Changes to Figure 11 ...................................................................... 10
Changes to Figure 16 to Figure 19 ................................................ 11
Changes to Figure 20 to Figure 23 ................................................ 12
Changes to Figure 29 and Figure 30............................................. 13
Changes to Figure 33 and Figure 34............................................. 14
Changes to Table 9 .......................................................................... 18
Changes to Readback Operation Section .................................... 20
Changes to Hardware Reset (RESET) Section ............................... 22
Added Long-Term Temperature Drift Section and Figure 45 ..... 22
Changes to Ordering Guide ................................................................ 25
1/2014—Rev. 0 to Rev. A
Change to Table 2 .............................................................................. 3
Change to Table 7 .............................................................................. 9
Deleted Figure 10, Renumbered Sequentially ............................ 10
Deleted Long-Term Temperature Drift Section and
Figure 45 .......................................................................................... 23
2/2013—Revision 0: Initial Version
Data Sheet AD5313R
Rev. B | Page 3 of 26
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; 1.62 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE1
Resolution 10 Bits
Relative Accuracy ±0.12 ±0.5 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design
Zero-Code Error 0.4 1.5 mV All 0s loaded to DAC register
Offset Error +0.1 ±1.5 mV
Full-Scale Error
+0.01
±0.1
% of FSR
All 1s loaded to DAC register
Gain Error ±0.02 ±0.1 % of FSR
Total Unadjusted Error ±0.01 ±0.1 % of FSR External reference; gain = 2; TSSOP
±0.2 % of FSR Internal reference; gain = 1; TSSOP
Offset Error Drift2 ±1 µV/°C
Gain Temperature Coefficient2 ±1 ppm Of FSR/°C
DC Power Supply Rejection Ratio2 0.15 mV/V DAC code = midscale; VDD = 5 V ± 10%
DC Crosstalk2
±2 µV Due to single-channel, full-scale output change
±3 µV/mA Due to load current change
±2 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS2
Output Voltage Range 0 VREF V Gain = 1
0 2 × VREF V Gain = 2; see Figure 28
Capacitive Load Stability
2
nF
R
L
= ∞
10 nF RL = 1 kΩ
Resistive Load3 1 kΩ
Load Regulation 80 µV/mA 5 V ± 10%, DAC code = midscale;
−30 mA ≤ IOUT ≤ 30 mA
80 µV/mA 3 V ± 10%, DAC code = midscale;
−20 mA ≤ IOUT ≤ 20 mA
Short-Circuit Current4 40 mA
Load Impedance at Rails5 25 Ω See Figure 28
Power-Up Time 2.5 µs Coming out of power-down mode; VDD = 5 V
REFERENCE OUTPUT
Output Voltage6 2.4975 2.5025 V At ambient
Reference Temperature Coefficient7, 8 2 5 ppm/°C See the Terminology section
Output Impedance2 0.04 Ω
Output Voltage Noise2 12 µV p-p 0.1 Hz to 10 Hz
Output Voltage Noise Density2 240 nV/√Hz At ambient; f = 10 kHz, CL = 10 nF
Load Regulation Sourcing2 20 µV/mA At ambient
Load Regulation Sinking2 40 µV/mA At ambient
Output Current Load Capability2 ±5 mA VDD ≥ 3 V
Line Regulation2 100 µV/V At ambient
Thermal Hysteresis2 125 ppm First cycle
25 ppm Additional cycles
LOGIC INPUTS2
Input Current ±2 µA Per pin
Input Low Voltage (VINL) 0.3 × VLOGIC V
Input High Voltage (VINH) 0.7 × VLOGIC V
Pin Capacitance 2 pF
AD5313R Data Sheet
Rev. B | Page 4 of 26
Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC OUTPUTS (SDO)2
Output Low Voltage (VOL) 0.4 V ISINK = 200 µA
Output High Voltage (VOH) VLOGIC − 0.4 V ISOURCE = 200 µA
Floating State Output Capacitance 4 pF
POWER REQUIREMENTS
VLOGIC 1.62 5.5 V
ILOGIC 3 µA
VDD 2.7 5.5 V Gain = 1
VREF + 1.5 5.5 V Gain = 2
IDD VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
Normal Mode9 0.59 0.7 mA Internal reference off
1.1 1.3 mA Internal reference on, at full scale
All Power-Down Modes10 1 4 µA −40°C to +85°C
6
µA
−40°C to +105°C
1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV; it exists only when VREF = VDD with gain = 1 or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 4 to 1020.
2 Guaranteed by design and characterization; not production tested.
3 Channel A can have an output current of up to 30 mA. Similarly, Channel B can have an output current of up to 30 mA, up to a junction temperature of 110°C.
4 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature may be exceeded
during current limit, but operation above the specified maximum operation junction temperature can impair device reliability.
5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 28).
6 Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.
7 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C.
8 Reference temperature coefficient is calculated as per the box method. See the Terminology section for more information.
9 Interface is inactive, both DACs are active, and DAC outputs are unloaded.
10 Both DACs are powered down.
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; 1.62 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Temperature range = −40°C to +105°C, typical at 25°C. Guaranteed by design and characterization; not production tested.
Table 3.
Parameter1 Min Typ Max Unit Test Conditions/Comments
Output Voltage Settling Time 5 7 µs ¼ to ¾ scale settling to ±2 LSB
Slew Rate
0.8
V/µs
Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry
Digital Feedthrough 0.13 nV-sec
Digital Crosstalk 0.1 nV-sec
Analog Crosstalk 0.2 nV-sec
DAC-to-DAC Crosstalk 0.3 nV-sec
Total Harmonic Distortion (THD)2 −80 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
Output Noise Spectral Density (NSD) 300 nV/√Hz DAC code = midscale, 10 kHz; gain = 2
Output Noise 6 µV p-p 0.1 Hz to 10 Hz
Signal-to-Noise Ratio (SNR) 90 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
Spurious Free Dynamic Range (SFDR) 83 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
Signal-to-Noise-and-Distortion Ratio
(SINAD)
80 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
1 See the Terminology section.
2 Digitally generated sine wave at 1 kHz.
Data Sheet AD5313R
Rev. B | Page 5 of 26
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
1.62 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V
Parameter1 Symbol Min Max Min Max Unit
SCLK Cycle Time t1 20 20 ns
SCLK High Time t2 10 10 ns
SCLK Low Time t3 10 10 ns
SYNC to SCLK Falling Edge Setup Time t4 15 10 ns
Data Setup Time
t
5
5
5
ns
Data Hold Time t6 5 5 ns
SCLK Falling Edge to SYNC Rising Edge t7 10 10 ns
Minimum SYNC High Time t8 20 20 ns
SYNC Rising Edge to SYNC Rising Edge (DAC Register Updates) t9 870 830 ns
SYNC Falling Edge to SCLK Fall Ignore t10 16 10 ns
LDAC Pulse Width Low t11 15 15 ns
SYNC Rising Edge to LDAC Rising Edge t12 20 20 ns
SYNC Rising Edge to LDAC Falling Edge t13 30 30 ns
LDAC Falling Edge to SYNC Rising Edge t14 840 800 ns
Minimum Pulse Width Low t15 30 30 ns
Pulse Activation Time t16 30 30 ns
Power-Up Time2 4.5 4.5 µs
1Guaranteed by design and characterization; not production tested.
2 Time to exit power-down to normal mode of AD5313R operation, SYNCE rising edge to 90% of DAC midscale value, with output unloaded.
Figure 2. Serial Write Operation
11254-002
t
4
t
3
SCLK
SYNC
SDIN
t
1
t
2
t
5
t
6
t
7
t
14
t
9
t
8
DB23
t
10
t
11
t
12
LDAC
1
LDAC
2
t
13
1
ASYNCHRO NOUS LDAC UPDATE MODE.
2
SYNCHRO NOUS LDAC UPDATE MODE.
RESET
t
15
t
16
V
OUT
DB0
AD5313R Data Sheet
Rev. B | Page 6 of 26
18BDAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and Figure 5.
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, V REF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. VDD = 2.7 V to 5.5 V.
Table 5.
1.62 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V
Parameter14F
1 Symbol Min Max Min Max Unit
SCLK Cycle Time t1 66 40 ns
SCLK High Time t2 33 20 ns
SCLK Low Time t3 33 20 ns
ASYNCEE
A to SCLK Falling Edge t4 33 20 ns
Data Setup Time
t
5
5
5
ns
Data Hold Time t6 5 5 ns
SCLK Falling Edge to ASYNCEE
A Rising Edge t7 15 10 ns
Minimum ASYNCEE
A High Time t8 60 30 ns
SDO Data Valid from SCLK Rising Edge t9 45 30 ns
ASYNCEE
A Rising Edge to SCLK Falling Edge t10 15 10 ns
ASYNCEE
A Rising Edge to SDO Disable t11 60 60 ns
1 Guaranteed by design and characterization; not production tested.
43BCircuit and Timing Diagrams
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
Figure 4. Daisy-Chain Timing Diagram
200µA IOL
200µA IOH
VOH (MIN)
TO OUTPUT
PIN CL
20pF
11254-003
11254-004
t
4
t
1
t
2
t
3
t
5
t
6
t
8
SDO
SDIN
SYNC
SCLK
4824
DB23 DB0 DB23 DB0
DB23
INPUT W ORD F OR DAC NUNDEFINED
INPUT W ORD F OR DAC N + 1INPUT W ORD F OR DAC N
DB0
t
7
t
10
t
9
Data Sheet AD5313R
Rev. B | Page 7 of 26
Figure 5. Readback Timing Diagram
10485-005
SYNC
t
8
t
6
SCLK 24
124
1
t
8
t
4
t
2
t
10
t
7
t
3
t
1
DB23 DB0 DB23 DB0
SDIN
NOP CONDITIONINPUT WORD SPECIFIES
REGISTER TO BE RE AD
t
5
DB23 DB0
SDO
SELECTED REGISTER DATA
CLOCKED O UT
HI-Z
t
9
t
11
AD5313R Data Sheet
Rev. B | Page 8 of 26
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VDD to GND −0.3 V to +7 V
VLOGIC to GND −0.3 V to +7 V
VOUT to GND −0.3 V to VDD + 0.3 V
VREF to GND −0.3 V to VDD + 0.3 V
Digital Input Voltage to GND −0.3 V to VLOGIC + 0.3 V
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 125°C
16-Lead TSSOP, θJA Thermal Impedance,
0 Airflow (4-Layer Board)
112.6°C/W
16-Lead LFCSP, θJA Thermal Impedance,
0 Airflow (4-Layer Board)
70°C/W
Reflow Soldering Peak Temperature,
Pb Free (J-STD-020)
260°C
ESD1 4 kV
1 Human body model (HBM) classification.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Data Sheet AD5313R
Rev. B | Page 9 of 26
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 6. 16-Lead LFCSP Pin Configuration Figure 7. 16-Lead TSSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic Description LFCSP TSSOP
1 3 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
2 4 GND Ground Reference Point for All Circuitry on the AD5313R.
3 5 VDD Power Supply Input. The AD5313R can be operated from 2.7 V to 5.5 V. Decouple the supply with
a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
4 6 NC No Connect. Do not connect to this pin.
5 7 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
6 8 SDO
Serial Data Output. SDO can be used to daisy-chain a number of AD5313R devices together, or it
can be used for readback. The serial data is transferred on the rising edge of SCLK and is valid on
the falling edge of the clock.
7 9 LDAC LDAC can be operated in two modes: asynchronous and synchronous. Pulsing this pin low allows
either or both DAC registers to be updated if the input registers have new data; both DAC outputs
can be updated simultaneously. This pin can also be tied permanently low.
8 10 GAIN
Gain Select. When this pin is tied to GND, both DACs output a span from 0 V to VREF. If this pin is tied
to VLOGIC, both DACs output a span of 0 V to 2 × VREF.
9 11 VLOGIC Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V.
10 12 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
11 13 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, data is transferred in on the falling edges of the next 24 clocks.
12 14 SDIN Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the
falling edge of the serial clock input.
13 15 RESET Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses
are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale
or midscale, depending on the state of the RSTSEL pin. If the pin is not used, tie it permanently to VLOGIC.
If the pin is forced low at power-up, the POR circuit does not initialize correctly until the pin is released.
14 16 RSTSEL
Power-On Reset Select. Tying this pin to GND powers up both DACs to zero scale. Tying this pin to
VLOGIC powers up both DACs to midscale.
15 1 VREF Reference Voltage. The AD5313R has a common reference pin. When using the internal reference,
this is the reference output pin. When using an external reference, this is the reference input pin.
The default for this pin is as a reference output.
16 2 NC No Connect. Do not connect to this pin.
17 N/A EPAD Exposed Pad. The exposed pad must be tied to GND.
12
11
10
1
3
4
SDIN
SYNC
SCLK
9V
LOGIC
V
OUT
A
V
DD
2
GND
NC
6
SDO
5
V
OUT
B
7
LDAC
8
GAIN
16 NC
15 V
REF
14 RSTSEL
13 RESET
TOP VIEW
(Not to Scale)
AD5313R
NOTES
1. THE EXPOSED PAD MUST BE TIED TO GND.
2. NC = NO CONNECT. DO NOT CONNECT TO
THIS PIN.
11254-006
1
2
3
4
5
6
7
8
NC
V
OUT
A
GND
V
OUT
B
NC
V
DD
V
REF
SDO
16
15
14
13
12
11
10
9
RESET
SDIN
SYNC
GAIN
LDAC
V
LOGIC
SCLK
RSTSEL
NOTES
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
TOP VIEW
(Not to Scale)
AD5313R
11254-007
AD5313R Data Sheet
Rev. B | Page 10 of 26
3BTYPICAL PERFORMANCE CHARACTERISTICS
Figure 8. Internal Reference Voltage vs. Temperature
Figure 9. Reference Output Temperature Drift Histogram
Figure 10. Internal Reference Noise Spectral Density vs. Frequency
Figure 11. Internal Reference Noise, 0.1 Hz to 10 Hz
Figure 12. Internal Reference Voltage vs. Load Current
Figure 13. Internal Reference Voltage vs. Supply Voltage
–40 –20 020 40 60 80 100 120
V
REF
(V)
TEMPERATURE (°C)
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
DEVICE 5
2.4980
2.4985
2.4990
2.4995
2.5000
2.5005
2.5010
2.5015
2.5020 V
DD
= 5V
11254-008
90
0
10
20
30
40
50
60
70
80
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
NUMBER O F UNI TS
TEMPERATURE DRI FT ( pp m/°C)
VDD = 5V
11254-010
1600
0
200
400
600
800
1000
1200
1400
10 100 1k 10k 100k 1M
NSD (nV/ Hz)
FREQUENCY (MHz)
VDD = 5V
TA = 25° C
11254-012
11254-013
CH1 2µV M1.0s A CH1 160mV
1
T
V
DD
= 5V
T
A
= 25° C
2.5000
2.4999
2.4998
2.4997
2.4996
2.4995
2.4994
2.4993
–0.005 –0.003 –0.001 0.001 0.003 0.005
VREF (V)
ILOAD (A)
VDD = 5V
TA = 25° C
11254-014
2.5002
2.5000
2.4998
2.4996
2.4994
2.4992
2.49902.5 3.0 3.5 4.0 4.5 5.0 5.5
V
REF
(V)
V
DD
(V)
D1
D3
D2
T
A = 25° C
11254-015
Data Sheet AD5313R
Rev. B | Page 11 of 26
Figure 14. Integral Nonlinearity (INL) vs. Code
Figure 15. Differential Nonlinearity (DNL) vs. Code
Figure 16. INL Error and DNL Error vs. Temperature
Figure 17. INL Error and DNL Error vs. VREF
Figure 18. INL Error and DNL Error vs. Supply Voltage
Figure 19. Gain Error and Full-Scale Error vs. Temperature
11254-016
0.5
–0.5
–0.3
–0.1
0.1
0.3
0156312468625781938
INL (LSB)
CODE
11254-017
DNL (LSB)
CODE
0.5
–0.5
–0.3
–0.1
0.1
0.3
CODE
0156312468625781938
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–40 1106010
ERROR (LS B)
TEMPERATURE (°C)
INL
DNL
11254-018
V
DD
= 5V
INTERNAL RE FERE NCE = 2.5V
05.04.54.03.53.02.52.01.51.00.5 V
REF
(V)
INL
DNL
11254-019
V
DD
= 5V
T
A
= 25° C
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
ERROR (LS B)
2.7 5.24.74.23.73.2 SUPPLY VOLT AGE (V)
INL
DNL
T
A
= 25° C
INTERNAL RE FERE NCE = 2.5V
11254-020
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
ERROR (LS B)
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
–40 –20 020 40 60 80 100 120
ERROR (% of FSR)
TEMPERATURE (°C)
GAI N E RROR
FULL- S CALE E RROR
V
DD
= 5V
INTERNAL RE FERE NCE = 2.5V
11254-021
AD5313R Data Sheet
Rev. B | Page 12 of 26
Figure 20. Zero-Code Error and Offset Error vs. Temperature
Figure 21. Gain Error and Full-Scale Error vs. Supply
Figure 22. Zero-Code Error and Offset Error vs. Supply
Figure 23. Total Unadjusted Error vs. Temperature
Figure 24. Total Unadjusted Error vs. Supply Voltage, Gain = 1
Figure 25. Total Unadjusted Error vs. Code
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–40–200 20406080100120
ERROR (mV)
TEMPERATURE (°C)
OFFSET ERROR
ZERO-CODE ERROR
11254-022
V
DD
= 5V
INTERNAL REFERENCE = 2.5V
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
2.7 5.24.74.23.73.2
ERROR (% of FSR)
SUPPLY VOLTAGE (V)
GAIN ERROR
FULL-SCALE ERROR
11254-023
T
A
= 25°C
INTERNAL REFERENCE = 2.5V
1.5
–1.5
–1.0
–0.5
0
0.5
1.0
2.7 5.24.74.23.73.2
ERROR (mV)
SUPPLY VOLTAGE (V)
ZERO-CODE ERROR
OFFSET ERROR
11254-024
T
A
= 25°C
INTERNAL REFERENCE = 2.5V
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
–40–200 20406080100120
TOTAL UNADJUSTED ERROR (% of FSR)
TEMPERATURE (°C)
V
DD
= 5V
INTERNAL REFERENCE = 2.5V
11254-025
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
2.7 5.24.74.23.73.2
TOTAL UNADJUSTED ER
R
OR (
%
of FSR)
SUPPLY VOLTAGE (V)
V
DD
=5V
T
A
=25°C
INTERNAL REFERENCE = 2.5V
11254-026
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
–0.09
–0.10
0 10000 20000 30000 40000 50000 60000 65535
TOTAL UNADJUSTED ERROR (
%
o
f
F
SR)
CODE
V
DD
=5V
T
A
=25°C
INTERNAL REFERENCE = 2.5V
11254-027
Data Sheet AD5313R
Rev. B | Page 13 of 26
Figure 26. IDD Histogram with External Reference, VDD = 5 V
Figure 27. IDD Histogram with Internal Reference, VREF = 2.5 V, Gain = 2
Figure 28. Headroom/Footroom vs. Load Current
Figure 29. Source and Sink Capability at VDD = 5 V
Figure 30. Source and Sink Capability at VDD = 3 V
Figure 31. Supply Current vs. Temperature
25
20
15
10
5
0
540 560 580 600 620 640
HITS
IDD (µA)
VDD = 5V
TA = 25°C
EXTERNAL
REFERENCE = 2.5V
11254-028
30
25
20
15
10
5
0
1000 1020 1040 1060 1080 1100 1120 1140
HITS
IDD (µA)
VDD = 5V
TA = 25°C
INTERNAL
REFERENCE = 2.5V
11254-029
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 5 10 15 20 25 30
∆V
OUT
(V)
LOAD CURRENT (mA)
SOURCING 2.7V
SOURCING 5V
SINKING 2.7V
SINKING 5V
11254-030
7
–2
–1
0
1
2
3
4
5
6
–0.06 –0.04 –0.02 0 0.02 0.04 0.06
V
OUT
(V)
LOAD CURRENT (A)
0xFFFF
0x4000
0x8000
0xC000
0x0000
V
DD
= 5V
T
A
= 25°C
GAIN = 2
INTERNAL
REFERENCE = 2.5V
11254-031
I
OUT
(mA)
11254-032
V
OUT
(V)
–2
–1
0
1
2
3
4
5
–60 –40 –20 0 20 40 60
0xFFFF
0x4000
0x8000
0xC000
0x0000
V
DD
= 3V
T
A
= 25°C
GAIN = 1
EXTERNAL
REFERENCE = 2.5V
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
–40 1106010
SUPPLY CURRENT (mA)
TEMPERATURE (°C)
FULL SCALE
ZERO CODE
EXTERNAL REFERENCE, FULL-SCALE
11254-033
AD5313R Data Sheet
Rev. B | Page 14 of 26
Figure 32. Digital-to-Analog Glitch Impulse
Figure 33. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Figure 34. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference
Figure 35. Noise Spectral Density
Figure 36. Total Harmonic Distortion at 1 kHz
Figure 37. Multiplying Bandwidth, External Reference = 2.5 V, ±0.1 V p-p,
10 kHz to 10 MHz
2.4988
2.5008
2.5003
2.4998
2.4993
012810
4 62
VOUT (V)
TIME (µs)
CHANNEL B
TA = 25° C
VDD = 5.25V
REFE RE NCE = 2.5V
POSITIVE MAJOR CODE TRANSITION
ENERG Y = 0.227206n V - sec
11254-034
11254-035
CH1 2µV M1.0s A CH1 802mV
1
T
V
DD
= 5V
T
A
= 25° C
EXT E RNAL REFERE NCE = 2.5V
11254-036
CH1 2µV M1.0s A CH1 802mV
1
T
V
DD
= 5V
T
A
= 25° C
INTERNAL RE FERE NCE = 2.5V
0
200
400
600
800
1000
1200
1400
1600
10 1M100k1k 10k100
NSD (nV/ Hz)
FREQUENCY (Hz)
FULL SCALE
MIDSCALE
ZERO SCALE
V
DD
= 5V
T
A
=25°C
INTERNAL REFERENCE = 2.5V
11254-037
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
20
02000016000
8000 1200040002000 1800010000 140006000
THD ( dBV)
FREQUENCY ( Hz )
V
DD
= 5V
T
A
= 25° C
REFE RE NCE = 2.5V
11254-038
–60
–50
–40
–30
–20
–10
0
10k 10M1M100k
BANDWIDTH ( dB)
FREQUENCY ( Hz )
V
DD
= 5V
T
A
= 25° C
REFE RE NCE = 2.5V, ±0. 1V p-p
11254-039
Data Sheet AD5313R
Rev. B | Page 15 of 26
4BTERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 14.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot is shown in Figure 15
Zero-Code Error
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5313R because the output of the DAC cannot go below
0 V due to a combination of the offset errors in the DAC and
the output amplifier. Zero-code error is expressed in mV. A plot
of zero-code error vs. temperature is shown in Figure 20.
Full-Scale Error
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed in
percent of full-scale range (% of FSR). A plot of full-scale error
vs. temperature is shown in Figure 19.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal and is expressed as % of FSR.
Offset Error Drift
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
Gain Temperature Coefficient
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in ppm
of FSR/°C.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD5313R
with Code 8 loaded in the DAC register. It can be negative
or positive.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. It is the ratio of the change in VOUT to a
change in VDD for the full-scale output of the DAC. It is measured
in mV/V. VREF is held at 2 V, and VDD is varied by ±10%.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for the
output of a DAC to settle to a specified level for a ¼ to ¾ full-
scale input change and is measured from the rising edge of ASYNCE
A.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by 1 LSB
at the major carry transition, that is, 0x7FFF to 0x8000 (see
Figure 32).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC; it
is measured when the DAC output is not updated. It is specified
in nV-sec and measured with a full-scale code change on the
data bus, that is, from all 0s to all 1s and vice versa.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in dB.
Noise Spectral Density (NSD)
NSD is a measurement of the internally generated random noise.
Random noise is characterized as a spectral density. It is measured,
in nV/√Hz, by loading the DAC to midscale and measuring
noise at the output. A plot of noise spectral density is shown in
Figure 35.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change (or soft power-down and power-
up) on one DAC while monitoring another DAC kept at
midscale. It is expressed in μV.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in μV/mA.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another DAC.
It is measured in standalone mode and expressed in nV-sec.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa). Then execute a software
LDAC and monitor the output of the DAC whose digital code
was not changed. The area of the glitch is expressed in nV-sec.
AD5313R Data Sheet
Rev. B | Page 16 of 26
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by loading
the attack channel with a full-scale code change (all 0s to all 1s
and vice versa), using the write to and update commands while
monitoring the output of the victim channel that is at midscale.
The energy of the glitch is expressed in nV-sec.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
Voltage Reference Temperature Coefficient
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given tempera-
ture range expressed in ppm/°C, as follows:
6
10×
×
−
=
TempRangeV
VV
TC
REFnom
REFminREFmax
where:
VREFmax is the maximum reference output measured over the
total temperature range.
VREFmin is the minimum reference output measured over the total
temperature range.
VREFnom is the nominal reference output voltage, 2.5 V.
TempRange is the specified temperature range of −40°C to +105°C.
Data Sheet AD5313R
Rev. B | Page 17 of 26
5BTHEORY OF OPERATION
20BDIGITAL-TO-ANALOG CONVERTER (DAC)
The AD5313R is a dual 10-bit, serial input, voltage output DAC
with an internal reference. The part operates from supply voltages
of 2.7 V to 5.5 V. Data is written to the AD5313R in a 24-bit word
format via a 3-wire serial interface. The AD5313R incorporates a
power-on reset circuit to ensure that the DAC output powers up to
a known output state. The device also has a software power-down
mode that reduces the typical current consumption to 4 µA.
21BTRANSFER FUNCTION
The internal reference is on by default. To use an external
reference, only a nonreference option is available. Because the
input coding to the DAC is straight binary, the ideal output
voltage when using an external reference is given by
×=
N
REF
OUT
D
GainVV 2
where:
Gain is the output amplifier gain and is set to 1 by default. It can
be set to ×1 or ×2 using the gain select pin. When the GAIN pin
is tied to GND, both DAC outputs have a span from 0 V to VREF.
If the GAIN pin is tied to VLOGIC, both DACs output a span of
0 V to 2 × VREF.
D is the decimal equivalent of the binary code that is loaded to
the DAC register as follows: 0 to 1,024 for the 10-bit device.
N is the DAC resolution.
22BDAC ARCHITECTURE
The DAC architecture consists of a string DAC followed by an
output amplifier. Figure 38 shows a block diagram of the DAC
architecture.
Figure 38. Single DAC Channel Architecture Block Diagram
The resistor string structure is shown in Figure 39. It is a string
of resistors, each of Value R. The code loaded to the DAC register
determines the node on the string where the voltage is to be tapped
off and fed into the output amplifier. The voltage is tapped off
by closing one of the switches connecting the string to the
amplifier. Because it is a string of resistors, it is guaranteed
monotonic.
Figure 39. Resistor String Structure
44BInternal Reference
The AD5313R on-chip reference is on at power-up but can be
disabled via a write to a control register. See the Internal
Reference Setup section for details.
The AD5313R has a 2.5 V, 2 ppm/°C reference, giving a full-
scale output of 2.5 V or 5 V, depending on the state of the
GAIN pin. The internal reference associated with the device is
available at the VREF pin. This buffered reference is capable of
driving external loads of up to 10 mA.
45BOutput Amplifiers
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. The actual
range depends on the value of VREF, the GAIN pin, the offset
error, and the gain error. The GAIN pin selects the gain of the
output, as follows:
• If the GAIN pin is tied to GND, both DAC outputs have
a gain of 1, and the output range is 0 V to VREF.
• If the GAIN pin is tied to VLOGIC, both DAC outputs have
a gain of 2, and the output range is 0 V to 2 × VREF.
These amplifiers are capable of driving a load of 1 kΩ in parallel
with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale
settling time of 5 µs.
INPUT
REGISTER
2.5V
REF
DAC
REGISTER RESISTOR
STRING
REF (+)
VREF
GND
REF ( –)
VOUTX
GAIN
(GAIN = 1 OR 2)
11254-040
R
R
R
R
RTO OUTPUT
AMPLIFIER
VREF
11254-041
AD5313R Data Sheet
Rev. B | Page 18 of 26
23BSERIAL INTERFACE
The AD5313R has a 3-wire serial interface (ASYNCE
A, SCLK, and
SDIN) that is compatible with SPI, QSPI™, and MICROWIRE®
interface standards as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence. The AD5313R
contains an SDO pin that allows the user to daisy-chain multiple
devices together (see the Daisy-Chain Operation section) or read
back data.
46BInput Shift Register
The input shift register of the AD5313R is 24 bits wide, and data
is loaded MSB first (DB23). The first four bits are the command
bits (C3 to C0, as listed in Table 9), followed by the 4-bit DAC
address bits listed in Table 8 (DAC B, two don’t care bits set to 0,
and DAC A). Finally, the data-word completes the input shift
register.
The data-word comprises 10-bit input code, followed by six don’t
care bits (see Figure 40). These data bits are transferred to the
input shift register on the 24 falling edges of SCLK and are
updated on the rising edge of ASYNCE
A.
Commands can be executed on individual DAC channels or on
both DAC channels, depending on the address bits selected.
Table 8. Address Commands
Address (n)
Selected DAC Channel DAC B 0 0 DAC A
0 0 0 1 DAC A
1 0 0 0 DAC B
1 0 0 1 DAC A and DAC B
Table 9. Command Definitions
Command
C3 C2 C1 C0 Description
0 0 0 0 No operation
0 0 0 1 Write to Input Register n (dependent on ALDACE
A)
0 0 1 0 Update DAC Register n with contents of Input Register n
0 0 1 1 Write to and update DAC Channel n
0 1 0 0 Power down/power up DAC
0 1 0 1 Hardware ALDACE
A mask register
0 1 1 0 Software reset (power-on reset)
0 1 1 1 Internal reference setup register
1 0 0 0 Set up DCEN register (daisy-chain enable)
1 0 0 1 Set up readback register (readback enable)
1 0 1 0 Reserved
… … … … Reserved
1 1 1 1 No operation, daisy-chain mode
Figure 40. Input Shift Register Content
ADDRESS BIT S
COMMAND BITS
DAC
B0 0 DAC
AD9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X
C3 C2 C1 C0
DB23 (MS B)
DB0 (L S B)
DATA BI TS
11254-042
Data Sheet AD5313R
Rev. B | Page 19 of 26
24BSTANDALONE OPERATION
The write sequence begins by bringing the ASYNCE
A line low. Data
from the SDIN line is clocked into the 24-bit input shift register
on the falling edge of SCLK. After the last of 24 data bits is clocked
in, ASYNCE
A is brought high. The programmed function is then
executed; that is, an ALDACE
A-dependent change in DAC register
contents and/or a change in the mode of operation occurs.
If ASYNCE
A is taken high before the 24th clock, it is considered a valid
frame, and invalid data may be loaded to the DAC. ASYNCE
A must
be brought high for a minimum of 20 ns (single channel, see t8
in Figure 2) before the next write sequence so that a falling edge
of ASYNCE
A can initiate the next write sequence. Idle ASYNCE
A at the
rails between write sequences for an even lower power operation
of the part. The ASYNCE
A line is kept low for 24 falling edges of
SCLK, and the DAC is updated on the rising edge of ASYNCE
A.
When the data has been transferred into the input register of
the addressed DAC, both DAC registers and outputs can be
updated by taking ALDACE
A low while the ASYNCE
A line is high.
25BWRITE AND UPDATE COMMANDS
47BWrite to Input Register n (Dependent on ALDACE
A)
Command 0001 allows the user to write to the dedicated input
register of each DAC individually. When ALDACE
A is low, the input
register is transparent (if not controlled by the ALDACE
A mask
register).
48BUpdate DAC Register n with Contents of Input Register n
Command 0010 loads the DAC registers/outputs with the
contents of the input registers selected and updates the DAC
outputs directly.
49BWrite to and Update DAC Channel n (Independent of ALDACE
A)
Command 0011 allows the user to write to the DAC registers
and update the DAC outputs directly.
26BDAISY-CHAIN OPERATION
For systems that contain several DACs, the SDO pin can be
used to daisy-chain several devices together. SDO is enabled
through a software executable daisy-chain enable (DCEN)
command. Command 1000 is reserved for this DCEN function
(see Table 9). The daisy-chain mode is enabled by setting Bit DB0
in the DCEN register. The default setting is standalone mode,
where DB0 (LSB) = 0. Table 10 shows how the state of the bit
corresponds to the mode of operation of the device.
Table 10. Daisy-Chain Enable (DCEN) Register
DB0 (LSB) Description
0 Standalone mode (default)
1
DCEN mode
Figure 41. Daisy-Chaining Multiple AD5313R Devices
The SCLK pin is continuously applied to the input shift register
when ASYNCE
A is low. If more than 24 clock pulses are applied, the
data ripples out of the input shift register and appears on the
SDO line. This data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting this line to the
SDIN input on the next DAC in the chain, a daisy-chain interface
is constructed. Each DAC in the system requires 24 clock pulses.
Therefore, the total number of clock cycles must equal 24 × N,
where N is the total number of devices that are updated. If ASYNCE
A
is taken high at a clock that is not a multiple of 24, it is considered
a valid frame, and invalid data may be loaded to the DAC. When
the serial transfer to all devices is complete, ASYNCE
A is taken high.
This latches the input data in each device in the daisy chain and
prevents any further data from being clocked into the input shift
register. The serial clock can be continuous or a gated clock. A
continuous SCLK source can be used only if ASYNCE
A can be held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
be used, and ASYNCE
A must be taken high after the final clock to latch
the data.
68HC11*
MISO
SDIN
SCLK
MOSI
SCK
PC7
PC6 SDO
SCLK
SDO
SCLK
SDO
SDIN
SDIN
SYNC
SYNC
SYNC
LDAC
LDAC
LDAC
AD5313R
AD5313R
AD5313R
*ADDITIONAL PINS OMITTED FOR CLARITY.
11254-043
AD5313R Data Sheet
Rev. B | Page 20 of 26
27BREADBACK OPERATION
Readback mode is invoked through a software executable readback
command. If the SDO output is disabled via the daisy-chain mode
disable bit in the control register, it is automatically enabled for
the duration of the read operation, after which it is disabled again.
Command 1001 is reserved for the readback function. This com-
mand, in association with selecting one of the address bits, DAC B
or DAC A, determines the register to be read. Note that only one
DAC register can be selected during readback. The remaining
three address bits (which includes the two don’t care bits) must
be set to Logic 0. The remaining data bits in the write sequence
are ignored. If more than one address bit is selected or no address
bits are selected, DAC Channel A is read back by default. During
the next SPI write, the data appearing on the SDO output contains
the data from the previously addressed register.
For example, to read back the DAC register for Channel A,
implement the following sequence:
1. Write 0x900000 to the AD5313R input register. This setting
configures the device for read mode with the Channel A
DAC register selected. Note that all data bits, DB15 to DB0,
are don’t care bits.
2. Follow this write operation with a second write, a NOP
condition, 0x000000 (0xF00000 in daisy-chain mode).
During this write, the data from the register is clocked out
on the SDO line. DB23 to DB20 contain undefined data,
and the last 16 bits contain the DB19 to DB4 DAC register
contents.
28BPOWER-DOWN OPERATION
The AD5313R contains three separate power-down modes.
Command 0100 controls the power-down function (see Table 9).
These power-down modes are software-programmable by
setting eight bits, Bit DB7 to Bit DB0, in the input shift register.
There are two bits associated with each DAC channel. Table 11
explains how the state of the two bits corresponds to the mode
of operation of the device.
Table 11. Modes of Operation
Operating Mode PDx1 PDx0
Normal Operation Mode 0 0
Power-Down Modes
1 kΩ to GND 0 1
100 kΩ to GND 1 0
Three-State 1 1
Either DAC or both DACs (DAC A and DAC B) can be powered
down to the selected mode by setting the corresponding bits. See
Table 12 for the contents of the input shift register during the
power-down/power-up operation.
When both Bit PDx1 and Bit PDx0 (where x is the channel that
is selected) in the input shift register are set to 0, the AD5313R
works normally, with a normal power consumption of 4 mA at
5 V. However, for the three power-down modes of the AD5313R,
the supply current falls to 4 μA at 5 V. Not only does the supply
current fall, but the output stage is also internally switched from
the output of the amplifier to a resistor network of known values.
This switchover has the advantage that the output impedance of
the part is known while the part is in power-down mode. The
three power-down options are as follows:
• The output is connected internally to GND through a 1 kΩ
resistor.
• The output is connected internally to GND through a 100 kΩ
resistor.
• The output is left open-circuited (three-state).
The output stage is illustrated in Figure 42.
Figure 42. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down, and the DAC register can
be updated while the device is in power-down mode. The time
that is required to exit power-down is typically 4.5 µs for VDD = 5 V.
To further reduce the current consumption, the on-chip reference
can be powered off (see the Internal Reference Setup section).
Table 12. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation15F
1
DB23
(MSB) DB22 DB21 DB20 DB19 to DB16 DB15 to DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1
DB0
(LSB)
0 1 0 0 X X PDB1 PDB0 1 1 1 1 PDA1 PDA0
Command bits (C3 to C0) Address bits; don’t care Power-down,
select DAC B
Set to 1 Set to 1 Power-down,
select DAC A
1 X = don’t care.
RESISTOR
NETWORK
V
OUT
X
DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
11254-044
Data Sheet AD5313R
Rev. B | Page 21 of 26
29BLOAD DAC (HARDWARE ALDACE
A PIN)
The AD5313R DACs have double buffered interfaces consisting
of two banks of registers: input registers and DAC registers. The
user can write to any combination of the input registers. Updates
to the DAC register are controlled by the ALDACE
A pin.
Figure 43. Simplified Diagram of Input Loading Circuitry for a Single DAC
50BInstantaneous DAC Updating (ALDACE
A Held Low)
ALDACE
A is held low while data is clocked into the input register
using Command 0001. Both the addressed input register and
the DAC register are updated on the rising edge of ASYNCE
A, and
then the output begins to change (see Table 14 and Table 15).
51BDeferred DAC Updating (ALDACE
A Pulsed Low)
ALDACE
A is held high while data is clocked into the input register
using Command 0001. Both DAC outputs are asynchronously
updated by taking ALDACE
A low after ASYNCE
A is taken high. The
update then occurs on the falling edge of ALDACE
A.
ALDACE
A MASK REGISTER
Command 0101 is reserved for a software ALDACE
A mask function,
which allows the address bits to be ignored. A write to the DAC
using Command 0101 loads the 4-bit ALDACE
A mask register (DB3
to DB0). The default setting for each channel is 0; that is,
the ALDACE
A pin works normally. Setting the selected bit to 1 forces
the DAC channel to ignore transitions on the ALDACE
A pin, regardless
of the state of the hardware ALDACE
A pin. This flexibility is useful
in applications where the user wishes to select which channels
respond to the ALDACE
A pin.
The ALDACE
A mask register gives the user extra flexibility and control
over the hardware ALDACE
A pin (see Table 13). Setting an ALDACE
A bit
(DB3, DB0) to 0 for a DAC channel means that the update of
this channel is controlled by the hardware ALDACE
A pin.
Table 13. ALDACE
A Overwrite Definition
Load ALDACE
A Register
ALDACE
A Bits
(DB3, DB0) ALDACE
A Pin ALDACE
A Operation
0 1 or 0 Determined by the ALDACE
A pin.
1
X
1
DAC channels update and override
the ALDACE
A pin. DAC channels see
the ALDACE
A pin as set to 1.
1 X = don’t care.
Table 14. 24-Bit Input Shift Register Contents for ALDACE
A Operation16F
1
DB23
(MSB) DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB4 DB3 DB2 DB1
DB0
(LSB)
0 0 0 1 X X X X X DAC B 0 0 DAC A
Command bits (C3 to C0)
Address bits, don’t care
Don’t care
Setting the
ALDACE
A
bit to 1 overrides the
ALDACE
A
pin
1 X = don’t care.
Table 15. Write Commands and ALDACE
A Pin Truth Table17F
1
Command Description
Hardware ALDACE
A
Pin State Input Register Contents DAC Register Contents
0001 Write to Input Register n
(dependent on ALDACE
A)
VLOGIC Data update No change (no update)
GND18F
2 Data update Data update
0010 Update DAC Register n with
contents of Input Register n
VLOGIC No change Updated with input register contents
GND No change Updated with input register contents
0011 Write to and update DAC Channel n VLOGIC Data update Data update
GND Data update Data update
1 A high-to-low hardware LDAC pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked
(blocked) by the LDAC mask register.
2 When the LDAC pin is permanently tied low, the LDAC mask bits are ignored.
SYNC
SCLK
V
OUT
X
DAC
REGISTER
INTERFACE
LOGIC
OUTPUT
AMPLIFIER
LDAC
SDO
SDIN
V
REF
INPUT
REGISTER
10-BIT
DAC
11254-045
AD5313R Data Sheet
Rev. B | Page 22 of 26
HARDWARE RESET (RESET)
RESET is an active low reset that allows the outputs to be cleared
to either zero scale or midscale. The clear code value is user
selectable via the power-on reset select pin (RSTSEL). RESET
must be kept low for a minimum amount of time to complete
the operation (see Figure 2). When the RESET signal is returned
high, the output remains at the cleared value until a new value is
programmed. The outputs cannot be updated with a new value
while the RESET pin is low. There is also a software executable
reset function that resets the DAC to the power-on reset code.
Command 0110 is designated for this software reset function
(see Table 9). Any events on LDAC during a power-on reset are
ignored. If the RESET pin is pulled low at power-up, the device
does not initialize correctly until the pin is released.
RESET SELECT PIN (RSTSEL)
The AD5313R contains a power-on reset circuit that controls
the output voltage during power-up. When the RSTSEL pin is
connected low (to GND), the output powers up to zero scale.
Note that this is outside the linear region of the DAC. When the
RSTSEL pin is connected high (to VLOGIC), VOUTX powers up to
midscale. The output remains powered up at this level until a valid
write sequence is sent to the DAC.
INTERNAL REFERENCE SETUP
Command 0111 is reserved for setting up the internal reference
(see Table 9). By default, the on-chip reference is on at power-up.
To reduce the supply current, this reference can be turned off by
setting the software-programmable bit, DB0, as shown in Table 17.
Table 16 shows how the state of the bit corresponds to the mode
of operation.
Table 16. Internal Reference Setup Register
Internal Reference
Setup Register (DB0) Action
0 Reference on (default)
1 Reference off
SOLDER HEAT REFLOW
As with all IC reference voltage circuits, the reference value
experiences a shift induced by the soldering process. Analog
Devices, Inc., performs a reliability test, called precondition,
that mimics the effect of soldering a device to a board. The
output voltage specification that is listed in Table 2 includes the
effect of this reliability test.
Figure 44 shows the effect of solder heat reflow (SHR) as
measured through the reliability test (precondition).
Figure 44. SHR Reference Voltage Shift
LONG-TERM TEMPERATURE DRIFT
Figure 45 shows the change in the VREF (ppm) value after
1000 hours at 25°C ambient temperature.
Figure 45. Reference Drift Through to 1000 Hours
Table 17. 24-Bit Input Shift Register Contents for Internal Reference Setup Command1
DB23
(MSB) DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1
DB0
(LSB)
0 1 1 1 X X X X X 0 or 1
Command bits (C3 to C0) Address bits (A3 to A0) Don’t care Reference setup register
1 X = don’t care
60
0
10
20
30
40
50
2.498 2.499 2.500 2.501 2.502
HITS
V
REF
(V)
POSTSOLDER
HEAT REFLOW
PRESOLDER
HEAT REFLOW
11254-046
INTERNAL REFERENCE DRIFT (PPM)
ELAPSED TIME (Hours)
140
120
100
80
60
40
20
0
0 100 200 300 400 500 600 700 800 900 1000
–20
11254-100
Data Sheet AD5313R
Rev. B | Page 23 of 26
THERMAL HYSTERESIS
Thermal hysteresis is the voltage difference induced on the ref-
erence voltage by sweeping the temperature from ambient to
cold, then to hot, and then back to ambient.
Thermal hysteresis data is shown in Figure 46. It is measured
by sweeping the temperature from ambient to −40°C, next to
+105°C, and then returning to ambient. The VREF delta is then
measured between the two ambient measurements and shown
in blue in Figure 46. The same temperature sweep and measure-
ments are immediately repeated, and the results are shown in
red in Figure 46.
Figure 46. Thermal Hysteresis
9
8
7
6
5
4
3
2
1
0500–50–100–150–200
HITS
DISTORTION (ppm)
FIRST TEMPERATURE SWEEP
SUB
SEQUENT TEMPERATURE SWEEPS
11254-048
AD5313R Data Sheet
Rev. B | Page 24 of 26
APPLICATIONS INFORMATION
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5313R is achieved via a
serial bus using a standard protocol that is compatible with DSP
processors and microcontrollers. The communications channel
requires a 3-wire or 4-wire interface consisting of a clock signal,
a data signal, and a synchronization signal. The device requires
a 24-bit data-word with data valid on the rising edge of SYNC.
AD5313R TO ADSP-BF531 INTERFACE
The SPI interface of the AD5313R is designed to be easily
connected to industry-standard DSPs and microcontrollers.
Figure 47 shows the AD5313R connected to an Analog Devices
Blackfin® DSP. The Blackfin has an integrated SPI port that can
be connected directly to the SPI pins of the AD5313R.
Figure 47. AD5313R to ADSP-BF531 Interface
AD5313R TO SPORT INTERFACE
The Analog Devices ADSP-BF527 has one SPORT serial port.
Figure 48 shows how one SPORT interface can be used to
control the AD5313R.
Figure 48. AD5313R to SPORT Interface
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to ensure
the rated performance. Design the PCB on which the AD5313R
is mounted such that the AD5313R lies on the analog plane.
Provide the AD5313R with ample supply bypassing of 10 µF in
parallel with 0.1 µF on each supply, located as close to the package
as possible, ideally right up against the device. The 10 µF capa-
citors are of the tantalum bead type. Use a 0.1 µF capacitor with
low effective series resistance (ESR) and low effective series
inductance (ESI), such as the common ceramic types, which
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
In systems where there are many devices on one board, it is
often useful to provide some heat sinking capability to allow
the power to dissipate easily.
The AD5313R has an exposed paddle beneath the device.
Connect this paddle to the GND supply for the part. For
optimum performance, use special considerations to design the
motherboard and to mount the package. For enhanced thermal,
electrical, and board level performance, solder the exposed paddle
on the bottom of the package to the corresponding thermal land
paddle on the PCB. Design thermal vias into the PCB land paddle
area to further improve heat dissipation.
The GND plane on the device can be increased (as shown in
Figure 49) to provide a natural heat sinking effect.
Figure 49. Paddle Connection to Board
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. The
iCoupler® products from Analog Devices provide voltage isolation
in excess of 2.5 kV. The serial loading structure of the AD5313R
makes the part ideal for isolated interfaces because the number of
interface lines is kept to a minimum. Figure 50 shows a 4-channel
isolated interface to the AD5313R using an ADuM1400. For
more information, visit http://www.analog.com/icouplers.
Figure 50. Isolated Interface
ADSP-BF531
SYNC
SPISELx SCLK
SCK SDIN
MOSI
LDAC
PF9 RESET
PF8
AD5313R
11254-049
ADSP-BF527
SYNCSPORT_TFS SCLKSPORT_TSCK SDIN
SPORT_DTO
LDAC
GPIO0 RESETGPIO1
AD5313R
11254-050
AD5313R
GND
PLANE
BOARD
11254-051
ENCODE
SERIAL
CLO CK IN
CONTROLLER
ADuM1400
1
SERIAL
DATA O UT
SYNC O UT
LO AD DAC
OUT
DECODE TO
SCLK
TO
SDIN
TO
SYNC
TO
LDAC
V
IA
V
OA
ENCODE DECODE
V
IB
V
OB
ENCODE DECODE
V
IC
V
OC
ENCODE DECODE
V
ID
V
OD
1
ADDITIONAL PINS OMITTED FOR CLARITY.
11254-052
Data Sheet AD5313R
Rev. B | Page 25 of 26
OUTLINE DIMENSIONS
Figure 51. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
Figure 52. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Resolution
Temperature
Range Accuracy
Reference
Tempco
(ppm/°C)
Package
Description
Package
Option Branding
AD5313RBCPZ-RL7 10 Bits −40°C to +105°C ±2 LSB INL ±5 (max) 16-Lead LFCSP_WQ CP-16-22 DKZ
AD5313RBRUZ 10 Bits −40°C to +105°C ±2 LSB INL ±5 (max) 16-Lead TSSOP RU-16
AD5313RBRUZ-RL7 10 Bits −40°C to +105°C ±2 LSB INL ±5 (max) 16-Lead TSSOP RU-16
EVAL-AD5313RDBZ Evaluation Board
1 Z = RoHS Compliant Part.
3.10
3.00 SQ
2.90
0.30
0.23
0.18
1.75
1.60 SQ
1.45
08-16-2010-E
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
EXPOSED
PAD
PIN 1
INDICATOR
0.50
0.40
0.30
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.80
0.75
0.70
COMPLIANT
TO
JEDEC STANDARDS MO-220-WEED-6.
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
