4 Megabit High Speed CMOS SRAM
DPS512X8MKN3
PRELIMINARY
DESCRIPTION:
The DPS512X8MKN3 High Speed SRAM ‘’STACK’’
devices are a revolutionary new memory subsystem
using Dense-Pac Microsystems’ ceramic Stackable
Leadless Chip Carriers (SLCC) mounted on a co-fired
ceramic substrate having side-brazed leads. The
device packs 4-Megabits of low-power CMOS static
RAM in a 600-mil-wide, 32-pin dual-in-line package
that conforms to the same JEDEC standard pin
configuration.
The DPS512X8MKN3 STACK devices contain an
individual 512K x 8 SRAM die, packaged in a
hermetically sealed SLCC, making the devices suitable
for commercial, industrial and military applications.
By using SLCCs, the ‘’Stack’’ family of devices offer a
higher board density of memory than available with
conventional through-hole, surface mount or hybrid
techniques.
FEATURES:
•Organizations Available: 512K x 8
•Access Times:
20, 25, 30, 35, 45ns
•Fully Static Operation
- No clock or refresh required
•Single +5V Power Supply, ±10% Tolerance
•TTL Compatible
•Common Data Inputs and Outputs
•Low Data Retention Voltage: 2.0V min.
•Package Available: 32 Pin DIP
FUNCTIONAL BLOCK DIAGRAM
PIN NAMES
A0 - A18 Address Inputs
I/O0 - I/O7 Data Input/Output
CE Low Chip Enable
WE Write Enable
OE Output Enable
VDD Power (+5V)
VSS Ground
512Kx8, 20 - 45ns, STACK/DIP
30A129-11 D
This document contains information on a product presently under
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
PIN-OUT DIAGRAM
30A129-11
REV. D 1
DPS512X8MKN3 Dense-Pac Microsystems, Inc.
PRELIMINARY
RECOMMENDED OPERATING RANGE 3
Symbol Characteristic Min. Typ. Max. Unit
VDD Supply Voltage 4.5 5.0 5.5 V
VIH Input HIGH Voltage 2.2 VDD+0.3 V
VIL Input LOW Voltage -0.520.8 V
TAOperating
Temperature
M/B -55 +25 +125 oCI-40 +25 +85
C0+25 +70
TRUTH TABLE
Mode CE WE OE I/O Pin Supply
Current
Not Selected HX X High-Z Standby
DOUT Disable LH H High-Z Active
Read LHLDOUT Active
Write L L XDIN Active
H = HIGH L = LOW X = Don’t Care
DC OUTPUT CHARACTERISTICS
Symbol Parameter Conditions Min. Max. Unit
VOH HIGH Voltage IOH= -4.0mA 2.4 V
VOL LOW Voltage IOL=8.0mA 0.4 V
ABSOLUTE MAXIMUM RATINGS 3
Symbol Parameter Value Unit
TSTC Storage Temperature -65 to +150 °C
TBIAS Temperature Under Bias -55 to +125 °C
VDD Supply Voltage 1 -0.5 to +7.0 °C
VI/O Input/Output Voltage 1 -0.5 to VDD+0.5 V
CAPACITANCE 4: TA = 25°C, F = 1.0MHz
Symbol Parameter Max. Unit Condition
CADR Address Input 10
pF VIN2 = 0V
CCE Chip Enable 10
CWE Write Enable 10
COE Output Enable 10
CI/O Data Input/Output 12 +5V
255Ω
480Ω
CL*
DOUT
Figure 1. Output Load
* Including Probe and Jig Capacitance.
OUTPUT LOAD
Load CLParameters Measured
1100pF except tLZ, tHZ, tOHZ, tOLZ, and tWHZ
25pF tLZ, tHZ, tOHZ, tOLZ, and tWHZ
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Pulse Rise and Fall Times 5ns
Input and Output
Timing Reference Levels 1.5V
DC OPERATING CHARACTERISTICS: Over operating ranges
Symbol Characteristics Test Conditions Typ.
(†)
CIM/B Unit
Min. Max. Min. Max. Min. Max.
IIN Input
Leakage Current VIN = 0V to VDD --5 +5 -5 +5 -5 +5 µA
IOUT Output
Leakage Current VI/O = 0V to VDD,
CE = VIH, or WE = VIL --10 +10 -10 +10 -10 +10 µA
ICC Operating
Supply Current Cycle=min., Duty=100%
IOUT = 0mA 125 170 180 180 mA
ISB1 Full Standby
Supply Current VIN ≥ VDD -0.2V or
VIN ≤ VSS +0.2V 110 10 15 mA
ISB2 Standby Current (TTL) CE = VIH 20 60 60 60 mA
IDR3 Data Retention
Supply Current (3.0V) VDR = 3V, CE ≥ VDR -0.2V 150 500 1000 2000 µA
IDR2 Data Retention
Supply Current (2.0V) VDR = 2V, CE ≥ VDR -0.2V 100 300 800 1800 µA
VOL Output Low Voltage IOUT = 8.0mA -0.4 0.4 0.4 V
VOH Output High Voltage IOUT = -4.0mA -2.4 2.4 2.4 V
† Typical measurements made at +25oC, Cycle = min., VDD = 5.0V.
30A129-11
REV. D
2
Dense-Pac Microsystems, Inc. DPS512X8MKN3
PRELIMINARY
Data Retention AC Characteristics 8
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDR VDD for Data Retention CE ≥ VDR -0.2V 2.0 - - V
VCDR Chip Disable to
Data Retention Time See Data Retention Waveform 0- - ns
tROperation Recovery Time See Data Retention Waveform 5- - ms
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges
No. Symbol Parameter 20ns 25ns 30ns 35ns 45ns Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
1tRC Read Cycle Time 20 25 30 35 45 ns
2tAA Address Access Time 20 25 30 35 45 ns
3tCO CE to Output Valid 20 25 30 35 45 ns
4tOE Output Enable to Output Valid 10 12 15 20 25 ns
5tLZ CE to Output in LOW-Z 4, 5 3 3 33 3 ns
6tOLZ Output Enable to Output in LOW-Z 4, 5 0 0 00 0 ns
7tHZ CE to Output in HIGH-Z 4, 5 810 15 20 25 ns
8tOHZ Output Enable to Output in HIGH-Z 4, 5 08010 015 020 025 ns
9tOH Output Hold from Address Change 4 5 55 5 ns
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE 6, 7: Over operating ranges
No. Symbol Parameter 20ns 25ns 30ns 35ns 45ns Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
10 tWC Write Cycle Time 20 25 30 35 45 ns
11 tAW Address Valid to End of Write 13 15 20 25 35 ns
12 tCW Chip Enable to End of Write 13 15 20 25 35 ns
13 tAS Address Set-Up Time * 00000ns
14 tWP Write Pulse Width 13 15 20 25 35 ns
15 tWR Write Recovery Time 00000ns
16 tWHZ Write Enable to Output in HIGH-Z 4, 5 0 8 010 012 015 020 ns
17 tDW Data to Write Time Overlap 910 12 15 20 ns
18 tDH Data Hold from Write Time 00000ns
19 tOW Output Active from End of Write 33333ns
* Valid for both Read and Write Cycles.
DATA RETENTION WAVEFORM: CE Controlled.
VDD
4.5V
2.3V
VDR1
CE
0V
CE ≥ VDD -0.2V
30A129-11
REV. D 3
DPS512X8MKN3 Dense-Pac Microsystems, Inc.
PRELIMINARY
READ CYCLE
ADDRESS
CE
OE
DATA I/O
WRITE CYCLE 1: CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
WAVEFORM KEY
Data Valid Transition from Transition from Data Undefined
HIGH to LOW LOW to HIGH or Don’t Care
30A129-11
REV. D
4
Dense-Pac Microsystems, Inc. DPS512X8MKN3
PRELIMINARY
WRITE CYCLE 2: WE Controlled. OE is HIGH. 8
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 3: WE Controlled. OE is LOW. 8
ADDRESS
CE
WE
DATA IN
DATA OUT
30A129-11
REV. D 5
DPS512X8MKN3 Dense-Pac Microsystems, Inc.
PRELIMINARY
MECHANICAL DRAWING
ORDERING INFORMATION
Dense-Pac Microsystems, Inc.
7321 Lincoln Way ¿ Garden Grove , California 92841-1428
(714) 898-0007 (800) 642-4477 (Outside CA) ¿ FAX: (714) 897-1772 ¿ http://www.dense-pac.com
NOTES:
1. All voltages are with respect to VSS.
2. -2.0V min. for pulse width less than 20ns (VIL min. =
-0.5V at DC level).
3. Stresses greater than those under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
4. This parameter is guaranteed and not 100% tested.
5. Transition is measured at the point of ±500mV from
steady state voltage.
6. When OE and CE are LOW and WE is HIGH, I/O pins are
in the output state,and input signals of opposite phase to
the outputs must not be applied.
7. The outputs are in a high impedance state when WE is
LOW.
8. CE and WE can initiate and terminate WRITE Cycle.
30A129-11
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